JP2013098374A - Semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To separately form transistors having different withstanding voltages from each other by using a GaN-based semiconductor.SOLUTION: A semiconductor device manufacturing method comprises: laminating first, second GaN-based semiconductor layers 3, 4, an electrode layer 5, and a first insulation film 6 above a substrate 1; forming a first structure in which a first gate electrode 5 and a first insulation film 6 are laminated, and a second structure in which a second gate electrode 5 and the first insulation film 6 are laminated by patterning the electrode layer 5 and the first insulation film 6; forming a second insulation film 7 that covers the first, the second structures; anisotropically etching the second insulation film 7 by using a first mask having a first opening 8SD that exposes the first gate electrode 5 and regions on both sides, and second, third openings 8S, 8D arranged on one side and the other side of the second gate electrode 5 to form in the first opening 8SD, contact holes 9S, 9D across the first gate electrode while leaving a sidewall insulation film 7SW on a lateral face of the first structure; and forming contact holes 9S, 9D in the second and third openings, respectively, and forming an electrode in each contact hole.

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  Transistors using a two-dimensional electron gas layer as a channel, such as a high electron mobility transistor (HEMT), have been developed (see, for example, Patent Documents 1 and 2). For example, a HEMT can be formed using a GaN-based semiconductor.

JP 2010-10663 A JP 2010-109322 A

  An object of the present invention is to provide a method for manufacturing a semiconductor device, in which transistors having different breakdown voltages using a GaN-based semiconductor can be separately formed on the same substrate.

  According to an aspect of the present invention, a step of forming a first GaN-based semiconductor layer above a substrate, and a second GaN-based semiconductor layer having a band gap different from that of the first GaN-based semiconductor layer are formed on the first GaN-based semiconductor layer. Forming a gate electrode layer above the second GaN-based semiconductor layer; forming a first insulating film on the gate electrode layer; and the gate electrode layer and the first insulating film. To form a first structure in which a first gate electrode and a first portion of the first insulating film are stacked in a first region above the second GaN-based semiconductor layer, and the second GaN-based semiconductor layer Forming a second structure in which a second gate electrode and a second portion of the first insulating film are stacked in an upper second region; covering the first structure and the second structure; Above the 2GaN-based semiconductor layer, the second A step of forming an edge film; a first opening exposing the first gate electrode and regions on both sides thereof; a second opening and a third opening disposed on one side and the other side of the second gate electrode, respectively; The first gate is formed while anisotropically etching the second insulating film using a first mask having a sidewall insulating film on the side surface of the first structure in the first opening. A first source electrode forming contact hole is formed on one side of the electrode, a first drain electrode forming contact hole is formed on the other side, and a second source electrode forming contact hole is formed in the second opening. Forming a second drain electrode forming contact hole in the third opening; forming a first source electrode in the first source electrode forming contact hole; and A first drain electrode is formed in the contact hole for forming the second electrode, a second source electrode is formed in the contact hole for forming the second source electrode, and a second drain electrode is formed in the contact hole for forming the second drain electrode. And a method of manufacturing a semiconductor device, wherein a distance from the second gate electrode to the second drain electrode is longer than a distance from the first gate electrode to the first drain electrode. Is done.

  Transistors with different breakdown voltages using GaN-based semiconductors can be made on the same substrate.

1A to 1C are schematic cross-sectional views showing main steps of a semiconductor device manufacturing method according to a first embodiment. 1D and 1E are schematic cross-sectional views showing the main steps of the semiconductor device manufacturing method according to the first embodiment. 1F and 1G are schematic cross-sectional views showing the main steps of the semiconductor device manufacturing method according to the first embodiment. 1H and FIG. 1I are schematic cross-sectional views showing the main steps of the semiconductor device manufacturing method according to the first embodiment. 1J and 1K are schematic cross-sectional views showing the main steps of the semiconductor device manufacturing method according to the first embodiment. 2A and 2B are schematic cross-sectional views showing the main steps of the semiconductor device manufacturing method according to the second embodiment. 2C and 2D are schematic cross-sectional views showing the main steps of the semiconductor device manufacturing method according to the second embodiment. 3A and 3B are schematic cross-sectional views showing the main steps of the semiconductor device manufacturing method according to the third embodiment. 3C and 3D are schematic cross-sectional views showing the main steps of the semiconductor device manufacturing method according to the third embodiment. 3E and 3F are schematic cross-sectional views showing the main steps of the semiconductor device manufacturing method according to the third embodiment. 4A and 4B are schematic cross-sectional views showing main steps of a semiconductor device manufacturing method according to the fourth embodiment. 4C and 4D are schematic cross-sectional views showing the main steps of the semiconductor device manufacturing method according to the fourth embodiment. 4E and 4F are schematic cross-sectional views showing the main steps of the semiconductor device manufacturing method according to the fourth embodiment. 4G and 4H are schematic cross-sectional views showing the main steps of the semiconductor device manufacturing method according to the fourth embodiment. 5A and 5B are schematic cross-sectional views showing the main steps of a semiconductor device manufacturing method according to the fifth embodiment. 5C and 5D are schematic cross-sectional views showing the main steps of the semiconductor device manufacturing method according to the fifth embodiment. 6A and 6B are schematic cross-sectional views showing the main steps of the method of manufacturing a semiconductor device according to the sixth embodiment. 6C and 6D are schematic cross-sectional views showing the main steps of the method of manufacturing a semiconductor device according to the sixth embodiment. 6E and 6F are schematic cross-sectional views showing the main steps of the semiconductor device manufacturing method according to the sixth embodiment. 7A and 7B are schematic cross-sectional views showing the main steps of the semiconductor device manufacturing method according to the seventh embodiment. 7C and 7D are schematic cross-sectional views showing the main steps of the semiconductor device manufacturing method according to the seventh embodiment. 7E and 7F are schematic cross-sectional views showing the main steps of the semiconductor device manufacturing method according to the seventh embodiment. FIG. 8 is a schematic sectional view of a semiconductor device according to the eighth embodiment. FIG. 9 is a schematic circuit diagram of an isolated DCDC converter according to a first application example. FIG. 10 is a schematic circuit diagram of an isolated DCDC converter according to the second application example and the third application example. FIG. 11 is a circuit diagram schematically showing main parts of a voltage measurement circuit according to a second application example. FIG. 12 is a circuit diagram schematically showing main parts of a voltage measuring circuit according to a third application example.

  A method for manufacturing a semiconductor device according to an embodiment of the present invention will be described. In the embodiment, a high electron mobility transistor (HEMT) using a GaN-based semiconductor is formed, and relatively low withstand voltage, medium withstand voltage, and high withstand voltage transistors are simultaneously formed. Note that the GaN-based semiconductor contains at least Ga and N.

  First, a method for manufacturing a semiconductor device according to the first embodiment will be described. 1A to 1K are schematic cross-sectional views illustrating main steps of a method for manufacturing a semiconductor device according to a first embodiment. The left part, the center part, and the right part of each figure show the portions of the low breakdown voltage transistor, the medium breakdown voltage transistor, and the high breakdown voltage transistor, respectively.

  Reference is made to FIG. 1A. A GaN buffer layer 2, a GaN layer 3 serving as a channel layer, and an AlGaN layer 4 serving as an electron supply layer are sequentially formed on a substrate (for example, Si substrate) 1 from below, for example, by metal organic chemical vapor deposition (MOCVD). Form. The laminated thickness of the GaN buffer layer 2, the GaN layer 3, and the AlGaN layer 4 is, for example, 3 μm to 5 μm.

  A two-dimensional electron gas layer is formed at the interface between the GaN layer 3 and the AlGaN layer 4 having a wider band gap than the GaN layer 3. Note that the laminated structure of the GaN-based semiconductor layers for forming the two-dimensional electron gas layer is not limited to this example. A two-dimensional electron gas layer can be formed by stacking at least a first GaN-based semiconductor layer and a second GaN-based semiconductor layer having different band gaps.

  Refer to FIG. 1B. A gate electrode layer 5 is formed on the AlGaN layer 4. The gate electrode layer 5 is, for example, a metal layer such as Al or TaN, and is formed with a thickness of about 300 nm by sputtering (evaporation). Note that the gate electrode layer 5 may have a metal film and an insulating film, a polysilicon film and an insulating film, and a laminated structure of the three layers and the GaN layer described on the left. The insulating film is, for example, a SiO film or a SiN film.

  An insulating film 6 is formed on the gate electrode layer 5. The insulating film 6 is, for example, a silicon nitride (SiN) film or a silicon oxide (SiO) film, and is formed with a thickness of about 200 nm by, for example, chemical vapor deposition (CVD).

  Reference is made to FIG. 1C. On the insulating film 6, a resist pattern M11 having a gate electrode shape is formed. Using the resist pattern M11 as a mask, the insulating film 6 and the gate electrode layer 5 are patterned to form the gate electrodes 5 of the low breakdown voltage transistor, the medium breakdown voltage transistor, and the high breakdown voltage transistor. A structure in which an insulating film 6 is laminated on the gate electrode 5 is formed for each of the low breakdown voltage transistor, the medium breakdown voltage transistor, and the high breakdown voltage transistor. Thereafter, the resist pattern M11 is removed.

  Reference is made to FIG. 1D. An insulating film 7 is formed on the AlGaN layer 4 so as to cover the structure in which the insulating film 6 is stacked on the gate electrode 5. The insulating film 7 is, for example, a SiN film or a SiO film, and is formed with a thickness of about 200 nm to 500 nm by, for example, CVD. Tetraethoxysilane (TEOS) can also be used as the SiO film material.

  Reference is made to FIG. 1E. A resist pattern M12 is formed on the insulating film 7. The resist pattern M12 has a contact hole-shaped opening 8S for forming a source electrode and a contact hole-shaped opening 8D for forming a drain electrode in each of the medium-voltage transistor portion and the high-voltage transistor portion. In the medium voltage transistor portion and the high voltage transistor portion, the vicinity of the gate electrode 5 is covered with the resist pattern M12.

  The opening 8SD in the low breakdown voltage transistor portion of the resist pattern M12 is formed from a source electrode contact hole forming region disposed on one side of the gate electrode 5 to a drain electrode contact hole disposed on the other side of the gate electrode 5. The formation area is exposed. That is, in the low breakdown voltage transistor portion, the formation region of the gate electrode 5 is also exposed in the opening 8SD of the resist pattern M12.

  The insulating film 7 is etched by anisotropic dry etching using the resist pattern M12 as a mask. In the medium breakdown voltage transistor portion and the high breakdown voltage transistor portion, a contact hole 9S for forming a source electrode is formed in the opening 8S, and a contact hole 9D for forming a drain electrode is formed in the opening 8D.

  In the low breakdown voltage transistor portion, the insulating film 7 formed on the upper surface of the insulating film 6 is removed, and the insulating film 7 remains on the side surface of the stacked structure of the gate electrode 5 and the insulating film 6 due to etching anisotropy. Then, the sidewall insulating film 7SW is formed. The thickness of the sidewall insulating film 7SW is, for example, about 200 nm.

  In the opening 8SD, the insulating film 7 outside the sidewall insulating film 7SW is removed, and a contact hole 9S for forming a source electrode is formed on one side with the gate electrode 5 in between. A contact hole 9D for forming a drain electrode is formed on the side. Thereafter, the resist pattern M12 is removed.

  The AlGaN layer 4 can be further removed using the insulating film 7 in which the contact hole 9S and the contact hole 9D are formed as a mask.

  As described above, in the low breakdown voltage transistor, the position of the end portion on the gate electrode side of the contact hole 9S and the position of the end portion on the gate electrode side of the contact hole 9D are determined by the sidewall insulating film 7SW. That is, in the low breakdown voltage transistor, the position of the gate electrode side end (gate end) of the source electrode and the drain electrode is determined by self-alignment. On the other hand, in the medium voltage transistor and the high voltage transistor, the positions of the gate ends of the source electrode and the drain electrode are determined by the mask M12.

  Examples of the voltage applied to each electrode are as follows, for example. In each of the low breakdown voltage transistor, the medium breakdown voltage transistor, and the high breakdown voltage transistor, for example, 0 V is applied to the source electrode, and for example, 0 V is applied to the gate electrode, and 1 V to 10 V is applied to the gate electrode. For example, 1 V to 10 V is applied to the drain electrode, 10 V to 100 V is applied to the medium voltage transistor, and 100 V to 1000 V is applied to the high voltage transistor.

  The low voltage transistor has a maximum voltage difference of about 10 V between the gate and source and between the gate and drain, for example. Therefore, the distance from the gate electrode to the source electrode and the distance from the gate electrode to the drain electrode can be made relatively short, and the positions of the gate ends of the source electrode and the drain electrode are determined by self-alignment. Can do.

  In order to improve the breakdown voltage, the distance from the gate electrode to the gate end of the drain electrode is longer for the medium breakdown voltage transistor than for the low breakdown voltage transistor and longer for the high breakdown voltage transistor than for the medium breakdown voltage transistor. The distance from the gate electrode to the gate end of the drain electrode is, for example, about 200 nm for a low breakdown voltage transistor, about 2 μm for a medium breakdown voltage transistor, and about 20 μm for a high breakdown voltage transistor.

  Reference is made to FIG. 1F. A conductive film 10 is formed on the entire surface so as to cover the inner surface of the contact hole 9S and the inner surface of the contact hole 9D. The conductive film 10 is formed as follows, for example. First, as a barrier metal layer, a stacked layer of a Ti film and a TiN film is formed by sputtering. An Al layer, an AlCu layer, a TiN layer, or a W layer is formed on the barrier metal layer by sputtering or CVD. The thickness of the conductive film 10 is, for example, about 300 nm.

  Reference is made to FIG. 1G. A resist pattern M13 is formed on the conductive film 10. The resist pattern M13 is formed in a source electrode shape and a drain electrode shape for each of the low withstand voltage transistor portion and the medium withstand voltage transistor portion, and in the high withstand voltage transistor portion, the source electrode shape, the drain electrode shape, and the field plate shape are formed. It is formed with.

  Using the resist pattern M13 as a mask, the conductive film 10 is patterned to form the source electrode 10S and the drain electrode 10D of each of the low breakdown voltage transistor, the medium breakdown voltage transistor, and the high breakdown voltage transistor, and the field plate 10FP of the high breakdown voltage transistor. Thereafter, the resist pattern M13 is removed. A two-dimensional electron gas layer 2DEG is shown between the gate electrode 5 and the source electrode 10S and between the gate electrode 5 and the drain electrode 10D.

  Even if the source electrode 10S or the drain electrode 10D of the low withstand voltage transistor is patterned so as to overlap the end portion of the gate electrode 5, the source electrode 10S or the drain electrode is formed by the insulating film 6 left on the gate electrode 5. Short circuit between 10D and the gate electrode 5 is suppressed.

  The field plate 10FP of the high voltage transistor is disposed on the insulating film 7 between the gate electrode 5 and the drain electrode 10D. The applied voltage to the field plate 10FP is, for example, 0V. The field plate 10FP can alleviate electric field concentration between the gate electrode 5 and the gate end of the drain electrode 10D, and can increase the breakdown voltage.

  Refer to FIG. 1H. Over the entire surface, for example, SiO is deposited by CVD to form an interlayer insulating film 11. The upper surface of the interlayer insulating film 11 is planarized by chemical mechanical polishing (CMP).

  Reference is made to FIG. A resist pattern M14 is formed on the interlayer insulating film 11. The resist pattern M14 has a contact hole-shaped opening that exposes each source electrode 10S and a contact hole-shaped opening that exposes each drain electrode 10D.

  Using the resist pattern M14 as a mask, the interlayer insulating film 11 is etched to form a contact hole 12S exposing the source electrode 10S and a contact hole 12D exposing the drain electrode 10D. Thereafter, the resist pattern M14 is removed.

  Reference is made to FIG. 1J. A conductive film 13 is formed on the entire surface filling the contact hole 12S and the contact hole 12D. The conductive film 13 is formed as follows, for example. First, as a barrier metal layer, a stacked layer of a Ti film and a TiN film is formed by sputtering. An Al layer, an AlCu layer, a TiN layer, or a W layer is formed on the barrier metal layer by sputtering or CVD.

  Reference is made to FIG. 1K. On the conductive film 13, a resist pattern M15 having a wiring shape connected to each source electrode 10S and a wiring shape connected to each drain electrode 10D is formed. Using the resist pattern M15 as a mask, the conductive film 13 is patterned to form the wiring layer 13S and the wiring layer 13D. Thereafter, the resist pattern M15 is removed.

  In the wiring layer 13S and the wiring layer 13D of the first embodiment, the conductive plug portion embedded in the interlayer insulating film 11 and the wiring portion disposed on the interlayer insulating film 11 are integrally formed.

  Furthermore, a multilayer wiring structure can be formed above if necessary. In this way, the semiconductor device according to the first embodiment is formed.

  Next, a semiconductor device manufacturing method according to the second embodiment will be described. 2A to 2D are schematic cross-sectional views showing the main steps of the method of manufacturing a semiconductor device according to the second embodiment.

  First, the contact hole 12S and the contact hole 12D are formed in the interlayer insulating film 11 in the same manner as the process described in the first embodiment with reference to FIG. 1I.

  Refer to FIG. 2A. A conductive film 21 is formed on the entire surface filling the contact hole 12S and the contact hole 12D. The conductive film 21 is formed as follows, for example. First, as a barrier metal layer, a stacked layer of a Ti film and a TiN film is formed by sputtering. A W layer is formed by CVD on the barrier metal layer.

  Refer to FIG. 2B. The upper portion of the conductive film 21 is removed by CMP to expose the interlayer insulating film 11. Thereby, the conductive plug 21S and the conductive plug 21D are formed in the contact hole 12S and the contact hole 12D, respectively.

  Refer to FIG. 2C. A conductive film 22 is formed on the entire surface so as to cover the conductive plug 21S and the conductive plug 21D. The conductive film 22 is formed as follows, for example. First, as a barrier metal layer, a stacked layer of a Ti film and a TiN film is formed by sputtering. An Al layer, an AlCu layer, a TiN layer, or a W layer is formed on the barrier metal layer by sputtering or CVD.

  Reference is made to FIG. 2D. On the conductive film 22, a resist pattern M21 having a wiring shape connected to each conductive plug 21S and a wiring shape connected to each conductive plug 21D is formed. Using the resist pattern M21 as a mask, the conductive film 22 is patterned to form wirings 22S and wirings 22D. Thereafter, the resist pattern M21 is removed.

  As in the second embodiment, the wiring layer connected to the source electrode 10S and the wiring layer connected to the drain electrode 10D are arranged on the conductive plug portion embedded in the interlayer insulating film 11 and on the interlayer insulating film 11. The wiring portion can also be formed in separate steps.

  Furthermore, a multilayer wiring structure can be formed above if necessary. In this way, the semiconductor device according to the second embodiment is formed.

  Next, a method for fabricating a semiconductor device according to the third embodiment will be described. 3A to 3F are schematic cross-sectional views illustrating main steps of a method for manufacturing a semiconductor device according to a third embodiment.

  First, the contact hole 9S and the contact hole 9D are formed in the insulating film 7 in the same manner as the process described with reference to FIG. 1E in the first embodiment.

  Refer to FIG. 3A. A conductive film 31 is formed on the entire surface filling the contact hole 9S and the contact hole 9D. The conductive film 31 is formed as follows, for example. First, as a barrier metal layer, a stacked layer of a Ti film and a TiN film is formed by sputtering. A W layer is formed by CVD on the barrier metal layer.

  Refer to FIG. 3B. The upper part of the conductive film 31 is removed by CMP. In the low breakdown voltage transistor, the insulating film 6 is exposed above the gate electrode 5, the insulating film 7 is exposed outside the contact hole 9S and the contact hole 9D, the source electrode 31S is formed in the contact hole 9S, and the contact hole 9D is formed. A drain electrode 31D is formed on the substrate.

  In the medium voltage transistor and the high voltage transistor, the insulating film 7 is removed together with the conductive film 31 above the gate electrode 5 to expose the insulating film 6, and the insulating film 7 is exposed outside the contact hole 9S and the contact hole 9D. A source electrode 31S is formed in the contact hole 9S, and a drain electrode 31D is formed in the contact hole 9D.

  Not only the method for forming the source electrode and the drain electrode by patterning the conductive film as in the first embodiment, but the unnecessary portions of the conductive film are polished and removed to form the source electrode and the drain electrode as in the third embodiment. You can also

  Refer to FIG. 3C. A conductive film 32 is formed on the entire surface. The conductive film 32 is formed as follows, for example. First, as a barrier metal layer, a stacked layer of a Ti film and a TiN film is formed by sputtering. An Al layer, an AlCu layer, a TiN layer, or a W layer is formed on the barrier metal layer by sputtering or CVD.

  Reference is made to FIG. 3D. A resist pattern M31 is formed on the conductive film 32. The resist pattern M31 has a wiring shape connected to the source electrode 31S and a wiring shape connected to the drain electrode 31D for each of the low breakdown voltage transistor portion, the medium breakdown voltage transistor portion, and the high breakdown voltage transistor portion. , Has a field plate shape.

  Using the resist pattern M31 as a mask, the conductive film 32 is patterned to form a wiring 32S, a wiring 32D, and a field plate 32FP. Thereafter, the resist pattern M31 is removed.

  Refer to FIG. 3E. On the entire surface, for example, SiO is deposited by CVD to form an interlayer insulating film 33. The upper surface of the interlayer insulating film 33 is planarized by CMP.

  Reference is made to FIG. 3F. A resist pattern M32 is formed on the interlayer insulating film 33. The resist pattern M32 has a contact hole-shaped opening that exposes the wiring 32S and a contact hole-shaped opening that exposes the wiring 32D.

  Using the resist pattern M32 as a mask, the interlayer insulating film 33 is etched to form a contact hole 34S exposing the wiring 32S and a contact hole 34D exposing the wiring 32D. Thereafter, the resist pattern M32 is removed.

  Furthermore, a multilayer wiring structure can be formed above if necessary. In this way, the semiconductor device according to the third embodiment is formed.

  Next, a method for fabricating a semiconductor device according to the fourth embodiment will be described. 4A to 4H are schematic cross-sectional views showing the main steps of the method of manufacturing a semiconductor device according to the fourth embodiment.

  First, a structure in which the insulating film 6 remains on the gate electrode 5 is formed in the same manner as the process described with reference to FIG. 1C in the first embodiment.

  Reference is made to FIG. 4A. Similar to the formation process of the insulating film 7 described with reference to FIG. 1D in the first embodiment, an insulating film 41 is formed on the AlGaN layer 4 so as to cover the structure in which the insulating film 6 is stacked on the gate electrode 5. Form.

  In the first embodiment (to the third embodiment), the positions of the gate ends of the source and drain electrodes of the low breakdown voltage transistor are determined by self-alignment. Even in the medium withstand voltage transistor and the high withstand voltage transistor, the potential difference between the gate and the source is about 10 V at the maximum. Therefore, in the fourth embodiment, as described below, the positions of the gate ends of the source electrodes of the medium withstand voltage transistor and the high withstand voltage transistor are also determined by self-alignment.

  Refer to FIG. 4B. A resist pattern M41 is formed on the insulating film 41. Using the resist pattern M41 as a mask, the insulating film 41 is anisotropically dry etched to form a contact hole 42S for forming a source electrode and a contact hole 42D for forming a drain electrode.

  The opening shape of the resist pattern M41 according to the fourth embodiment is as follows. The opening 43SD in the low breakdown voltage transistor portion is the same as the opening 8SD in the resist pattern M12 according to the first embodiment. For the low breakdown voltage transistor portion, as in the first embodiment, the side wall insulating film 41SW is formed on the side surfaces of the gate electrode 5 on the source electrode side and the drain electrode side, and the contact hole 42S and the contact hole 42D are formed. .

  In the medium breakdown voltage transistor portion and the high breakdown voltage transistor portion, the source electrode formation opening 43S overlaps to the source electrode side end portion of the gate electrode 5 to expose the gate electrode formation region. The opening 43D for forming the drain electrode is the same as the opening 8D of the resist pattern M12 according to the first embodiment. The drain electrode side end of the gate electrode 5 is covered with a resist pattern M41.

  Therefore, in the fourth embodiment, also in the medium breakdown voltage transistor portion and the high breakdown voltage transistor portion, the sidewall insulating film 41SW is formed on the side surface on the source electrode side of the gate electrode 5, and the contact hole 42S is formed. In other words, the position of the gate end of the source electrode is also determined by self-alignment in the medium breakdown voltage transistor and the high breakdown voltage transistor.

  The AlGaN layer 4 can also be removed using the insulating film 41 in which the contact hole 42S and the contact hole 42D are formed as a mask.

  Reference is made to FIG. 4C. A conductive film 44 is formed on the entire surface covering the contact hole 42S and the contact hole 42D in the same manner as the formation process of the conductive film 10 described with reference to FIG. 1F in the first embodiment.

  Reference is made to FIG. 4D. A resist pattern M42 formed in a source electrode shape, a drain electrode shape, and a field plate shape is formed in the same manner as the process described with reference to FIG. 1G in the first embodiment. Using the resist pattern M42 as a mask, the conductive film 44 is patterned to form a source electrode 44S, a drain electrode 44D, and a field plate 44FP. Thereafter, the resist pattern M42 is removed.

  Reference is made to FIG. 4E. An interlayer insulating film 45 is formed on the entire surface in the same manner as the step of forming the interlayer insulating film 11 described with reference to FIG. 1H in the first embodiment.

  Reference is made to FIG. 4F. Similar to the process described with reference to FIG. 1I in the first embodiment, a contact hole-shaped opening exposing the source electrode 44S and a contact hole-shaped exposing the drain electrode 44D are formed on the interlayer insulating film 45. A resist pattern M43 having an opening is formed.

  Using the resist pattern M43 as a mask, the interlayer insulating film 45 is etched to form a contact hole 46S exposing the source electrode 44S and a contact hole 46D exposing the drain electrode 44D. Thereafter, the resist pattern M43 is removed.

  Reference is made to FIG. 4G. In the same manner as the formation process of the conductive film 13 described with reference to FIG. 1J in the first embodiment, the contact hole 46S and the contact hole 46D are filled, and the conductive film 47 is formed on the entire surface.

  Refer to FIG. 4H. A wiring shape resist pattern M44 connected to the source electrode 44S and a wiring shape resist pattern M44 connected to the drain electrode 44D are formed on the conductive film 47 in the same manner as described with reference to FIG. 1K in the first embodiment. .

  Using the resist pattern M44 as a mask, the conductive film 47 is patterned to form a wiring layer 47S and a wiring layer 47D. Thereafter, the resist pattern M44 is removed.

  Furthermore, a multilayer wiring structure can be formed above if necessary. In this way, the semiconductor device according to the fourth embodiment is formed.

Next, a method for fabricating a semiconductor device according to the fifth embodiment will be described. The fifth embodiment is an example in which the wiring formation method of the second embodiment is applied to the fourth embodiment in which the source electrode gate end position is determined by self-alignment also in the medium breakdown voltage transistor and the high breakdown voltage transistor. 5A to 5D are schematic cross-sectional views showing main steps of a method for manufacturing a semiconductor device according to a fifth embodiment.
First, the contact hole 46S and the contact hole 46D are formed in the interlayer insulating film 45 in the same manner as the process described in the fourth embodiment with reference to FIG. 4F.

  Refer to FIG. 5A. Similar to the formation process of the conductive film 21 described with reference to FIG. 2A in the second embodiment, the contact hole 46S and the contact hole 46D are filled, and the conductive film 51 is formed on the entire surface.

  Refer to FIG. 5B. Similar to the process described with reference to FIG. 2B in the second embodiment, the upper portion of the conductive film 51 is removed by CMP to form the conductive plug 51S and the conductive plug 51D in the contact hole 46S and the contact hole 46D, respectively. .

  Refer to FIG. 5C. A conductive film 52 is formed on the entire surface in the same manner as the conductive film 22 forming step described with reference to FIG. 2C in the second embodiment.

  Refer to FIG. 5D. Similar to the process described with reference to FIG. 2D in the second embodiment, a wiring pattern connected to the conductive plug 51S and a resist pattern M51 connected to the conductive plug 51D are formed on the conductive film 52. To do. Using the resist pattern M51 as a mask, the conductive film 52 is patterned to form wirings 52S and wirings 52D. Thereafter, the resist pattern M51 is removed. Furthermore, a multilayer wiring structure can be formed above if necessary. In this way, the semiconductor device according to the fifth embodiment is formed.

  Next, a semiconductor device manufacturing method according to the sixth embodiment will be described. In the sixth embodiment, the source / drain electrode forming method of the third embodiment is applied to the fourth embodiment in which the source electrode gate end position is determined by self-alignment even in the medium breakdown voltage transistor and the high breakdown voltage transistor. It is an example. 6A to 6F are schematic cross-sectional views showing main steps of a semiconductor device manufacturing method according to the sixth embodiment.

  First, the contact hole 42S and the contact hole 42D are formed in the insulating film 41 in the same manner as the process described in the fourth embodiment with reference to FIG. 4B.

  Refer to FIG. 6A. Similar to the formation process of the conductive film 31 described with reference to FIG. 3A in the third embodiment, the contact hole 42S and the contact hole 42D are filled, and the conductive film 61 is formed on the entire surface.

  Reference is made to FIG. 6B. Similar to the process described with reference to FIG. 3B in the third embodiment, the upper portion of the conductive film 61 is removed by CMP to form the source electrode 61S and the source electrode 61D in the contact hole 42S and the contact hole 42D, respectively. .

  Refer to FIG. 6C. A conductive film 62 is formed on the entire surface in the same manner as the conductive film 32 forming step described in the third embodiment with reference to FIG. 3C.

  Reference is made to FIG. 6D. Similar to the process described with reference to FIG. 3D in the third embodiment, a wiring shape connected to the source electrode 61S, a wiring shape connected to the drain electrode 61D, and a field plate-shaped resist are formed on the conductive film 62. A pattern M61 is formed. Using the resist pattern M61 as a mask, the conductive film 62 is patterned to form a wiring 62S, a wiring 62D, and a field plate 62FP. Thereafter, the resist pattern M61 is removed.

  Reference is made to FIG. 6E. An interlayer insulating film 63 is formed on the entire surface in the same manner as the step of forming the interlayer insulating film 33 described with reference to FIG. 3E in the third embodiment.

  Reference is made to FIG. 6F. Similar to the process described with reference to FIG. 3F in the third embodiment, a contact hole-shaped opening exposing the wiring 62S and a contact hole-shaped opening exposing the wiring 62D are formed on the interlayer insulating film 63. A resist pattern M62 is formed.

  Using the resist pattern M62 as a mask, the interlayer insulating film 63 is etched to form a contact hole 64S exposing the wiring 62S and a contact hole 64D exposing the wiring 62D. Thereafter, the resist pattern M62 is removed.

  Furthermore, a multilayer wiring structure can be formed above if necessary. In this way, the semiconductor device according to the sixth embodiment is formed.

  Next, a method for fabricating a semiconductor device according to the seventh embodiment will be described. 7A to 7F are schematic cross-sectional views showing main steps of a method for manufacturing a semiconductor device according to a seventh embodiment.

  First, the insulating film 7 is formed on the entire surface covering the structure in which the insulating film 6 is laminated on the gate electrode 5 in the same manner as the process described in the first embodiment with reference to FIG. 1D.

  Refer to FIG. 7A. The insulating film 7 on the entire surface is subjected to anisotropic dry etching. In the low breakdown voltage transistor portion, the medium breakdown voltage transistor portion, and the high breakdown voltage transistor portion, the sidewall insulating film 7SW is formed on the side surface of the stacked structure of the gate electrode 5 and the insulating film 6.

  Refer to FIG. 7B. Over the entire surface, for example, SiO is deposited by CVD to form an insulating film 71. The insulating film 71 is preferably made of a material that can be selectively etched with respect to the insulating film 6 (for example, SiN film) and the sidewall insulating film 7 (for example, SiN film). Then, the upper surface of the insulating film 71 is planarized by CMP.

  Refer to FIG. 7C. A resist pattern M71 is formed on the insulating film 71. Using the resist pattern M71 as a mask, the insulating film 71 is anisotropically dry etched to form a contact hole 72S for forming a source electrode and a contact hole 72D for forming a drain electrode. For example, it is preferable to set the etching conditions such that the insulating film 71 made of SiO is selectively etched with respect to the insulating film 6 and the sidewall insulating film 7SW made of SiN, for example.

  The opening pattern of the resist pattern M71 is the same as the resist pattern M12 used in the process described with reference to FIG. 1E in the first embodiment. That is, in the low breakdown voltage transistor portion, etching is performed with an opening pattern that exposes the gate electrode arrangement region and its both side regions. The insulating film 71 is etched outside the sidewall insulating film 7SW, and a contact hole 72S and a contact hole 72D are formed on one side and the other side of the gate electrode 5 and the sidewall insulating film 7SW, respectively.

  Further, in the medium withstand voltage transistor portion and the high withstand voltage transistor portion, etching is performed with an opening pattern disposed in the source electrode formation region and the drain electrode formation region, thereby forming a contact hole 72S and a contact hole 72D.

  Further, using the resist pattern M71 and the insulating film 71 as a mask, the AlGaN layer 4 exposed at the bottoms of the contact hole 72S and the contact hole 72D is etched. Thereafter, the resist pattern M71 is removed. Thus, in the seventh embodiment, the AlGaN layer 4 is removed, and the contact hole 72S and the contact hole 72D with the GaN layer 3 exposed at the bottom are formed.

  Refer to FIG. 7D. A conductive film 73 is formed on the entire surface filling the contact hole 72S and the contact hole 72D. The conductive film 73 is formed as follows, for example. First, as a barrier metal layer, a stacked layer of a Ti film and a TiN film is formed by sputtering. A W layer is formed by CVD on the barrier metal layer.

  The upper portion of the conductive film 73 is removed by CMP to expose the insulating film 71 and the insulating film 6. Thereby, the source electrode 73S and the source electrode 73D are formed in the contact hole 72S and the contact hole 72D, respectively.

  Refer to FIG. 7E. On the entire surface, for example, SiO is deposited by CVD to form an interlayer insulating film 74.

  A resist pattern M72 is formed on the interlayer insulating film 74. The resist pattern M72 has a contact hole-shaped opening that exposes the source electrode 73S, a contact hole-shaped opening that exposes the source electrode 73D, and a field plate-shaped opening of the high breakdown voltage transistor.

  Using the resist pattern M72 as a mask, the interlayer insulating film 74 is etched, the contact hole 75S exposing the source electrode 73S, the contact hole 75D exposing the drain electrode 73D, and the insulating film 71 exposed at the bottom, and the field plate A recessed portion 75FP to be embedded is formed. Thereafter, the resist pattern M72 is removed.

  Reference is made to FIG. 7F. A conductive film 76 is formed on the entire surface by filling the contact hole 75S, the contact hole 75D, and the recess 75FP. The conductive film 76 is formed as follows, for example. First, as a barrier metal layer, a stacked layer of a Ti film and a TiN film is formed by sputtering. An Al layer, an AlCu layer, a TiN layer, or a W layer is formed on the barrier metal layer by sputtering or CVD.

  On the conductive film 76, a wiring shape connected to the source electrode 73S, a wiring shape connected to the drain electrode 73D, and a field plate-shaped resist pattern M73 are formed. Using the resist pattern M73 as a mask, the conductive film 76 is patterned to form a wiring layer 76S, a wiring layer 76D, and a field plate 76FP. Thereafter, the resist pattern M73 is removed.

Furthermore, a multilayer wiring structure can be formed above if necessary. In this way, the semiconductor device according to the seventh embodiment is formed.
As a modification of the seventh embodiment, the position of the gate end of the source electrode of the medium withstand voltage transistor and the high withstand voltage transistor can be determined by self-alignment as in the fourth embodiment.

  Next, a semiconductor device according to the eighth embodiment will be described with reference to FIG. FIG. 8 is a schematic sectional view of a transistor according to the eighth embodiment. The transistor of the eighth embodiment has a structure in which a field plate 10FPS is formed between the gate electrode 5 and the source electrode 10S in addition to the field plate 10FP between the gate electrode 5 and the drain electrode 10D. The transistor of the eighth embodiment can be formed by appropriately changing the manufacturing process of the high voltage transistor of the first embodiment. The drain electrode side field plate 10FP and the source electrode side field plate 10FPS can also be electrically connected.

  As described above with reference to the first to eighth embodiments, the low breakdown voltage, medium breakdown voltage, and high breakdown voltage transistors can be simultaneously formed on the same substrate in the HEMT using the GaN-based semiconductor. it can.

  Next, an insulated direct current-direct current (DCDC) converter according to an application example will be described. The isolated DCDC converter is a part of the power supply device, and is a circuit that steps down the power supply voltage of, for example, 380V generated by the power factor correction circuit to, for example, about 48V.

  FIG. 9 is a schematic circuit diagram of an isolated DCDC converter according to a first application example. In the isolated DCDC converter, an input circuit 101A to which an input voltage (for example, 380V) is input and an output circuit 101B to which an output voltage (for example, 48V) is output are electrically insulated from each other. The ground reference voltage VSS1 and the ground reference voltage VSS2 of the output circuit 101B are independent.

  The input circuit 101A is formed including a drive circuit 102, a gate driver 103, and a control circuit 104. The drive circuit 102, the gate driver 103, and the control circuit 104 are formed on the same semiconductor chip 105.

An input voltage _VIN is input to the drive circuit 102. The drive circuit 102 is formed including transistors QH1 to QH4. A series connection of the transistors QH1 and QH2 and a series connection of the transistors QH3 and QH4 are connected in parallel between the input voltage _VIN and the ground reference voltage VSS1. Transistors QH1 and QH3 are arranged on the input voltage _VIN side, and transistors QH2 and QH4 are arranged on the ground reference voltage VSS1 side.

  Control signals G1 to G4 supplied from the gate driver 103 are input to the gate electrodes of the transistors QH1 to QH4, respectively, to control on / off of the transistors QH1 to QH4.

  Coil L1 is connected between node N1, which is the connection point between the drain electrode of transistor QH2 and the source electrode of transistor QH1, and node N2, which is the connection point between the drain electrode of transistor QH4 and the source electrode of transistor QH3. ing.

  The control signals G1 to G4 include the first period in which the transistors QH1 and QH4 are turned on and the transistors QH2 and QH3 are turned off, the transistors QH1 and QH4 are turned off, and the transistors QH2 and QH3 are turned on. The second period of turning on is periodically switched. The switching frequency is, for example, about 100 kHz.

  In the first period, a current flows in a direction passing through the transistor QH1, the node N1, the coil L1, the node N2, and the transistor QH4. On the other hand, in the second period, a current flows through the transistor QH3, the node N2, the coil L1, the node N1, and the transistor QH2. That is, in the first period, the current direction flows from the node N1 to the node N2, and in the second period, the current direction is reversed and flows from the node N2 to the node N1. Therefore, an alternating current flows through the coil L1 by periodically switching between the first period and the second period.

The output circuit 101B has coils L2 and L3 connected in series. Coils L2 and L3 are coupled to coil L1 of input circuit 101A. The ground reference voltage VSS2 is connected to a node N4 that is a connection point between the coil L2 and the coil L3. An end N3 of the coil L2 opposite to the node N4 and an end N5 of the coil L3 opposite to the node N4 are connected to the output point V _out via rectifying diodes D1 and D2, respectively. Yes. A capacitor C3 is connected between the output point _Vout and the ground reference voltage VSS2, and power is supplied to the load RL beyond that.

Data on the voltage value output from the output point _Vout is input to the input terminal VSENSE of the control circuit 104 via the photocoupler PC. An input current flowing through the drive circuit 102 is measured by the current coil CC, and an input current value is input to the input terminal CSENSE of the control circuit 104.

  The control circuit 104 generates the control signal PWM based on the input current value and the output voltage value so that a desired output voltage can be obtained. Based on the control signal PWM supplied from the control circuit 104, the gate driver 103 generates control signals G1 to G4 of the transistors QH1 to QH4 included in the drive circuit 102.

  It is desirable that the transistor QH1 and the like used in the drive circuit 102 have a high breakdown voltage. On the other hand, the transistors used for the control circuit 104 and the gate driver 103 may have a lower withstand voltage than the driving circuit 102.

  By using the method described in the above embodiment, low withstand voltage, medium withstand voltage, and high withstand voltage transistors can be formed on the same substrate, and the low withstand voltage, medium withstand voltage, and high withstand voltage transistors can be used as appropriate. The driver circuit 102, the gate driver 103, and the control circuit 104 can be formed on the semiconductor chip.

  An insulating DCDC converter in which the drive circuit 102, the gate driver 103, and the control circuit 104 are formed on different semiconductor chips is used as a comparative example. The isolated DCDC converter of the application example can be operated, for example, at a higher speed than the comparative example because the drive circuit 102, the gate driver 103, and the control circuit 104 are formed on the same semiconductor chip.

  FIG. 10 is a schematic circuit diagram of an isolated DCDC converter according to a second application example. The difference from the first application example is that the current coil CC is not used to measure the input current to the drive circuit 102.

  In the second application example, the current flowing through the drive circuit 102 is measured by measuring the voltage at the node N1 and the node N2 of the drive circuit 102. Since the resistance of each transistor can be measured in advance, a current value can be obtained by voltage measurement. The voltage of the node N1 is input to the input terminal CSENSE1 of the control circuit 104, and the voltage of the node N2 is input to the input terminal CSENSE2 of the control circuit 104.

  FIG. 11 is a circuit diagram schematically showing main parts of the voltage measurement circuit 104C according to the second application example. The voltage measurement circuit 104C is included in the control circuit 104. As a representative, the input terminal CSENSE1 side portion connected to the node N1 is shown, but the input terminal CSENSE2 side portion connected to the node N2 has the same structure.

  A differential amplifier including a pair of sense transistors QL11 and QL12 is formed. The ground reference voltage VSS1 is input to the gate electrode of the sense transistor QL12, the voltage of the node N1 is input to the gate electrode of the sense transistor QL11 via the transistor QH11, and the voltage of the node N1 is measured.

  The sense transistors QL11 and QL12 are formed of low breakdown voltage transistors. The transistor QH11 is formed of a high voltage transistor. When the transistor QH1 of the drive circuit 102 is on and the transistor QH2 is off, the voltage at the node N1 increases to, for example, near 380V. If such a high voltage is applied to the gate electrode of the sense transistor QL11, the transistor QL11 is destroyed. Therefore, in the voltage measurement circuit 104C of the second application example, the high breakdown voltage transistor QH11 is inserted between the transistor QL11 and the node N1.

The voltage V _N12 of the gate (node N12) of the transistor QH11 is set to the threshold value Vth of the transistor QH11 + several volts. For example, the threshold of the transistor QH11 as 1V, when the gate voltage _{V N12} of transistors QH11 and 3V, the voltage of the source (node N11) of the transistor QH11, i.e., the voltage _{V N11} applied to the gate of the sense transistor QL11 is, 2V It becomes. By suppressing the gate voltage V _N11 to several volts, the transistor QL11 is prevented from being broken.

Note that when the transistor QH2 of the drive circuit 102 is on and the transistor QH1 is off, the voltage of the node N1 is lowered to, for example, about 1V. Even when the transistor QH2 is on and the transistor QH1 is off, the gate voltage V _N12 of the transistor QH11 is determined so that the transistor QH11 is on and the voltage measurement circuit 104C functions.

Next, referring to FIG. 10 again, an isolated DCDC converter according to a third application example will be described. In the third application example, as in the second application example, the input current to the drive circuit 102 is measured without using the current coil CC, but the structure of the measurement circuit portion is different. In the third application example, as indicated by a broken line in FIG. 10, the input voltage _VIN is supplied to the control circuit 104.

  FIG. 12 is a circuit diagram schematically showing main parts of the voltage measurement circuit 104C according to the third application example. The voltage measurement circuit 104C is included in the control circuit 104. As a representative, the input terminal CSENSE1 side portion connected to the node N1 is shown, but the input terminal CSENSE2 side portion connected to the node N2 has the same structure.

A differential amplifier including a pair of sense transistors QM11 and QM12 is formed. As a power supply voltage, an input voltage _VIN is applied to the drain side of the sense transistors QM11 and QM12. The input voltage _VIN is input to the gate electrode of the sense transistor QM12, the voltage of the node N1 is input to the gate electrode of the sense transistor QM11, and the voltage of the node N1 is measured.

  When the transistor QH1 of the drive circuit 102 is off and the transistor QH2 is on, the voltage at the node N1 is lowered to, for example, near 0V, and the voltage difference between the gate and the drain of the sense transistor QM11 and between the gate and the source is, for example, near 380V. It will be very high. When the transistor QH1 is off, the transistor QH2 is on, and the node N1 is lowered to a low potential (for example, 0 V), a current flows through the transistor QM12 (in the path of QFP13, QM12, and QFP14), and the node N12 becomes a high potential.

  In the voltage measurement circuit 104C of the third application example, a field plate is formed on the drain side of the sense transistor QM11 and a field plate is also formed on the source side to improve the breakdown voltage between the gate and the drain and between the gate and the source. (Refer to the eighth embodiment). In FIG. 12, the field plate forming part is shown as a transistor, the drain side field plate forming part is shown as QFP11, and the source side field plate forming part is shown as QFP12.

  Also for the sense transistor QM12, a drain-side field plate QFP13 and a source-side field plate QFP14 are formed so as to be symmetrical with the sense transistor QM11 side.

  As described above, for HEMTs using GaN-based semiconductors, low withstand voltage, medium withstand voltage, and high withstand voltage transistors can be formed simultaneously on the same substrate. Thereby, for example, the drive circuit, the gate driver, and the control circuit in the input circuit of the isolated DCDC converter can be formed on the same semiconductor chip, and for example, the operation speed can be increased.

  Although the present invention has been described with reference to the embodiments, the present invention is not limited thereto. It will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

The following additional notes are further disclosed with respect to the embodiments including the first to eighth embodiments described above.
(Appendix 1)
Forming a first GaN-based semiconductor layer above the substrate;
Forming a second GaN semiconductor layer having a band gap different from that of the first GaN semiconductor layer on the first GaN semiconductor layer;
Forming a gate electrode layer above the second GaN-based semiconductor layer;
Forming a first insulating film on the gate electrode layer;
A first structure in which the gate electrode layer and the first insulating film are patterned, and a first gate electrode and a first portion of the first insulating film are stacked in a first region above the second GaN-based semiconductor layer. Forming a second structure in which a second gate electrode and a second portion of the first insulating film are stacked in a second region above the second GaN-based semiconductor layer;
Forming a second insulating film over the second GaN-based semiconductor layer so as to cover the first structure and the second structure;
Using a first mask having a first opening exposing the first gate electrode and regions on both sides thereof, and a second opening and a third opening disposed on one side and the other side of the second gate electrode, respectively. The second insulating film is anisotropically etched to leave a sidewall insulating film on the side surface of the first structure in the first opening, and on the one side across the first gate electrode. A first source electrode forming contact hole is formed; a first drain electrode forming contact hole is formed on the other side; a second source electrode forming contact hole is formed in the second opening; and And forming a contact hole for forming the second drain electrode,
A first source electrode is formed in the first source electrode forming contact hole, a first drain electrode is formed in the first drain electrode forming contact hole, and a first source electrode is formed in the second source electrode forming contact hole. Forming two source electrodes and forming a second drain electrode in the second drain electrode forming contact hole,
A method for manufacturing a semiconductor device, wherein a distance from the second gate electrode to the second drain electrode is longer than a distance from the first gate electrode to the first drain electrode.
(Appendix 2)
Forming the first source electrode forming contact hole, the first drain electrode forming contact hole, the second source electrode forming contact hole, and the second drain electrode forming contact hole;
In the first mask, the second opening partially exposes the formation region of the second gate electrode,
The anisotropic etching of the second insulating film, wherein the second source electrode forming contact hole is formed while leaving a sidewall insulating film on the side surface of the second structure on the second source electrode side. Semiconductor device manufacturing method.
(Appendix 3)
Forming the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode;
A first conductive film is formed over the first source electrode forming contact hole, the first drain electrode forming contact hole, the second source electrode forming contact hole, and the second drain electrode forming contact hole. And a process of
The first conductive film is formed using a second mask that covers the formation region of the first source electrode, the formation region of the first drain electrode, the formation region of the second source electrode, and the formation region of the second drain electrode. The method of manufacturing a semiconductor device according to appendix 1 or 2, further comprising: patterning the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode.
(Appendix 4)
In the step of patterning the first conductive film, the second mask covers a formation region of a field plate disposed between the second gate electrode and the second drain electrode, and patterning the first conductive film. 4. The method of manufacturing a semiconductor device according to appendix 3, wherein a field plate is formed.
(Appendix 5)
Forming the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode;
A second conductive film is formed above the first source electrode forming contact hole, the first drain electrode forming contact hole, the second source electrode forming contact hole, and the second drain electrode forming contact hole. And a process of
By polishing, a part of the second conductive film and the second insulating film remaining above the second structure are removed to form the first source electrode formation contact hole and the first drain electrode formation. In the contact hole, in the second source electrode forming contact hole, and in the second drain electrode forming contact hole, respectively, the first source electrode, the first drain electrode, the second source electrode, and The manufacturing method of the semiconductor device according to appendix 1 or 2, including a step of forming the second drain electrode.
(Appendix 6)
further,
Forming a third conductive film over the second insulating film so as to cover the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode;
A wiring formation region connected to the first source electrode, a wiring formation region connected to the first drain electrode, a wiring formation region connected to the second source electrode, and a wiring connected to the second drain electrode The third conductive film is patterned by using a third mask that covers the formation region and covers the formation region of the field plate disposed between the second gate electrode and the second drain electrode. Appendix 5 having a step of forming a wiring connected to the source electrode, a wiring connected to the first drain electrode, a wiring connected to the second source electrode, a wiring connected to the second drain electrode, and a field plate The manufacturing method of the semiconductor device of description.
(Appendix 7)
The method for manufacturing a semiconductor device according to appendix 1 or 2, further comprising a step of forming a field plate between the second gate electrode and the second drain electrode above the second insulating film.
(Appendix 8)
Forming a first GaN-based semiconductor layer above the substrate;
Forming a second GaN semiconductor layer having a band gap different from that of the first GaN semiconductor layer on the first GaN semiconductor layer;
Forming a gate electrode layer above the second GaN-based semiconductor layer;
Forming a first insulating film on the gate electrode layer;
A first structure in which the gate electrode layer and the first insulating film are patterned, and a first gate electrode and a first portion of the first insulating film are stacked in a first region above the second GaN-based semiconductor layer. Forming a second structure in which a second gate electrode and a second portion of the first insulating film are stacked in a second region above the second GaN-based semiconductor layer;
Forming a second insulating film over the second GaN-based semiconductor layer so as to cover the first structure and the second structure;
Anisotropically etching the second insulating film to form a sidewall insulating film on the side surface of the first structure and the side surface of the second structure;
Covering the first structure, the sidewall insulating film on the side surface of the first structure, the second structure, and the sidewall insulating film on the side surface of the second structure, and above the second GaN-based semiconductor layer And forming a third insulating film;
Using a mask having a first opening exposing the first gate electrode and regions on both sides thereof, and a second opening and a third opening respectively disposed on one side and the other side across the second gate electrode, By etching the third insulating film, a first source electrode forming contact hole is formed on one side of the first opening with the first gate electrode and the sidewall insulating film interposed therebetween, and the first opening is formed on the other side. Forming a first drain electrode forming contact hole, forming a second source electrode forming contact hole in the second opening, and forming a second drain electrode forming contact hole in the third opening; ,
A first source electrode is formed in the first source electrode forming contact hole, a first drain electrode is formed in the first drain electrode forming contact hole, and a first source electrode is formed in the second source electrode forming contact hole. Forming two source electrodes and forming a second drain electrode in the second drain electrode forming contact hole,
A method for manufacturing a semiconductor device, wherein a distance from the second gate electrode to the second drain electrode is longer than a distance from the first gate electrode to the first drain electrode.
(Appendix 9)
Forming the first source electrode forming contact hole, the first drain electrode forming contact hole, the second source electrode forming contact hole, and the second drain electrode forming contact hole;
In the mask, the second opening partially exposes the formation region of the second gate electrode,
Item 8. The supplementary note 8, wherein the sidewall insulating film on the side surface of the second structure is exposed in the second opening by etching the third insulating film, and a contact hole for forming a second source electrode is formed. A method for manufacturing a semiconductor device.
(Appendix 10)
The method for manufacturing a semiconductor device according to appendix 8 or 9, further comprising a step of forming a field plate between the second gate electrode and the second drain electrode above the third insulating film.

DESCRIPTION OF SYMBOLS 1 Si substrate 2 GaN buffer layer 3 GaN layer 4 AlGaN layer 5 Gate electrode layer, gate electrode 6, 7 Insulating film 7SW Side wall insulating film 8SD, 8S, 8D Mask opening 9S, 9D Contact hole 10 Conductive film 10S Source electrode 10D Drain electrode 10FP Field plate 11 Interlayer insulating film 12S, 12D Contact hole 13 Conductive film 13S, 13D Wiring layer 21, 22 Conductive plug 21S, 21D Conductive plug 22S, 22D Wiring 31 Conductive film 31S Source electrode 31D Drain electrode 32S, 32D Wiring 32FP Field plate 33 Interlayer insulating film 34S, 34D Contact hole 41 Insulating film 42S, 42D Contact hole 43SD, 43S, 43D Mask opening 44 Conductive film 44S Source electrode 44D Drain electrode 44FP Field Plate 45 Interlayer insulating film 46S, 46D Contact hole 47 Conductive film 47S, 47D Wiring layer 51, 52 Conductive film 51S, 51D Conductive plug 52S, 52D Wiring 61 Conductive film 61S Source electrode 61D Drain electrode 62S, 62D Wiring 62FP Field plate 63 Interlayer Insulating film 64S, 64D Contact hole 71 Insulating film 72S, 72D Contact hole 73 Conductive film 73S Source electrode 73D Drain electrode 74 Interlayer insulating film 75S, 75D Contact hole 75FP Recess 76S, 76D Wiring layer 76FP Field plate 10FPS Field plates M11-M15, M21, M31, M32, M41 to M44, M51, M61, M62, M71 to M73 Resist pattern

Claims (5)

Forming a first GaN-based semiconductor layer above the substrate;
Forming a second GaN semiconductor layer having a band gap different from that of the first GaN semiconductor layer on the first GaN semiconductor layer;
Forming a gate electrode layer above the second GaN-based semiconductor layer;
Forming a first insulating film on the gate electrode layer;
A first structure in which the gate electrode layer and the first insulating film are patterned, and a first gate electrode and a first portion of the first insulating film are stacked in a first region above the second GaN-based semiconductor layer. Forming a second structure in which a second gate electrode and a second portion of the first insulating film are stacked in a second region above the second GaN-based semiconductor layer;
Forming a second insulating film over the second GaN-based semiconductor layer so as to cover the first structure and the second structure;
Using a first mask having a first opening exposing the first gate electrode and regions on both sides thereof, and a second opening and a third opening disposed on one side and the other side of the second gate electrode, respectively. The second insulating film is anisotropically etched to leave a sidewall insulating film on the side surface of the first structure in the first opening, and on the one side across the first gate electrode. A first source electrode forming contact hole is formed; a first drain electrode forming contact hole is formed on the other side; a second source electrode forming contact hole is formed in the second opening; and And forming a contact hole for forming the second drain electrode,
A first source electrode is formed in the first source electrode forming contact hole, a first drain electrode is formed in the first drain electrode forming contact hole, and a first source electrode is formed in the second source electrode forming contact hole. Forming two source electrodes and forming a second drain electrode in the second drain electrode forming contact hole,
A method for manufacturing a semiconductor device, wherein a distance from the second gate electrode to the second drain electrode is longer than a distance from the first gate electrode to the first drain electrode. Forming the first source electrode forming contact hole, the first drain electrode forming contact hole, the second source electrode forming contact hole, and the second drain electrode forming contact hole;
In the first mask, the second opening partially exposes the formation region of the second gate electrode,
The anisotropic etching of the second insulating film forms the second source electrode forming contact hole while leaving a sidewall insulating film on the second source electrode side surface of the second structure. The manufacturing method of the semiconductor device of description.   The method for manufacturing a semiconductor device according to claim 1, further comprising a step of forming a field plate between the second gate electrode and the second drain electrode above the second insulating film. Forming a first GaN-based semiconductor layer above the substrate;
Forming a second GaN semiconductor layer having a band gap different from that of the first GaN semiconductor layer on the first GaN semiconductor layer;
Forming a gate electrode layer above the second GaN-based semiconductor layer;
Forming a first insulating film on the gate electrode layer;
A first structure in which the gate electrode layer and the first insulating film are patterned, and a first gate electrode and a first portion of the first insulating film are stacked in a first region above the second GaN-based semiconductor layer. Forming a second structure in which a second gate electrode and a second portion of the first insulating film are stacked in a second region above the second GaN-based semiconductor layer;
Forming a second insulating film over the second GaN-based semiconductor layer so as to cover the first structure and the second structure;
Anisotropically etching the second insulating film to form a sidewall insulating film on the side surface of the first structure and the side surface of the second structure;
Covering the first structure, the sidewall insulating film on the side surface of the first structure, the second structure, and the sidewall insulating film on the side surface of the second structure, and above the second GaN-based semiconductor layer And forming a third insulating film;
Using a mask having a first opening exposing the first gate electrode and regions on both sides thereof, and a second opening and a third opening respectively disposed on one side and the other side across the second gate electrode, By etching the third insulating film, a first source electrode forming contact hole is formed on one side of the first opening with the first gate electrode and the sidewall insulating film interposed therebetween, and the first opening is formed on the other side. Forming a first drain electrode forming contact hole, forming a second source electrode forming contact hole in the second opening, and forming a second drain electrode forming contact hole in the third opening; ,
A first source electrode is formed in the first source electrode forming contact hole, a first drain electrode is formed in the first drain electrode forming contact hole, and a first source electrode is formed in the second source electrode forming contact hole. Forming two source electrodes and forming a second drain electrode in the second drain electrode forming contact hole,
A method for manufacturing a semiconductor device, wherein a distance from the second gate electrode to the second drain electrode is longer than a distance from the first gate electrode to the first drain electrode.   The method of manufacturing a semiconductor device according to claim 4, further comprising a step of forming a field plate between the second gate electrode and the second drain electrode above the third insulating film.

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