JP2015053387A - Compound semiconductor substrate and magnetic sensor, and method for manufacturing compound semiconductor substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a compound semiconductor substrate and a magnetic sensor, and a method for manufacturing the compound semiconductor substrate which can easily control concentration and resistivity of an N-type carrier to a desired range, in a compound semiconductor layer on an Si substrate.SOLUTION: A compound semiconductor substrate includes: an Si substrate 100 in which a plane direction of a substrate surface is a (111) plane; a first compound semiconductor layer 21 formed on the Si substrate 100; and a second compound semiconductor layer 22 formed on the first compound semiconductor layer 21. The first compound semiconductor layer 21 is a GaAsSb(0≤x≤0.1) layer. The second compound semiconductor layer 22 is a GaAsSb(0<y≤0.05) layer. The second compound semiconductor layer 22 has a doped region which is formed by doping an impurity and has an N-type carrier for working as an active layer.

Description

  The present invention relates to a compound semiconductor substrate, a magnetic sensor, and a method for manufacturing a compound semiconductor substrate. More specifically, the present invention relates to a compound semiconductor substrate including a compound semiconductor layer including a GaAsSb layer on an Si substrate, a magnetic sensor including the compound semiconductor substrate, and a method for manufacturing the compound semiconductor substrate.

  In recent years, magnetic sensors have been used for various purposes. Among them, GaAs-based magnetic sensors having excellent temperature stability have been used in various fields such as in-vehicle, consumer, and industrial equipment. In particular, taking advantage of its excellent temperature stability, sales have been greatly increased in the applications of precision position detection of lenses for autofocus and camera shake correction in digital cameras and smartphones. As digital cameras become smaller and smartphones become thinner, there is a strong demand for thinner magnetic sensors.

  Conventionally, a GaAs Hall element generally forms a magnetic sensor by implanting Si or the like into a GaAs single crystal substrate by ion implantation and patterning the substrate on an activation process. Alternatively, a GaAs Hall element is formed by forming a GaAs epitaxial film doped with Si or the like on a GaAs single crystal substrate by molecular beam epitaxy (MBE) or metal organic chemical vapor deposition (MOCVD). In general, a magnetic sensor is formed by patterning a formed substrate (epi substrate). The magnetic sensor formed in this way is thinned by back grinding, and further separated and packaged.

Therefore, the thinning of the GaAs substrate is an extremely important technique for meeting the demand for thinning the magnetic sensor. However, GaAs is more fragile and easier to break than Si and the like, and the yield is deteriorated in mass production of less than 100 μm, and it is considered difficult to reduce the thickness to 50 μm in mass production.
Therefore, if it is possible to form a magnetic sensor by forming GaAs on a Si substrate that is inexpensive, difficult to crack, and easy to increase in diameter, the magnetic sensor can be thinned at the mass production level. Many studies have been made to form a GaAs thin film on a Si substrate. For example, Patent Document 1 discloses that a high-quality GaAs film can be formed by irradiating Ga and As after irradiating a Si substrate first. In particular, a very good quality GaAs film is obtained on a Si (111) substrate, and if the desired N-type carrier can be generated by doping this film with impurities, it is considered that the above problem is solved.

International Publication No. 2009/035079

Journal of Crystal Growth 111 (1991) 284-287

  It is difficult to produce N-type carriers by doping impurities in a GaAs (111) film grown on a Si (111) substrate at an industrial level. For example, when Si is doped as an impurity, N-type carriers can be formed only under a considerably high As pressure. However, it is generally known that both P-type and N-type are generated (non-conversion). Patent Document 1). That is, in the prior art, a compound semiconductor layer containing GaAs having a desired N-type carrier concentration has not been obtained.

In order to put it to practical use as a magnetic sensor, it is essential to achieve excellent temperature stability. Specifically, the temperature change of the constant current sensitivity is required to be −0.1 [% / ° C.] or higher and −0.01 [% / ° C.] or lower in the range of 25 ° C. to 85 ° C. Further, considering constant current driving, the element resistance is required to be 3500Ω or less at a temperature of 25 ° C. (that is, room temperature) from the viewpoint of power consumption. For this purpose, an N-type carrier having a concentration of 1.0 × 10 ¹⁶ [/ cm ³ ] or more and 8.0 × 10 ¹⁷ [/ cm ³ ] or less at a temperature of 25 ° C. and having a resistivity of 0. Realization of a range of 001 [Ω · cm] to 0.1 [Ω · cm] is essential, but as described above, compound semiconductor layers containing GaAs cannot be stably doped with N-type at an industrial level. Is the current situation.

  Accordingly, the present invention has been made in view of such circumstances, and a compound semiconductor that can easily adjust the concentration and resistivity of N-type carriers to a desired range for a compound semiconductor layer on a Si substrate. It is an object of the present invention to provide a method for manufacturing a substrate, a magnetic sensor, and a compound semiconductor substrate.

In order to solve the above problems, a compound semiconductor substrate according to one embodiment of the present invention includes a Si substrate having a (111) plane orientation of the substrate surface, and a first compound semiconductor layer formed over the Si substrate. And a second compound semiconductor layer formed on the first compound semiconductor layer, and the first compound semiconductor layer is a GaAs _1-x Sb _x (0 ≦ x ≦ 0.1) layer. The second compound semiconductor layer is a GaAs _1-y Sb _y (0 <y ≦ 0.05) layer, and is formed by doping impurities in the second compound semiconductor layer and functions as an active layer. There is a doped region having an N-type carrier for the purpose.

In the compound semiconductor substrate, the concentration of the N-type carrier in the doped region is 1.0 × 10 ¹⁶ [cm ⁻³ ] or more and 8.0 × 10 ¹⁷ [cm ⁻³ ] or less at a temperature of 25 ° C. Yes, and
The resistivity of the doped region may be 0.001 [Ω · cm] or more and 0.1 [Ω · cm] or less at a temperature of 25 ° C.

In the compound semiconductor substrate, the impurity may be Si.
A magnetic sensor according to one aspect of the present invention includes the above-described compound semiconductor substrate and an electrode formed on the compound semiconductor substrate, and the second compound semiconductor layer of the compound semiconductor substrate is formed in a mesa pattern. The electrode is electrically connected to the mesa pattern.

In the above magnetic sensor, the temperature change of the constant current sensitivity is in the range of 25 ° C. to 85 ° C., and in the range of −0.1 [% / ° C.] to −0.01 [% / ° C.]. And the input resistance may be 3500Ω or less.
The method of manufacturing a compound semiconductor substrate according to one aspect of the present invention includes a step of forming a first compound semiconductor layer on a Si substrate having a (111) plane orientation of the substrate surface, and the first compound semiconductor layer Forming a second compound semiconductor layer thereon, wherein the first compound semiconductor layer is a GaAs _1-x Sb _x (0 ≦ x ≦ 0.1) layer, and the second compound semiconductor The layer is a GaAs _1-y Sb _y (0 <y ≦ 0.05) layer. In the step of forming the second compound semiconductor layer, impurities are doped into the second compound semiconductor layer during the film formation. A doped region having an N-type carrier for acting as an active layer is formed in the second compound semiconductor layer.

  According to one embodiment of the present invention, the concentration and resistivity of an N-type carrier can be easily adjusted within a desired range for a compound semiconductor layer on a Si substrate.

It is the top view and sectional drawing which show the structural example of the compound semiconductor substrate 10 which concerns on this embodiment. It is the top view and sectional drawing which show the structural example of the magnetic sensor 110 which concerns on this embodiment. It is the top view and sectional drawing which show the magnetic sensor 210 which concerns on the modification of this embodiment.

Hereinafter, a form (this embodiment) for carrying out the present invention will be described.
The compound semiconductor substrate of the present embodiment includes a Si (111) substrate whose substrate surface has a (111) plane, a first compound semiconductor layer formed on the Si (111) substrate, a first compound semiconductor layer, It is a compound semiconductor substrate provided with the 2nd compound semiconductor layer formed on the compound semiconductor layer. The first compound semiconductor layer is a GaAs _1-x Sb _x (0 ≦ x ≦ 0.1) layer. The second compound semiconductor layer is a GaAs _1-y Sb _y (0 <y ≦ 0.05) layer.

In the second compound semiconductor layer, there is a doped region that is formed by doping impurities and has N-type carriers to serve as an active layer. That is, in the second compound semiconductor layer, there is a doped region in which N-type carriers for acting as an active layer are formed by impurity doping. The concentration of the N-type carrier in the doped region is, for example, 1.0 × 10 ¹⁶ [cm ⁻³ ] or more and 8.0 × 10 ¹⁷ [cm ⁻³ ] when measured at a temperature of 25 ° C. (that is, room temperature). Within the following range. The resistivity of the doped region is in the range of 0.001 [Ω · cm] to 0.1 [Ω · cm] when measured at a temperature of 25 ° C.

In the compound semiconductor substrate of the present embodiment, the second compound semiconductor layer is a GaAs _1-y Sb _y (0 <y ≦ 0.05) layer, and N-type carriers for acting as an active layer are formed by impurity doping. A doped region is formed in the second compound semiconductor layer. Thereby, it is possible to form an N-type carrier of 1.0 × 10 ¹⁶ [cm ⁻³ ] or more and 8.0 × 10 ¹⁷ [cm ⁻³ ] or less sufficient to obtain a magnetic sensor in the doped region. become. Si, Sn, Se, Te, or the like can be used as an impurity to be doped to form an N-type carrier. From the viewpoint of ease of production, the impurity to be doped is preferably Si.

  In addition, the magnetic sensor of the present embodiment is realized by forming a mesa pattern and an electrode serving as a magnetic sensitive part on the compound semiconductor substrate of the present embodiment. By using the compound semiconductor substrate of the present embodiment described above, the temperature change of the constant current sensitivity is −0.1 [% / ° C.] or more and −0.01 [% / ° C. in a temperature range of 25 ° C. to 85 ° C. It is possible to realize a magnetic sensor within the following range and having a device resistance of 3500Ω or less at a temperature of 25 ° C.

Next, the compound semiconductor substrate and the magnetic sensor according to the present embodiment will be described in more detail with reference to the drawings. In each drawing referred to below, parts having the same configuration are denoted by the same reference numerals, and repeated description thereof is omitted.
(Compound semiconductor substrate)
1A and 1B are a plan view showing a configuration example of a compound semiconductor substrate 10 according to an embodiment of the present invention, and a cross-sectional view of the plan view taken along the line AA ′. As shown in FIGS. 1A and 1B, this compound semiconductor substrate 10 includes a Si substrate 100 whose surface orientation is the (111) plane, and a first compound formed on the Si substrate 100. A semiconductor layer 21 and a second compound semiconductor layer 22 formed on the first compound semiconductor layer 21 are provided. In the second compound semiconductor layer 21, there is a doped region 22b in which N-type carriers for acting as an active layer are formed by impurity doping. In this doped region 22b, an N-type carrier of 1.0 × 10 ¹⁶ [cm ⁻³ ] or more and 8.0 × 10 ¹⁷ [cm ⁻³ ] or less (temperature 25 ° C.) is formed, and resistivity (temperature) 25 ° C.) is 0.001 [Ω · cm] or more and 0.1 [Ω · cm] or less.

  The compound semiconductor substrate 10 is formed using various film forming methods. For example, a molecular beam epitaxy (MBE) method or a metal organic vapor phase epitaxy (MOVPE) method is a preferable method. The compound semiconductor substrate 10 is formed using these methods. Hereinafter, each layer shown in FIG. 1 will be described.

[Si (111) substrate]
The Si substrate 100 is not particularly limited as long as the surface orientation of the substrate surface is the (111) plane. A single crystal substrate of Si is preferably used. The single crystal substrate may be a semi-insulating substrate, or may be a conductive substrate doped N-type or P-type with donor impurities or acceptor impurities. In the case of the N type, it is preferable that the resistivity is higher for forming the magnetic sensor.

Here, “the surface orientation of the substrate surface is the (111) plane” is not only the case where the surface orientation of the substrate surface is exactly the same as the (111) plane, but the surface orientation of the substrate surface is relative to the (111) plane Including the case of tilting within a range of 5 ° or less.
Before forming the first compound semiconductor layer 21 on the Si substrate 100, the surface of the Si substrate 100 may be heated in vacuum to remove the oxide film, or contaminants such as organic substances and metals are removed. Then, the hydrogen termination treatment may be performed by removing the oxide film on the surface using a hydrogen fluoride aqueous solution having a concentration of 1.0 wt%.

[First compound semiconductor layer]
In the present embodiment, the first compound semiconductor layer 21 is a GaAs _1-x Sb _x (0 ≦ x ≦ 1) layer. The first compound semiconductor layer 21 serves as an underlayer for forming the second compound semiconductor layer 22 having good crystallinity and excellent surface flatness. As a matter of course, it is preferable that the first compound semiconductor layer 21 itself as the underlayer also has good crystallinity and excellent surface flatness.

When the first compound semiconductor layer 21 is formed at a high temperature, the unevenness of the surface becomes severe and sufficient flatness cannot be ensured. Therefore, the first compound semiconductor layer 21 is often formed at a relatively low temperature. The temperature during formation is preferably 150 ° C. or more from the viewpoint of crystallinity. Moreover, it is preferable that the temperature at the time of formation is 350 degrees or less from a viewpoint of ensuring flatness.
When the first compound semiconductor layer 21 is formed at a low temperature, the surface flatness is sufficient, but the crystallinity may not always be good. However, if the temperature of the first compound semiconductor layer 21 is raised and maintained after the formation of the first compound semiconductor layer 21, both the crystallinity and the surface flatness can be improved by the annealing effect. For example, after the first compound semiconductor layer 21 is formed at a low temperature, the temperature is raised and maintained so that the annealing effect is exhibited, and then the second compound semiconductor layer 22 is formed on the first compound semiconductor layer 21 at a high temperature. Are often formed.

The film thickness of the first compound semiconductor layer 21 is preferably 5 nm or more from the viewpoint of ensuring crystallinity and covering properties. The film thickness of the first compound semiconductor layer 21 is preferably 50 nm or less from the viewpoint of the improvement effect due to the crystallinity and the annealing effect.
The Sb composition x of the first compound semiconductor layer 21 is preferably 0 or more and 0.1 or less from the viewpoint of crystallinity. In particular, when x = 0, that is, when the first compound semiconductor layer 21 is GaAs, the crystallinity is very good.

  In addition, after removing contaminants such as organic substances and metals, a hydrogen termination process is performed by removing the oxide film on the surface using a hydrogen fluoride aqueous solution having a concentration of 1.0 wt%. Then, As is irradiated on the Si substrate 100 in advance. In this manner, when a substance having an As concentration higher than that of the first compound semiconductor layer 21 is present in an island shape between the first compound semiconductor layer 21 formed after the prior irradiation of As and the Si substrate 100, The first compound semiconductor layer 21 is preferable because of good crystallinity and excellent surface flatness.

[Second Compound Semiconductor Layer]
In the present embodiment, the second compound semiconductor layer 22 is a GaAs _1-y Sb _y (0 <y ≦ 0.05) layer. The second compound semiconductor layer 22 includes a doped region 22b in which N-type carriers for acting as an active layer are formed by impurity doping. By irradiating the Sb and impurities at the same time as GaAs film, conventionally which was difficult impurity doped into GaAs (111) layer becomes ^{possible, 1.0 × 10 16 [cm -3} ] or more, 8.0 × It has an N-type carrier of 10 ¹⁷ [cm ⁻³ ] or less (temperature 25 ° C.) and has a resistivity (temperature 25 ° C.) of 0.001 [Ω · cm] or more and 0.1 [Ω · cm] or less. A certain doped region 22b can be formed. As described above, Si, Sn, Se, Te or the like can be used as the impurity to be doped, and Si and Sn are preferable from the viewpoint of manufacturability. From the viewpoint of more excellent manufacturability, Si is preferable, and Sn is preferable when a highly doped N-type carrier is required.

In the step of forming a second compound semiconductor layer 22, for illuminating the Sb during GaAs film, although _{GaAs 1-y} Sb _y is formed as the second compound semiconductor layer 22, the composition y at that time From the viewpoint of crystallinity, it is preferably 0.05 or less, more preferably 0.03 or less. In order to realize temperature stability of the magnetic sensor and the same degree of GaAs (100) which is Si-doped, it is preferably a band gap of the same order as GaAs, mixed of _{GaAs 1-y} Sb y in order that The smaller the crystal composition ratio y, the better. On the other hand, in order to dope impurities such as Si to the GaAs (111) film, simultaneous irradiation with Sb is essential, and as a result, the Sb composition y becomes a value larger than 0, and stable N-type doping is performed during growth. Therefore, as a result, the Sb composition is preferably 0.001 or more.

The temperature at the time of forming the second compound semiconductor layer 22 is preferably 550 ° C. or higher from the viewpoint of crystallinity and surface flatness. The temperature at the time of forming the second compound semiconductor layer 22 is 700 degrees or less from the viewpoint of preventing re-evaporation of the group V elements As and Sb and ensuring crystallinity and surface flatness. preferable.
The formation rate of the second compound semiconductor layer 22 is preferably 1.5 μm / h or less, more preferably 0.3 μm / h or less from the viewpoint of ensuring crystallinity. The formation rate of the second compound semiconductor layer 22 is preferably 0.05 μm / h or more, and more preferably 0.1 μm / h or more from the viewpoint of formation time. The formation rate of the second compound semiconductor layer 22 can be appropriately determined according to desired crystallinity and formation time.

The second compound semiconductor layer 22 is not particularly limited as long as the above-described doped region 22b is formed. For example, all of the second compound semiconductor layer 22 (that is, the entire region from the lower surface to the upper surface of the second compound semiconductor layer 22) may be the doped region 22b. In addition to the doped region 22b, a buffer region 22a and / or a cap region 22c may be provided as shown in FIG. When the buffer region 22a and the cap region 22c are provided, the regions are preferably formed in the order of the buffer region 22a, the doped region 22b, and the cap region 22c from the side close to the first compound semiconductor layer 21. The buffer region 22a and the cap region 22c are preferably non-doped regions. That is, it becomes a region of non-doped GaAs _1-y Sb _y (0 <y ≦ 0.05).

  The buffer region 22a functions as a buffer between the first compound semiconductor layer 21 and the doped region 22b. In order to shorten the film formation time and increase the production efficiency, the buffer region 22a is not necessarily an essential condition. The thickness of the buffer region 22a is normally 0 μm or more and 0.3 μm or less, but is not limited thereto. From the viewpoint of ensuring crystallinity, 0.05 μm or more is preferable, and 0.1 μm or more is more preferable.

  The cap region 22c is formed to prevent damage in the element formation process, and the film thickness is preferably 0.15 μm or more, and more preferably 0.20 μm or more. The doped region 22b is preferably 0.05 μm or more and more preferably 0.2 μm or more from the viewpoint of ensuring sufficient crystallinity. Moreover, it is preferable that the film thickness as the whole 2nd compound semiconductor layer 22 is 5 micrometers or less from a viewpoint of formation time.

  The compound semiconductor substrate 10 according to this embodiment may include other layers in addition to the first compound semiconductor layer 21 and the second compound semiconductor layer 22. For example, a buffer layer (not shown) may be provided between the first compound semiconductor layer 21 and the second compound semiconductor layer 21. Further, a cap layer (for example, a third compound semiconductor layer 30 described later) for preventing damage in the element formation process may be provided on the second compound semiconductor layer 22. As the buffer layer and the cap layer, a layer made of GaAs or GaAsSb can be employed. When the entire region of the second compound semiconductor layer 22 is the doped region 22b, it is preferable to include the above-described buffer layer and / or cap layer (not shown).

(Magnetic sensor)
2A and 2B are a plan view illustrating a configuration example of the magnetic sensor according to the present embodiment, and a cross-sectional view of the plan view taken along the line BB ′. This magnetic sensor 110 is obtained by processing the compound semiconductor substrate 10 shown in FIGS. 1 (a) and 1 (b).

  That is, as shown in FIGS. 2A and 2B, the magnetic sensor 110 includes the above-described compound semiconductor substrate 10 and the third compound formed on the second compound semiconductor layer 22 of the compound semiconductor substrate 10. A semiconductor layer 30, an ohmic electrode 40 formed on the compound semiconductor substrate 10 and ohmically connected to the second compound semiconductor layer 22, and an Si substrate 100 and a first compound semiconductor layer 21 formed on the compound semiconductor substrate 10. And a passivation layer 50 covering each of the second compound semiconductor layer 22 and the third compound semiconductor layer 30 exposed to the outside.

  The third compound semiconductor layer 30 is made of GaAs having a lower conductivity than the second compound semiconductor layer 22. The third compound semiconductor layer 30 is formed by, for example, the MBE method or the MOCVD method. As a method for obtaining GaAs having a conductivity lower than that of the second compound semiconductor layer 22, a method of doping impurities at a lower concentration than the second compound semiconductor layer 22, or a method of intentionally not doping impurities (that is, Non-doped).

The material constituting the ohmic electrode 40 is not particularly limited, but an electrode structure in which AuGe, Ni, and Au are sequentially deposited in this order can be cited from the viewpoint of obtaining good ohmic connection. The ohmic electrode 40 may be in direct contact with the second compound semiconductor layer 22, or may be connected to the second compound semiconductor layer 22 via the third compound semiconductor layer 30.
As the magnetic sensor 110, by using the compound semiconductor substrate 10 according to the present embodiment, a mesa pattern, that is, a magnetic sensitive part by dry or wet processing, and an ohmic electrode 40 that is in ohmic connection with the magnetic sensitive part are formed. It is possible to operate as a Hall element which is one form of a magnetic sensor. In FIG. 2A, the second compound semiconductor layer 22 in a region intersecting in a cross shape functions as a magnetic sensitive portion and operates as a Hall element.

From the viewpoint of reliability, it is desirable to form a passivation layer 50 made of SiN or SiO ₂ as a protective film on the mesa pattern, but the passivation layer 50 is not essential in this embodiment.
In the plan view shown in FIG. 2A, the outline of the passivation layer 50 formed on the mesa pattern is indicated by a broken line in order to make the shape of the mesa pattern and the ohmic electrode 40 easy to understand. The passivation layer 50 formed in FIG.

(Effect of this embodiment)
According to the present embodiment, the concentration and resistivity of the N-type carrier can be easily adjusted within a desired range for the compound semiconductor layer on the Si substrate 100 whose plane orientation is the (111) plane. For example, the crystallinity is good and the concentration is 1.0 × 10 ¹⁶ [/ cm ³ ] or more and 8.0 × 10 ¹⁷ [/ cm ³ ] or less (when measured at a temperature of 25 ° C.) sufficient for magnetic sensor formation. Second compound semiconductor layer (GaAsSb) which has an N-type carrier and can realize a range of resistivity 0.001 [Ω · cm] or more and 0.1 [Ω · cm] or less (when measured at a temperature of 25 ° C.). Layer) 22 can be easily formed on the Si substrate 100.

  When a magnetic sensor is formed using the compound semiconductor substrate 10 including the second compound semiconductor layer 22 as described above, it is possible to industrially produce a magnetic sensor 110 having temperature stability equivalent to that of a magnetic sensor using GaAs. is there. Further, since the magnetic sensor 110 is formed on the Si substrate 100, it is easy to reduce the thickness. That is, it is possible to industrially realize a thin magnetic sensor with excellent temperature stability.

(Modification)
3A and 3B are a plan view showing a magnetic sensor 210 according to a modification of the present embodiment, and a cross-sectional view of the plan view cut along the line CC ′.
The magnetic sensor 210 is different from the magnetic sensor 110 shown in FIGS. 2A and 2B in that the ohmic electrode 40 includes a first electrode layer 41 and a second electrode layer 42. Different.

That is, as shown in FIGS. 3A and 3B, the ohmic electrode 40 is formed on the first electrode layer 41 and the first electrode layer 41 that is in ohmic contact with the second compound semiconductor layer 22. The second electrode layer 42 is provided. Even in such a configuration, the magnetic sensor 210 operates in the same manner as the magnetic sensor 110 described above, and has the same effect.
In addition, the magnetic sensor 210 is configured such that when the ohmic electrode 40 and another member are electrically connected by a conductive thin wire (wire), a solder ball, or the like, the second electrode layer 42 is made of an appropriate material or a laminated structure. It may be preferable to do so. That is, if the second electrode layer 42 is selected to have good connectivity with conductive thin wires (wires) or solder balls, it is suitable for connecting the magnetic sensor 210 to other members. .

In the plan view shown in FIG. 3A, the outline of the passivation layer 50 formed on the mesa pattern is indicated by a broken line in order to make the shape of the mesa pattern and the ohmic electrode 40 easy to understand. The passivation layer 50 formed in FIG.
Hereinafter, the compound semiconductor substrate and the magnetic sensor according to this embodiment will be described in more detail based on examples.

Example 1
First, after removing contaminants such as organic substances and metals on a Si substrate whose surface orientation is (111) plane, that is, Si (111) substrate, an aqueous hydrogen fluoride solution having a concentration of 1.0 wt% The surface oxide film was removed using, and hydrogen termination treatment was performed. The Si (111) substrate subjected to the hydrogen treatment termination is immediately introduced into the MBE apparatus, and the substrate temperature becomes 300 ° C. in a vacuum of 1 × 10 ⁻⁶ Torr (1.333 × 10 ⁻⁴ Pa) or less. As the temperature became constant, the substrate surface was irradiated with As.

Subsequently, the substrate surface is simultaneously irradiated with Ga having a molecular beam intensity of 7 × 10 ⁻⁸ Torr and As ₂ molecules generated by cracking, ie heating, As ₄ molecules having a molecular beam intensity of 3 × 10 ⁻⁵ Torr. Thus, a GaAs layer, which is a first compound semiconductor layer having a thickness of 20 nm, was formed at a formation rate of 0.1 μm per hour.
Thereafter, the Si (111) substrate on which the GaAs layer is formed is heated until the substrate temperature reaches 660 ° C. When the temperature becomes constant, Ga having a molecular beam intensity of 7 × 10 ⁻⁷ Torr and molecular beam The substrate surface was simultaneously irradiated with As ₂ molecules generated by cracking or heating As ₄ molecules having an intensity of 3 × 10 ⁻⁵ Torr and Sb having a molecular beam intensity of 1.66 × 10 ⁻⁶ Torr. As a result, a GaAsSb layer, which is a second compound semiconductor layer having a thickness of 600 nm, was formed on the GaAs layer, which is the first compound semiconductor layer, at a formation rate of 1 μm per hour. At this time, the converted Sb / Ga molecular beam intensity ratio is 2.37. The converted Sb / Ga molecular beam intensity ratio is the ratio of the molecular beam intensity of the Sb material to the molecular beam intensity of the Ga material necessary for the formation rate of the GaAsSb layer to be 1 μm per hour.

In the second compound semiconductor layer, when viewed from the interface with the first compound semiconductor layer, the region has a thickness of 200 nm to 400 nm (that is, 200 nm or more and 400 nm or less from the interface along the thickness direction). The region was irradiated with Si at a Si cell temperature of 1180 ° C. to form a Si-doped GaAsSb region.
When the X-ray diffraction peak corresponding to the (111) plane of the second compound semiconductor layer was analyzed, the Sb composition y was 0.033. Further, when evaluated at a measurement temperature of 25 ° C. using a Hall effect measurement system “HL5500PC” manufactured by Accent Co., it was found that the conductivity type was N type, the sheet resistance was 1300Ω / □, and the mobility was 500 [cm ^2. / V · s], and the sheet carrier concentration was 9.7 × 10 ¹² [cm ⁻² ]. Since the thickness of the portion doped with Si to form a conductive layer is 200 nm as described above, the carrier concentration is 4.9 × 10 ¹⁷ [cm ⁻³ ] and the resistivity is 0.026 [Ω · cm].

  When a magnetic sensor is manufactured using the compound semiconductor substrate formed in this way, the characteristic average value of the elements in the wafer surface is 1700Ω input resistance, constant voltage sensitivity 4.8 mV (6 V, 20 mT applied), constant current sensitivity. An element of 1.3 mV (1 mA, 20 mT applied) is obtained. The change in temperature of the constant current sensitivity from 25 ° C. to 85 ° C. is −0.03 [% / ° C.], which is desirable for practical use as a magnetic sensor, −0.1 [% / ° C.] The temperature change is in the range of 0.01 [% / ° C.] or less, and the element resistance at a temperature of 25 ° C. is also 3500Ω or less.

The manufacturing method of the magnetic sensor is as follows (1)-(10).
(1) A compound semiconductor substrate on which a third compound semiconductor layer is stacked is prepared. Next, a resist pattern for forming a mesa pattern as shown in FIGS. 3A and 3B was formed on the third compound semiconductor layer by photolithography.
(2) Next, the third compound semiconductor layer, the second compound semiconductor layer, and the first compound semiconductor layer are sequentially etched using the resist pattern as a mask, so that a cross-shaped mesa pattern (on the other hand) The rectangular region has a width of 70 μm and a length of 100 μm, and the other rectangular region has a width of 30 μm and a length of 110 μm.
(3) Next, a resist pattern for forming an ohmic electrode electrically connected to each end of the cross-shaped mesa pattern was formed.
(4) Next, 200 nm of AuGe, 50 nm of Ni, and 350 nm of Au were deposited in this order.

(5) Next, the 1st electrode layer which comprises an ohmic electrode was formed by the lift-off method. Thereafter, an ohmic junction between the first electrode layer and the second compound semiconductor layer was formed by alloying the first electrode layer and the second compound semiconductor layer.
(6) Next, a SiN layer was formed at 280 nm using a plasma CVD apparatus.
(7) Next, a resist pattern for forming a passivation layer was formed. Then, using this resist pattern as a mask, the SiN layer was etched to form a passivation layer having an opening on the first electrode layer.
(8) Next, a resist pattern for forming the second electrode layer was formed.
(9) Next, Ti was deposited to 100 nm and Au was deposited to 350 nm in this order.
(10) Next, a second electrode layer was formed by a lift-off method. As a result, a magnetic sensor operating as a Hall element was obtained.

(Example 2)
In Example 2, the Si cell temperature when irradiating the second compound semiconductor layer with Si was set to a temperature (1200 ° C.) higher than that of Example 1. Details are as follows. In Example 2, the process up to the step of forming the first compound semiconductor layer is the same as that in Example 1.
After the step of forming the first compound semiconductor layer, the Si (111) substrate on which the GaAs layer is formed is heated until the substrate temperature reaches 660 ° C. When the temperature becomes constant, the molecular beam intensity is 7 × 10 ⁻⁷ Torr Ga, As ₂ molecules generated by cracking or heating As ₄ molecules with molecular beam intensity 3 × 10 ⁻⁵ Torr, and molecular beam intensity 1.66 × 10 ⁻⁶ Torr The substrate surface was simultaneously irradiated with Sb. As a result, a GaAsSb layer, which is a second compound semiconductor layer having a thickness of 600 nm, was formed on the GaAs layer, which is the first compound semiconductor layer, at a formation rate of 1 μm per hour. At this time, the converted Sb / Ga molecular beam intensity ratio is 2.37.

Further, in the second compound semiconductor layer, a region having a film thickness of 200 nm to 400 nm as viewed from the interface with the first compound semiconductor layer is irradiated with Si at a Si cell temperature of 1200 degrees, so that a Si-doped GaAsSb region is obtained. Formed.
When the X-ray diffraction peak corresponding to the (111) plane of the second compound semiconductor layer was analyzed, the Sb composition y was 0.033. Further, when evaluated at a measurement temperature of 25 ° C. using a Hall effect measurement system “HL5500PC” manufactured by Accent Co., it was found that the conductivity type was N type, the sheet resistance was 800Ω / □, and the mobility was 670 [cm ^2]. / V · s], and the sheet carrier concentration was 1.2 × 10 ¹² [cm ⁻² ]. Since the thickness of the portion doped with Si to form the conductive layer is 200 nm as described above, the carrier concentration is 5.9 × 10 ¹⁷ [cm ⁻³ ] and the resistivity is 0.016 [Ω · cm].

(Example 3)
In Example 3, the thickness of the buffer region in the second compound semiconductor layer was 50 nm, which was 150 nm thinner than Example 1. Details are as follows. In Example 3, the process up to the step of forming the first compound semiconductor layer is the same as in Example 1.
After the step of forming the first compound semiconductor layer, the Si (111) substrate on which the GaAs layer is formed is heated until the substrate temperature reaches 660 ° C. When the temperature becomes constant, the molecular beam intensity is 7 × 10 ⁻⁷ Torr Ga, As ₂ molecules generated by cracking or heating As ₄ molecules with molecular beam intensity 3 × 10 ⁻⁵ Torr, and molecular beam intensity 1.66 × 10 ⁻⁶ Torr The substrate surface was simultaneously irradiated with Sb. Thus, a GaAsSb layer as a second compound semiconductor layer having a thickness of 450 nm was formed on the GaAs layer as the first compound semiconductor layer at a formation rate of 1 μm per hour. At this time, the converted Sb / Ga molecular beam intensity ratio is 2.37.

Further, in the second compound semiconductor layer, a region having a film thickness of 50 nm to 250 nm as viewed from the interface with the first compound semiconductor layer is irradiated with Si at a Si cell temperature of 1180 degrees, so that a Si-doped GaAsSb region is obtained. Formed. That is, the thickness of the buffer region located under the Si-doped GaAsSb region was 50 nm.
When the X-ray diffraction peak corresponding to the (111) plane of the second compound semiconductor layer was analyzed, the Sb composition y was 0.033. Further, when evaluated at a measurement temperature of 25 ° C. using a Hall effect measurement system “HL5500PC” manufactured by Accent Co., it was found that the conductivity type was N type, the sheet resistance was 1500Ω / □, and the mobility was 450 [cm ^2. / V · s], and the sheet carrier concentration was 9.3 × 10 ¹² [cm ⁻² ]. Since the thickness of the portion doped with Si to form the conductive layer is 200 nm as described above, the carrier concentration is 4.6 × 10 ¹⁷ [cm ⁻³ ] and the resistivity is 0.030 [Ω · cm].

Example 4
In Example 4, the converted Sb / Ga molecular beam intensity ratio was made larger than that in Example 1 to form a second compound semiconductor layer having a large Sb composition y. Details are as follows. In Example 4, the process up to the step of forming the first compound semiconductor layer is the same as Example 1.
After the step of forming the first compound semiconductor layer, the Si (111) substrate on which the GaAs layer is formed is heated until the substrate temperature reaches 660 ° C. When the temperature becomes constant, the molecular beam intensity is 7 × 10 ⁻⁷ Torr of Ga, As ₂ molecules generated by cracking or heating As ₄ molecules of molecular beam intensity of 3 × 10 ⁻⁵ Torr, and molecular beam intensity of 2.8 × 10 ⁻⁶ Torr The substrate surface was simultaneously irradiated with Sb. As a result, a GaAsSb layer, which is a second compound semiconductor layer having a thickness of 600 nm, was formed on the GaAs layer, which is the first compound semiconductor layer, at a formation rate of 1 μm per hour. At this time, the converted Sb / Ga molecular beam intensity ratio is 4. In addition, in the second compound semiconductor layer, a region having a film thickness of 200 nm to 400 nm as viewed from the interface with the first compound semiconductor layer is irradiated with Si at a Si cell temperature of 1180 degrees, so that a Si-doped GaAsSb region is obtained. Formed.

When the X-ray diffraction peak corresponding to the (111) plane of the second compound semiconductor layer was analyzed, the Sb composition y was 0.05. Further, when evaluated at a measurement temperature of 25 ° C. using a Hall effect measurement system “HL5500PC” manufactured by Accent Co., it was found that the conductivity type was N type, the sheet resistance was 1200Ω / □, and the mobility was 550 [cm ^2. / V · s], and the sheet carrier concentration was 9.5 × 10 ¹² [cm ⁻² ]. Since the thickness of the portion doped with Si to form the conductive layer is 200 nm as described above, the carrier concentration is 4.7 × 10 ¹⁷ [cm ⁻³ ] and the resistivity is 0.024 [Ω · cm].

(Example 5)
In Example 5, the converted Sb / Ga molecular beam intensity ratio was made larger than that in Example 1, and a second compound semiconductor layer having a large Sb composition y was formed. In addition, the impurity doping of the second compound semiconductor layer was performed with Sn instead of Si. Details are as follows. In Example 5, the process up to the step of forming the first compound semiconductor layer is the same as Example 1.

After the step of forming the first compound semiconductor layer, the Si (111) substrate on which the GaAs layer is formed is heated until the substrate temperature reaches 660 ° C. When the temperature becomes constant, the molecular beam intensity is 7 × 10 ⁻⁷ Torr of Ga, As ₂ molecules generated by cracking or heating As ₄ molecules of molecular beam intensity of 3 × 10 ⁻⁵ Torr, and molecular beam intensity of 2.8 × 10 ⁻⁶ Torr The substrate surface was simultaneously irradiated with Sb. Thus, a GaAsSb layer as a second compound semiconductor layer having a thickness of 500 nm was formed on the GaAs layer as the first compound semiconductor layer at a formation rate of 1 μm per hour. At this time, the converted Sb / Ga molecular beam intensity ratio is 4. In addition, an Sn-doped GaAsSb region was formed by irradiating Sn at an Sn cell temperature of 900 degrees in all regions of the second compound semiconductor layer.

When the X-ray diffraction peak corresponding to the (111) plane of the second compound semiconductor layer was analyzed, the Sb composition y was 0.05. Further, when evaluated at a measurement temperature of 25 ° C. using a Hall effect measurement system “HL5500PC” manufactured by Accent Co., it was found that the conductivity type was N type, the sheet resistance was 80Ω / □, and the mobility was 1300 [cm ^2]. / V · s], and the sheet carrier concentration was 6.1 × 10 ¹³ [cm ⁻² ]. Since the thickness of the portion doped with Sn to form the conductive layer is 500 nm as described above, the carrier concentration is 1.2 × 10 ¹⁸ [cm ⁻³ ], and the resistivity is 0.004 [Ω · cm].

(Comparative Example 1)
In Comparative Example 1, not the GaAsSb layer but the GaAs layer was formed as the second compound semiconductor layer. That is, Sb irradiation was not performed when forming the second compound semiconductor layer. Details are as follows. In Comparative Example 1, the process up to the step of forming the first compound semiconductor layer is the same as that of Example 1.

After the step of forming the first compound semiconductor layer, the Si (111) substrate on which the GaAs layer is formed is heated until the substrate temperature reaches 660 ° C. When the temperature becomes constant, the molecular beam intensity is 7 × 10 ⁻⁷ Torr Ga and As ₂ molecules generated by cracking, ie heating, As ₄ molecules having a molecular beam intensity of 3 × 10 ⁻⁵ Torr were simultaneously irradiated. As a result, a GaAs layer as a second compound semiconductor layer having a thickness of 600 nm was formed on the GaAs layer as the first compound semiconductor layer at a formation rate of 1 μm per hour. At this time, the converted Sb / Ga molecular beam intensity ratio is 0 because Sb is not irradiated. Further, in the second compound semiconductor layer, as viewed from the interface with the first compound semiconductor layer, a region having a thickness of 200 nm to 400 nm is irradiated with Si at a cell temperature of 1180 ° C. to form a Si-doped GaAs region. did.

When the X-ray diffraction peak corresponding to the (111) plane of the second compound semiconductor layer was analyzed, the Sb composition y was 0 because Sb was not irradiated. Further, when evaluated at a measurement temperature of 25 ° C. using a Hall effect measurement system “HL5500PC” manufactured by Accent Co., it was found that the conduction type was P type, the sheet resistance was 18000Ω / □, and the mobility was 20 [cm ^2. / V · s], and the sheet carrier concentration was 1.7 × 10 ¹³ [cm ⁻² ]. Since the thickness of the conductive layer formed by doping Si is 200 nm as described above, the carrier concentration is 8.7 × 10 ¹⁷ [cm ⁻³ ] and the resistivity is 0.360 [Ω · cm].
The sheet resistance of Comparative Example 1 is higher by one digit or more than that of Example 1. Since the conductivity of the second compound semiconductor layer is P-type, N-type conversion by Si doping is difficult when there is no Sb irradiation.

(Comparative Example 2)
In Comparative Example 2, a GaAs layer was formed as the second compound semiconductor layer instead of the GaAsSb layer. That is, Sb irradiation was not performed when forming the second compound semiconductor layer.
Impurity doping was performed with Sn in all regions of the second compound semiconductor layer. Details are as follows. In Comparative Example 2, the process up to the step of forming the first compound semiconductor layer is the same as that of Example 1.

After the step of forming the first compound semiconductor layer, the Si (111) substrate on which the GaAs layer is formed is heated until the substrate temperature reaches 660 ° C. When the temperature becomes constant, the molecular beam intensity is 7 × 10 ⁻⁷ Torr Ga and As ₂ molecules generated by cracking, ie heating, As ₄ molecules having a molecular beam intensity of 3 × 10 ⁻⁵ Torr were simultaneously irradiated. Thus, a GaAs layer as a second compound semiconductor layer having a thickness of 500 nm was formed on the GaAs layer as the first compound semiconductor layer at a formation rate of 1 μm per hour. At this time, the converted Sb / Ga molecular beam intensity ratio is 0 because Sb is not irradiated. In addition, the Sn-doped GaAs region was formed in all regions of the second compound semiconductor layer by irradiating Sn at an Sn cell temperature of 900 degrees.

When the X-ray diffraction peak corresponding to the (111) plane of the second compound semiconductor layer was analyzed, the Sb composition y was 0 because Sb was not irradiated. In addition, when the evaluation was made at a measurement temperature of 25 ° C. using a Hall effect measurement system “HL5500PC” manufactured by Accent Co., it was found that the conduction type was N type, but the sheet resistance was 9200Ω / □, and the mobility was 50 [ cm ² / V · s], and the sheet carrier concentration was 1.3 × 10 ¹³ [cm ⁻² ]. Since the thickness of the portion doped with Sn to form the conductive layer is 500 nm as described above, the carrier concentration is 2.5 × 10 ¹⁷ [cm ⁻³ ] and the resistivity is 0.462 [Ω · cm].

  The sheet resistance of Comparative Example 2 is a value two digits or more higher than that of Example 5, and the carrier concentration is the same Sn irradiation amount (same dose amount, same Sn cell temperature), About an order of magnitude lower. This indicates that it is difficult to dope the N-type site stably without Sb irradiation during impurity doping.

DESCRIPTION OF SYMBOLS 10 Compound semiconductor substrate 100 Si substrate 21 1st compound semiconductor layer 22 2nd compound semiconductor layer 30 3rd compound semiconductor layer 40 Ohmic electrode 41 1st electrode layer 42 2nd electrode layer 50 Passivation layers 110 and 210 Magnetic sensor

Claims (6)

A Si substrate whose surface orientation is (111) plane;
A first compound semiconductor layer formed on the Si substrate;
A second compound semiconductor layer formed on the first compound semiconductor layer,
The first compound semiconductor layer is a GaAs _1-x Sb _x (0 ≦ x ≦ 0.1) layer,
Said second compound semiconductor layer is _{GaAs 1-y Sb y (0} <y ≦ 0.05) layer,
A compound semiconductor substrate comprising a doped region formed by doping impurities and having an N-type carrier for acting as an active layer in the second compound semiconductor layer. The concentration of the N-type carrier in the doped region is 1.0 × 10 ¹⁶ [cm ⁻³ ] or more and 8.0 × 10 ¹⁷ [cm ⁻³ ] or less at 25 ° C., and
2. The compound semiconductor substrate according to claim 1, wherein the resistivity of the doped region is 0.001 [Ω · cm] or more and 0.1 [Ω · cm] or less at 25 ° C. 3.   The compound semiconductor substrate according to claim 1, wherein the impurity is Si or Sn. The compound semiconductor substrate according to any one of claims 1 to 3,
An electrode formed on the compound semiconductor substrate,
The second compound semiconductor layer of the compound semiconductor substrate is formed in a mesa pattern;
The magnetic sensor, wherein the electrode is electrically connected to the mesa pattern.   The temperature change of the constant current sensitivity is 25 ° C or more and 85 ° C or less, -0.1 [% / ° C] or more and -0.01 [% / ° C] or less, and the input resistance is 3500Ω or less. The magnetic sensor according to claim 4, wherein Forming a first compound semiconductor layer on a Si substrate having a (111) plane orientation of the substrate surface;
Forming a second compound semiconductor layer on the first compound semiconductor layer,
The first compound semiconductor layer is a GaAs _1-x Sb _x (0 ≦ x ≦ 0.1) layer,
Said second compound semiconductor layer is _{GaAs 1-y Sb y (0} <y ≦ 0.05) layer,
In the step of forming the second compound semiconductor layer, the second compound semiconductor layer is doped with impurities during film formation, and a doped region having an N-type carrier for acting as an active layer is formed in the second compound semiconductor layer. A method for producing a compound semiconductor substrate, comprising: forming in a semiconductor layer.

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