JP2016092037A - Semiconductor laminate, light receiving element and sensor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor laminate, a light receiving element and a sensor, which are capable of improving sensitivity.SOLUTION: A semiconductor laminate 10 comprises: base layers 20, 30 each composed of a group III-V compound semiconductor and has n-type conductivity; a quantum well structure 40 composed of a group III-V compound semiconductor; a diffusion block layer 60 which is composed of a group III-V compound semiconductor and has a thickness of 50 nm and over and a p-type impurity concentration equal to or lower than 1×10cm; and a contact layer 50 which is composed of a group III-V compound semiconductor and has p-type conductivity. The base layers 20, 30, the quantum we structure 40, the diffusion block layer 60 and the contact layer 50 are arranged by lamination of this order.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor laminate, a light receiving element, and a sensor.

  A semiconductor stacked body including a structure in which a semiconductor layer made of a group III-V compound semiconductor is formed on a substrate made of a group III-V compound semiconductor is used for manufacturing a light receiving element corresponding to light in the near infrared region, for example. it can. Specifically, for example, a buffer layer, a light receiving layer, and a contact layer made of a group III-V compound semiconductor are sequentially laminated on a substrate made of a group III-V compound semiconductor, and further, an appropriate electrode is formed. The light receiving element can be obtained. Regarding such a light receiving element, there is a report on a photodiode having a cutoff wavelength of 2 μm or more (for example, see Non-Patent Document 1).

R. Sidhu, et al. "A Long-Wavelength Photodiode on InP Using Lattice-Matched GaInAs-GaAsSb Type-II Quantum Wells", IEEE PHOTOTONICS TECHNOLOGY LETTERS, VOL. 17, NO. 12, DECEMBER 2005, p. 2715-2717

  In the light receiving element, further improvement in sensitivity is required. Therefore, an object is to provide a semiconductor laminate, a light receiving element, and a sensor that can improve sensitivity.

A semiconductor laminate according to the present invention is made of a III-V compound semiconductor, a base layer having an n-type conductivity, a quantum well structure made of a III-V compound semiconductor, and a III-V compound semiconductor. A diffusion block layer having a thickness of 50 nm or more and a p-type impurity concentration of 1 × 10 ¹⁶ cm ⁻³ or less, and a contact layer made of a III-V compound semiconductor and having a p-type conductivity. Prepare. The base layer, quantum well structure, diffusion block layer, and contact layer are stacked in this order.

  A light receiving element according to the present invention includes the above-described semiconductor stacked body and an electrode formed on the semiconductor stacked body.

  A sensor according to the present invention includes the light receiving element and a readout circuit connected to the light receiving element.

  According to the semiconductor laminate, the light receiving element, and the sensor, an improvement in sensitivity can be achieved.

3 is a schematic cross-sectional view showing the structure of the semiconductor stacked body in the first embodiment. FIG. 3 is a schematic cross-sectional view showing the structure of the light receiving element in the first embodiment. FIG. 3 is a flowchart showing an outline of a method for manufacturing a semiconductor stacked body and a light receiving element in the first embodiment. 5 is a schematic cross-sectional view for illustrating the method for manufacturing the semiconductor stacked body and the light receiving element in the first embodiment. FIG. 5 is a schematic cross-sectional view for illustrating the method for manufacturing the semiconductor stacked body and the light receiving element in the first embodiment. FIG. 5 is a schematic cross-sectional view for illustrating the method for manufacturing the semiconductor stacked body and the light receiving element in the first embodiment. FIG. 5 is a schematic cross-sectional view for illustrating the method for manufacturing the semiconductor stacked body and the light receiving element in the first embodiment. FIG. FIG. 6 is a schematic cross-sectional view showing a structure of a semiconductor stacked body in a second embodiment. FIG. 6 is a schematic cross-sectional view showing a structure of a light receiving element in a second embodiment. 6 is a schematic cross-sectional view showing a structure of a semiconductor stacked body in a third embodiment. FIG. 6 is a schematic cross-sectional view showing a structure of a light receiving element in Embodiment 3. FIG. 6 is a schematic cross-sectional view showing structures of a light receiving element and a sensor in a fourth embodiment. It is a figure which shows the relationship between the film thickness of a diffusion block layer, and the impurity concentration in a light reception layer. It is a figure which shows the relationship between the film thickness of a diffusion block layer, and light reception sensitivity.

[Description of Embodiment of Present Invention]
First, embodiments of the present invention will be listed and described. The semiconductor stacked body of the present application is made of a III-V group compound semiconductor, a base layer having a conductivity type of n-type, a quantum well structure made of a group III-V compound semiconductor, and a group III-V compound semiconductor having a thickness. Is a diffusion block layer having a p-type impurity concentration of 1 × 10 ¹⁶ cm ⁻³ or less and a contact layer made of a III-V group compound semiconductor and having a p-type conductivity. The base layer, quantum well structure, diffusion block layer, and contact layer are stacked in this order.

  The present inventors have studied a measure for improving the sensitivity of a light receiving element including a structure in which a base layer, a quantum well structure, and a contact layer made of a III-V group compound semiconductor are stacked. As a result, impurities introduced into the contact layer to generate majority carriers in the contact layer of p-type conductivity (p-type impurity) diffuse into the quantum well structure that functions as a light-receiving layer, reducing sensitivity. It has become clear that

In the semiconductor stacked body of the present application, a diffusion made of a III-V compound semiconductor between the contact layer and the quantum well structure, having a thickness of 50 nm or more and a p-type impurity concentration of 1 × 10 ¹⁶ cm ⁻³ or less. A block layer is arranged. A diffusion block layer having a low p-type impurity concentration and a sufficient thickness is disposed between the contact layer and the quantum well structure, thereby suppressing diffusion of the p-type impurity from the contact layer to the quantum well structure. . As a result, according to the semiconductor laminate of the present application, the sensitivity of the light receiving element manufactured using the semiconductor laminate can be improved.

  In the semiconductor stacked body, the diffusion block layer may have a thickness of 500 nm or more. By doing so, the light receiving sensitivity can be improved more reliably.

  In the semiconductor laminate, the diffusion block layer may have a thickness of 2000 nm or less. If the thickness of the diffusion block layer becomes too large, the light receiving sensitivity decreases. By setting the thickness of the diffusion block layer to 2000 nm or less, high light receiving sensitivity can be achieved more reliably.

  In the semiconductor stacked body, the p-type impurity contained in the diffusion block layer may be one or more elements selected from the group consisting of Zn, Be, Mg, and C. By adopting a diffusion block layer in which these impurities are reduced, which are suitable as p-type impurities contained in the contact layer, diffusion of these p-type impurities into the quantum well structure is suppressed, and the light receiving sensitivity is effectively improved. be able to.

  In the semiconductor stacked body, the quantum well structure may be a type II type. By adopting a type II type quantum well structure suitable as a light-receiving layer of the light-receiving element, it is possible to obtain a semiconductor laminate particularly suitable for manufacturing the light-receiving element.

  In the semiconductor stacked body, the quantum well structure may include any repeating structure selected from the group consisting of InGaAs / GaAsSb, GaInNAs / GaAsSb, and InAs / GaSb. These repeating structures are suitable as a repeating structure constituting a type II type quantum well structure.

  The light receiving element of this application is provided with the said semiconductor laminated body and the electrode formed on the semiconductor laminated body. By including the semiconductor stacked body in which the diffusion of impurities from the contact layer to the quantum well structure is suppressed, according to the light receiving element of the present application, high sensitivity can be obtained.

  The sensor of the present application includes the light receiving element and a readout circuit connected to the light receiving element. By including the light receiving element of the present application, according to the sensor of the present application, high sensitivity can be obtained.

[Details of the embodiment of the present invention]
(Embodiment 1)
Next, Embodiment 1 which is one embodiment of a semiconductor laminate according to the present invention will be described below with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

  With reference to FIG. 1, the semiconductor stacked body 10 in the present embodiment includes a substrate 20, a buffer layer 30, a quantum well structure 40, a diffusion block layer 60, and a contact layer 50. The substrate 20, the buffer layer 30, the quantum well structure 40, the diffusion block layer 60, and the contact layer 50 are all made of a III-V group compound semiconductor. The substrate 20 and the buffer layer 30 constitute a base layer.

  The substrate 20 is made of a III-V group compound semiconductor. Moreover, the diameter of the board | substrate 20 is 50 mm or more, for example, is 3 inches. For example, InP (indium phosphide), GaSb (gallium antimony), InAs (indium arsenide), GaAs (gallium arsenide), or the like can be used as the III-V group compound semiconductor constituting the substrate 20. By employing the substrate 20 made of these III-V group compound semiconductors, it is possible to obtain the semiconductor laminate 10 suitable for manufacturing a light receiving element for infrared light. The diameter of the substrate 20 can be set to 80 mm or more (for example, 4 inches) for the purpose of improving the production efficiency and the yield of the light receiving element using the semiconductor laminate 10, and is further 105 mm or more (for example, 5 inches), further 130 mm. It can be set to the above (for example, 6 inches). Impurities that generate n-type carriers (n-type impurities) are introduced into the substrate 20. Examples of the n-type impurity contained in the substrate 20 include S (sulfur), Fe (iron), Sn (tin), and Te (tellurium). As a result, the conductivity type of the substrate 20 is n-type.

  The buffer layer 30 is disposed so as to be in contact with one main surface 20 </ b> A of the substrate 20. As the group III-V compound semiconductor constituting the buffer layer 30, for example, InGaAs (indium gallium arsenide), InP, GaAs, GaP (gallium phosphide), GaSb, InAs, or the like can be employed. The buffer layer 30 may be composed of a plurality of layers. For example, a layer in which an InGaAs layer is stacked on an InP layer can be employed. An n-type impurity is introduced into the buffer layer 30. Examples of the n-type impurity contained in the buffer layer 30 include Si (silicon), Ge (germanium), Te (tellurium), Sn (tin), S (sulfur), Se (selenium), and the like. As a result, the conductivity type of the buffer layer 30 is n-type.

  The quantum well structure 40 is disposed so as to be in contact with the main surface 30A of the buffer layer 30 opposite to the side facing the substrate 20. The quantum well structure 40 has a structure in which two element layers made of a group III-V compound semiconductor are alternately stacked. More specifically, the quantum well structure 40 has a structure in which first element layers 41 and second element layers 42 are alternately stacked. As a material constituting the first element layer 41, for example, GaAsSb (gallium arsenide antimony) can be employed. Further, as a material constituting the second element layer 42, for example, InGaAs can be employed. The thickness of the quantum well structure 40 is preferably 500 nm or more. Thereby, the light reception sensitivity of the light receiving element manufactured using the semiconductor laminated body 10 can be improved.

  The thickness of the first element layer 41 and the second element layer 42 can be 3 nm, for example. The quantum well structure 40 may be formed by stacking, for example, 250 sets of unit structures including the first element layer 41 and the second element layer 42. The quantum well structure 40 may be a type II multiple quantum well having such a structure.

  The quantum well structure 40 having a structure in which GaAsSb layers and InGaAs layers are alternately stacked is suitable as a light-receiving layer for near infrared light. Therefore, by adopting such a structure, the semiconductor stacked body 10 can be made suitable for manufacturing a light receiving element for near infrared light. The combination of the III-V group compound semiconductors constituting the first element layer 41 and the second element layer 42 is not limited to this. For example, a combination of a GaAsSb layer and a GaInNAs (gallium indium nitrogen arsenide) layer, a GaSb layer and an InAs It may be a combination with a layer. The quantum well structure 40 is not limited to a multiple quantum well, and may be a single quantum well composed of a single layer.

The diffusion block layer 60 is formed so as to be in contact with the main surface 40A on the opposite side of the quantum well structure 40 from the side facing the buffer layer 30. The diffusion block layer 60 contacts the quantum well structure 40 on one main surface 60A, and contacts the contact layer 50 on the other main surface 60B. The diffusion block layer 60 is made of a III-V group compound semiconductor. The material constituting the diffusion block layer 60 can be determined in consideration of lattice matching with the quantum well structure 40 and the contact layer 50. Specifically, the diffusion block layer 60 can be made of, for example, InGaAs, GaAsSb, or the like. The thickness of the diffusion block layer 60 is 50 nm or more. The p-type impurity concentration in the diffusion block layer 60 is 1 × 10 ¹⁶ cm ⁻³ or less.

The contact layer 50 is formed so as to be in contact with the other main surface 60 </ b> B of the diffusion block layer 60. As the group III-V compound semiconductor constituting the contact layer 50, for example, InGaAs, InAs, GaSb, GaAs, InP, or the like can be employed. Impurities that generate p-type carriers (p-type impurities) are introduced into the contact layer 50. Examples of the p-type impurity contained in the contact layer 50 include Zn (zinc), Be (beryllium), Mg (magnesium), C (carbon), and the like. Thereby, the conductivity type of the contact layer 50 is p-type. Further, in the diffusion block layer 60, the concentration of p-type impurities including these p-type impurities is 1 × 10 ¹⁶ cm ⁻³ or less.

In the semiconductor laminated body 10 of this Embodiment, it consists of a III-V group compound semiconductor between the contact layer 50 and the quantum well structure 40, thickness is 50 nm or more, and p-type impurity density | concentration is 1 * 10 < ¹⁶ > cm. A diffusion block layer 60 that is ⁻³ or less is disposed. A diffusion block layer 60 having a low p-type impurity concentration and a sufficient thickness is disposed between the contact layer 50 and the quantum well structure 40, so that the p-type impurity from the contact layer 50 to the quantum well structure 40 is reduced. Diffusion is suppressed. As a result, the sensitivity of the light receiving element manufactured using the semiconductor stacked body 10 can be improved.

  In the semiconductor stacked body 10, the thickness of the diffusion block layer 60 is preferably 500 nm or more. Thereby, the light receiving sensitivity can be improved more reliably.

  In the semiconductor stacked body 10, the thickness of the diffusion block layer 60 is preferably 2000 nm or less. When the thickness of the diffusion block layer 60 becomes too large, the light receiving sensitivity is lowered. By setting the thickness of the diffusion block layer 60 to 2000 nm or less, a high light receiving sensitivity can be achieved more reliably.

  Next, an infrared light receiving element (photodiode) that is an example of a light receiving element manufactured using the semiconductor laminate 10 will be described. Referring to FIG. 2, infrared light receiving element 1 in the present embodiment is manufactured using semiconductor stacked body 10 of the present embodiment, and is a substrate stacked in the same manner as semiconductor stacked body 10. 20, a buffer layer 30, a quantum well structure 40, a diffusion block layer 60, and a contact layer 50. In the infrared light receiving element 1, a trench 99 that penetrates the contact layer 50, the diffusion block layer 60, and the quantum well structure 40 and reaches the buffer layer 30 is formed. That is, the contact layer 50, the diffusion block layer 60, and the quantum well structure 40 are exposed at the side wall 99 </ b> A of the trench 99. The bottom wall 99B of the trench 99 is located in the buffer layer 30.

  Further, the infrared light receiving element 1 includes a passivation film 80, an n-side electrode 91, a p-side electrode 92, and an antireflection film 29. The passivation film 80 is disposed so as to cover the bottom wall 99B of the trench 99, the side wall 99A of the trench 99, and the second main surface 50B that is the main surface opposite to the side facing the diffusion block layer 60 in the contact layer 50. ing. The passivation film 80 is made of an insulator such as silicon nitride or silicon oxide.

  An opening 81 is formed in the passivation film 80 that covers the bottom wall 99B of the trench 99 so as to penetrate the passivation film 80 in the thickness direction. An n-side electrode 91 is arranged so as to fill the opening 81. The n-side electrode 91 is disposed so as to contact the buffer layer 30 exposed from the opening 81. The n-side electrode 91 is made of a conductor such as metal. More specifically, the n-side electrode 91 can be made of, for example, Au (gold) / Ge (germanium) / Ni (nickel). The n-side electrode 91 is in ohmic contact with the buffer layer 30.

  An opening 82 is formed in the passivation film 80 covering the second main surface 50B of the contact layer 50 so as to penetrate the passivation film 80 in the thickness direction. A p-side electrode 92 is arranged so as to fill the opening 82. The p-side electrode 92 is disposed so as to contact the contact layer 50 exposed from the opening 82. The p-side electrode 92 is made of a conductor such as metal. More specifically, the p-side electrode 92 can be made of, for example, Au / Zn. The p-side electrode 92 is in ohmic contact with the contact layer 50.

  The antireflection film 29 is formed so as to cover the other main surface 20 </ b> B of the substrate 20. The antireflection film 29 is made of, for example, SiON (silicon oxynitride). By forming the antireflection film 29, reflection of light incident from the other main surface 20B side of the substrate 20 is suppressed, and the sensitivity of the infrared light receiving element 1 is improved.

  When infrared rays are incident on the infrared light receiving element 1 from the other main surface 20B side of the substrate 20, the infrared rays are absorbed between the quantum levels in the quantum well structure 40, and pairs of electrons and holes are generated. Then, the generated electrons and holes are taken out from the infrared light receiving element 1 as photocurrent signals, whereby infrared rays are detected.

  The p-side electrode 92 is a pixel electrode. The infrared light receiving element 1 may include only one p-side electrode 92 as a pixel electrode as shown in FIG. 2, or may include a plurality of pixel electrodes (p-side electrode 92). It may be. Specifically, the infrared light receiving element 1 has a structure shown in FIG. 2 as a unit structure, and the unit structure has a structure that is repeated a plurality of times in the direction in which one main surface 20A of the substrate 20 extends in FIG. It may be. In this case, the infrared light receiving element 1 has a plurality of p-side electrodes 92 corresponding to the pixels, while only one n-side electrode 91 is disposed. Such a structure will be described in a fourth embodiment described later.

In the infrared light receiving element 1 of the present embodiment, a III-V compound semiconductor is formed between the contact layer 50 and the quantum well structure 40, the thickness is 50 nm or more, and the p-type impurity concentration is 1 × 10 ^16. A diffusion block layer 60 that is cm ⁻³ or less is disposed. A diffusion block layer 60 having a low p-type impurity concentration and a sufficient thickness is disposed between the contact layer 50 and the quantum well structure 40, so that the p-type impurity from the contact layer 50 to the quantum well structure 40 is reduced. Diffusion is suppressed. For this reason, the infrared light receiving element 1 in the present embodiment is a light receiving element with improved sensitivity.

  Next, an outline of a method for manufacturing the semiconductor stacked body 10 and the infrared light receiving element 1 in the present embodiment will be described.

  Referring to FIG. 3, in the method for manufacturing semiconductor stacked body 10 and infrared light receiving element 1 in the present embodiment, first, a substrate preparation step is performed as a step (S10). In this step (S10), referring to FIG. 4, for example, substrate 20 made of InP having a diameter of 50 mm is prepared. More specifically, the substrate 20 made of InP is obtained by slicing an ingot made of InP. After the surface of the substrate 20 is polished, a substrate 20 in which the flatness and cleanliness of one main surface 20A is ensured through a process such as cleaning is prepared.

  Next, an operation layer forming step is performed as a step (S20). In this step (S20), the buffer layer 30, the quantum well structure 40, the diffusion block layer 60, and the contact layer 50, which are operation layers, are formed on one main surface 20A of the substrate 20 prepared in the step (S10). The This operation layer can be formed, for example, by metal organic vapor phase epitaxy. The operation layer is formed by metal organic vapor phase epitaxy, for example, by placing the substrate 20 on a rotary table equipped with a heater for heating the substrate, and supplying the source gas onto the substrate while heating the substrate 20 with the heater. Can be implemented.

  Specifically, referring to FIG. 4, first, for example, an n-type InP layer (n-InP layer) having a conductivity type of n-type is formed so as to be in contact with one main surface 20A of substrate 20. An InGaAs layer (n-InGaAs layer) whose conductivity type is n-type is laminated on the InP layer layer. The n-InP layer and the n-InGaAs layer are formed by metal organic chemical vapor deposition. Thereby, the buffer layer 30 made of a III-V group compound semiconductor and having n type conductivity is formed.

  Next, referring to FIGS. 4 and 5, for example, from GaAsSb which is a group III-V compound semiconductor so as to be in contact with main surface 30 </ b> A opposite to the side facing substrate 20 of buffer layer 30. The quantum well structure 40 is formed by alternately stacking the first element layer 41 and the second element layer 42 made of InGaAs, which is a III-V group compound semiconductor. The quantum well structure 40 can be formed by metal organic vapor phase epitaxy following the formation of the buffer layer 30. That is, the quantum well structure 40 can be formed by changing the source gas in a state where the substrate 20 is disposed in the apparatus used when the buffer layer 30 is formed.

  The first element layer 41 and the second element layer 42 can each be formed to have a thickness of 3 nm, for example, and 250 unit structures composed of the first element layer 41 and the second element layer 42 can be stacked, for example. Thereby, the quantum well structure 40 which is a type II multiple quantum well can be formed.

  Next, referring to FIG. 5 and FIG. 1, for example, a group III-V compound semiconductor is in contact with main surface 40 </ b> A opposite to the side facing buffer layer 30 of quantum well structure 40. A diffusion block layer 60 made of InGaAs is formed. The diffusion block layer 60 can be formed by metal organic vapor phase epitaxy following the formation of the quantum well structure 40. In other words, the diffusion block layer 60 can be formed by changing the source gas in a state where the substrate 20 is disposed in the apparatus used for forming the quantum well structure 40.

  Next, referring to FIG. 1, for example, group III-V is brought into contact with the other main surface 60 </ b> B which is the main surface opposite to the side facing the quantum well structure 40 of the diffusion block layer 60. A contact layer 50 made of p-type InGaAs (p-InGaAs), which is a compound semiconductor, is formed. The contact layer 50 can be formed by metal organic vapor phase epitaxy following the formation of the diffusion block layer 60. That is, the contact layer 50 can be formed by changing the source gas in a state where the substrate 20 is disposed in the apparatus used for forming the diffusion block layer 60.

With the above procedure, the semiconductor stacked body 10 in the present embodiment is completed. As described above, the production efficiency of the semiconductor stacked body 10 can be improved by performing the step (S20) by metal organic vapor phase epitaxy. Note that the step (S20) is not limited to the metal organic chemical vapor deposition method (all metal organic chemical vapor deposition method) using only the organic metal raw material, and for example, AsH ₃ (arsine) which is a hydride of As is used as the raw material of As. You may implement by the used organometallic vapor phase growth method. Further, each semiconductor layer can be formed by a method other than metal organic vapor phase epitaxy. For example, an MBE (Molecular Beam Epitaxy) method may be used.

  Referring to FIG. 3, a trench formation step is performed next as a step (S30). In this step (S30), referring to FIG. 1 and FIG. 6, contact layer 50, diffusion block layer 60 and quantum well structure 40 are added to semiconductor stacked body 10 manufactured in the above steps (S10) to (S20). A trench 99 that penetrates and reaches the buffer layer 30 is formed. The trench 99 can be formed, for example, by performing etching after forming a mask layer having an opening corresponding to the shape of the trench 99 on the second main surface 50B of the contact layer 50.

  Next, a passivation film forming step is performed as a step (S40). In this step (S40), with reference to FIGS. 6 and 7, a passivation film 80 is formed on semiconductor stacked body 10 in which trench 99 is formed in step (S30). Specifically, a passivation film 80 made of an insulator such as silicon oxide or silicon nitride is formed by, for example, CVD (Chemical Vapor Deposition). The passivation film 80 is formed so as to cover the bottom wall 99B of the trench 99, the side wall 99A of the trench 99, and the second main surface 50B that is the main surface opposite to the side facing the diffusion block layer 60 in the contact layer 50. The

  Next, an electrode formation step is performed as a step (S50). In this step (S50), referring to FIG. 7 and FIG. 2, n-side electrode 91 and p-side electrode 92 are formed on semiconductor stacked body 10 on which passivation film 80 is formed in step (S40). Specifically, for example, a mask having an opening at a position corresponding to a region where the n-side electrode 91 and the p-side electrode 92 are to be formed is formed on the passivation film 80, and the opening 81 is formed in the passivation film 80 using the mask. , 82 are formed. Thereafter, for example, an n-side electrode 91 and a p-side electrode 92 made of an appropriate conductor are formed by vapor deposition.

  Next, an antireflection film forming step is performed as a step (S60). In this step (S60), referring to FIG. 2, an antireflection film 29 made of, for example, SiON is formed so as to cover the other main surface 20B of substrate 20. The antireflection film 29 can be formed by, for example, CVD. The infrared light receiving element 1 in the present embodiment is completed through the above steps. After that, each element is separated by, for example, dicing.

(Embodiment 2)
Next, a second embodiment which is another embodiment of the semiconductor laminate and the light receiving element according to the present invention will be described. Referring to FIGS. 8 and 1, semiconductor stacked body 10 in the second embodiment has basically the same structure as semiconductor stacked body 10 in the first embodiment, and has the same effects. Referring to FIGS. 9 and 2, infrared light receiving element 1 in the second embodiment has basically the same structure as infrared light receiving element 1 in the first embodiment, and has the same effects. However, semiconductor stacked body 10 and infrared light receiving element 1 in the second embodiment are different from those in the first embodiment in the structure of contact layer 50.

  Referring to FIGS. 8 and 9, contact layer 50 of the second embodiment includes first contact layer 51 arranged to include first main surface 50A that is the main surface on diffusion block layer 60 side, 2nd contact layer 52 arranged so that the 2nd principal surface 50B which is the principal surface opposite to 1A principal surface 50A may be included. The impurity concentration of the first contact layer 51 (p-type impurity concentration) is lower than the impurity concentration of the second contact layer 52. That is, the impurity concentration of the region including the first main surface 50A that is the main surface on the diffusion block layer 60 side of the contact layer 50 is the same as that of the second main surface 50B that is the main surface opposite to the first main surface 50A. It is lower than the impurity concentration of the included region.

  In the semiconductor stacked body 10 and the infrared light receiving element 1 of the present embodiment, the impurity concentration in the region including the first main surface 50A that is the main surface of the contact layer 50 on the diffusion block layer 60 side (quantum well structure 40 side) is The impurity concentration in the region including the second main surface 50B, which is the main surface opposite to the first main surface 50A, is set lower. By setting the impurity concentration in the region including the first main surface 50A, which is the main surface on the quantum well structure 40 side, low, it is possible to suppress the diffusion of impurities into the quantum well structure 40 and contribute to the improvement of sensitivity. . Further, by setting the impurity concentration in a region including the second main surface 50B, which is the main surface opposite to the first main surface 50A, to be high, an electrode (p side) disposed in contact with the second main surface 50B It is possible to reduce the contact resistance between the electrode 92) and the contact layer 50. Thus, according to the semiconductor laminated body 10 and the infrared light receiving element 1 in this Embodiment, the further improvement in a sensitivity can be achieved.

  The semiconductor laminate 10 and the infrared light receiving element 1 in the second embodiment can be manufactured by changing the method for forming the contact layer 50 in the manufacturing method described in the first embodiment. Contact layer 50 of the second embodiment can be formed by, for example, metal organic chemical vapor deposition. Specifically, after forming the first contact layer 51 on the diffusion block layer 60, the second contact layer 52 is formed on the first contact layer 51. At this time, the concentration of the source gas for introducing the p-type impurity is lower than that of the second contact layer 52 when the first contact layer 51 is formed.

(Embodiment 3)
Next, Embodiment 3 which is another embodiment of the semiconductor laminate and the light receiving element according to the present invention will be described. Referring to FIGS. 10 and 1, semiconductor stacked body 10 in the third embodiment has basically the same structure as semiconductor stacked body 10 in the first embodiment and has the same effects. Referring to FIGS. 11 and 2, infrared light receiving element 1 in the third embodiment has basically the same structure as infrared light receiving element 1 in the first embodiment, and has the same effects. However, the semiconductor laminate 10 and the infrared light receiving element 1 in the third embodiment are different from those in the first embodiment in the structure of the contact layer 50.

  10 and 11, the dots in the contact layer 50 schematically represent p-type impurities contained in the contact layer 50. Referring to FIGS. 10 and 11, contact layer 50 in the third embodiment is made of a III-V group compound semiconductor layer. In the contact layer 50, the concentration of the p-type impurity is from the second main surface 50B which is the main surface opposite to the first main surface 50A (the main surface in contact with the p-side electrode 92) to the quantum well structure 40 side. It gradually decreases toward the first main surface 50A, which is the main surface. The concentration of the p-type impurity in the contact layer 50 monotonously decreases from the second main surface 50B toward the first main surface 50A. By adopting such a structure, the impurity concentration in the region including the first main surface 50A of the contact layer 50 is lower than that in the region including the second main surface 50B, and the same as in the second embodiment. An effect can be obtained.

  The semiconductor laminate 10 and the infrared light receiving element 1 in the third embodiment can be manufactured by changing the method for forming the contact layer 50 in the manufacturing method described in the first embodiment. The contact layer 50 of the third embodiment can be formed by, for example, metal organic chemical vapor deposition. When the contact layer 50 is formed, the contact layer 50 of the third embodiment can be formed by gradually increasing the concentration of the source gas of the p-type impurity.

(Embodiment 4)
Next, the light receiving element and the sensor in the fourth embodiment will be described. Referring to FIGS. 12 and 2, infrared light receiving element 1 of Embodiment 4 has the structure shown in FIG. 2 as a unit structure, and the unit structure extends in the direction in which one main surface 20 </ b> A of substrate 20 extends. Multiple structures are repeated. The infrared light receiving element 1 has a plurality of p-side electrodes 92 corresponding to the pixels. On the other hand, only one n-side electrode 91 is arranged.

  More specifically, the n-side electrode 91 of the infrared light receiving element 1 of Embodiment 4 is formed on the bottom wall of the trench 99 located at the end in the direction in which the substrate 20 extends. Further, the p-side electrode 92 on the contact layer 50 adjacent to the trench 99 located at the end is omitted. Infrared sensor 100 in the present embodiment includes infrared light receiving element 1 having such a structure, and a read-out integrated circuit (ROIC) 70 electrically connected to infrared light receiving element 1. . The readout circuit 70 is, for example, a CMOS (Complementary Metal Oxide Semiconductor) circuit.

  A plurality of readout electrodes (not shown) provided on the main body 71 of the readout circuit 70 and a plurality of p-side electrodes 92 functioning as pixel electrodes in the infrared light receiving element 1 are arranged via bumps 73 so as to have a one-to-one relationship. Are electrically connected. In addition, the infrared light receiving element 1 has a wiring 75 that contacts the n-side electrode 91 and extends along the bottom wall and the side wall of the trench 99 where the n-side electrode 91 is located and reaches the contact layer 50. It is formed. The wiring 75 and a ground electrode (not shown) provided on the main body 71 of the readout circuit 70 are electrically connected via the bumps 72. With this structure, light reception information for each pixel of the infrared light receiving element 1 is output from each p-side electrode 92 (pixel electrode) to the read electrode of the read circuit 70, and the light reception information is aggregated in the read circuit 70. Thus, for example, a two-dimensional image can be obtained.

  A light receiving element having the same structure as that of the infrared light receiving element 1 described in the first embodiment and having a different diffusion block layer 60 thickness was manufactured as a sample. Then, the relationship between the thickness of the diffusion block layer 60 and the maximum value of the p-type impurity in the quantum well structure 40 was investigated (Experiment 1). In addition, the relationship between the thickness of the diffusion block layer 60 and the light receiving sensitivity was also investigated (Experiment 2).

  The substrate 20 was made of InP and added with S (sulfur) as an n-type impurity. The buffer layer 30 was formed by laminating an n-InGaAs layer having a thickness of 150 nm on an n-InP layer having an thickness of 11 nm. As the first element layer 41 and the second element layer 42 of the quantum well structure 40, a GaAsSb layer and an InGaAs layer are employed, respectively, and a structure in which this combination is repeated 250 cycles is employed. The thickness of the contact layer 50 was 100 nm. The contact layer 50 is a p-InGaAs layer containing Zn as a p-type impurity. In Experiment 1, the concentration of the p-type impurity in the quantum well structure 40 was measured, and the maximum value of the concentration was investigated. Further, in Experiment 2, the light receiving sensitivity was investigated by making light having a wavelength of 2.0 μm incident from the antireflection film 29 side under the conditions that the reverse bias was 5 V and the temperature was room temperature. The results of Experiment 1 and Experiment 2 are shown in FIGS. 13 and 14, respectively.

Referring to FIG. 13, as the thickness of diffusion block layer 60 increases, the maximum value of the impurity concentration in quantum well structure 40 decreases. Here, considering the influence on the sensitivity of the impurities contained in the quantum well structure, it is acceptable if the maximum value of the impurity concentration is 1 × 10 ¹⁶ cm ⁻³ or less. As shown in FIG. 13, when the thickness of the diffusion block layer is 50 nm or more, the maximum value of the p-type impurity concentration can be 1 × 10 ¹⁶ cm ⁻³ or less.

  Referring to FIG. 14, in a region where diffusion block layer 60 has a small thickness, the light receiving sensitivity improves as the diffusion block layer 60 increases in thickness. In order to obtain high light receiving sensitivity, the thickness of the diffusion block layer 60 is preferably 500 nm or more, and more preferably 1000 nm or more. On the other hand, when the thickness of the diffusion block layer 60 exceeds 1500 nm, the light receiving sensitivity is lowered. That is, if the thickness of the diffusion block layer 60 is too large, the light receiving sensitivity is lowered. In order to suppress a decrease in sensitivity due to the thickness of the diffusion block layer 60 being too large, the thickness of the diffusion block layer 60 is preferably 2000 nm or less, and more preferably 1750 nm or less.

  It should be understood that the embodiments and examples disclosed herein are illustrative in all respects and are not restrictive in any respect. The scope of the present invention is defined by the scope of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the scope of the claims.

  The semiconductor laminate, the light receiving element, and the sensor of the present application can be particularly advantageously applied to a light receiving element and a sensor that are required to improve sensitivity, and a semiconductor laminate used for manufacturing the same.

DESCRIPTION OF SYMBOLS 1 Infrared light receiving element 10 Semiconductor laminated body 20 Substrate 20A One main surface 20B The other main surface 29 Antireflection film 30 Buffer layer 30A Main surface 40 Quantum well structure 40A Main surface 41 First element layer 42 Second element layer 50 Contact layer 50A First main surface 50B Second main surface 51 First contact layer 52 Second contact layer 60 Diffusion block layer 60A One main surface 60B The other main surface 70 Read circuit 71 Main body 72, 73 Bump 75 Wiring 80 Passivation film 81, 82 Opening 91 N-side electrode 92 P-side electrode 99 Trench 99A Side wall 99B Bottom wall 100 Infrared sensor

Claims (8)

A base layer made of a group III-V compound semiconductor and having an n-type conductivity;
A quantum well structure made of a III-V compound semiconductor;
A diffusion block layer made of a III-V group compound semiconductor, having a thickness of 50 nm or more and a p-type impurity concentration of 1 × 10 ¹⁶ cm ⁻³ or less;
A contact layer made of a group III-V compound semiconductor and having a conductivity type of p-type,
The base layer, the quantum well structure, the diffusion block layer, and the contact layer are stacked in this order.   The semiconductor laminate according to claim 1, wherein the diffusion block layer has a thickness of 500 nm or more.   The semiconductor laminate according to claim 1, wherein the diffusion block layer has a thickness of 2000 nm or less.   4. The semiconductor stacked body according to claim 1, wherein the p-type impurity contained in the diffusion block layer is one or more elements selected from the group consisting of Zn, Be, Mg, and C. 5.   The semiconductor multilayer body according to claim 1, wherein the quantum well structure is a type II type.   6. The semiconductor stacked body according to claim 5, wherein the quantum well structure includes any one of repeating structures selected from the group consisting of InGaAs / GaAsSb, GaInNAs / GaAsSb, and InAs / GaSb. The semiconductor laminate according to any one of claims 1 to 6,
A light receiving element comprising: an electrode formed on the semiconductor laminate. A light receiving element according to claim 7;
And a readout circuit connected to the semiconductor device.

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