JP2015049437A - Display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that although the potential fluctuation of a drain line is relatively small during column reverse drive, an electric field noise is generated from a display device due to drain line fluctuation in pixel writing in the case of displaying a checkered image by an RGB time division system.SOLUTION: A display device includes: an intermediate potential generation circuit; a first buffer; a first terminal connected to the first buffer; first, second and third switch circuits connected to the first terminal; a first drain line connected to the first switch circuit; a second drain line connected to the second switch circuit; and a third drain line connected to the third switch circuit. The intermediate potential generation circuit is configured to output an intermediate potential to the first terminal when the first, second and third drain lines shift from a voltage lower than the intermediate potential to a voltage higher than the intermediate potential, or from a voltage higher than the intermediate potential to a voltage lower than the intermediate potential.

Description

  The present disclosure relates to a display device and can be applied to, for example, a display device driven by RGB time division.

  A high-resolution liquid crystal display device can be realized by forming a peripheral circuit and a liquid crystal display portion on the same substrate by using a low-temperature polysilicon thin film transistor (LTPS-TFT). However, when realizing a high-resolution and high-definition liquid crystal display device, the clock frequency of peripheral circuits, particularly signal circuits, is as high as several tens of MHz. However, since the operating frequency of the peripheral circuit using the LTPS-TFT is as low as about several MHz to about 10 MHz, it is difficult to realize a high-resolution liquid crystal display device in which the peripheral circuit is formed around the liquid crystal display unit.

  Therefore, as a method for realizing a high-resolution, high-definition liquid crystal display device using LTPS-TFT, for example, R (red) using a time-division switch provided on the same substrate as the liquid crystal display unit and a driver IC , G (green), B (blue) corresponding to time-division driving (RGB time-division driving) method has been proposed (Patent Document 1). A column inversion driving method has been proposed for improving image quality and reducing power consumption (Patent Document 1).

JP 2000-275611 A

  Although the column inversion drive has a relatively small potential fluctuation of the drain line, when displaying a checkered image by the RGB time division method, electric field noise is generated from the display device due to the drain line fluctuation at the time of pixel writing.

  Other problems and novel features will become apparent from the description of the present disclosure and the accompanying drawings.

The outline of a representative one of the present disclosure will be briefly described as follows.
That is, the display device is configured such that the drain line passes through the intermediate potential at the time of pixel writing.

  According to the display device, the level of electric field noise can be reduced.

It is a figure which shows the structure of the display apparatus which concerns on an Example. It is a figure which shows the structure of the RGB-SW circuit which concerns on an Example. It is a figure which shows a dot checkered image. It is a figure which shows a pixel checkered image. 6 is a diagram showing a display device according to Comparative Example 1. FIG. It is a figure which shows the timing of FIG. 3C. 1 is a diagram illustrating a display device according to a first embodiment. FIG. 6 is a timing chart when the display device according to the first embodiment drives a pixel checkered image. FIG. 6 is a timing chart when the display device according to the first embodiment drives a dot checkered image. It is a figure shown in the display apparatus concerning the modification 1. FIG. 10 is a timing chart when the display device according to the first modification drives a pixel checkered image. FIG. 10 is a timing chart when the display device according to the first modification drives a dot checkered image. FIG. 6 is a diagram illustrating a display device according to a second embodiment. FIG. 10 is a timing chart when the display device according to the second embodiment drives a pixel checkered image. FIG. 6 is a timing chart when the display device according to the first embodiment drives a dot checkered image. It is a figure shown in the display apparatus concerning the modification 2. FIG. 10 is a timing chart when a display device according to Modification 2 drives a pixel checkered image. FIG. 10 is a timing chart when a display device according to Modification 2 drives a dot checkered image. 3 is a block diagram of a driver IC according to Embodiment 1. FIG. It is a figure for demonstrating the electric field noise generate | occur | produced before and after a blanking period. It is a figure which shows a mode that the electric field noise which generate | occur | produces before and after a blanking period was reduced.

The outline of the embodiment will be described as follows.
(1) The display device (11) includes an intermediate potential generation circuit (91), a first buffer (151), and first terminals (T1, T2) connected to the first buffer (151). ), The first, second and third switch circuits (141, 142, 143, 145, 146, 147) connected to the first terminals (T1, T2), and the first switch circuit (141, 145), the first drain lines (DR1, DR2) connected to the second switch circuit (142), the second drain lines (DG1, DG2) connected to the second switch circuit (143, 147) connected to the third drain line (DB1, DB2). The intermediate potential generation circuit (91) is configured such that the first, second and third drain lines (DR1, DR2, DG1, DG2, DB1, DB2) have a voltage lower than the intermediate potential to a voltage higher than the intermediate potential, or intermediate When transitioning from a voltage higher than the potential to a voltage lower than the intermediate potential, the intermediate potential is output to the first terminals (T1, T2).
(2) In the display device of (1), the intermediate potential generation circuit (91) includes the first storage device (94) that holds the image data of the current line and the image data one line before the current line. A second storage device (93) to hold, and the intermediate potential is determined by comparing the contents of the first storage device (94) with the content of the second storage device (93). The
(3) In the display device of (2), the intermediate potential generation circuit (91) includes the MSB of data held in the first storage device (94) and the data held in the second storage device (93). The intermediate potential is determined by comparing the MSBs.

  According to the display device of the embodiment, since the drain line passes through the intermediate potential at the time of pixel writing, the noise fluctuation of the drain line is dispersed, and the level of electric field noise can be reduced.

  Hereinafter, examples and modifications will be described with reference to the drawings. However, in the following description, the same components are denoted by the same reference numerals, and repeated description is omitted.

  FIG. 1 is a diagram illustrating the configuration of the display device according to the first embodiment. The display device 11 includes a display region 12, gate scan circuits 13R and 13L, an RGB-SW circuit 14, and a driver IC 15 on a substrate. The display area 12 includes a gate line GL, a drain line DL, and a pixel PE. The pixel PE has a thin film transistor (TFT) 16, a capacitor 17 formed by a source electrode and a common electrode. The gate scan circuits 13R and 13L and the RGB-SW circuit 14 are formed of TFTs. The driver IC 15 is mounted on a substrate by COG (Chip On Glass). The driver IC 15 is formed on one silicon semiconductor substrate by CMOS circuit technology.

  FIG. 2 is a diagram illustrating the configuration of the RGB-SW circuit according to the first embodiment. The RGB-SW circuit 14 includes switch circuits SWR, SEG, and SWB formed of single channel (for example, n channel type) TFTs. Each of the switch circuits SWRn−1, SWRn, SWRn + 1, and SWRn + 2 is connected to the red (R) pixel (Rn−1, Rn, Rn + 1, Rn + 2) by the signal of the control signal line ASW1. , DRn, DRn + 1, DRn + 2), the gradation voltage is transmitted from the driver IC 15. Each of the switch circuits SWGn−1, SWGn, SWGn + 1, and SWGn + 2 is a drain line DL (DGn−1) connected to a green (G) pixel (Gn−1, Gn, Gn + 1, Gn + 2) by a signal of the control signal line ASW2. , DGn, DGn + 1, DGn + 2) from the driver IC 15. Each of the switch circuits SWBn−1, SWBn, SWBn + 1, and SWBn + 2 is connected to the blue (B) pixel (Bn−1, Bn, Bn + 1, Bn + 2) by the signal of the control signal line ASW3. , DBn, DBn + 1, DBn + 2), the gradation voltage is transmitted from the driver IC 15. The drain line DL is connected to the output terminal of the driver IC 15 so that the polarity is alternately reversed. In FIG. 2, positive polarity is represented by + and negative polarity is represented by-. As shown in FIG. 3D, the control signal lines ASW1, ASW2, and ASW3 are driven at different times (time division) in one horizontal period (during the writing of one line) to drive the drain lines in a time division manner. The RGB-SW circuit is a time division switch circuit.

<Electric noise generation principle>
3A, 3B, 3C, and 3D are diagrams for explaining the principle of electric field noise generation due to drain line fluctuation. FIG. 3A is a diagram showing a dot checkered image. FIG. 3B is a diagram illustrating a pixel checkered image. FIG. 3C is a diagram illustrating a display device according to a comparative example. FIG. 3D is a timing diagram of FIG. 3C.

  As shown in FIG. 3A, in the Nth line, the pixel R1 has a positive (+) white voltage, the pixel G1 has a negative (−) black voltage, the pixel B1 has a positive white voltage, and the pixel R2 has a negative polarity. Black voltage, the pixel G2 is a positive white voltage, and the pixel B2 is a negative black voltage. In the (N + 1) th line, the pixel R1 has a positive black voltage, the pixel G1 has a negative white voltage, the pixel B1 has a positive black voltage, the pixel R2 has a negative white voltage, and the pixel G2 has a positive black voltage. Pixel B2 has a negative white voltage. Here, the white voltage is a voltage when the absolute value of the gradation voltage is maximum, and the black voltage is a voltage when the absolute value of the gradation voltage is minimum. The driving method is sub-pixel column inversion driving (the polarity is inverted for each drain line). The dot checkered image is the worst pattern of drain line fluctuation.

  As shown in FIG. 3B, in the Nth line, the pixel R1 has a positive (+) white voltage, the pixel G1 has a negative (−) white voltage, the pixel B1 has a positive white voltage, and the pixel R2 has a negative polarity. Black voltage, the pixel G2 is a positive black voltage, and the pixel B2 is a negative black voltage. In the (N + 1) th line, the pixel R1 has a positive black voltage, the pixel G1 has a negative black voltage, the pixel B1 has a positive black voltage, the pixel R2 has a negative white voltage, and the pixel G2 has a positive white voltage. Pixel B2 has a negative white voltage. The driving method is sub-pixel column inversion driving (the polarity is inverted for each drain line).

  The display device 11R according to the comparative example 1 includes an RG-SW circuit 14 and a driver IC 15R. The pixel in FIG. 3C represents a dot checkered image, where the uppercase letter of the pixel represents a white voltage and the lowercase letter of the alphabet represents a black voltage. For example, “R1” represents a white voltage and “r1” represents a black voltage. The RGB-SW circuit 14 includes switch circuits 141, 142, 143, 145, 146, and 147. The switch circuits 141, 143, and 146 transmit a signal (S1) from the terminal T1 of the driver IC 15R, and the switch circuits 142, 145, and 147 transmit a signal (S2) from the terminal T2 of the driver IC 15R. The switch circuits 141, 142, 143, 145, 146, and 147 are constituted by single-channel TFTs as described with reference to FIG. The driver IC 15R includes an output buffer 151 that outputs a positive signal and an output buffer 152 that outputs a negative signal. The output of the output buffer 151 is sent to terminals T1 and T2 via switch circuits SW + 1 and SW + 2, respectively. The output of the output buffer 152 is sent to terminals T1 and T2 via switch circuits SW-1 and SW-2, respectively. In FIG. 3C, a switch circuit represented by a symbol ◎ represents a switch circuit that transmits a positive signal, and a switch circuit represented by a symbol marked with a circle in the circle represents a negative signal. The switch circuit to transmit is represented.

As shown in FIG. 3D, the drain line DR1 transitions from a positive black voltage to a white voltage at the rise of the signal of the control signal line ASW1 of the RGB-SW circuit 14 in the first line. In this case the drain line DG1, DB1, DG2, DB2 does not vary the drain line D R2 varies the black voltage from a negative white voltage. As a result, when the signal on the control signal line ASW1 rises, both the drain lines DR1 and DR2 change in the positive direction, and positive electric field noise is generated. Similarly, positive electric field noise is generated by the drain lines DG1 and DG2 at the rising timing of the signal of the control signal line ASW2, and by the drain lines DB1 and DB2 at the rising timing of the signal of the control signal line ASW3. The drain line DR2 transitions from a negative black voltage to a white voltage when the signal on the control signal line ASW1 of the RGB-SW circuit 14 rises to the second line. At this time, the drain lines DG1, DB1, DG2, and DB2 do not change, but the drain line DR1 changes from a positive white voltage to a black voltage. As a result, when the signal of the control signal line ASW1 rises, the drain lines DR1 and DR2 both change in the negative direction, and negative electric field noise is generated. Similarly, negative electric field noise is generated by the drain lines DG1 and DG2 at the rising timing of the signal of the control signal line ASW2 and by the drain lines DB1 and DB2 at the rising timing of the signal of the control signal line ASW3.

<Subpixel column inversion drive>
In order to reduce electric field noise, the fluctuation width of one drain line is reduced. That is, the drain line is once set to the intermediate potential. The present embodiment is an example of subpixel column inversion driving, and will be described in detail below.

  4A, 4B, and 4C are diagrams illustrating a driving method and effects according to the first embodiment. FIG. 4A is a diagram illustrating the display device according to the first embodiment. The display device 11 includes an RGB-SW circuit 14 and a driver IC 15. The RGB-SW circuit 14 includes switch circuits 141 (SWRn-1), 142 (SWGn-1), 143 (SWBn-1), 145 (SWRn), 146 (SWGn), and 147 (SWBn). The switch circuits 141, 143, and 146 transmit a signal (S1) from the terminal T1 of the driver IC 15R, and the switch circuits 142, 145, and 147 transmit a signal (S2) from the terminal T2 of the driver IC 15R. The switch circuits 141, 142, 143, 145, 146, and 147 are constituted by single-channel TFTs as described with reference to FIG. The driver IC 15 includes an output buffer 151 that outputs a positive signal and an output buffer 152 that outputs a negative signal. The output of the output buffer 151 is sent to terminals T1 and T2 via switch circuits SW + 1 and SW + 2, respectively. The output of the output buffer 152 is sent to terminals T1 and T2 via switch circuits SW-1 and SW-2, respectively.

  Since both the pixel checkered image and the dot checkered image have the RGB-SW circuit 14, the driver output signal (S 1) changes as R 1 + → G 2 + → B 1 +... And the driver output signal (S 2) is , R2-⇒G1-⇒B2-. FIG. 4B shows a pixel checkered pattern, and FIG. 4C shows a driver output waveform and electric field noise waveform at dot checkered time.

  In the pixel checkered image shown in FIG. 3B, R1 of the Nth line is a positive (+) white voltage, G2 is a positive (+) black voltage, and B1 is a positive (+) white voltage. In the (N + 1) th line, R1 is a positive (+) black voltage, G2 is a positive (+) white voltage, and B1 is a positive (+) black voltage. R2 on the Nth line is a negative (−) white voltage, G1 is a negative (−) black voltage, and B2 is a negative (−) white voltage. In the (N + 1) th line, R2 is a negative (−) black voltage, G1 is a negative (−) white voltage, and B2 is a negative (−) black voltage. Therefore, in the pixel checkered image, the driver output signals (S1, S2) change as shown in FIG. 4B.

  In the dot pixel checkered image shown in FIG. 3A, R1 of the Nth line is a positive (+) white voltage, G2 is a positive (+) white voltage, and B1 is a positive (+) white voltage. In the (N + 1) th line, R1 is a positive (+) black voltage, G2 is a positive (+) black voltage, and B1 is a positive (+) black voltage. R2 on the Nth line is a negative (−) black voltage, G1 is a negative (−) black voltage, and B2 is a negative (−) black voltage. In the (N + 1) th line, R2 is a negative (−) white voltage, G1 is a negative (−) white voltage, and B2 is a negative (−) white voltage. Therefore, in the pixel checkered image, the driver output signals (S1, S2) change as shown in FIG. 4C.

  As shown in FIGS. 4B and 4C, the electric field noise is generated when each drain line fluctuates according to the driver output signals (S1, S2) at the timing of switching R, G, B.

  When the drain line changes from the Low level to the High level and from the High level to the Low level due to the change of the image data, the driver output signals (S1, S2) pass through the intermediate potential. As shown in FIG. 4B and FIG. 4C, the electric field noise of Example 1 can be reduced as compared with Comparative Example 1. Here, Comparative Example 1 indicated by a broken line in FIGS. 4B and 4C is a case where the signals (S1, S2) of the driver output do not pass through the intermediate potential.

  More specifically, in order to reduce electric field noise, an intermediate potential is passed between R1 + on the (N-1) th line and R1 + on the Nth line. In order to realize this, the R1 + image data of the (N−1) th line is held, and compared with the R1 + image data of the Nth line, an intermediate potential is determined. This operation is performed on all image data. However, this method requires a memory for one line and a comparison operation circuit, which increases the circuit scale. For this reason, as described later, only the most significant bit (MSB) of the image data of the previous line (N-1 line) and the current line (N line) is compared, and only when the MSB changes, a specific intermediate potential The circuit scale can be reduced by outputting.

  Since the drain line passes through the intermediate potential at the time of RGB pixel writing, the noise fluctuation of the drain line is dispersed, and the level of electric field noise can be reduced.

<Intermediate potential generation circuit>
Next, generation of an intermediate potential in the driver IC will be described below.
FIG. 8 is a circuit configuration diagram of the driver IC according to the first embodiment. The driver IC 15 includes an intermediate potential generation circuit 91, a gradation voltage generation circuit 92, an output buffer 151, a switch circuit SW + 1, and a terminal T1. The intermediate potential generation circuit 91 includes a register 93, a register 94, a data comparison circuit 95, a switch circuit 97, and an inverter circuit 96. The register 93 stores the MSB data of the image data of the (N−1) th line. The register 94 stores the MSB data of the Nth line image data. The switch circuit 97 is configured by connecting an n-channel MOSFET and a p-channel MOSFET in parallel. The inverter circuit 96 controls the gate of the p-channel MOSFET of the switch circuit 97. The MSB data of the (N−1) -th line image data input from the host is held in the register 93, and after the MSB data of the N-th line image data is input to the register 94, the MSB of the register 93 and the register 94 is stored. Data is compared by the data comparison circuit 95. When the MSB data match, the output of the data comparison circuit 95 is at a low level, and the switch circuit 97 is turned off. When the MSB data does not match (when the MSB data changes from 0 to 1 or from 1 to 0), the output of the data comparison circuit is at a high level and the switch circuit 97 is turned on. When the switch circuit 97 is turned on, the intermediate potential (W127) generated by the gradation voltage generation circuit 92 is output to the terminal T1. When the intermediate potential (W127) is output to the terminal T1, the switch circuit SW + 1 is in an off state. In addition, when the intermediate potential (W127) is output for a predetermined period, the output of the data comparison circuit 95 becomes a low level, and the switch circuit 97 is turned off. When the switch circuit 97 is turned off, the switch circuit SW + 1 is turned on and the original gradation voltage is output. The output buffer 152 and the switch circuit 97 connected to the terminal T2 are similarly controlled.

  A driver used in a display device that performs RGB time-division driving is equipped with a memory that holds image data, compares image data between lines, and selects and outputs an appropriate intermediate potential according to the change. Mount. When performing RGB time-division driving, the driver output signal and the drain line fluctuation do not correspond one-to-one, so that an appropriate intermediate potential cannot be selected only by changing the driver output signal. For this reason, the electric field noise generated from the display device can be suppressed by passing the intermediate potential when the drain line fluctuates by the above method.

<Modification 1>
5A, 5B, and 5C are diagrams illustrating a driving method and effects according to the first modification. FIG. 5A is a diagram illustrating a display device according to a modification. A display device 11A according to Modification 1 includes an RGB-SW circuit 14A and a driver IC 15A. The RGB-SW circuit 14A is a case where the RGB-SW circuit is a straight wiring. The RGB-SW circuit 14A has the same switch circuits 141, 142, 143, 145, 146, and 147 as the RGB-SW circuit 14, but the connection relationship with the terminals T1 and T2 of the driver IC 15 is different. That is, the switch circuits 141, 142, and 143 of the RGB-SW circuit 14A transmit the signal (S1) from the terminal T1 of the driver IC 15A, and the switch circuits 145, 146, and 147 are signals (from the terminal T2 of the driver IC 15). S2) is transmitted. The driver IC 15A has the same configuration as the driver IC 15 of FIG. 4A, but the control of the switch circuits SW + 1, SW + 2, SW-1, and SW-2 is different. The intermediate potential generation circuit of the driver IC 15A has the same configuration as that of FIG.

  Since both the pixel checkered image and the dot checkered image have the RGB-SW circuit 14A, the driver output signal (S1) changes from R1 + to G1 to B1 +... And the driver output signal (S2). Changes from R2-> G2 +-> B2-. FIG. 5B shows a pixel checkered pattern, and FIG. 5C shows a driver output waveform and electric field noise waveform at the time of dot checkered.

  In the pixel checkered image shown in FIG. 3B, R1 of the Nth line is a positive (+) white voltage, G1 is a negative (−) white voltage, and B1 is a positive (+) white voltage. In the (N + 1) th line, R1 is a positive (+) black voltage, G1 is a negative (+) black voltage, and B1 is a positive (+) black voltage. R2 on the Nth line is a negative (−) black voltage, G2 is a positive (+) black voltage, and B2 is a negative (−) black voltage. In the (N + 1) th line, R2 is a negative (−) white voltage, G2 is a positive (+) white voltage, and B2 is a negative (−) white voltage. Therefore, in the pixel checkered image, the driver output signals (S1, S2) change as shown in FIG. 4B.

  In the dot pixel checkered image shown in FIG. 3A, R1 of the Nth line is a positive (+) white voltage, G1 is a negative (−) black voltage, and B1 is a positive (+) white voltage. In the (N + 1) th line, R1 is a positive (+) black voltage, G1 is a negative (−) black voltage, and B1 is a positive (+) black voltage. R2 on the Nth line is a negative (−) black voltage, G2 is a positive (+) white voltage, and B2 is a negative (−) black voltage. In the (N + 1) th line, R2 is a negative (−) white voltage, G2 is a positive (+) black voltage, and B2 is a negative (−) white voltage. Therefore, in the pixel checkered image, the driver output signals (S1, S2) change as shown in FIG. 4C.

  As shown in FIGS. 5B and 5C, the electric field noise is generated when each drain line fluctuates in accordance with the driver output signals (S1, S2) at the timing of switching R, G, B.

  When the drain line changes from the Low level to the High level and from the High level to the Low level due to the change of the image data, the driver output signals (S1, S2) pass through the intermediate potential. As shown in FIGS. 5B and 5C, the electric field noise of the first modification can be reduced as compared with the second comparative example. Here, Comparative Example 2 indicated by a broken line in FIGS. 5B and 5C is a case where the signals (S1, S2) of the driver output do not pass through the intermediate potential.

  As can be seen from the first embodiment and the first modification, it is effective to reduce electric field noise regardless of the configuration of the RG-SW circuit.

The second embodiment is an example of pixel column inversion driving and will be described in detail below.
6A, 6B, and 6C are diagrams illustrating a driving method and effects according to the second embodiment. FIG. 6A is a diagram illustrating the display device according to the embodiment. The display device 11B according to the second embodiment includes an RGB-SW circuit 14 and a driver IC 15B. The RGB-SW circuit 14 according to the second embodiment has the same configuration as the RGB-SW circuit 14 according to the first embodiment. The driver IC 15B has the same configuration as the driver IC 15 of the first embodiment, but the control of the switch circuits SW + 1, SW + 2, SW-1, and SW-2 is different. The intermediate potential generation circuit of the driver IC 15B has the same configuration as that of FIG.

  Since both the pixel checkered image and the dot checkered image have the RGB-SW circuit 14, the driver output signal (S 1) changes from R 1 + → G 2 → B 1 +... And the driver output signal (S 2). Changes from R2-> G1 +-> B2-. FIG. 6B shows a pixel checkered pattern, and FIG. 6C shows a driver output waveform and electric field noise waveform at the time of dot checkered.

  In the pixel checkered image shown in FIG. 3B, R1 of the Nth line is a positive (+) white voltage, G2 is a negative (−) black voltage, and B1 is a positive (+) white voltage. In the (N + 1) th line, R1 is a positive (+) black voltage, G2 is a negative (+) white voltage, and B1 is a positive (+) black voltage. In the N-th line, R2 is a negative (−) black voltage, G1 is a positive (+) white voltage, and B2 is a negative (−) black voltage. In the (N + 1) th line, R2 is a negative (−) white voltage, G1 is a positive (+) black voltage, and B2 is a negative (−) white voltage. Therefore, in the pixel checkered image, the driver output signals (S1, S2) change as shown in FIG. 6B.

  In the dot pixel checkered image shown in FIG. 3A, R1 of the Nth line is a positive (+) white voltage, G2 is a negative (−) white voltage, and B1 is a positive (+) white voltage. In the (N + 1) th line, R1 is a positive (+) black voltage, G2 is a negative (−) black voltage, and B1 is a positive (+) black voltage. R2 on the Nth line is a negative (−) black voltage, G1 is a positive (+) black voltage, and B2 is a negative (−) black voltage. In the (N + 1) th line, R2 is a negative (−) white voltage, G1 is a positive (+) white voltage, and B2 is a negative (−) white voltage. Therefore, in the pixel checkered image, the driver output signals (S1, S2) change as shown in FIG. 6C.

As shown in FIGS. 6B and 6C, the electric field noise is generated when each drain line fluctuates in accordance with the driver output signals (S1, S2) at the timing of R, G, B switching.
When the drain line changes from the Low level to the High level and from the High level to the Low level due to the change of the image data, the driver output signals (S1, S2) pass through the intermediate potential. As shown in FIG. 6B and FIG. 6C, the electric field noise of Example 2 can be reduced as compared with Comparative Example 3. Here, Comparative Example 3 indicated by a broken line in FIGS. 6B and 6C is a case where the signals (S1, S2) of the driver output do not pass through the intermediate potential.

<Modification 2>
7A, 7B, and 7C are diagrams illustrating a driving method and effects according to the second modification. FIG. 7A is a diagram illustrating a display device according to a modification. A display device 11C according to the second modification includes an RGB-SW circuit 14A and a driver IC 15. The RGB-SW circuit 14A according to the second modification is a case where RGB-SW is a straight wiring, and has the same configuration as the RGB-SW circuit 14A according to the first modification. The driver IC 15 according to Modification 2 has the same configuration as the driver IC 15 according to the first embodiment.

  Since both the pixel checkered image and the dot checkered image have the RGB-SW circuit 14, the driver output signal (S 1) changes as R 1 + → G 1 + → B 1 +..., And the driver output signal (S 2) , R2-⇒G2-⇒B2-. FIG. 7B shows a pixel checkered pattern and FIG. 7C shows a driver output waveform and electric field noise waveform at the time of dot checkered.

  In the pixel checkered image shown in FIG. 3B, R1 of the Nth line is a positive (+) white voltage, G2 is a positive (+) white voltage, and B1 is a positive (+) white voltage. In the (N + 1) th line, R1 is a positive (+) black voltage, G2 is a positive (+) black voltage, and B1 is a positive (+) black voltage. R2 on the Nth line is a negative (−) black voltage, G1 is a negative (−) black voltage, and B2 is a negative (−) black voltage. In the (N + 1) th line, R2 is a negative (−) white voltage, G1 is a negative (−) white voltage, and B2 is a negative (−) white voltage. Therefore, in the pixel checkered image, the driver output signals (S1, S2) change as shown in FIG. 7B.

  In the dot pixel checkered image shown in FIG. 3A, R1 of the Nth line is a positive (+) white voltage, G2 is a positive (+) black voltage, and B1 is a positive (+) white voltage. R1 of the (N + 1) th line is a positive (+) white voltage, G2 is a positive (+) black voltage, and B1 is a positive (+) white voltage. In the Nth line, R2 is a negative (−) black voltage, G1 is a negative (−) white voltage, and B2 is a negative (−) black voltage. In the (N + 1) th line, R2 is a negative (−) white voltage, G1 is a negative (−) black voltage, and B2 is a negative (−) white voltage. Therefore, in the pixel checkered image, the driver output signals (S1, S2) change as shown in FIG. 7C.

As shown in FIGS. 7B and 7C, the electric field noise is generated when each drain line fluctuates in accordance with the driver output signals (S1, S2) at the timing of R, G, B switching.
When the drain line changes from the Low level to the High level and from the High level to the Low level due to the change of the image data, the driver output signals (S1, S2) pass through the intermediate potential. As shown in FIG. 7B and FIG. 7C, the electric field noise of Modification 2 can be reduced as compared with Comparative Example 4. Here, the comparative example 4 indicated by a broken line in FIGS. 7B and 7C is a case where the signals (S1, S2) of the driver output do not pass through the intermediate potential.

[Electric field noise generated before and after the return period]
Electric field noise also occurs before and after the retrace period. FIG. 9 is a diagram for explaining electric field noise generated before and after the blanking period. FIG. 9A shows the generation timing of electric field noise, and FIG. 9B shows the principle. In the blanking period, the driver output is set to GND or black voltage. However, when the display period is a negative white voltage (NegaW255), the drain line voltage greatly changes when the blanking period starts. . In addition, when the display period starts with a positive white voltage (PosiW255), the drain line voltage greatly changes when the display period starts. Therefore, electric field noise as shown in FIG. In addition, three electric field noises are generated before and after the blanking period, respectively.

  For example, when the driver outputs GND during the blanking period, the drain 1 has a positive voltage and the drain 2 has a negative voltage. When the switch circuit of the RGB-SW circuit 14 is a switch circuit using an n-channel TFT, when Vg rises, the on-voltage (Vgs) of the switch circuit differs between the positive signal and the negative signal, and VgsN Since the relationship is> VgsP, the drain 2 becomes GND first. As a result, a large electric field noise is generated in the positive direction. Also, when switching from the blanking period to the display period, electric field noise is generated in the negative direction for the same reason.

  FIG. 10 is a diagram showing a state in which electric field noise generated before and after the blanking period is reduced. FIG. 10A shows a period corresponding to the first one line of the blanking period, in which the R white voltage changes to GND or black voltage via the intermediate potential, and then the G white voltage passes through the intermediate potential. In this case, the voltage changes to GND or black voltage, and then the white voltage of B changes to GND or black voltage via an intermediate potential. FIG. 10A shows a period of one line at the end of the blanking period. R changes from GND or black voltage to white voltage via an intermediate potential, and then G changes from GND or black voltage to intermediate. It shows a case where the white voltage is changed via the potential, and then B is changed from the GND or black voltage to the white voltage via the intermediate potential. As a result, the electric field noise described with reference to FIG. 9 can also be reduced by a method similar to the method described with reference to FIGS. 4A, 4B, and 4C.

  FIG. 10B shows a period corresponding to the first line of the blanking period. The white voltage of R changes to an intermediate potential, then the white voltage of G changes to an intermediate potential, and then the white voltage of B changes. Change to intermediate potential, then R changes from intermediate potential to GND or black voltage, then G changes from intermediate potential to GND or black voltage, then B changes from intermediate potential to GND or black voltage Shows the case. FIG. 10B shows a period corresponding to one line at the end of the blanking period, where R changes from GND or black voltage to an intermediate potential, and then G changes from GND or black voltage to an intermediate potential. B changes from GND or black voltage to intermediate potential, and then R changes from intermediate potential to white voltage, then G changes from intermediate potential to white voltage, and then B changes from intermediate potential to intermediate potential. The case where it changes to white voltage is shown. Regarding the electric field noise in the blanking period, as shown in FIG. 10B, the noise level can be reduced even after passing through the intermediate potential for one line.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments, examples, and modifications. However, the present invention is not limited to the above-described embodiments, examples, and modifications. It goes without saying that various changes can be made.

11, 11A, 11B, 11R ... display device 12 ... display area 13L, 13R ... gate scan circuit 14, 14A ... RGB-SW circuit 141, 142, 143, 145, 146, 147,. .Switch circuit 15, 15A, 15B, 15R ... Driver IC
91 ... Intermediate potential generation circuit 92 ... Gradation voltage generation circuits 93, 94 ... Register 95 ... Data comparison circuit 97 ... Switch circuits SW + 1, SW-1, SW + 2, SW-2,. .Switch circuits T1, T2 ... terminals

Claims (14)

An intermediate potential generation circuit;
A first buffer;
A first terminal adapted to be connected to the first buffer;
First, second and third switch circuits connected to the first terminal;
A first drain line connected to the first switch circuit;
A second drain line connected to the second switch circuit;
A third drain line connected to the third switch circuit;
Have
In the intermediate potential generation circuit, the first, second and third drain lines transition from a voltage lower than the intermediate potential to a voltage higher than the intermediate potential, or from a voltage higher than the intermediate potential to a voltage lower than the intermediate potential. A display device configured to output an intermediate potential to the first terminal. The display device according to claim 1.
The intermediate potential generation circuit includes a first storage device that holds image data of the current line, and a second storage device that holds image data of one line before the current line, and the first storage device The intermediate potential is determined by comparing the contents of the device with the contents of the second storage device. The display device according to claim 2.
The intermediate potential generation circuit determines the intermediate potential by comparing the MSB of data held in the first storage device and the MSB of data held in the second storage device. . The display device of claim 1 further includes:
A second buffer;
A second terminal adapted to connect to the first and second buffers;
Fourth, fifth and sixth switch circuits connected to the second terminal;
A fourth drain line connected to the fourth switch circuit;
A fifth drain line connected to the fifth switch circuit;
A sixth drain line connected to the sixth switch circuit;
Have
The first terminal is connected to the second buffer;
The intermediate potential generation circuit transits from a voltage lower than the intermediate potential of the fourth, fifth and sixth drain lines to a voltage higher than the intermediate potential, or from a voltage higher than the intermediate potential to a voltage lower than the intermediate potential. A display device configured to output an intermediate potential to the first and second terminals. The display device according to claim 4.
The fourth drain line is disposed adjacent to the first drain line;
The second drain line is disposed adjacent to the fourth drain line;
The fifth drain line is disposed adjacent to the second drain line;
The third drain line is disposed adjacent to the fifth drain line;
The sixth drain line is disposed adjacent to the third drain line;
The first, second, third, fourth, fifth and sixth drain lines are driven so that the signal polarities of the drain lines arranged adjacent to each other are opposite. The display device according to claim 4.
The second drain line is disposed adjacent to the first drain line;
The third drain line is disposed adjacent to the second drain line;
The fourth drain line is disposed adjacent to the third drain line;
The fifth drain line is disposed adjacent to the fourth drain line;
The sixth drain line is disposed adjacent to the fifth drain line;
The first, second, third, fourth, fifth and sixth drain lines are driven so that the signal polarities of the drain lines arranged adjacent to each other are opposite. A display area;
A time-division switch circuit composed of TFTs and a driver IC;
Comprising
The display area is
A first drain line;
A second drain line disposed adjacent to the first drain line;
A third drain line disposed adjacent to the second drain line;
A fourth drain line disposed adjacent to the third drain line;
A fifth drain line disposed adjacent to the fourth drain line;
A sixth drain line disposed adjacent to the fifth drain line;
Have
The time division switch circuit is:
A first switch circuit connected to the first drain line;
A second switch circuit connected to the second drain line;
A third switch circuit connected to the third drain line;
A fourth switch circuit connected to the fourth drain line;
A fifth switch circuit connected to the fifth drain line;
A sixth switch circuit connected to the sixth drain line;
Have
The driver IC is
A first terminal connected to the first, third and fifth switch circuits;
A second terminal connected to the second, fourth and sixth switch circuits;
A first buffer adapted to be connected to the first and second terminals;
A second buffer adapted to be connected to the first and second terminals;
An intermediate potential generation circuit;
Have
The driver IC drives the first, second, third, fourth, fifth and sixth drain lines so that the signal polarities of the drain lines arranged adjacent to each other are opposite to each other. And
The intermediate potential generation circuit is configured such that the first, second, third, fourth, fifth and sixth drain lines have a voltage lower than the intermediate potential to a voltage higher than the intermediate potential, or an intermediate voltage according to input image data. A display device configured to output an intermediate potential to the first and second terminals when transitioning from a voltage higher than a potential to a voltage lower than an intermediate potential. The display device according to claim 7.
The intermediate potential generation circuit includes a first storage device that holds image data of the current line, and a second storage device that holds image data of one line before the current line, and the first storage device The intermediate potential is determined by comparing the contents of the device with the contents of the second storage device. The display device according to claim 8.
The intermediate potential generation circuit determines the intermediate potential by comparing the MSB of the data held in the first storage device with the MSB of the data held in the second storage device. . The display device according to claim 9.
The display area
A red pixel connected to the first drain line;
A green pixel connected to the second drain line;
A blue pixel connected to the third drain line;
A red pixel connected to the fourth drain line;
A green pixel connected to the fifth drain line;
A blue pixel connected to the sixth drain line;
It is made to have. A display area;
A time-division switch circuit composed of TFTs and a driver IC;
Comprising
The display area is
A first drain line;
A second drain line disposed adjacent to the first drain line;
A third drain line disposed adjacent to the second drain line;
A fourth drain line disposed adjacent to the third drain line;
A fifth drain line disposed adjacent to the fourth drain line;
A sixth drain line disposed adjacent to the fifth drain line;
Have
The time division switch circuit is:
A first switch circuit connected to the first drain line;
A second switch circuit connected to the second drain line;
A third switch circuit connected to the third drain line;
A fourth switch circuit connected to the fourth drain line;
A fifth switch circuit connected to the fifth drain line;
A sixth switch circuit connected to the sixth drain line;
Have
The driver IC is
A first terminal connected to the first, second and third switch circuits;
A second terminal connected to the fourth, fifth and sixth switch circuits;
A first buffer adapted to be connected to the first and second terminals;
A second buffer adapted to be connected to the first and second terminals;
An intermediate potential generation circuit;
Have
The driver IC drives the first, second, third, fourth, fifth and sixth drain lines so that the signal polarities of the drain lines arranged adjacent to each other are opposite to each other. And
The intermediate potential generation circuit is configured such that the first, second, third, fourth, fifth and sixth drain lines have a voltage lower than the intermediate potential to a voltage higher than the intermediate potential, or an intermediate voltage according to input image data. A display device configured to output an intermediate potential to the first and second terminals when transitioning from a voltage higher than a potential to a voltage lower than an intermediate potential. The display device according to claim 11.
The intermediate potential generation circuit includes a first storage device that holds image data of the current line, and a second storage device that holds image data of one line before the current line, and the first storage device The intermediate potential is determined by comparing the contents of the device with the contents of the second storage device. The display device of claim 12,
The intermediate potential generation circuit determines the intermediate potential by comparing the MSB of the data held in the first storage device with the MSB of the data held in the second storage device. . The display device of claim 12,
The display area
A red pixel connected to the first drain line;
A green pixel connected to the second drain line;
A blue pixel connected to the third drain line;
A red pixel connected to the fourth drain line;
A green pixel connected to the fifth drain line;
A blue pixel connected to the sixth drain line;
It is made to have.

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