JP2015046130A5 - - Google Patents

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Publication number
JP2015046130A5
JP2015046130A5 JP2013178320A JP2013178320A JP2015046130A5 JP 2015046130 A5 JP2015046130 A5 JP 2015046130A5 JP 2013178320 A JP2013178320 A JP 2013178320A JP 2013178320 A JP2013178320 A JP 2013178320A JP 2015046130 A5 JP2015046130 A5 JP 2015046130A5
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JP
Japan
Prior art keywords
processing
memory
synchronization signal
access
control means
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2013178320A
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English (en)
Japanese (ja)
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JP2015046130A (ja
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Publication date
Application filed filed Critical
Priority to JP2013178320A priority Critical patent/JP2015046130A/ja
Priority claimed from JP2013178320A external-priority patent/JP2015046130A/ja
Priority to US14/459,406 priority patent/US20150066854A1/en
Publication of JP2015046130A publication Critical patent/JP2015046130A/ja
Publication of JP2015046130A5 publication Critical patent/JP2015046130A5/ja
Pending legal-status Critical Current

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JP2013178320A 2013-08-29 2013-08-29 データ処理装置、その制御方法およびプログラム Pending JP2015046130A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2013178320A JP2015046130A (ja) 2013-08-29 2013-08-29 データ処理装置、その制御方法およびプログラム
US14/459,406 US20150066854A1 (en) 2013-08-29 2014-08-14 Data processing apparatus and its control method and program

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2013178320A JP2015046130A (ja) 2013-08-29 2013-08-29 データ処理装置、その制御方法およびプログラム

Publications (2)

Publication Number Publication Date
JP2015046130A JP2015046130A (ja) 2015-03-12
JP2015046130A5 true JP2015046130A5 (cg-RX-API-DMAC7.html) 2016-09-23

Family

ID=52584671

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2013178320A Pending JP2015046130A (ja) 2013-08-29 2013-08-29 データ処理装置、その制御方法およびプログラム

Country Status (2)

Country Link
US (1) US20150066854A1 (cg-RX-API-DMAC7.html)
JP (1) JP2015046130A (cg-RX-API-DMAC7.html)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9753522B2 (en) 2015-03-02 2017-09-05 Sandisk Technologies Llc Dynamic clock rate control for power reduction
US9467150B2 (en) * 2015-03-02 2016-10-11 Sandisk Technologies Llc Dynamic clock rate control for power reduction
JP2020027520A (ja) 2018-08-15 2020-02-20 セイコーエプソン株式会社 制御装置、表示装置、メモリーの制御方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5640202A (en) * 1994-04-26 1997-06-17 Canon Kabushiki Kaisha Imaging system which changes the frame rate of the image signal
US7113208B1 (en) * 1998-02-24 2006-09-26 Canon Kabushiki Kaisha Image processing apparatus, image processing method and recording medium
JP2004062333A (ja) * 2002-07-25 2004-02-26 Sharp Corp 画像処理装置
JP4436367B2 (ja) * 2004-06-24 2010-03-24 パナソニック株式会社 低バンド幅で局所集中アクセスを保証する調停装置、調停方法、及び調停装置を含む動画処理装置
JP2006252341A (ja) * 2005-03-11 2006-09-21 Canon Inc 電子機器、制御方法、及びコンピュータプログラム
JP2007334641A (ja) * 2006-06-15 2007-12-27 Sony Corp 情報処理装置および方法、並びにプログラム
JP2008158764A (ja) * 2006-12-22 2008-07-10 Toshiba Corp メモリアクセス制御方法
JP5424726B2 (ja) * 2009-06-05 2014-02-26 オリンパス株式会社 撮像装置

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