JP2015035780A - Signal transmission circuit and semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a signal transmission circuit and a semiconductor integrated circuit that have a reduced circuit scale and power consumption without compromising a transmission rate and a transmission band.SOLUTION: The signal transmission circuit has: a plurality of pre-drivers 31a, 31b-34a, 34b for preprocessing received input data din1, din1x-din4, din4x; a plurality of final stage drivers 41-44 for generating output data dout, doutx according to outputs of the plurality of pre-drivers; an output monitor circuit 1 for monitoring the outputs of the final stage drivers; and a regulator circuit 2 (21-24) for controlling supply voltages pvdd1, pvss1-pvdd4, pvss4 applied to the pre-drivers 31a, 31b-34a, 34b, respectively, according to an output of the output monitor circuit.

Description

  The embodiments referred to in this specification relate to a signal transmission circuit and a semiconductor integrated circuit.

  In recent years, the performance of components applied to computers and other information processing devices has been remarkably improved. For example, the performance improvement of semiconductor memory devices such as SRAM (Static Random Access Memory) and DRAM (Dynamic Random Access Memory), and CPU (Central Processing Unit) and switching LSI (Large Scale Integration) is remarkable. There is something.

  As the performance of these semiconductor storage devices, processors, and the like is improved, it is difficult to improve the performance of the system unless the signal transmission speed between each component or component is improved. .

  That is, the signal transmission speed between the main storage device such as a DRAM and a processor, between servers via a network, between boards (printed wiring boards), between semiconductor chips, or between elements and circuit blocks in one chip. Improvement is important.

  By the way, as a final stage driver of a signal transmission circuit (transmitter), the use is shifted from a CML (Current Mode Logic) driver to an SST (Source Series Terminated) driver because data can be transmitted with low power consumption. It is coming. Such a signal transmission circuit is provided with a pre-emphasis function for compensating for attenuation characteristics in the signal transmission path, for example.

  For example, in an SST driver having a pre-emphasis function, the impedance adjustment function for termination required for the final stage driver and the driver strength adjustment function for pre-emphasis are controlled by activating the number of SST cells having the same configuration. It is realized by.

  Therefore, the circuit scale becomes large because a large number of SST cells are provided, and a large amount of power is consumed for buffering a pre-driver for driving these SST cells. Furthermore, since the load capacity at the output end to which the SST cell is connected increases, there is a possibility that the transmission speed and transmission band of the signal transmission circuit are deteriorated.

  By the way, conventionally, various types of signal transmission circuits with low power consumption and high speed and wide bandwidth have been proposed.

JP 2007-251469 A

Kosuke Suzuki, et al., "A 24-Gb / s Source-Series Terminated Driver with Inductor Peaking in 28-nm CMOS," IEEE Asian Solid-State Circuits Conference, Kobe, Japan, pp.137-140 (5-3 ), November 12-14, 2012

  As described above, for example, an SST driver having a pre-emphasis function may cause an increase in circuit scale and a deterioration in signal transmission speed and transmission band.

  Therefore, for example, the resistance by the symmetrical load of nMOS / pMOS is used, the difference between the power supply / ground of the pre-driver and the final stage driver is adjusted to adjust the resistance value, and the number of slicers is adjusted by the impedance adjustment of the terminal. Something to remove.

  Alternatively, it is also possible to delete the number of slicers by the amount corresponding to the driver strength adjustment by performing the driver strength adjustment for pre-emphasis only by the resistance value.

  However, in the former method, it is difficult to generate a double or half resistance value using a symmetric load, so that the strength of pre-emphasis is adjusted using a large number of slicers, and the circuit scale is reduced. Reduction will be limited.

  Even in the latter method, in order to satisfy both the pre-emphasis intensity adjustment and the impedance adjustment at the same time, a plurality of slicers are prepared in order to change the number of activations for each slicer. Therefore, the number of SST driver cells (slicers) is still increased, and the load capacity at the output end of the signal transmission circuit is also increased.

  According to one embodiment, a plurality of pre-drivers that receive input data and perform preprocessing, a plurality of final-stage drivers that generate output data according to outputs of the plurality of pre-drivers, an output monitor circuit, and a regulator circuit A signal transmission circuit is provided.

  The output monitor circuit monitors the output of the final stage driver, and the regulator circuit controls a power supply voltage applied to each pre-driver according to the output of the output monitor circuit.

  The disclosed signal transmission circuit and semiconductor integrated circuit have the effect of reducing the circuit scale and power consumption without sacrificing the transmission speed and transmission band.

FIG. 1 is a block diagram showing the overall configuration of a signal transmission circuit with a pre-emphasis function. FIG. 2 is a diagram for explaining an example of the signal transmission circuit. FIG. 3 is a diagram for explaining another example of the signal transmission circuit. FIG. 4 is a diagram for explaining still another example of the signal transmission circuit. FIG. 5 is a block diagram showing the signal transmission circuit of this embodiment. FIG. 6 is a block diagram showing a first embodiment of the output monitor circuit. FIG. 7 is a flowchart for explaining an example of the operation of the output monitor circuit shown in FIG. FIG. 8 is a block diagram showing a second embodiment of the output monitor circuit. FIG. 9 is a block diagram showing a third embodiment of the output monitor circuit. FIG. 10 is a block diagram showing an example of a semiconductor integrated circuit to which the signal transmission circuit of this embodiment is applied.

  First, before describing embodiments of a signal transmission circuit and a semiconductor integrated circuit in detail, an example of a signal transmission circuit with a pre-emphasis function and its problems will be described with reference to FIGS.

  FIG. 1 is a block diagram showing the overall configuration of a signal transmission circuit with a pre-emphasis function. In FIG. 1, reference numerals 100 and 300 are semiconductor integrated circuits, 110 is a signal transmission circuit (transmitter), 200 is a signal transmission path, and 310 is a signal reception circuit (receiver).

  As shown in FIG. 1, the signal transmission circuit 110 with a pre-emphasis function is provided in the semiconductor integrated circuit 100 and transmits data to the signal receiving circuit 310 provided in the semiconductor integrated circuit 300 via the signal transmission path 200. To do.

  The signal transmission circuit 110 includes a signal conversion unit 101, a multiplexer unit 102, a pre-driver unit 103, and a final stage driver unit (SST (Source Series Terminated) driver unit) 104. In the present specification, an example in which four taps (Tap1 to Tap4) are provided will be described as an example, but needless to say, the number of taps is not limited to four.

  For example, the signal conversion unit 101 receives the parallel signal Din, operates in synchronization with the clock signal CLK, and controls the delay time and polarity inversion for each of the taps Tap1 to Tap4 to output to the multiplexer unit 102.

  The multiplexer unit 102 includes four multiplexers 121 to 124 provided for the taps Tap1 to Tap4, respectively. Each of the multiplexers 121 to 124 operates in synchronization with the clock signal CLK, sequentially selects one of the input parallel signals, performs parallel-serial conversion, and converts the converted serial data din1 to din4 into a pre-driver unit. To 103.

  The pre-driver unit 103 includes four pre-drivers 131 to 134 that receive and amplify the serial data din1 to din4. The pre-drivers 131 to 134 drive the final stage drivers 141 to 144 in the final stage driver unit 104, respectively.

  The outputs of the final stage drivers 141 to 144 are collected and transmitted as serial data Dout to the signal receiving circuit 310 provided in the semiconductor integrated circuit 300 via the signal transmission path 200.

  Here, the semiconductor integrated circuits 100 and 300 may be the same semiconductor integrated circuit. In this case, the signal transmission path 200 is also provided in the semiconductor integrated circuit 100 (300), and data from the circuit block including the signal transmission circuit 110 is transmitted to the circuit block including the signal receiving circuit 310 via the signal transmission path 200. Will be.

  The signal transmission circuit 110 and the signal reception circuit 310 are used for data transmission within the same circuit board, or data transmission between different circuit boards such as between daughter cards (daughter boards) via a backplane. You may apply. Furthermore, the signal transmission circuit 110 and the signal reception circuit 310 can also be applied to data transmission between different devices such as between servers.

  2 is a diagram for explaining an example of a signal transmission circuit, FIG. 2 (a) is a diagram showing an example of a driver circuit (SST driver circuit), and FIG. 2 (b) is a diagram of FIG. It is a figure for demonstrating the impedance adjustment and pre-emphasis intensity | strength adjustment by the driver circuit shown to a).

  As shown in FIG. 2A, the SST driver circuit includes a plurality of SST cells CE each having a pre-driver 130 and a final-stage driver 140. 2A shows a circuit for one tap. For example, in the case of four taps Tap1 to Tap4, four circuit configurations in FIG. 2A are provided. Become.

  As shown in FIG. 2A, the pre-driver 130 includes a NAND gate NAND1, a NOR gate NOR1, and an inverter I1, and the final stage driver 140 includes a pMOS transistor Tp1, an nMOS transistor Tn1, and a resistor R1.

  Here, an enable signal en for activating the circuit is input to one input of the NAND gate NAND1, and a signal (enx) obtained by inverting the enable signal en by the inverter I1 is input to one input of the NOR gate NOR1. . Input data din is input to the other inputs of NAND1 and NOR1.

  The source of the pMOS transistor Tp1 is connected to the high potential power supply line Vdd, the source of the nMOS transistor Tn1 is connected to the low potential power supply line Vss, and the drains of Tp1 and Tn1 are commonly connected to one end of the resistor R1.

  The gate of Tp1 is supplied with the output of NAND1, the gate of Tn1 is supplied with the output of NOR1, and the other end of the resistor R1 is commonly connected to the other ends of the resistors in the other SST cells CE. From there, output data dout is output.

  The SST cell CE has an output resistance value defined by, for example, the resistance value when the transistors Tp1 and Tn1 operate and the resistance value of the resistor R1, and Tp1 and Tn1 operate in a complementary manner. The output resistance value is made constant.

  As shown in FIG. 2B, the SST driver circuit has, for example, an impedance adjustment function for termination required for the final stage driver of the signal transmission circuit and a driver strength adjustment function for pre-emphasis having the same configuration. The number of SST cells CE is activated. Here, reference symbols α, β, γ, and ε indicate pre-emphasis parameters.

  As shown in FIG. 2A and FIG. 2B, the SST driver circuit includes a large number of SST cells CE in order to perform impedance adjustment and pre-emphasis intensity adjustment according to the number of activations of the SST cells CE. become.

  Therefore, the circuit scale of the SST driver circuit (signal transmission circuit) is increased, and a large amount of power is consumed for buffering the pre-driver for driving a large number of SST cells CE. Furthermore, since the load capacity at the output end to which the SST cell is connected increases, there is a possibility that the transmission speed and transmission band of the signal transmission circuit are deteriorated.

  FIG. 3 is a diagram for explaining another example of the signal transmission circuit, FIG. 3A is a diagram showing another example of the SST driver circuit, and FIG. 3B is a diagram showing FIG. It is a figure for demonstrating pre-emphasis intensity | strength adjustment by the SST driver circuit shown to a).

  As shown in FIG. 3A, the SST driver circuit has a differential configuration of an nMOS transistor and a pMOS transistor, and the regulator 105 controls the power supply voltages pvdda and pvssa for the pre-drivers (130a and 130b). It has become.

  That is, the pre-driver 130 includes a pre-driver unit 130a that processes a positive logic input signal din and a pre-driver unit 130b that processes a negative logic input signal dinx, and drives a symmetric load type final stage driver 140. To do.

  Here, the predriver units 130a and 130b have the same circuit configuration as the predriver 130 shown in FIG. 2A described above, and include NAND gates NAND1a and NAND1b, NOR gates NOR1a and NOR1b, and inverters I1a and I1b.

  The final stage driver 140 substantially corresponds to the predriver units 130a and 130b that process the differential (complementary) input signals din and dinx, and the final stage driver (Tp1,1) shown in FIG. Two Tn1) are included.

  Further, by connecting n and pMOS transistors of opposite conductivity type in parallel to the p and nMOS transistors Tp1 and Tn1 and providing a differential signal to their gates, nonlinear characteristics are compensated. Yes.

  That is, the source of the pMOS transistor Tp11a is connected to the high potential power supply line Vdd, the source of the nMOS transistor Tn12a is connected to the low potential power supply line Vss, and the output dout is extracted from the drains of Tp11a and Tn12a. . Here, the output of NAND1a in the positive logic pre-driver unit 130a is given to the gate of Tp11a, and the output of NOR1a is given to the gate of Tn12a.

  An nMOS transistor Tn11a is connected in parallel between the source and drain of the transistor Tp11a, and a pMOS transistor Tp12a is connected in parallel between the source and drain of the transistor Tn12a. Here, the output of NOR1b in the negative logic pre-driver unit 130b is given to the gate of Tn11a, and the output of NAND1b is given to the gate of Tp12a.

  Similarly, the source of the pMOS transistor Tp11b is connected to the high potential power supply line Vdd, the source of the nMOS transistor Tn12b is connected to the low potential power supply line Vss, and the output dout is extracted from the drains of Tp11b and Tn12ba. Yes. Here, the output of NAND1b in the negative logic pre-driver unit 130b is given to the gate of Tp11b, and the output of NOR1b is given to the gate of Tn12b.

  An nMOS transistor Tn11b is connected in parallel between the source and drain of the transistor Tp11b, and a pMOS transistor Tp12b is connected in parallel between the source and drain of the transistor Tn12b. Here, the output of NOR1a in the positive logic pre-driver unit 130a is given to the gate of Tn11b, and the output of NAND1a is given to the gate of Tp12b.

  The regulator 105 performs impedance adjustment by controlling the high potential power supply voltage (first power supply voltage) pvdda and the low potential power supply voltage (second power supply voltage: ground voltage) pvssa for the pre-driver units 130a and 130b.

  That is, the driver circuit shown in FIG. 3A and FIG. 3B uses the resistance of the symmetric load type SST driver (final stage driver) 140, and the pre-drivers (130a, 130b) and the final stage driver 140 are used. The resistance value is adjusted by creating a difference between the power supply / ground of the power supply.

  As a result, impedance adjustment at the end of the driver circuit (signal transmission circuit) is performed, and the number of SST cells CE (slicers) described with reference to FIGS. 2 (a) and 2 (b) is reduced. .

  However, it is difficult to generate a resistance value of a predetermined relationship (for example, double or half) using a symmetric load, and the strength of pre-emphasis is adjusted using a large number of SST cells CE. The reduction in circuit scale is limited.

  FIG. 4 is a diagram for explaining still another example of the signal transmission circuit, FIG. 4A is a diagram showing still another example of the SST driver circuit, and FIG. It is a figure for demonstrating the pre-emphasis intensity | strength adjustment by the SST driver circuit shown to 4 (a).

  In FIG. 4A, reference numeral 106 denotes a basic code generation circuit, 107 denotes a buffer, and 108 denotes a weight control circuit. The basic code generation circuit 106 includes a calibration resistor 161 and a logic circuit 162, generates a basic code, and outputs the basic code to the weight control circuit 108 via the buffer 107.

  The weight control circuit 108 adjusts the pre-emphasis intensity by controlling the weights of the SST drivers 141 to 144 of the final stage driver unit (SST driver unit) 104. Specifically, in FIG. 4A, the weight of the SST driver 141 is “1”, the weight of the SST driver 142 is “3”, the weight of the SST driver 143 is “10”, and the weight of the SST driver 144 is “ 2 ”is shown.

  Here, a large number of SST drivers 141 to 144 are provided, and the number of SST drivers to be activated is controlled in order to adjust the impedance at the end of the signal transmission circuit.

  Also in the driver circuits shown in FIGS. 4A and 4B, in order to satisfy the pre-emphasis intensity adjustment and the impedance adjustment at the same time, the number of activated SST drivers 141 to 144 (slicers) is changed. A plurality of SST drivers are prepared. Therefore, the circuit scale of the driver circuit still increases, and the load capacity at the output end of the signal transmission circuit also increases.

  Hereinafter, the signal transmission circuit and the semiconductor integrated circuit of the present embodiment will be described in detail with reference to the accompanying drawings. FIG. 5 is a block diagram showing the signal transmission circuit of this embodiment. In FIG. 5, reference numeral 1 is an output monitor circuit, 2 is a regulator circuit, 31a, 31b to 34a and 34b are pre-driver units, and 41 to 44 are final stage drivers (SST drivers).

  The pre-driver units 31a, 31b to 34a, 34b receive differential (complementary) input data din1, din1x to din4, din4x and drive the corresponding final stage drivers 41 to 44 in the subsequent stages. Pre-processing is performed.

  For example, the pre-driver units 31 a and 31 b receive the differential input data din 1 and din 1 x and generate signals for driving the final stage driver 41. Further, for example, the pre-driver units 32a and 32b receive the differential input data din2 and din2x and generate signals for driving the final stage driver 42. Each of the predriver units 31a, 31b to 34a, 34b has the same circuit configuration as the predriver units 130a, 130b described with reference to FIG.

  That is, the predriver units 31a to 34a that receive the positive logic data din1 to din4 include the NAND gate NAND1a, the NOR gate NOR1a, and the inverter I1a, similarly to the predriver unit 130a.

  Similarly to the pre-driver unit 130b, the pre-driver units 31b to 34b that receive the negative logic data din1x to din4x include a NAND gate NAND1b, a NOR gate NOR1b, and an inverter I1b.

  Here, the enable signals en1 to en4 for controlling the activation of the circuits are input to the pre-driver units 31a, 31b to 34a and 34b, respectively, and adjustment processing is performed by sequentially switching taps (Tap1 to Tap4) as will be described later. Is supposed to do.

  The final stage drivers 41 to 44 have the same circuit configuration as that of the symmetric load type SST driver 140 described with reference to FIG. 3A, respectively, and the final stage drivers 41 to 44 are pre-emphasis drivers. Includes resistances corresponding to the parameters α, β, γ, ε.

  For example, the final stage driver 41 includes pMOS transistors Tp11a, Tp12a, Tp11b, Tp12b, nMOS transistors Tn11a, Tn12a, Tn11b, Tn12b, and resistors R11a, R11b having resistance values corresponding to the parameter α.

  The resistance (R11a, R11b) of the final stage driver 42 has a resistance value corresponding to the parameter β, the resistance of the final stage driver 43 has a resistance value corresponding to the parameter γ, and the resistance of the final stage driver 42 is And a resistance value corresponding to the parameter ε.

  The output monitor circuit 1 monitors the outputs of the final stage drivers 41 to 44, that is, the outputs dout and doutx of the signal transmission circuit, and supplies power to the pre-driver unit sets 31 a, 31 b to 34 a and 34 b via the regulator circuit 2. The voltages pvdd1, pvss1 to pvdd4, pvss4 are controlled. Each set of pre-driver units 31a, 31b to 34a, 34b drives the final stage drivers 41 to 44 at the subsequent stage, respectively.

  The regulator circuit 2 includes four regulators 21 to 24 provided corresponding to a group of four (plural) predriver units (four tap predrivers) 31a, 31b to 34a, 34b.

  Each of the regulators 21 to 24 has a high potential (first) power supply voltage pvdd1 to pvdd4 and a low potential (second) power supply applied to the respective pre-drivers 31a, 31b to 34a, 34b in accordance with a control signal from the output monitor circuit 1. Control the voltages pvss1 to pvss4.

  Here, the regulator circuit 2 controls, for example, one or both of the high potential power supply voltage (power supply voltage) pvdd1 and the low potential power supply voltage (ground voltage GND) pvss1 of the set 31a and 31b of the predriver unit. That is, at least one is controlled. This makes it possible to perform pre-emphasis intensity adjustment and impedance adjustment.

  For pre-emphasis intensity adjustment and impedance adjustment, for example, as a calibration process at the time of power-on, a set of pre-driver units is selected in order, and the respective high potential and low potential power supply voltages pvdd1, pvss1 to pvdd4, pvss4 are set. Set and do.

  As described above, according to the signal transmission circuit of the present embodiment, the load capacity at the output end can be reduced, high-speed signal transmission is possible in a wide band, and the number of drivers (slicers) is further reduced. Therefore, the circuit scale and power consumption can be reduced.

  FIG. 6 is a block diagram showing a first embodiment of the output monitor circuit (signal transmission circuit), which is shown together with the regulator circuit. Note that the pre-driver units 31a, 31b to 34a and 34b and the output stage drivers (SST drivers) 41 to 44 are the same as those described with reference to FIG. 5, and are omitted in FIG.

  In FIG. 6, the regulators 21 to 24 described with reference to FIG. 5 described above are divided into first regulators 21 a to 24 a and second regulators 21 b to 24 b.

  That is, the first regulators 21a to 24a apply the controlled high-potential power supply voltages pvdd1 to pvdd4 to the pre-driver unit sets 31a, 31b to 34a, 34b. The second regulators 21b to 24b apply controlled low-potential power supply voltages pvss1 to pvss4 to the pre-driver unit sets 31a, 31b to 34a, and 34b.

  As shown in FIG. 6, the output monitor circuit 1 includes a reference voltage generation circuit 11, a first comparator 12a, a second comparator 12b, a first control circuit 13a, a second control circuit 13b, and a first digital / analog conversion. A first DAC 14a and a second DAC 14b.

  Here, the resistor R10a is a resistor (first resistor) for converting the positive logic output dout of the differential output data into the voltage Vout, and the resistor R10b is a negative logic output doutx of the differential output data. Is a resistor (second resistor) for converting the voltage into a voltage Voutx.

  The reference voltage generation circuit 11 generates a first reference voltage Vr1 and a second reference voltage Vr2, supplies the first reference voltage Vr1 to the first comparator 12a, and supplies the second reference voltage Vr2 to the second comparator 12b. .

  The first comparator 12a compares the first reference voltage Vr1 with the positive logic output voltage Vout converted by the resistor R10a, and outputs the comparison result to the first control circuit 13a. The second comparator 12b compares the second reference voltage Vr2 with the negative logic output voltage Voutx converted by the resistor R10b, and outputs the comparison result to the second control circuit 13b.

  The first control circuit 13a generates a first digital control code for controlling the high potential power supply voltages (power supply voltages) pvdd1 to pvdd4 for each set of pre-driver units according to the output of the first control circuit 13a, and generates the first DAC 14a. Output to.

  The first DAC 14a converts the first digital control code from the first control circuit 13a into an analog signal and outputs it to the first regulators 21a to 24a to control the output voltages pvdd1 to pvdd4 of the first regulators 21a to 24a.

  The second control circuit 13b generates a second digital code for controlling the low-potential power supply voltages (ground voltages) pvss1 to pvss4 for each set of pre-driver units according to the output of the second control circuit 13b, and supplies the second digital code to the second DAC 14b. Output.

  The second DAC 14b converts the second digital control code from the second control circuit 13b into an analog signal and outputs it to the second regulators 21b to 24b to control the output voltages pvss1 to pvss4 of the second regulators 21b to 24b.

  In the output monitor circuit of the first embodiment shown in FIG. 6, for example, as a calibration process at the time of power-on, a set of pre-driver units is sequentially selected, and the high potential and low potential power supply voltages pvdd1, pvss1 to pvdd4, Set pvss4.

  That is, each set of the pre-driver units 31a, 31b to 34a, 34b is sequentially selected for each tap, and the reference voltages Vr1, Vr2 generated by the reference voltage generation circuit 11 are the final stage driver 41 of the selected tap. To the value required for ~ 44. Here, the resistors R10a and R10b for extracting the output voltages Vout and Voutx from the differential output data dout and doutx can be fixed resistors.

  Alternatively, the resistors R10a and R10b may be variable resistors, and the resistance values of the resistors R10a and R10b may be adjusted to values required for the final stage drivers 41 to 44 of the selected tap. At this time, the first reference voltage Vr1 and the second reference voltage Vr2 from the reference voltage generation circuit 11 can be fixed voltages.

  Then, for each selected tap, the first and second regulators 21a, 21b to 24a and 24b are controlled to switch and set the high potential and low potential power supply voltages pvdd1, pvss1 to pvdd4 and pvss4. Thereby, intensity adjustment and impedance adjustment of pre-emphasis of the signal transmission circuit can be performed.

  FIG. 7 is a flowchart for explaining an example of the operation of the output monitor circuit shown in FIG. As shown in FIG. 7, when the adjustment process by the output monitor circuit starts, first, in step ST1, the tap pre-driver adjusted by the control circuit is activated, and the resistance value of the SST driver (final stage driver) is maximized. adjust.

  That is, in step ST1, the first and second control circuits 13a and 13b control the enable signal en1 to activate the pre-driver units 31a and 31b corresponding to the tap Tap1 to be adjusted. Further, the resistance value of the SST driver 41 driven by the pre-driver units 31a and 31b is adjusted to the maximum.

  Next, the process proceeds to step ST2, and the reference voltage / resistance value required for the tap adjusted by the control circuit is adjusted.

  That is, in step ST2, the first control circuit 13a controls the reference voltage generation circuit 11 to tap the first reference voltage Vr1 applied to the first comparator 12a and the second reference voltage Vr2 applied to the second comparator 12b. Adjust to the value required for Tap1. At this time, the resistors R10a and R10b for extracting the output voltages Vout and Voutx from the differential output data dout and doutx can be fixed resistors.

  Alternatively, the resistors R10a and R10b may be variable resistors, and the resistance values of the resistors R10a and R10b may be adjusted to the values required for the tap Tap1 by the first control circuit 13a. At this time, the first reference voltage Vr1 and the second reference voltage Vr2 from the reference voltage generation circuit 11 can be fixed voltages.

  In step ST3, the output voltage of the SST driver is compared with the reference voltage to determine whether the resistance value of the SST driver is large or small. That is, in step ST3, the first comparator 12a compares the positive logic output voltage Vout voltage-converted by the resistor R10a with the reference voltage Vr1, and if the output voltage Vout is larger than the reference voltage Vr1, the process proceeds to step ST4. If so, the process proceeds to step ST5.

  In step ST3, the negative comparator output voltage Voutx converted by the resistor R10b is compared with the reference voltage Vr2 by the second comparator 12b. If the output voltage Voutx is greater than the reference voltage Vr2, the process proceeds to step ST4, where the output voltage Voutx is smaller. If so, the process proceeds to step ST5.

  In step ST4, the power supply voltage / ground voltage of the pre-driver is adjusted, the resistance value of the SST driver is lowered, and the process returns to step ST3. That is, in step ST4, the first and second control circuits 13a and 13b are connected to the power supply voltage (high potential power supply voltage) pvdd1 and the ground voltage (low potential power supply voltage) pvss1 output from the first and second regulators 21a and 21b. Is adjusted to lower the resistance value of the SST driver 41. In step ST3, the same processing is repeated until it is determined that the output voltage Voutx is smaller than the reference voltage Vr2.

  In step ST5, it is determined whether or not all the taps have been adjusted. If it is determined that all the taps have not been adjusted, processing for the next tap is performed. That is, in step ST5, the adjustment of the power supply voltage pvdd1 and the ground voltage pvss1 at the tap Tap1 is completed. . If it is determined in step ST5 that all taps have been adjusted, the process is terminated.

  FIG. 8 is a block diagram showing a second embodiment of the output monitor circuit (signal transmission circuit). As is apparent from the comparison between FIG. 8 and FIG. 6 described above, in the output monitor circuit of the second embodiment, a logical product that takes the logical product (AND) of the output of the first comparator 12a and the output of the second comparator 12b. A circuit 15 is provided, and the first and second control circuits 13 a and 13 b are used as one integrated control circuit 13.

  The output of the integrated control circuit 13 is output to the first DAC 14a and the second DAC 14b, and the power supply voltages pvdd1 to pvdd4 output from the first regulators 21a to 24a and the ground voltages pvss1 to pvss4 output from the second regulators 21b to 24b, respectively. Control.

  That is, in the output monitor circuit of the second embodiment, if either of the first comparator output and the second comparator output does not satisfy the condition, the processing is continued (proceeds to step ST4 in FIG. 7). It has become.

  Note that the logical product circuit 15 in FIG. 8 is a logical sum circuit, and if one of the outputs of the first comparator or the second comparator satisfies the condition, the process of the tap is finished (proceed to step ST5 in FIG. ) Can also be done.

  As described above, according to the output monitor circuit of the second embodiment, it is possible to reduce the circuit scale and the occupied area of the circuit and reduce the power consumption by integrating the control circuit into one. .

  FIG. 9 is a block diagram showing a third embodiment of the output monitor circuit (signal transmission circuit). As is clear from the comparison between FIG. 9 and FIG. 8, in the output monitor circuit of the third embodiment, the first DAC 14a and the first regulators 21a to 24a and the second DAC 14b and the second regulators 21b to 24b 1 and second coefficient circuits 16a and 16b are provided.

  Here, in the output monitor circuit of the third embodiment, the power supply voltage applied to each pre-driver and the ground voltages pvdd1, pvss1 to pvdd4, pvss4 have a predetermined relationship, that is, a predetermined ratio (for example, 1 : 3: 10: 2).

  That is, when the power supply voltage and the ground voltage pvdd1, pvss1 to pvdd4, pvss4 have a predetermined relationship, for example, the power supply voltage and the ground voltage pvdd1, pvss1 are adjusted, and the other power supply voltage and ground voltage pvdd2, pvss2 ~ Pvdd4 and pvss4 are adjusted by multiplying by coefficients.

  Therefore, the output monitor circuit of the third embodiment does not perform the process for all the taps in order in step ST5 of the flowchart shown in FIG. It is used for tap processing.

  As a result, the time required for adjusting the power supply voltage and the ground voltages pvdd1, pvss1 to pvdd4, pvss4 performed for each tap can be greatly reduced. In FIG. 9, the coefficient circuits 16a and 16b are shown as an example, but this is not a coefficient circuit but an LUT (Look Up Table), and signals corresponding to the outputs of the DACs 14a and 14b are supplied to the regulators 21a, 21b to 21b. You may make it output to 24a, 24b.

  FIG. 10 is a block diagram showing an example of a semiconductor integrated circuit to which the signal transmission circuit of this embodiment is applied, and shows a switch chip.

  As shown in FIG. 10, the signal transmission circuit 401 of this embodiment can be applied to the switch chip 400. The switch chip 400 further includes a signal receiving circuit 402 and a signal processing circuit (CPU) 403.

  The signal reception circuit 402 receives a signal (reception signal) transmitted from the outside of the switch chip 400, and the signal processing circuit 403 processes the reception signal received via the signal reception circuit 402 and also transmits the signal transmission circuit 401. A transmission signal to be transmitted via is generated.

  Note that the application of the signal transmission circuit of the present embodiment is not limited to the switch chip 400 shown in FIG. 10, but various semiconductor integrated circuit signal transmission circuits, I / O circuits (input / output circuits), and the like. Can be widely applied.

  The signal transmission circuit of the present embodiment is applied to data transmission between different circuit boards such as data transmission within the same circuit board or between daughter cards (daughter boards) via a backplane. May be. Furthermore, the signal transmission circuit of this embodiment can also be applied to data transmission between different devices such as between servers.

  Although the embodiment has been described above, all examples and conditions described herein are described for the purpose of helping understanding of the concept of the invention applied to the invention and the technology. It is not intended to limit the scope of the invention. Nor does such a description of the specification indicate an advantage or disadvantage of the invention. Although embodiments of the invention have been described in detail, it should be understood that various changes, substitutions and modifications can be made without departing from the spirit and scope of the invention.

Regarding the embodiment including the above examples, the following supplementary notes are further disclosed.
(Appendix 1)
Multiple pre-drivers that receive input data and perform pre-processing;
A plurality of final stage drivers for generating output data in accordance with the outputs of the plurality of pre-drivers;
An output monitor circuit for monitoring the output of the final stage driver;
A regulator circuit for controlling a power supply voltage applied to each of the pre-drivers according to the output of the output monitor circuit,
A signal transmission circuit characterized by that.

(Appendix 2)
The regulator circuit is:
A plurality of regulators provided corresponding to the plurality of pre-drivers;
Each said regulator is
Controlling at least one of a first power supply voltage and a second power supply voltage applied to a corresponding one of the plurality of pre-drivers according to an output of the output monitor circuit;
The signal transmission circuit according to appendix 1, wherein:

(Appendix 3)
The output monitor circuit includes:
A comparator that compares the output voltage of the final stage driver with a reference voltage;
A control circuit that controls a control signal output to the regulator according to an output of the comparator and controls at least one of the first power supply voltage and the second power supply voltage;
The signal transmission circuit according to appendix 2, wherein

(Appendix 4)
The input data is differential input data,
The pre-driver is
A first pre-driver unit for processing positive logic data of the differential input data;
A second pre-driver unit that processes negative logic data of the differential input data.
The signal transmission circuit according to appendix 1 or appendix 2, characterized in that.

(Appendix 5)
The regulator is
A plurality of first regulators for controlling the first power supply voltage applied to each set of the first pre-driver unit and the second pre-driver unit;
A plurality of second regulators for controlling the second power supply voltage applied to each set of the first pre-driver unit and the second pre-driver unit;
The signal transmission circuit according to appendix 4, wherein

(Appendix 6)
The output data is differential output data,
The output monitor circuit includes:
A first comparator that compares a voltage of positive logic data of the differential output data with a first reference voltage;
A second comparator that compares a voltage of negative logic data of the differential output data with a second reference voltage;
The signal transmission circuit according to appendix 4 or appendix 5, characterized in that.

(Appendix 7)
The output monitor circuit further includes:
A reference voltage generating circuit for generating the first reference voltage and the second reference voltage;
A first resistor for converting a positive logic output of the differential output data into a voltage;
A second resistor that converts a negative logic output of the differential output data into a voltage;
The signal transmission circuit according to appendix 6, wherein:

(Appendix 8)
The output monitor circuit further includes:
A first control circuit for controlling the first power supply voltage output from the first regulator in accordance with an output of the first comparator;
A second control circuit for controlling the second power supply voltage output from the second regulator according to the output of the second comparator;
The first control circuit performs control by adjusting at least one value of the first reference voltage and the first resistor,
The second control circuit performs control by adjusting at least one value of the second reference voltage and the second resistor.
The signal transmission circuit according to appendix 7, wherein

(Appendix 9)
The output monitor circuit further includes:
A first digital / analog converter that is provided between the first regulator and the first control circuit, converts a first digital control code from the first control circuit into an analog value, and supplies the analog value to the first regulator;
A second digital / analog converter that is provided between the second regulator and the second control circuit, converts a second digital control code from the second control circuit into an analog value, and supplies the analog value to the second regulator; Having
The signal transmission circuit according to appendix 8, wherein

(Appendix 10)
The output monitor circuit further includes:
A first coefficient circuit that multiplies the output of the first digital / analog converter by a predetermined coefficient and outputs the result to the first regulator;
A second coefficient circuit that multiplies the output of the second digital / analog converter by a predetermined coefficient and outputs the result to the second regulator.
The signal transmission circuit according to appendix 9, wherein

(Appendix 11)
The output monitor circuit further includes:
An AND circuit that takes the logical product of the output of the first comparator and the output of the second comparator;
Integrated to control the first power supply voltage output from the first regulator and the second power supply voltage output from the second regulator according to the output of the AND circuit, the first control circuit and the second control circuit Integrate as a control circuit,
11. The signal transmission circuit according to any one of appendices 8 to 10, wherein

(Appendix 12)
Each set of the first pre-driver unit and the second pre-driver unit is selected in order for each tap,
The first and second reference voltages generated by the reference voltage generation circuit or the first and second resistors are adjusted to values required for the final stage driver of the selected tap.
12. The signal transmission circuit according to any one of appendix 7 to appendix 11, which is characterized by the above.

(Appendix 13)
The signal transmission circuit receives differential parallel input data and outputs differential serial data;
The final stage driver is a symmetric load type SST driver.
13. The signal transmission circuit according to any one of supplementary notes 4 to 12, wherein

(Appendix 14)
Including the signal transmission circuit according to any one of appendix 1 to appendix 13, wherein a transmission signal is transmitted to the outside by the signal transmission circuit;
A semiconductor integrated circuit.

(Appendix 15)
further,
A signal receiving circuit for receiving a received signal sent from the outside of the semiconductor integrated circuit;
A signal processing circuit that processes the reception signal received through the signal reception circuit and generates a transmission signal to be transmitted through the signal transmission circuit.
15. The semiconductor integrated circuit according to appendix 14, wherein:

DESCRIPTION OF SYMBOLS 1 Output monitor circuit 2 Regulator circuit 11 Reference voltage generation circuit 12a 1st comparator 12b 2nd comparator 13 Integrated control circuit 13a 1st control circuit 13b 2nd control circuit 14a 1st digital / analog converter (1st DAC)
14b Second DAC
15 AND circuit
16a First coefficient circuit 16b Second coefficient circuit 21-24, 105 Regulator 21a-24a First regulator 21b-24b Second regulator 31a, 31b-34a, 34b Pre-driver unit 41-44, 140, 141-144 Final stage driver (SST driver)
DESCRIPTION OF SYMBOLS 100,300 Semiconductor integrated circuit 101 Signal conversion part 102 Multiplexer part 103 Pre-driver part 104 Final stage driver part (SST driver part)
106 Basic code generation circuit 107 Buffer 108 Weight control circuit 110, 401 Signal transmission circuit 130, 131-134 Pre-driver 161 Calibration resistor 162 Logic circuit 200 Signal transmission path 310, 402 Signal reception circuit 400 Semiconductor integrated circuit (switch chip)
403 Signal processing circuit (CPU)

Claims (11)

Multiple pre-drivers that receive input data and perform pre-processing;
A plurality of final stage drivers for generating output data in accordance with the outputs of the plurality of pre-drivers;
An output monitor circuit for monitoring the output of the final stage driver;
A regulator circuit for controlling a power supply voltage applied to each of the pre-drivers according to the output of the output monitor circuit,
A signal transmission circuit characterized by that. The regulator circuit is:
A plurality of regulators provided corresponding to the plurality of pre-drivers;
Each said regulator is
Controlling at least one of a first power supply voltage and a second power supply voltage applied to a corresponding one of the plurality of pre-drivers according to an output of the output monitor circuit;
The signal transmission circuit according to claim 1. The input data is differential input data,
The pre-driver is
A first pre-driver unit for processing positive logic data of the differential input data;
A second pre-driver unit that processes negative logic data of the differential input data.
The signal transmission circuit according to claim 1, wherein the signal transmission circuit is a signal transmission circuit. The output data is differential output data,
The output monitor circuit includes:
A first comparator that compares a voltage of positive logic data of the differential output data with a first reference voltage;
A second comparator that compares a voltage of negative logic data of the differential output data with a second reference voltage;
The signal transmission circuit according to claim 3. The output monitor circuit further includes:
A reference voltage generating circuit for generating the first reference voltage and the second reference voltage;
A first resistor for converting a positive logic output of the differential output data into a voltage;
A second resistor that converts a negative logic output of the differential output data into a voltage;
The signal transmission circuit according to claim 4. The output monitor circuit further includes:
A first control circuit for controlling the first power supply voltage output from the first regulator in accordance with an output of the first comparator;
A second control circuit for controlling the second power supply voltage output from the second regulator according to the output of the second comparator;
The first control circuit performs control by adjusting at least one value of the first reference voltage and the first resistor,
The second control circuit performs control by adjusting at least one value of the second reference voltage and the second resistor.
The signal transmission circuit according to claim 5. The output monitor circuit further includes:
A first digital / analog converter that is provided between the first regulator and the first control circuit, converts a first digital control code from the first control circuit into an analog value, and supplies the analog value to the first regulator;
A second digital / analog converter that is provided between the second regulator and the second control circuit, converts a second digital control code from the second control circuit into an analog value, and supplies the analog value to the second regulator; Having
The signal transmission circuit according to claim 6. The output monitor circuit further includes:
A first coefficient circuit that multiplies the output of the first digital / analog converter by a predetermined coefficient and outputs the result to the first regulator;
A second coefficient circuit that multiplies the output of the second digital / analog converter by a predetermined coefficient and outputs the result to the second regulator.
The signal transmission circuit according to claim 7. The output monitor circuit further includes:
An AND circuit that takes the logical product of the output of the first comparator and the output of the second comparator;
Integrated to control the first power supply voltage output from the first regulator and the second power supply voltage output from the second regulator according to the output of the AND circuit, the first control circuit and the second control circuit Integrate as a control circuit,
The signal transmission circuit according to any one of claims 6 to 8, wherein Each set of the first pre-driver unit and the second pre-driver unit is selected in order for each tap,
The first and second reference voltages generated by the reference voltage generation circuit or the first and second resistors are adjusted to values required for the final stage driver of the selected tap.
The signal transmission circuit according to any one of claims 5 to 9, wherein the signal transmission circuit is configured as described above. A signal transmission circuit according to any one of claims 1 to 10, wherein a transmission signal is transmitted to the outside by the signal transmission circuit.
A semiconductor integrated circuit.

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