JPH1127132A - Impedance matching circuit and semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To match an output impedance of an output buffer with an impedance of a transmission line automatically by allowing a counter to count up when an output level of the output buffer does not exceed a reference voltage and allowing the counter to count down when the output level exceeds the reference voltage and using the count to select an output impedance adjustment element of the output buffer. SOLUTION: A 1st comparator circuit CMP1 compares a voltage level Vno of an output node No of an output buffer OPB with a reference voltage Vref1. A 2nd comparator circuit CMP2 compares the voltage Vno with a reference voltage Vref2, and counters CNT1, CNT2 count up or down depending on the comparison result by the comparator circuits CMP1, CMP2. Then a signal of each bit of the counters CNT1, CNT2 is fed to gates of impedance adjustment MOSFETs Qp1-Qpn, Qn1-Qnn.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an impedance matching technology for a semiconductor integrated circuit, and more particularly to a technology effective when applied to an impedance matching circuit for automatically matching the output impedance and the transmission line impedance.
For example, the present invention relates to a technology effective for use in a dynamic semiconductor memory device.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit, it is known that signal reflection occurs if the output impedance of an output buffer does not match the impedance of a transmission line.
FIG. 6 shows an equivalent circuit of the transmission line. Assuming that the characteristic impedance of the transmission line is Zo and the output impedance of the signal source Vs is Zs, the signal level at the start A of the transmission line is
Since Vi + Vr = (Vi / Zo-Vr / Zo) / Zs (where Vi is the level of the input wave and Vr is the level of the reflected wave), the reflection coefficient ρ of the transmission line is ρ = Vr / Vi =
(Zs-Zo) / (Zs + Zo). From this, Z
It can be seen that signal reflection does not occur under the condition of s = Zo. Since the characteristic impedance of the transmission line is usually fixed, reflection of a signal can be suppressed by changing the output impedance of the output buffer.

FIG. 7 shows the principle of an impedance matching circuit used in a conventional static RAM. Pull-up MOSFET for output buffer OPB
Qpu and pull-down MOSFET Qpd and parallel-type impedance adjusting MOSFETs Qp1 to Qp respectively connected between power supply voltage and ground point
n and Qn1 to Qnn, and a register RE for holding control codes of these impedance adjusting MOSFETs.
G1 and REG2 are provided.

Further, a pull-up replica buffer RLCu having the same output impedance as the pull-up circuit of the output buffer, a pull-down replica buffer RLCd having the same output impedance as the pull-down circuit, and an output of these replica buffers. Comparator CMP for comparing the level with a preset level
1 and CMP2 and counters CNT1 and CNT2 which are incremented and decremented according to the comparison result, and output nodes N1 and N2 of the replica buffers RLCu and RLCd.
Is connected to external terminals P1 and P2 to which replica resistors Rru and Rrd having the same impedance as the characteristic impedance Zo of the transmission line are connected.
1 and CNT2 are held in the registers REG1 and REG2 provided corresponding to the output buffers.

[0005] The impedance matching circuit of FIG.
First, the potential Vn1 of the output node N1 and the reference voltage Vref are compared with the comparator CMP1 in a state where one pull-up adjustment MOSFET of the pull-up replica buffer RLCu is turned on and a current flows through the replica resistor Rrd. As a result, when Vn1 is lower, the counter CNT1 is counted up. Then, only one more pull-up side adjustment MOSFET of the replica buffer RLCu is turned on, the output impedance of the replica buffer RLCu changes, and the potential Vn1 of the output node N1 increases. Then, the potential and the reference voltage are compared again by the comparator CMP1, and the counter CNT1 is counted up or down according to the comparison result.

By repeating the above operation, when the output impedance of replica buffer RLCu matches the impedance of replica resistor Rrd, counter C
Since the value of NT1 converges, the value at that time is changed to the impedance adjustment MOSFET on the pull-up side of the output buffer.
The register REG1 is used as a control code for Qp1 to Qpn.
Set to.

Next, the pull-down replica buffer RL
With one of the pull-down side adjustment MOSFETs of Cd turned on and a current flowing through the replica resistor Rru, the potential Vn2 of the output node N2 and the reference voltage Vref are compared by the comparator CMP2. As a result, Vn2 is When it is low, the counter CNT2 is counted up. Then, the pull-down adjustment M of the replica buffer RLCd is adjusted.
Only one more OSFET is turned on,
The output impedance of replica buffer RLCd changes, and potential Vn2 at output node N2 decreases. And
The potential and the reference voltage are compared again by the comparator CMP2, and the counter CNT2 is counted up or down according to the comparison result.

By repeating the above operation, when the output impedance of replica buffer RLCd matches the impedance of replica resistor Rru, counter C
Since the value of NT2 converges, the value at that time is changed to the impedance adjustment MOSFET on the pull-down side of the output buffer.
The register REG2 is used as a control code for Qn1 to Qnn.
Set to.

In the impedance matching circuit, the pull-up side replica resistor Rru is omitted, the pull-down side replica buffer RLCd has the same configuration as the output buffer, and the pull-up side adjusting MOSFET Qn1 is used.
Qnn to replace the replica resistor Rru to reduce the number of external terminals, use a resistor K times the transmission line impedance as the replica resistor, and replace the element constituting the replica buffer with the element constituting the original output buffer. The output impedance is increased by a factor of K as a constant of 1 / K to reduce current consumption in the replica buffer.

[0010]

The impedance matching circuit as described above requires an external terminal for connecting a replica resistor, and when the impedance of the transmission line is different in the mounted state, each time or for each system. There is a problem that the replica resistance needs to be adjusted. For this reason, dynamic RA with no
The impedance matching circuit as described above could not be applied to M.

An object of the present invention is to provide an impedance matching circuit capable of automatically matching output impedance and transmission line impedance without using a replica resistor, that is, without providing extra pins or adjusting the resistance. It is in.

Another object of the present invention is to provide a dynamic semiconductor memory device having an impedance matching circuit.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0014]

The outline of a typical invention among the inventions disclosed in the present application is as follows.

That is, a plurality of elements for adjusting the output impedance are provided in the output buffer, a comparison circuit that compares the output level of the output buffer with a reference voltage, a counter that counts up or down according to the comparison result, A delay circuit for delaying the input signal to the buffer for a predetermined time, and after the input signal to the output buffer changes, the output level of the output buffer is compared with the reference voltage after the delay time by the delay circuit to determine the output level. It is determined whether or not the reference voltage has been exceeded. If the reference voltage has not been exceeded, the counter is counted up.If the reference voltage has been exceeded, the counter is counted down, and the output impedance adjusting element of the output buffer is selected with the count value. It was done.

According to the above-mentioned means, when the change of the output level with respect to the change of the input signal of the output buffer is slow, it is determined by the comparison circuit that the output level does not exceed the reference voltage, and the counter is counted up. When the output level changes rapidly with respect to the change in the input signal of the output buffer, the comparator determines that the output level has exceeded the reference voltage, counts down the counter, and increases the impedance of the output buffer. The counter value becomes constant at the optimum impedance. That is, the counter value converges to a constant value corresponding to the impedance of the transmission line, the counter value at that time is determined as the control code of the output impedance adjustment element, and the output impedance adjustment element corresponding to the control code is selected. As a result, the output impedance of the output buffer is automatically matched with the impedance of the transmission line.

Further, a logic gate circuit for selectively supplying the input signal to the delay circuit according to a control signal is provided on the input side of the delay circuit. As a result, the impedance matching operation of the output buffer is performed only under a predetermined condition such as when the power is turned on. In other cases, the function is stopped to reduce the current consumption and the output impedance of the output buffer becomes unstable. Can be prevented.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing one embodiment of the impedance matching circuit according to the present invention. In FIG. 1, MOSFETs with an arrow attached to a symbol are P-channel MOSFETs, and those without an arrow are N-channel MOSFETs.

In FIG. 1, Qpu and Qpd denote a pull-up MOSFET and a pull-down MOSFET constituting an output buffer OPB.
On the source terminal side of TQpu and the pull-down MOSFET Qpd, output impedance adjusting M
OSFET Qp1, Qp2 ‥‥ Qpn and Qn1, Qn
2 @ Qnn is connected between the power supply voltage Vcc and the ground point. Also, the output node No. of the output buffer OPB
Is connected to the external terminal Pout.

In this embodiment, a first comparison circuit CMP1 for comparing the voltage level Vno of the output node No of the output buffer OPB with the reference voltage Vref1, and Vno
Comparison circuit CMP2 for comparing the voltage Vref2 with the reference voltage Vref2
And counters CNT1 and CNT2 that count up or count down in accordance with the comparison results of these comparison circuits CMP1 and CMP2, and delay circuits DLY1 and D that delay the input signal Vin to the output buffer for a predetermined time.
An impedance matching circuit including LY2 is provided. Then, the counters CNT1, CNT2
Signal of each bit of the
The signals are applied to the gates of the ETs Qp1 to Qpn and Qn1 to Qnn.

The outputs of the delay circuits DLY1 and DLY2 are supplied to the comparison circuits CMP1 and CMP2, respectively, as comparison timing signals CT, so that after the input signal to the output buffer changes, the delay circuit DLY changes.
1, after the delay times Tpd1 and Tpd2 due to DLY2, the output level Vno of the output buffer is compared with the reference voltages Vref1 and Vref2 to determine whether the output level has exceeded the reference voltage. If not, the counter is counted. If it exceeds or exceeds, count down and use the count value to set the output impedance adjusting MOSFET Qp1.
To Qpn and Qn1 to Qnn are selectively turned on. MOS for adjusting the output impedance
The FETs Qp1 to Qpn and Qn1 to Qnn are designed such that their constants (eg, gate width W) are 1: 2: 4: ‥‥ 2n.

The reference voltages Vref1 and Vref2 are not particularly limited, but are formed by a constant voltage generating circuit (not shown) provided inside the chip. Reference voltages Vref1, Vref2
Is appropriately determined according to the magnitude of the impedance of the transmission line, the magnitude of the delay time of the delay circuits DLY1 and DLY2, and the like. Alternatively, conversely, the reference voltages Vref1 and Vref2 may be determined first (for example, Vcc / 2, etc.), and the delay times Tpd1 and Tpd2 of the delay circuits DLY1 and DLY2 may be determined accordingly.

Next, the operation of the impedance matching circuit will be described with reference to FIG.

First, the value of the counter CNT2 is set to "1" in the initial state, and when the input signal Vin to the output buffer OPB changes from low level to high level,
The potential Vno of the output node No starts to gradually decrease as shown in FIG. At this time, at first, only the smallest constant Qn1 of the output impedance adjusting MOSFETs Qn1 to Qnn is turned on and the entire impedance is considerably large, so that the potential Vno gradually falls as shown in FIG. Therefore, at the time of the comparison timing t1 when the output of the delay circuit DLY2 rises, the potential Vno becomes equal to the reference voltage V.
Since ref1 is not exceeded, the comparison circuit CMP2 determines that Vno> V
Judge as ref1 and output high level signal. Thus, the counter CNT1 is counted up, and the output impedance adjusting MOSFETs Qn1 to Qnn are output.
In this case, instead of Qn1, Qn2 having a larger constant is turned on, and the overall impedance is lowered.

By repeating the above operation, the falling speed of the potential Vno of the output node No increases, and as shown in FIG. 2, the potential Vno at the comparison timing t1 exceeds the reference voltage Vref1, so that the comparison circuit CMP2 , Vno
<Vref1 is determined and a low-level signal is output. Thereby, the counter CNT1 is counted down, and the output impedance adjusting MOSFETs Qn1 to Qn1
As for nn, the number of elements to be turned on is reduced or the elements with a small constant are turned on, and the overall impedance is increased. Thus, the value of the counter CNT2 converges to a value corresponding to the magnitude of the impedance of the transmission line.

In the above description, the case where the optimum value is determined by gradually lowering the impedance of the output buffer has been described.
The comparison may be started by turning on all the SFETs Qn1 to Qnn. In this case, the falling speed of the potential Vno of the output node No is quite fast as shown in FIG.
At the comparison timing t1, the potential Vno exceeds the reference voltage Vref1. Therefore, the comparison circuit CMP2 first sets Vno <V
ref1 is determined and a low-level signal is output.
NT1 is counted down. In this manner, the optimum value can be determined while gradually decreasing the value of the counter and increasing the output impedance.

Also, instead of setting the value of the counter CNT2 to "1" in the initial state, an MO having the smallest constant is set.
The gate terminal of the SFET Qn1 may be connected to the power supply voltage Vcc so as to be always on (in this case, the initial value of the counter CNT2 is "0"). Alternatively, in the initial state, the value of the counter CNT2 is changed to the output impedance adjusting MOSFETs Qn1 to Qn.
The matching operation may be started by setting the impedance of the entire n to an intermediate value.

The impedance matching operation by the pull-down side output impedance adjusting MOSFETs Qn1 to Qnn has been described above. The pull-up side impedance matching operation is performed by lowering the input signal Vin to the output buffer by using the comparison circuit CM.
P1 and the counter CNT1 operate in the same manner as described above to adjust the output impedance adjusting MOSFETs Qp1 to Qp1.
This is performed by determining the ON / OFF state of pn.

The above-described impedance matching operation may be performed, for example, at the time of power-on, for example, in a dynamic RAM, by performing an operation such as an initial setting mode in which "0" and "1" are written into memory cells and read out. It can be executed by giving an appropriate clock to the output buffer OPB from outside. When applied to a data output buffer of a dynamic RAM, for example, 1
In the case of 6-bit output, 16 output buffers are also provided, but the delay circuits DLY1 and DLY2 and the comparison circuits CMP1 and CMP constituting the impedance matching circuit are provided.
2 and the counters CNT1 and CNT2 can be provided as a common circuit for the 16 output buffers. Because the dynamic RAM is generally connected to a microprocessor or the like via a bus, the length of the transmission line connected to each data output pin is the same, and the impedance is also the same.

Further, as shown in FIG.
An AND gate G1 and a NOR gate G2 controlled by a control signal MS are provided on the input sides of Y1 and DLY2, respectively, and the input signal Vin is supplied to the delay circuits DLY1 and DLY2 via these gates. Is also good. The control signal MS is internally generated as a high-level signal when the power is turned on or when a mode is set by a mode setting control signal input or a command input, and operates the gates G1 and G2 to operate the counters CNT1 and CNT.
When the time required for the value of 2 to converge has elapsed, the level changes to a low level, and the operations of the comparison circuits CMP1 and CMP2 are stopped. As a result, current consumption can be reduced, and the characteristics of the output buffer OPB can be prevented from changing during normal operation.

FIG. 4 shows the comparison circuits CMP1 and CMP2.
The following shows a specific example of the circuit. In the figure, AMP is CMO
S differential amplifier, TG1 and TG2 are CMOS differential amplifiers A
The output potential V of the output buffer OPB is applied to the input / output node of MP.
transmission gates for transmitting no and reference voltage Vref1 (or Vref2), INV1 is an output inverter connected to one input / output node of the CMOS differential amplifier AMP, and INV2 is the other of the CMOS differential amplifier AMP. Are dummy inverters connected to the input / output nodes for balancing the parasitic capacitance.

The transmission gates TG1 and TG2 are controlled by a comparison timing signal CT output from the delay circuit DLY1 or DLY2 and a signal obtained by inverting the comparison timing signal CT by an inverter INV3. Alternatively, when the comparison timing signal CT output from DLY2 changes to a high level, the gates TG1 and TG2 close, and the previous level is held at the input / output node of the CMOS differential amplifier AMP.

When the comparison timing signal CT changes to a high level, the pull-up MOSFET Qs1 connected to the internal node of the CMOS differential amplifier AMP changes from on to off, and the CMOS differential amplifier AMP changes. The constant current MOSFET Qc is changed from the off state to the on state, and the CMOS differential amplifier AMP is activated to amplify the potential difference between the input and output nodes. Then, the amplified voltage is input to the output inverter INV1, which is inverted and output as a comparison result. The output inverters INV1 and INV2 are constituted by clocked inverters using the comparison timing signal CT as a control signal. The output inverters INV1 and INV2 are activated at the same time as the CMOS differential amplifier AMP is activated, and the comparison result is obtained. Output.

FIG. 5 shows a configuration example of a synchronous dynamic RAM suitable for applying the impedance matching circuit of the present invention. In FIG. 5, reference numerals 11A and 11B denote an address input buffer circuit for taking in a row address signal and a column address signal input from the outside in a time-division manner and supplying them to predetermined internal circuits, and 12 denotes a memory cell for refreshing. Refresh counters 13A and 13B for generating the addresses of the above-mentioned rows decode the internal complementary address signals supplied from the address input buffer circuit 11A or the refresh counter 12 and select the corresponding word lines in the memory arrays 10A and 10B. A decoder 14 is a column address counter for generating a continuous column address required for reading / writing a plurality of bytes of data based on a column address input from the outside, and 15A and 15B are internal addresses supplied from the column address counter 14. Faith , And a column decoder 16A, 16B is a sense amplifier for amplifying data read to the bit line and a plurality of bit lines are connected via a column switch. I / O connected in common
There is a bus.

A data input buffer circuit 17 receives a write data signal and supplies it to the memory arrays 10A and 10B via the sense amplifier & I / O bus 16. A reference numeral 18 denotes a data input buffer circuit via the sense amplifier & I / O bus 16. A data output buffer circuit for outputting data read from the memory arrays 10A and 10B to the outside, and a timing 19 for forming a timing signal to be supplied to the internal circuit based on various control signals and clock signals input from the outside. It is a control circuit. The impedance matching circuit of the embodiment is applied to the data output buffer 18.

As a control signal externally input to the memory of this embodiment, in addition to the clock signal CLK, for example, a clock enable for controlling not to supply an input clock for reducing power consumption to an internal circuit. A signal CKE, a chip select signal / CS for indicating that the memory is selected, and a row address strobe signal / RA for giving a row address fetch timing.
S, a column address strobe signal / CAS for giving a timing for taking in a column address, a write control signal / WE for indicating that writing is valid, and masking so as not to read or write data of a predetermined bit. There is a control signal DQM or the like for requesting. In addition, the control signal in which "/"("-" is added to the sign in the figure) before each sign indicates that the low level is the effective level.

In the synchronous DRAM of this embodiment,
The various control signals CKE, / CS, / RAS, / CA
A predetermined combination of S, / WE, and DQM is regarded as a command and input, so that the read, write, or test mode and the impedance matching operation of the present embodiment are performed. When a predetermined combination of the control signals is input and a predetermined terminal among the address input terminals is in a predetermined state, an impedance matching mode may be set.

As described above, in the above embodiment, the output buffer is provided with a plurality of elements for adjusting the output impedance, and the comparison circuit for comparing the output level of the output buffer with the reference voltage is provided. A counter for counting up or counting down, and a delay circuit for delaying an input signal to the output buffer for a predetermined time,
After the input signal to the output buffer changes, the output level of the output buffer is compared with the reference voltage after the delay time of the delay circuit to determine whether the output level has exceeded the reference voltage. The above counter is counted up, and when it exceeds, the count value is reduced and the output impedance adjusting element of the output buffer is selected according to the count value, so that the output level changes slowly with respect to the input signal change of the output buffer. When the output level does not exceed the reference voltage, the counter counts up and the impedance of the output buffer is lowered. The circuit determines that the output level has exceeded the reference voltage and Since the impedance of the countdown to the output buffer is high, the value of the counter becomes constant when the optimum impedance. That is, the value of the counter converges to a constant value corresponding to the impedance of the transmission line, the counter value at that time is determined as the control code of the output impedance adjusting element, and the output impedance of the output buffer automatically changes to the transmission line impedance. This has the effect of being matched to

Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say. For example, in the above embodiment, after the input signal to the output buffer changes, the output level of the output buffer is compared with the reference voltage after the delay time by the delay circuit to determine whether the output level exceeds the reference voltage. When the output level does not exceed the reference voltage, the counter is counted up.When the output level exceeds the reference voltage, the counter is counted up.
If not exceeded, the countdown may be performed.

In the above description, the case where the invention made by the present inventor is mainly applied to a synchronous DRAM, which is the field of application as the background, has been described. However, the present invention is not limited to this, and is not limited to the DRAM. It can be widely used for semiconductor memories (for example, SRAM), microprocessors, and other semiconductor integrated circuits.

[0041]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, an impedance matching circuit capable of automatically matching the output impedance with the impedance of the transmission line without providing extra pins or adjusting the resistance, and a dynamic semiconductor memory having an output impedance matching function. The device can be realized.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of an impedance matching circuit according to the present invention.

FIG. 2 is a waveform chart showing operation waveforms of the impedance matching circuit of the embodiment.

FIG. 3 is a circuit diagram showing another embodiment of the impedance matching circuit according to the present invention.

FIG. 4 is a circuit diagram showing one embodiment of a comparison circuit constituting the impedance matching circuit of the embodiment.

FIG. 5 is a block diagram showing an embodiment of a synchronous dynamic RAM as an example of a semiconductor integrated circuit suitable for applying the present invention.

FIG. 6 is a conceptual diagram illustrating a relationship between a signal source and a transmission line.

FIG. 7 is a circuit diagram showing a configuration example of a conventional impedance matching circuit.

[Explanation of symbols]

 OPB Output buffer Zo Impedance of transmission line CMP1, CMP2 Comparison circuit CNT1, CNT2 Counter DLY1, DLY2 Delay circuit 10A, 10B Memory array 11A, 11B Address input buffer circuit 12 Refresh counter 13A, 13B Row decoder 14 Column address counter 15A, 15B Column Decoder 16A, 16B Sense amplifier & I / O bus 17 Data input buffer circuit 18 Data output buffer circuit 19 Timing control circuit

Claims (5)

[Claims] An output buffer including a plurality of elements for adjusting output impedance, a comparison circuit for comparing an output level of the output buffer with a reference voltage, and counting up or counting down according to the comparison result of the comparison circuit And a delay circuit for delaying the input signal to the output buffer for a predetermined time, and after the input signal to the output buffer changes, the output level and the reference voltage of the output buffer after the delay time by the delay circuit. To determine whether the output level has exceeded the reference voltage.If not, the counter is counted up or down.If not, the counter is counted down or counted up. Set the output impedance adjustment element of the output buffer to the selected state. An impedance matching circuit characterized by being configured. 2. The output impedance adjusting element according to claim 1,
The pull-up MOSFET and the first
And a plurality of MOSFETs connected in parallel with each other between a pull-down MOSFET and a second power supply terminal forming the output. The impedance matching circuit according to claim 1, wherein 3. The logic circuit according to claim 1, wherein a logic gate circuit for selectively supplying the input signal to the delay circuit according to a control signal is provided on an input side of the delay circuit. The described impedance matching circuit. 4. The comparing circuit includes: a differential amplifier circuit; and transmission means for transmitting an output voltage of the output buffer and the reference voltage to a pair of input / output terminals of the differential amplifier circuit, respectively, by an output of the delay circuit. And an output logic gate circuit connected to one input / output terminal of the differential amplifier circuit, and a dummy logic gate circuit connected to the other input / output terminal of the differential amplifier circuit. The impedance matching circuit according to claim 1, 2 or 3, wherein: 5. A semiconductor memory device, wherein the impedance matching circuit according to claim 1 is provided corresponding to at least one data output buffer.