JP2015027019A - Solid state imaging apparatus used for three-dimensional shape measurement - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid state imaging apparatus used for a three-dimensional measurement apparatus which, in three-dimensional shape measurement of a measurement object, is capable of shortening a time for the measurement and reducing a data amount for calculating three-dimensional data from an image acquired by an imaging apparatus.SOLUTION: When irradiating a measurement object with sheet light and acquiring its image with an MOS-type solid state imaging apparatus, a row output circuit determines pixels irradiated with the sheet light and including three-dimensional information and pixels not including the information, and a pixel circuit effectively performs row output. Rows determined to include no three-dimensional information by the row output circuit are not read out and only rows including the three-dimensional information are read out.

Description

  The present invention relates to a solid-state imaging device, and more particularly to a solid-state imaging device used for three-dimensional shape measurement.

  As a conventional solid-state imaging device, a MOS-type solid-state imaging device including a photodiode for photoelectric conversion for each imaging pixel and various MOS transistors for transferring, selecting, amplifying, and resetting photoelectrons accumulated in the photodiode ( Hereinafter, a CMOS image sensor) has been proposed.

1 is a circuit diagram showing a configuration example of a conventional pixel portion in a CMOS image sensor, FIG. 2 is a conceptual diagram showing a configuration example of a conventional drive circuit in a CMOS image sensor, and FIG. 3 is a diagram of the pixel portion shown in FIG. It is a timing chart which shows an operation example.
FIG. 1 shows a configuration until photoelectrons accumulated in the photodiode 1 are output to the vertical signal line 2.

As shown in FIG. 1, four MOS transistors 3, 4, 5, and 6 are provided around the photodiode 1.
First, a transfer transistor 3, a reset transistor 4, an amplification transistor 5, and a selection transistor 6 are provided from the photodiode 1 side. A drive power supply (hereinafter referred to as VDD) and a reset transistor 4 are provided on the drain side of the reset transistor 4 and the amplification transistor 5. Are connected to the drain of the transfer transistor 3 and the gate of the amplification transistor 5, and a floating diffusion portion (hereinafter referred to as FD) 7 is provided between them.

A transfer pulse is input to the gate of the transfer transistor 3 from the transfer transistor wiring 8 that connects the transfer transistor 3 of each pixel in the row direction, and the reset transistor 4 of each pixel in the row direction is connected to the gate of the reset transistor 4. A reset pulse is inputted from the reset transistor wiring 9 to be selected, and a selection pulse is inputted to the gate of the selection transistor 6 from the selection transistor wiring 10 connecting the selection transistor 6 of each pixel in the row direction.
In such a configuration, when the selection transistor 6 is turned on, the amplification transistor 5 and the constant current source outside the imaging unit form a source follower, so that the potential of the vertical signal line 2 is the gate voltage of the amplification transistor 5, that is, the FD portion 7. The value follows the potential. This value is the pixel output.

Next, a driving method in the conventional pixel portion will be described with reference to FIG.
First, at the timing of “t10” shown on the horizontal axis of FIG. 3, photoelectrons are accumulated in PD1.
Next, the selection transistor pulse SELj in the j-th row is input through the selection transistor wiring 10 at the timing “t11”, and the selection transistor 6 is turned on.
Then, the reset pulse RXj in the j-th row is input to the reset transistor 4 via the reset transistor wiring 9 at the timing of “t12”, and the FD unit 7 is reset.
Thereafter, during the period indicated by “t13”, the potential (reset signal) of the vertical signal line 2 is captured by the column output circuit 11 shown in FIG.
Then, the transfer pulse TXj in the j-th row is input to the transfer transistor 3 via the transfer transistor wiring 8 at the timing of “t14”, and photoelectrons are transferred from the PD 1 to the FD unit 7.

Thereafter, in the period “t15”, the potential (optical signal) of the vertical signal line 12 is captured again by the column output circuit 11 in the subsequent stage. Here, the column output circuit 11 holds the two voltages subsequently captured. In the case of the above operation, the circuit holds the above-described reset signal value and optical signal value.
Through the above operation, the reset signal and the optical signal in the j-th row are held in the column output circuit 11, and then each signal in each column in the j-th row held in the column output circuit 11 in the period “t16”. Are sequentially output to the outside as image signals.
The period “t17” is a period related to driving of the (j + 1) th row and is the same as that of the jth row.

  A reset transistor pulse RX, a transfer transistor pulse TX, and a selection transistor pulse SEL for signal output of each pixel 12 are generated by the timing generation circuit 13 shown in FIG. Drive.

  For example, Japanese Patent No. 4803568 reports a three-dimensional shape measurement using a CMOS image sensor as described above. 4 and 5 show the measurement environment for three-dimensional shape measurement by the light cutting method. A sheet-like light 18 (sheet light) is emitted from the pattern light source 16 to the measurement object 15, and the sheet light 18 is distorted according to the three-dimensional shape of the measurement object 15. A sheet light irradiation image is acquired by the imaging device 17 equipped with the CMOS image sensor as described above for the distortion, and the three-dimensional shape of the measurement object 15 is obtained by the triangulation principle by a computer or the like.

Japanese Patent No. 4434530 Japanese Patent No. 4803568

  As described above, in the light cutting method, in the process of scanning the target object with the sheet light, the sheet light irradiates the target object a plurality of times, acquires a plurality of these images, and the distortion amount of the target object is obtained. It is necessary to obtain a three-dimensional shape that is an overall image.

  Thus, since it is necessary to image the target object a plurality of times, in order to speed up the measurement, it is desirable that the time required for each imaging (time for obtaining one image) is short.

  In view of the above, it is an object of the present invention to provide a solid-state imaging device used for three-dimensional shape measurement that can quickly perform three-dimensional shape measurement.

  In order to achieve the above object, pixels are arranged in a matrix on a semiconductor substrate, a photodiode that converts light into signal charges and accumulates in the pixels, and voltage conversion of charges accumulated in the photodiodes. And a column signal output line for receiving a signal from the pixel for each column of the pixels, and a row signal output line for receiving a signal from the pixel for each row of the pixels. Before outputting the signal on the column signal output line, outputting the pixel signal on the row signal output line, and determining a read row and a non-read row by a row signal determination circuit disposed on the semiconductor substrate. However, the non-reading row is not read.

  According to the three-dimensional shape measuring apparatus using the solid-state imaging device of the present invention, three-dimensional information of the measurement object can be quickly acquired.

Configuration example of conventional pixel unit Conventional drive circuit configuration example Timing chart showing a conventional driving method of a pixel portion Measurement environment diagram Measurement target diagram Overview of imaging device CMOS image sensor configuration diagram of the first embodiment of the present invention Configuration diagram of a pixel unit according to the first embodiment of the present invention. Timing chart of the first embodiment of the present invention Timing chart of three-dimensional information holding row according to the first embodiment of the present invention Column output circuit configuration diagram of the first embodiment of the present invention Configuration diagram of pixel portion of second embodiment of the present invention CMOS image sensor block diagram of 3rd embodiment in this invention

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 4 is an explanatory diagram of a measurement environment for three-dimensional shape measurement using the CMOS image sensor of the present invention, and FIG. 5 is an explanatory diagram of a measurement object. The measurement environment is the same as in the prior art, and a sheet-like light 18 (sheet light) is irradiated from the pattern light source 16 to the measurement object 15, and the sheet light 18 is distorted according to the three-dimensional shape of the measurement object 15. A sheet light irradiation image is acquired by the imaging device 17 equipped with the CMOS image sensor as described above for the distortion, and the three-dimensional shape of the measurement object 15 is obtained by the triangulation principle by a computer or the like. The CMOS image sensor of the present invention is mounted on the imaging device 17.

FIG. 6 is a schematic explanatory diagram of the imaging device of the imaging device 7 shown in FIGS. 4 and 5. The imaging device is a so-called camera system, and a lens 19 for condensing the reflected light from the measurement object on the CMOS image sensor 20 is mounted on the imaging device. The voltage signal photoelectrically converted by the CMOS image sensor 20 is output to the outside from the CMOS image sensor and needs to be adjusted on the side receiving the voltage signal in accordance with the output method. Here, an FPGA (Field Programmable Gate Array) 21 is used. An integrated circuit with a high degree of freedom is shown, but a DSP (Digital) developed exclusively for camera systems
(Signal Processing) or the like can be substituted. The FPGA 21 can also send a drive setting signal for the CMOS image sensor. Next, in order to send an image including three-dimensional information acquired by the CMOS image sensor 20 to a three-dimensional computer processor outside the imaging device 17, input / output signals of the FPGA 21 and the three-dimensional computer processor 23 are matched. An input / output interface 22 is mounted on the imaging device 17. The three-dimensional information calculated by the three-dimensional computer 23 is displayed on a monitor 24 of a personal computer. FIG. 6 shows an example of the configuration of the imaging apparatus of the present invention.

  FIG. 7 shows a configuration diagram of a CMOS image sensor according to the first embodiment of the present invention. This CMOS image sensor block diagram is a block diagram of the CMOS image sensor 20 shown in FIG. In FIG. 7, as in FIG. 6, the reset signal and the optical signal of each pixel 12 are read out to the column output circuit 11, and a reset transistor pulse RX, a transfer transistor pulse TX, a selection transistor for signal output of each pixel 12 are displayed. The pulse SEL is generated by the timing generation circuit 13 shown in FIG. 7 and drives each pixel 12 via the row selection circuit 14.

  In FIG. 7, the difference from FIG. 6 is the conventional signal output only in the column direction. However, in the present invention, the output configuration in the row direction is provided, and the signal of the row output circuit is determined. The determination circuit is provided, and the output line for outputting the determination result is provided. Each configuration will be described along the driving method.

  When the measurement object of FIG. 5 is photographed, the sheet light 18 is incident on each pixel 12 of FIG. 7 according to the measurement object 15. The three-dimensional information pixel 25 on which the sheet light 18 is incident is limited to a part of the two-dimensionally arranged pixels 12, and only the three-dimensional information pixel 25 is necessary for the three-dimensional shape measurement. . A feature of the present invention is that by selectively reading out the three-dimensional information pixel 25 that holds information necessary for the three-dimensional shape, the driving speed of the CMOS image sensor is greatly improved and the data necessary for the calculation processing is greatly increased. This greatly reduces the processing load on the computer.

  Information from all the pixels 12 of the pixels 12 arranged in a two-dimensional manner is simultaneously read out to the row output circuit 26, and the row from each pixel 12 is selected as a means for selectively judging the row including the three-dimensional information pixel 25 and the row not including it. A horizontal signal line 27 for outputting a signal to the output circuit 26, a determination circuit 28 for determining a row including the 3D information pixel 25 and a row not including the three-dimensional information pixel 25, and sequentially determining the determination of each row in accordance with the pixel driving timing. Each row is provided with a determination switch (RJ) 29. The row selected from the timing generation circuit turns ON the determination switch 29, and the row signal is transmitted to the determination circuit 28 for determination. A row including the three-dimensional information pixel 25 outputs a signal via the column output circuit 11 by the same means as in the conventional technique, and a pixel not including the pixel is skipped. At this time, a selected row number output line 30 is provided for informing the 3D computer 23 which row has been output. The configuration and driving according to the present invention will be described in detail.

  FIG. 8 shows a pixel configuration diagram according to the first embodiment of the present invention. Both the pixel 12 and the three-dimensional information pixel 25 in FIG. 7 have the same circuit configuration, and FIG. 8 shows a pixel configuration diagram thereof. FIG. 8 shows a configuration until photoelectrons accumulated in the photodiode 1 are output to the vertical signal line 2 and the horizontal signal line 27 as in the conventional pixel unit configuration example of FIG.

  Around the photodiode 1, five MOS transistors 3, 4, 5, 6, 31 are provided. A transfer transistor 3, a reset transistor 4, an amplifying transistor 5, a selection transistor 6, and a row output amplifying transistor 31 are provided from the photodiode 1 side. VDD and a reset transistor are provided on the drain side of the reset transistor 4 and the amplifying transistor 5. 4 and the drain of the transfer transistor 3, the gate of the amplification transistor 5, and the gate of the row output PMOS amplification transistor 31 are connected, and an FD 7 is provided therebetween.

A transfer pulse is input to the gate of the transfer transistor 3 from the transfer transistor wiring 8 that connects the transfer transistor 3 of each pixel in the row direction, and the reset transistor 4 of each pixel in the row direction is connected to the gate of the reset transistor 4. A reset pulse is inputted from the reset transistor wiring 9 to be selected, and a selection pulse is inputted to the gate of the selection transistor 6 from the selection transistor wiring 10 connecting the selection transistor 6 of each pixel in the row direction.
In such a configuration, when the selection transistor 6 is turned on, the amplification transistor 5 and the constant current source outside the imaging unit form a source follower, so that the potential of the vertical signal line 2 is the gate voltage of the amplification transistor 5, that is, the FD portion 7. The value follows the potential. This value is the pixel output.

  The difference from the configuration example of the conventional pixel portion of FIG. 1 is that a row output PMOS amplifying transistor 31 and a horizontal signal line 27 are provided for row output. At this time, since the row output PMOS amplifying transistor 31 is composed of PMOS, the output level of the three-dimensional information pixel 25 is higher than that of the pixel 12 that does not hold the three-dimensional information.

  When the reset transistor 4 resets the FD unit 7, the FD unit 7 is reset to a high level, and when the charge accumulated in the photodiode 1 is transferred to the FD by the transfer transistor 3, the level of the FD 7 is high according to the optical signal. From low to low. That is, the FD7 level of the pixel having the optical signal is lower than the FD7 level of the pixel having no optical signal. The source of the NMOS amplification transistor 5 is source-follower connected to the column output circuit 11, and the potential of the signal output line 2 changes according to the potential of the FD 7 connected to the gate of the amplification transistor 5. When the potential is high, the potential of the signal output line 2 becomes high, and when the potential is low, the potential of the signal output line 2 becomes low. Therefore, the output level of the pixel having the optical signal is lower than the output level of the pixel not having the optical signal.

  A plurality of sources of the row output PMOS amplifying transistors 31 of the pixels 12 are connected to the horizontal signal line 27 in the row direction. In order to obtain information of the three-dimensional information pixel 25 on which the sheet light 18 is incident, the output level from the three-dimensional information pixel 25 needs to be higher than that of the normal pixel 12 on which the sheet light 18 is not incident. . When the NMOS amplification transistor is employed as the row output amplification transistor, the output level of the three-dimensional information pixel 25 is lower than that of the normal pixel 12 on which the sheet light 18 is not incident, as described above. In the first embodiment of the present invention, PMOS is adopted as the row output amplification transistor. The source follower of the PMOS transistor has a reverse characteristic to the NMOS source follower described above, in which the source output is lowered when the gate voltage is high.

  The timing chart of the first embodiment of the present invention will be described with reference to FIG. First, at the timing of “t20” shown on the horizontal axis of FIG. 9, the reset pulse RXall is input to the reset transistors 4 of all the pixels through the reset transistor wiring 9 to reset the FD7. At the timing of “t21”, the transfer pulse TXall is input to the transfer transistors 3 of all the pixels via the transfer transistor wiring 8, and the photoelectrons are transferred from the PD1 of all the pixels to the FD7 of all the pixels. By this operation, the potential corresponding to the optical signal is held in the FD portions of all the pixels.

  FIG. 7 shows the pixel arrangement from i columns to i + 6 columns in the row direction and j rows to j + 6 rows in the column direction, but some of the many pixels arranged two-dimensionally. Means. The three-dimensional information pixels 25 on which the sheet light 18 is incident exist in the i + 2 to i + 4 rows, and the three-dimensional information pixels 25 do not exist in the other i rows, i + 1 rows, i + 5 rows, and i + 6 rows. The potential corresponding to the optical signal is held in the FDs 7 of all the pixels at the timing of “t21” in FIG. 9, and the signal of each row is transmitted to the row output circuit 26 via the row output PMOS amplification transistor 31 and the horizontal signal line 27. To do. As described above, the signal level of the row where the three-dimensional information pixel 25 is present is high, and the signal level of the row where the three-dimensional information pixel 25 is not present is low. Subsequently, the process proceeds to a determination period for determining a row in which the three-dimensional information pixel 25 exists.

  At the timing of “t22”, the determination on the j-th row is performed. A signal for turning on the determination switch RJj of the j-th row is sent from the timing generation circuit 13, and the row output level of the j-th row transmitted to the row output circuit 26 is transmitted to the determination circuit 28, and the three-dimensional information pixel 25 is transmitted. Is included. As shown in FIG. 7, here, since the three-dimensional information pixel is not included in the j-th row, it is determined that the three-dimensional information pixel is not included in the j-th row, and the next row is determined. At the timing of “t23”, the determination on the (j + 1) th row is performed, and since the three-dimensional information pixels are not included like the jth row, the determination is made on the next row. At the timing of “t24”, the determination of the j + 2th row is performed. As shown in FIG. 7, the j + 2th row includes the three-dimensional information pixel 25, and the operation shifts to the reading operation of the j + 2th row. Details of driving from the determination timing “t25” on the j + 3th row from “t + 24” will be described in detail in the timing chart of the three-dimensional information holding row of the first embodiment of the present invention in FIG.

  The determination timing of the jth row of “t24” shown in FIG. 10 means the same timing as “t24” of FIG. After it is determined that the three-dimensional information pixel 25 is included in the j + 2 row, in the operation of reading the pixel signal of the j + 2 row to the column output circuit 11, first, the row read at the timing “t30”, here the j + 2 row A selection pulse SELj + 2 is input to the selection transistor 6 through the selection transistor wiring 10. At this time, the optical signal of the photodiode 1 has already been transferred to the FD 7 at the timing of “t21”, and the output level of each pixel corresponding to the optical signal is transmitted to the vertical signal line 2, and the output level is the column output. It is transmitted to the circuit 11.

  An example of the configuration of the column output circuit 11 will be described with reference to the column output circuit configuration diagram of the first embodiment of the present invention shown in FIG. As described above, the pixel 12 has two output lines, which are the horizontal signal line 27 connected to the row output circuit 26 and the vertical signal line 2 connected to the column output circuit 11. The column output circuit 11 is provided with an optical signal holding capacitor 32 and a reset signal holding capacitor 33 for holding an optical signal and a reset signal in each column. These capacitors are connected to the vertical signal line 2 through switches, and each switch is an SHS (Sample Hold Signal) switch 34 and an SHR (Sample Hold Reset) switch 35. By turning on these switches, The signal potential of the signal level of the output signal line 2 is held in each holding capacitor. The held signal potential is output to the outside by turning on the column selection switch 36, and between the column selection switch 36 and the capacitor, a signal source configured by a current source 37 and an in-column amplification transistor 38 is used for signal amplification. Source follower connections are made.

  In the row selected at the timing “t30” in FIG. 10, the output level of each pixel corresponding to the optical signal is transmitted to the optical signal holding capacitor 32 by turning on the SHS switch 34 at the timing “t31”. When the reset pulse RXj + 2 is input to the reset transistor 4 at the timing of “t32”, the charge corresponding to the optical signal stored in the FD 7 is reset, and each pixel corresponding to the reset signal at the timing of “t33” Is transmitted to the reset signal holding capacitor 33 when the SHR switch 35 is turned on. With these operations, the optical signal and the reset signal of each pixel in the j + 2 row are transmitted to the column output circuit 11.

  The optical signal and the reset signal held in the column output circuit 11 are sequentially output to the outside by sequentially turning on the column selection switch 36. For example, the signal of the optical signal holding capacitor 32-1 corresponding to the optical signal in the i column at the timing of “t34” is turned ON by turning on the column selection switch (HdecSi) 36-1, and i at the timing of “t35”. The signal of the reset signal holding capacitor 33-1 corresponding to the column reset signal is output to the outside by turning on the column selection switch (HdecRi) 36-2, and the optical signal corresponding to the optical signal of the i + 1 column at the timing of “t36”. The column selection switch (HdecSi + 1) 36-3 is turned on to output the signal of the storage capacitor 32-2 to the outside, and the signal of the reset signal storage capacitor 33-2 corresponding to the reset signal of the i + 1 column at the timing "t37" The selection switch (HdecRi + 1) 36-3 is turned ON and output to the outside. By performing these driving operations for each column, the light signals and reset signals of all the pixels in the (j + 2) th row are output to the outside, and the process proceeds to the row determination in the (j + 3) th row at the next timing “t25”. The same driving as described above is performed at the timing “t26” for the j + 4 row, at the timing “t27” for the j + 5 row, and at the timing “t28” for the j + 6 row. In order to cancel the potential variation in each pixel, the difference between the optical signal and the reset signal is obtained by an external circuit or a circuit provided in the CMOS image sensor.

Compared to the conventional technique for reading all pixels, the present invention is capable of speeding up the reading time by selectively reading only the rows including the three-dimensional information pixels 25 and reducing the amount of data used for the three-dimensional calculation. It is an effect.
A selected row for transmitting a row number from the timing generation circuit 13 of FIG. 7 to the outside in order to inform the three-dimensional computer 23 of what row the read row including the three-dimensional information pixel 25 is. A number output line 30 is provided.

An example of speeding up, which is an effect of the present invention, will be described. For example, if a pulse is generated with a clock of 24 MHz, the row determination period determined by one pulse, for example, the period of “t22” and “t23” is 41 nsec (= 1 sec / 24M), and includes the three-dimensional information pixel 25. The determination is made at 41 nsec for a line that does not exist, and the process proceeds to the next line determination. The readout period of the row including the three-dimensional information pixel 25, for example, the period “t24” and “t25” includes the reset pulse RX, the SHS switch pulse, the SHR switch pulse, the row selection pulse SEL, and the column selection switch pulse Hdec. , From “t38” to “t39”, the reset pulse RX, SHS switch pulse, SHR switch pulse, and row selection pulse SEL are driven to each pixel and usually require several thousand nsec (several μsec). Here, the period from “t38” to “t39” is 4000 nsec. Next, the period from “t39” to “t25” is a pulse to the column selection switch 36 of each column, but this is in the column output circuit and can be driven by one pulse of 24 MHz as in the row determination period. is there. The number of pulses depends on the number of columns in the pixel arrangement. For example, in the case of a 100 × 100 pixel arrangement, a total of 200 pulses is required for the HdecS pulse and the HdecR pulse of 100 pulses, and 8200 nsec (= 41 nsec × 200 pulses). ) A period of 12200 nsec, which is a combination of the pixel drive time 4000 nsec from “t38” to “t39” and the output period 8200 nsec from “t39” to “t25”, is the readout period of the row including the three-dimensional information pixels 25.
That is, according to the configuration of the present embodiment, the drive period 41 nsec of the row not including the three-dimensional information pixel is approximately 1/300 times as long as the drive period of the including row, compared with the CMOS image sensor that reads all the pixels. , A significant speedup is possible.

  FIG. 12 shows a configuration diagram of a pixel unit according to the second embodiment of the present invention. The difference from the first embodiment shown in FIG. 8 is that the row output amplifying transistor uses a row output NMOS amplifying transistor 39 composed of NMOS. As described in the first embodiment, in the amplification transistor having the NMOS configuration, the voltage of the row output level from the three-dimensional information holding pixel 25 on which the sheet light is incident is lower than that of the pixel 25 on which the sheet light is not incident. Therefore, row determination including the three-dimensional information holding pixel 25 cannot be performed. In the first embodiment, a configuration in which the voltage is inverted by using the row output PMOS amplifying transistor is proposed. However, in the second embodiment, the gate of the NMOS configuration row amplifying NMOS amplifying transistor 39, the FD7, By arranging the signal inversion inverter 40 between the two, the row output level of the three-dimensional information holding pixel 25 is set higher than that of the pixel 25 on which no sheet light is incident.

  According to the configuration of the present embodiment, as an effect of using the row output NMOS amplifying transistor 40, the transfer transistor 3, the reset transistor 4, the amplifying transistor 5, the selection transistor 6, which are other transistors configured in the pixel, The same NMOS configuration can be achieved, and the unification of these transistor types increases the degree of freedom in layout.

FIG. 13 shows a configuration diagram of a CMOS image sensor according to the third embodiment of the present invention. In the CMOS sensor configuration diagram of FIG. 7 shown in the first embodiment, one determination circuit 28 is arranged and the signal of each row is sequentially determined by the determination circuit 28. However, the method of determining each row is also effective. Are the same. FIG. 13 shows an example of a configuration diagram of a CMOS image sensor for determination in each row. A horizontal signal line 27 in each row is connected to a determination circuit 28 arranged in each row, and the signal in each row is three-dimensionally displayed in that row. It is determined whether the information pixel 25 exists. The determination result is held in, for example, a register composed of flip-flops, etc., and a signal for selecting each row from the timing generation circuit 13 by the multiplexer 42 and the determination result held in the register 41 are taken and three-dimensional information is obtained. For the row determined to include the pixel 25, the read operation is performed.
The pixel configuration and timing chart are the same as those shown in the first and second embodiments, and the arrangement of the determination circuit is different in the third embodiment.

  As described above, according to the present invention, a row output circuit for determining a pixel including three-dimensional information and a pixel not including the three-dimensional information and an effective pixel circuit for outputting a row are configured to include three-dimensional information. By skipping the reading of the line determined to be absent and reading only the line including the three-dimensional information, the CMOS image sensor can be speeded up and the data used for the three-dimensional calculation can be reduced.

  The solid-state imaging device used for the three-dimensional shape measurement of the present invention is a device that inspects three-dimensional defects such as dents and scratches on the surface of a measurement object such as a medical product such as a tablet or food or industrial product at high speed without contact. It is also useful as a device for inspecting a three-dimensional defect of a structure such as a tunnel at high speed by mounting it on a vehicle.

DESCRIPTION OF SYMBOLS 1 Photodiode 2 Vertical signal line 3 Transfer transistor 4 Reset transistor 5 Amplification transistor 6 Selection transistor 7 Floating diffusion (FD)
8 Transfer transistor wiring 9 Reset transistor wiring 10 Selection transistor wiring 11 Column output circuit 12 Pixel 13 Timing generation circuit 14 Row selection circuit 15 Measurement object 16 Pattern light source 17 Imaging device 18 Sheet-like light (sheet light)
19 Lens 20 CMOS Image Sensor 21 FPGA (Field Programmable Gate Array)
22 I / O interface 23 3D computer 24 Monitor 25 3D information pixel 26 Row output circuit 27 Horizontal signal line 28 Judgment circuit 29 Judgment switch (RJ)
30 Selected row number output line 31 PMOS amplifier transistor for row output 32 Optical signal holding capacitor 33 Reset signal holding capacitor 34 SHS (Sample Hold Signal) switch 35 SHR (Sample Hold Reset) switch 36 Column selection switch 37 Current source 38 In the column circuit Amplifier transistor 39 Row output NMOS amplifier transistor 40 Signal inversion inverter 41 Register 42 Multiplexer

Claims (7)

A pixel is arranged in a matrix on a semiconductor substrate, and a photodiode that converts light into signal charges and stores the pixel, and a first amplification transistor that converts the charge stored in the photodiodes into voltage are disposed on the pixels. And
Each column of pixels comprises a column signal output line for receiving a signal from the pixel,
A row signal output line for receiving a signal from the pixel is provided for each row of the pixels,
Before outputting the signal from the column signal output line, the pixel signal is output from the row signal output line, a row signal determination circuit disposed on the semiconductor substrate is used to determine a read row and a non-read row, and the column A solid-state imaging device, wherein a non-reading row is not read out when outputting through a signal output line.
The period necessary for determining the non-reading row is the sum of the period necessary for determining the reading row and the period necessary for reading the pixel signal of the reading row output from the column signal output line. The solid-state imaging device according to claim 1, wherein the solid-state imaging device is shorter than 1/300.
The solid-state imaging device according to claim 1, further comprising means for outputting a row number determined as a read row by the row signal determination circuit to the outside.
The pixel has a source of the first amplification transistor connected to the column signal output line, a drain of the second amplification transistor connected to the row signal output line, a gate of the first amplification transistor and the first The solid-state imaging device according to claim 1, wherein the gates of the two amplification transistors are connected.
The solid-state imaging device according to claim 4, wherein the second amplification transistor is formed of a PMOS.
The pixel has a source of the first amplification transistor connected to the column signal output line, a source of a third amplification transistor connected to the row signal output line, a gate of the first amplification transistor and the first The solid-state imaging device according to claim 1, wherein the gates of the three amplification transistors are connected via an inverter.
The solid-state imaging device according to claim 6, wherein the third amplification transistor is formed of an NMOS.