JP2015019381A - Uninterruptible switching system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to upgrade, without interrupting a service, from single-system operation without a reserve system to a redundant system capable of uninterruptible switching.SOLUTION: An interruptible switching system of the invention includes an active memory and a standby memory that store communication data extracted from signals received from an active transmission system and a standby transmission system respectively. Delay adjusting means makes the amount of delay equal between the active transmission system and the standby transmission system by continuously changing a read-out clock frequency of the active memory in a range of frequency deviation capable of maintaining predetermined communication quality.

Description

  The present invention relates to an uninterruptible switching system for switching a path transmission path without instantaneous interruption and providing a highly reliable digital communication service in order to increase fault tolerance.

  Data traffic is increasing rapidly with the expansion of use of the Internet. In order to support such traffic, the transmission capacity of transmission devices that support the backbone network is steadily expanding. In such a transmission apparatus, there is OTN (Optical Transport Network) defined by ITU-T as an international standardization technique for transferring a wide variety of client signals including Ethernet (registered trademark) with high reliability. For example, the maximum transmission distance of Ethernet (registered trademark) defined by IEEE is 40 km, but by accommodating Ethernet (registered trademark) in OTN, highly reliable long-distance transfer exceeding 40 km becomes possible.

  In recent years, with the widespread use of Ethernet (registered trademark), the OTN standard has been greatly expanded to emphasize Ethernet (registered trademark) transfer (for example, see Non-Patent Document 1). Specifically, ODU0 that accommodates GbE, ODU2e that accommodates 10 GbE, and ODU4 that accommodates 100 GbE are defined as new ODUs (Optical Channel Data Units).

  In addition, ODUflex has been defined that can support new client signals that will appear in the future and provide an intermediate band. For example, when a client signal having a bit rate of 20 Gbit / s appears in the future, it is possible to efficiently accommodate the client signal by using ODUflex having a payload capacity of 20 Gbit / s. As an example of the intermediate band, it is possible to transfer 100 GbE at an effective band of 50 Gbit / s, and this can be realized by using ODUflex with a payload capacity of 50 Gbit / s. .

  As described above, while transmission capacity per wavelength increases in OTN, the signals multiplexed there are diversified. Specifically, ODUs (ODU0, ODU1, ODU2, ODU2e, ODU3, ODU4, ODUflex) accommodating client signals are appropriately multiplexed and transmitted at a 100G wavelength (ODU4 / OTU4). At that time, a digital cross-connect device (ODU cross-connect device) that cross-connects multiplexed signals plays an important role in improving the economics, flexibility, and operability of the network.

  Further, in an optical communication system that transfers a large amount of data, a redundant system is often configured to ensure reliability. Redundant system refers to, for example, another route and system that becomes a backup for the active system that provides the service. If a failure occurs in the active system, the system is trusted by switching to the standby system and continuing the service. Can be improved. When a redundant system is configured, the transmission signal passes through different routes in the active system and the standby system, so the amount of delay is different, and it takes a considerable amount of time from sudden failure to switching execution. Data interruption occurs when switching to the system.

  FIG. 1 shows an apparatus that realizes the conventional uninterruptible switching function proposed in Patent Document 1. In Fig. 1, bit errors are detected using bit error check methods (parity check or CRC (Cyclic Redundancy Check) code, etc.) independently on both sides of the same data signal transmitted through different paths, with the delays aligned on the receiving side. A check is always made, and when there is an error in the working transmission line and no error has occurred in the standby transmission line, the backup transmission line is switched without interruption.

  In addition, as described above, IP data is generally transferred by Ethernet (registered trademark) in a LAN environment, but Ethernet (registered trademark) has a maximum transmission distance of 40 km, In order to connect longer distances with Ethernet (registered trademark), a wide-area Ethernet (registered trademark) transfer technology is required. Extended OTN (Optical Transport Network) defined by ITU-T is important because it can accommodate various sizes of Ethernet (registered trademark) (1G / 10G / 40G / 100G) directly in ODU (optical channel data unit) frames Is increasing. With the advent of various IP services, it is expected that the dynamic characteristics of traffic will fluctuate greatly, and when forwarding over the ODU path, setting and deletion of various size paths will be repeated frequently, so halfway size There is a risk that time slots (arrangement of path capacity within one wavelength) and discontinuous wavelengths may occur. In order to avoid such a situation and reduce the cost of the network, it has been studied to optimize (rearrange) the time slots and wavelengths to be used.

  FIG. 2 shows a conventional wavelength control network system proposed in Patent Document 2. In FIG. In FIG. 2, the node device, wavelength switch device, or centralized management device receives a connection request message for connecting node devices using optical signals of a plurality of wavelengths, but there is no required number of consecutive free wavelengths. In addition, the requested number of consecutive free wavelengths are secured by rearranging the wavelengths being used by other node devices, and the requested node devices are connected using the reserved free wavelengths. When rearranging the existing used wavelengths in order to secure a free wavelength, path switching occurs. When path switching is performed, switching time between the original path and the switching destination path is required, and since the path length between the paths is generally different, the frame must be re-synchronized. Occur.

  In recent years, the data rate has been increasing more and more, a transmission apparatus having a bit rate of 40 Gbps has already been put into practical use, and a transmission apparatus having a 100 Gbps is also close to practical use. At such a transmission speed, a large amount of data is lost even if there is a momentary interruption of about 1 second, and the influence is great. In order to provide a more reliable service, a non-instantaneous switching method that does not cause instantaneous interruption of 1-bit data at the time of switching has been proposed, and a non-instantaneous switching function has been realized in a transmission device that requires high service quality. Yes.

  FIG. 3 shows an apparatus that realizes the conventional uninterruptible switching function proposed in Patent Document 2. In FIG. 3, the bit data is always checked by using a bit error check method (parity check or CRC code, etc.) independently of each other with the same data signal transmitted through different paths being delayed on the receiving side. When an error occurs in the transmission line and no error occurs in the backup transmission line, the backup transmission line is switched without interruption. In the non-instantaneous switching technique disclosed in Patent Document 2, it is necessary to determine an active system and a standby system in advance and to align delay lengths.

  If the path to be relocated for path optimization is a path to which switching without interruption is applied, it must be possible to maintain the active and standby systems even if the path relocation is switched. However, since the switching performed at the time of path optimization is a relocation destination designed at the time of requesting a path, and the result varies depending on the path usage status at that time, the route and route length of the relocation destination path cannot be predicted in advance. Therefore, the path optimization technique disclosed in Patent Document 1 cannot be applied to the non-instantaneous switching system disclosed in Patent Document 2. In other words, it is impossible to move to another path while maintaining an uninterrupted system.

JP-A-9-36826 JP2009-071614

ITU-T Recommendation G. 709 / Y. 1331 (12/2009), "Interfaces for Optical Transport Network (OTN)". Kawase et al., "Study of uninterrupted frame switching method in SDH network", vol. J78-B-I, no. 12, 1995/12.

The basic configuration of a conventional digital cross-connect device is shown in FIG. The network side interface (reception), the network side interface (transmission), the client side interface (reception), the client side interface (transmission), and the cross-connect unit. In such a digital cross-connect device,
(1) Path uninterrupted relocation to switch the transmission path of the path (ODU path in the case of OTN) without interruption (2) Path type uninterrupted change to change the path type without interruption (duplicated) Single path that has not been connected ← → Duplicated and non-instantaneous switching path that can be switched without instantaneous interruption)
(3) It is not possible to generate an uninterrupted switching path in a section that is not initially assumed. Explaining (2), with the technology so far, it is possible to change a path in operation (that is not duplicated) to a path that can be switched without duplication without affecting the service. could not. This is because the generation of a path that can be switched without duplication in the prior art is started after the delay difference between the two paths is adjusted before the operation is started, and then the operation is switched to the state that can be switched without hitting. It is. The reason for this operation method is that the delay adjustment cannot be performed without affecting the service on the operating path.

  Many studies have been made on the generation of the uninterruptible switching path (3) above (an example of the prior art is shown in FIG. 5). In addition, there is a technology (for example, refer to Non-Patent Document 2) that sets a non-interruption assuming a maximum path length difference (delay time difference) between fixed points at the start of operation. It could not cope with any path length difference (delay time difference).

  Briefly explaining the non-instantaneous switching technology, the non-instantaneous switching technology is to split the signal on the transmission side, transmit the same signal on multiple paths, and adjust the delay difference of multiple paths on the reception side. This is a technique for switching paths without disconnecting signals by switching between faults and plans by switching without missing one bit by a selector.

  If the digital cross-connect device can be used to transfer a path without interruption, change the path type without interruption, or generate a path without interruption, the signal can be transmitted without affecting the user. By changing the route or relocating the path without interruption, the multiplexed signals can be reconfigured without interruption, the path can be relocated without interruption, or the service can be requested without interruption. Accordingly, the path type can be changed (service reliability can be changed). FIG. 6 shows a conceptual diagram of non-instantaneous switching path generation, path type uninterruptible switching, and path uninterrupted relocation. Further, FIG. 7 shows a conceptual diagram of non-instantaneous recombination of multiple signals and relocation of non-instantaneous paths.

  In the method according to the above-described prior art (Patent Document 1), it is necessary to secure an active system and a standby system in advance, and the hardware is special and expensive, such as mounting a large-capacity memory, and disclosed in Patent Document 1. It has been difficult to apply to path switching for the purpose of optimizing the path being used.

  The present invention has been made in view of the above points, and provides an uninterruptible switching system capable of upgrading from a one-system operation without a standby system to a redundant system capable of instantaneously switching without interrupting service. That is.

  In addition, the purpose of the present invention is to interrupt the service while maintaining the uninterruptible switching system or the uninterrupted redundant system that enables downgrade from uninterrupted to single system operation without interrupting the service. It is to provide an uninterruptible switching system that can be relocated without doing so.

  In addition, another object of the present invention is to provide an uninterrupted path transfer, an uninterrupted path type change that can handle an arbitrary path length difference (delay time difference) between arbitrary points (including the end and middle of the ODU path), An object is to provide an uninterruptible switching system capable of generating an uninterrupted switching path.

In order to solve the above problem, according to one aspect of the present invention, an active transmission system that transmits a signal received from a first transmission path;
A standby transmission system for transmitting the signal received from the second transmission line;
Non-instantaneous switching device for detecting a delay difference in signals between the active transmission system and the standby transmission system and adjusting a delay between the active transmission system and the standby transmission system based on the detected delay difference And an uninterruptible switching system,
The uninterruptible switching device is
An active memory and a standby memory for storing communication data extracted from signals received from the active transmission system and the standby transmission system, respectively;
Delay adjustment for equalizing the amount of delay between the active transmission system and the standby transmission system by continuously changing the read clock frequency of the active memory within a frequency deviation range in which predetermined communication quality can be maintained Means,
A non-instantaneous switching system is provided.

  As described above, according to the present invention, an uninterruptible switching system capable of upgrading from a one-system operation without a standby system to a redundant system that can be switched without instantaneous interruption without interrupting the service. It is possible to provide an uninterruptible switching system that enables downgrade to system operation and an uninterruptible switching system that can be moved without interrupting services while maintaining an uninterrupted redundant system. In addition, the uninterruptible switching system according to the present invention can be operated with a simple (inexpensive) configuration before the upgrade because hardware necessary for starting the uninterruptible service is added.

It is a figure which shows the structure of the uninterruptible switching apparatus by a prior art. This is a conventional wavelength control network system. It is a conventional non-instantaneous switching device. It is a block diagram of the cross-connect apparatus of a prior art. It is a figure which shows the non-instantaneous interruption of a prior art. It is a conceptual diagram of path generation, path type change, and path relocation. It is a conceptual diagram of path rearrangement / multiple rearrangement. It is a block diagram of the digital cross-connect apparatus in the 1st Embodiment of this invention. It is an example of the delay adjustment part in the 1st Embodiment of this invention. It is a figure which shows the uninterruptible switching of the ODU path | pass (in the case of the structure of FIG. 8) in the 1st Embodiment of this invention. It is a figure which shows the uninterruptible switching of the certain area in the 1st Embodiment of this invention (in the case of the structure of FIG. 8). It is a block diagram of the digital cross-connect apparatus in the 2nd Embodiment of this invention. It is a block diagram of the digital cross-connect apparatus in the 3rd Embodiment of this invention. It is a figure which shows the uninterruptible switching of the ODU path | pass (in the case of the structure of FIG. 13) in the 3rd Embodiment of this invention. It is a figure which shows the non-instantaneous switching of a certain area in the 3rd Embodiment of this invention (in the case of a structure of FIG. 13). It is a block diagram of the digital cross-connect apparatus in the 4th Embodiment of this invention. It is a figure which shows the uninterruptible switching of the ODU path | pass (in the case of the structure of FIG. 16) in the 4th Embodiment of this invention. It is a figure which shows the uninterruptible switching (in the case of the structure of FIG. 16) of a certain area in the 4th Embodiment of this invention. It is a block diagram of the digital cross-connect apparatus in the 5th Embodiment of this invention. It is a block diagram of the digital cross-connect apparatus in the 6th Embodiment of this invention. It is a block diagram of the digital cross-connect apparatus in the 7th Embodiment of this invention. It is a figure which shows the uninterruptible switching of the ODU path | pass (in the case of the structure of FIG. 21) in the 7th Embodiment of this invention. It is a figure which shows the uninterruptible switching (in the case of the structure of FIG. 21) of a certain area in the 7th Embodiment of this invention. It is a block diagram of the digital cross-connect apparatus in the 8th Embodiment of this invention. It is FIG. (1) which shows the uninterrupted transfer process of the ODU path | pass in the 9th Embodiment of this invention. It is FIG. (2) which shows the uninterrupted transfer process of the ODU path | pass in the 9th Embodiment of this invention. It is FIG. (The 3) which shows the uninterrupted transfer process of the ODU path | pass in the 9th Embodiment of this invention. It is FIG. (4) which shows the uninterrupted transfer process of the ODU path | pass in the 9th Embodiment of this invention. It is FIG. (1) which shows the uninterrupted transfer process of the ODU path | pass in the 10th Embodiment of this invention. It is FIG. (2) which shows the uninterrupted transfer process of the ODU path | pass in the 10th Embodiment of this invention. It is FIG. (The 3) which shows the uninterrupted transfer process of the ODU path | pass in the 10th Embodiment of this invention. It is a figure which shows transfer of the path | pass in the 11th Embodiment of this invention. It is a figure which shows the triple corresponding | compatible interface in the 12th Embodiment of this invention. It is a figure which shows the triple corresponding | compatible interface (memory expansion) in the 12th Embodiment of this invention. It is a figure which shows the structure of the uninterruptible switching apparatus by 13th Embodiment of this invention. It is a figure which shows the modification of the uninterruptible switching device by 13th Embodiment of this invention. It is a figure which shows the structure of the uninterruptible switching device by 14th Embodiment of this invention. It is a figure which shows the structure of the uninterruptible switching device by 15th Embodiment of this invention. It is a figure explaining the process in the uninterruptible switching device by 15th Embodiment of this invention. It is a figure explaining the process in the uninterruptible switching device by 15th Embodiment of this invention. It is a figure explaining the process in the uninterruptible switching device by 15th Embodiment of this invention. It is a figure explaining the process in the uninterruptible switching device by 15th Embodiment of this invention. It is a figure which shows the structure of the uninterruptible switching device by 16th Embodiment of this invention. It is a figure which shows the structure of the uninterruptible switching apparatus by 17th Embodiment of this invention. It is a figure explaining the process in the uninterruptible switching device by 17th Embodiment of this invention. It is a figure explaining the process in the uninterruptible switching device by 17th Embodiment of this invention. It is a figure explaining the process in the uninterruptible switching device by 17th Embodiment of this invention. It is a figure explaining the process in the uninterruptible switching device by 17th Embodiment of this invention. It is a figure explaining the process in the uninterruptible switching device by 18th Embodiment of this invention. It is a figure explaining the process in the uninterruptible switching device by 18th Embodiment of this invention. It is a figure explaining the process in the uninterruptible switching device by 18th Embodiment of this invention. It is a figure explaining the process in the uninterruptible switching device by 18th Embodiment of this invention. It is a figure explaining the process in the uninterruptible switching device by 18th Embodiment of this invention. It is a figure explaining the process in the uninterruptible switching device by 18th Embodiment of this invention. It is a figure explaining the process in the uninterruptible switching device by 18th Embodiment of this invention. It is a figure which shows the structure of the uninterruptible switching device by 19th Embodiment of this invention. It is a figure which shows the structure and operation | movement for delay adjustment by the 19th Embodiment of this invention. It is a figure which shows the structure and operation | movement for delay adjustment by the 19th Embodiment of this invention. It is a figure which shows the other structure of the uninterruptible switching device by 19th Embodiment of this invention. It is a figure which shows the structure of the uninterruptible switching device by 20th Embodiment of this invention. It is a figure which shows the structure and operation | movement for delay adjustment by the 20th Embodiment of this invention. It is a figure which shows the structure and operation | movement for delay adjustment by the 20th Embodiment of this invention. It is a figure which shows the other structure of the uninterruptible switching device by 20th Embodiment of this invention. It is a block diagram of the uninterruptible switching device in the 21st embodiment of the present invention. It is a figure for demonstrating control of the uninterruptible switching apparatus in the 21st Embodiment of this invention. It is a figure for demonstrating the rearrangement of the wavelength in the 22nd Embodiment of this invention. It is a figure for demonstrating the rearrangement on the time slot in the 23rd Embodiment of this invention.

  Embodiments of the present invention will be described below with reference to the drawings.

[First Embodiment]
FIG. 8 shows the configuration of the digital cross-connect device in the first embodiment of the present invention.

The digital cross-connect device shown in the figure is
・ Cross connect part 10
-Network side interface (reception) 20
-Network side interface (transmission) 40
-Client side interface (reception) 30
-Client side interface (transmission) 50
Consists of Although only one interface is shown in the figure, there may be a plurality of identical ones or some may not exist.

  The cross-connect unit 10 has a plurality of input ports and a plurality of output ports, and can cross-connect signals input from the input ports and output them to any output port.

  Note that a cross-connect that is restricted to output only to a specific output port instead of an arbitrary output port may be used.

The network side interface (reception) 20 includes
Receiver 21: Receives transmitted signals and performs optical / electrical conversion:
Framer / separator 22: Receives an OTU signal from the receiver 21 and performs frame processing and separation of multiplexed ODU signals:
Branching unit 23: The ODU signal separated by the framer / separating unit 22 is branched into a plurality of parts:
Conversion unit 24: Converts the ODU signal to a signal format handled by the cross-connect unit 10 as necessary:
Is equipped.

In the network side interface (transmission) 40,
Conversion unit 41: Converts the signal format handled by the cross-connect unit 10 from an ODU signal as necessary.

Delay adjustment unit 42: Performs delay adjustment according to the delay control information from the selection unit 43:
Selection unit 43: Confirms the identity of a plurality of ODU signals input from the delay adjustment unit 42, detects a delay difference between the plurality of ODU signals, generates and transmits delay control information, and further inputs an arbitrary input Select and output ODU signal (can be switched without missing 1 bit when switching):
Framer / multiplexer 44: Receives and multiplexes a plurality of ODU signals from the selector 43, performs frame processing, and outputs them as OTU signals:
Transmitter 45: Receives the OTU signal from the framer / multiplexer, performs electrical / optical conversion, and sends the signal to the transmission path:
Is equipped.
The client side interface (reception) 30 includes
Client receiver 31: Receives signals from client devices and performs optical / electrical conversion:
Mapping unit 32: Frame-processes the client signal that has been electrically converted and outputs it as an ODU signal:
Branch unit 33: Branches the ODU signal into a plurality of:
Conversion unit 34: Converts an ODU signal to a signal format handled by the cross-connect unit 10 as necessary:
Is equipped.

In the client side interface (transmission) 50,
Conversion unit 51: Converts the signal format handled by the cross-connect unit 10 from an ODU signal as necessary:
Delay adjustment unit 52: Performs delay adjustment according to the delay control information from the selection unit 53:
Selection unit 53: confirms the identity of a plurality of ODU signals, detects a delay difference between the plurality of ODU signals, generates and transmits delay control information, and further selects and outputs an arbitrary input ODU signal (When switching, it is possible to switch without missing one bit):
Demapping unit 54: Demaps the client signal from the ODU signal:
Client transmission unit 55: Receives a signal from the demapping unit 54, performs electrical / optical conversion, and sends the signal to the client device:
Is equipped.

  The cross-connect unit 10 can switch the signal input from the input port to an arbitrary output port and output it. A synchronous switch, an asynchronous switch, a packet switch, or the like can be used to realize the cross-connect. Depending on the type of switch to be used, each interface converts the signal format using a conversion unit as necessary. Further, in the network side interface (reception) 20 and the client side interface (reception) 30, the order of the branching units 23 and 33 and the conversion units 24 and 34 may be reversed. In the network side interface (transmission) 40 and the client side interface (transmission) 50, the order of the conversion units 41 and 51 and the selection units 43 and 53 may be reversed.

  The configuration example of the delay adjustment units 42 and 52 includes an interface (IF) unit 1, a FIFO memory 2, and a clock adjustment unit 3, as shown in FIG. The interface (IF) unit 1 regenerates the clock of the input signal. The signal is input to the FIFO memory 2, and the regenerated clock is used as a FIFO write clock and also input to the clock adjustment unit 3. The clock adjustment unit 3 changes the frequency of the clock based on external delay control information. For example, as shown in FIG. 9B, when the clock frequency is intentionally lowered by 1 ppm within a certain time range, the delay time increases because the FIFO read clock is slower than the write clock. As shown in FIG. 9C, if the clock frequency is intentionally increased by 1 ppm within a certain time range, the delay time decreases because the FIFO read clock is earlier than the write clock. The change of the clock frequency changes the frequency continuously or discretely within a range that does not affect the client signal. The clock frequency should be within the ODU clock deviation specified in Recommendation G.709. In addition, FIFO overflow and underflow do not occur by intentionally changing the clock. The intentional amount of change in the clock frequency can take any value within a range that does not affect the client signal. If the amount of change is increased, the desired delay time can be set earlier.

  The following methods can be considered for checking the identity of the signals in the selection units 43 and 53 and detecting the delay time.

  The identity can be confirmed using a specific field of the ODUk overhead, such as the content of a TTI (Trail Trace Identifier). For the detection of the delay time, MFAS (MultiFrame Alignment Signal, in which values from 0 to 255 are sequentially given) can be used in the overhead area. If the delay difference is less than half of the maximum value assigned to the frame, the delay difference can be detected. (In the case of MFAS, the difference is recognized if the delay difference is within the time corresponding to 128 frames. can do). When the delay difference is more than that, it is possible to cope with a larger delay difference by assigning a number from 0 to 65535 to each frame, for example, similarly to MFAS using another overhead area.

  A digital cross-connect device composed of such components is installed at each site to form a network.

  FIG. 10 shows a state in which an uninterruptible switching path is operated between two bases A and B. The two dotted lines on the left and right represent the respective bases A and B, and the two bases are connected by the route a and the route b. The network-side interface (reception) 20, the network-side interface (transmission) 40, the client-side interface (reception) 30, the client-side interface (transmission) 50, and the cross-connect (XC) unit 10 shown in FIG. The NW side IF (RX) 20, the NW side IF (TX) 40, the Client side IF (RX) 30, the Client side IF (TX) 50, and the XC unit 10, respectively. Further, a wavelength demultiplexing unit for wavelength multiplexing transmission that multiplexes and transmits a plurality of wavelengths on one optical fiber is shown as WDM DEMUX 60, and a wavelength multiplexing unit is shown as WDM MUX 70. The WDM DEMUX 60 and WDM MUX 70 are not necessary. Although not shown in the drawing, an optical switch (optical cross connect, optical ADM, etc.) may be provided in a portion through which the optical signal passes.

  At the site A on the left side, the client signal from the client device is accommodated in the ODU signal by the client side IF (RX) 30 and then branched into two and input to the XC unit 10. The XC unit 10 inputs two signals to different NW-side IF (TX) 40 in accordance with network settings. A signal from each NW-side IF (TX) 40 is transmitted through the route a and the route b to the right base. At the base B on the right side, the two signals are respectively received by the NW side IF (RX) 20 and then input to the XC unit 10 and input to one client side IF (TX) 50. Here, in the client-side IF (TX), the selection unit 53 in the client-side IF (TX) 50 confirms the identity of the two signals and detects the delay difference, and the delay control information is also used as the client-side IF (TX) 50. The delay adjustment unit 52 adjusts the delay based on the delay control information so as to eliminate the delay difference between the two signals. In the selection unit 53 in the client-side IF (TX) 50, when there is no difference in delay between the two signals, it becomes possible to perform failure switching and plan switching without interruption.

  FIG. 10 shows a state where the uninterruptible switching path is operating at the end of the ODU path (between the base where the client signal is accommodated in the ODU and the base where the client signal is extracted from the ODU). A state in which a certain section in the middle of the path is duplicated to enable uninterrupted switching is shown. The NW-side IF (RX) 20 of the left base A is the start point of duplexing, and the NW-side IF (TX) 40 of the right base B is the end point of duplexing. At the right base B, the two delay adjustment units are controlled based on the delay control information in the NW-side IF (TX) 40, thereby enabling uninterrupted switching of the section.

[Second Embodiment]
In the present embodiment, a case where the delay adjustment unit is in the preceding stage of the cross-connect unit 10 is shown.

FIG. 12 shows the configuration of a digital cross-connect device according to the second embodiment of the present invention. In the figure, the same components as those of the first embodiment shown in FIG.
The difference from the configuration shown in FIG. 8 of the first embodiment is that the delay adjustment unit 26 is positioned before the cross-connect unit 10.

  There is a delay adjustment unit 26 in the network side interface (reception) 20, and the delay is based on delay control information from the selection unit 43 in the network side interface (transmission) 40 or the selection unit 53 in the client side interface (transmission) 50. Is adjusted.

The operations of the selection units 43 and 53 are the same as those in the first embodiment. Sending delay control information from the selecting section 43, 53 two NW side IF _(RX) 20 1, 20 _2, the delay adjusting unit 26 of the NW side IF (RX) 20 to adjust the delay on the basis of the delay control information Thus, adjustment is made to eliminate the delay difference between the two signals. As a result, since there is no delay difference between the two signals, it becomes possible to perform failure switching and planned switching without interruption.

[Third Embodiment]
In the present embodiment, an example in which an extended memory for performing delay adjustment is provided in the subsequent stage of the cross-connect unit 10 is shown.

  FIG. 13 shows the configuration of a digital cross-connect device according to the third embodiment of the present invention. In the figure, the same components as those of the first embodiment shown in FIG.

  The digital cross-connect device of this embodiment has the same basic configuration as that of the first embodiment, but is different in that an expansion memory 80 can be installed.

  The inputs of the selection units 43 and 53 of the network side interface (transmission) 40 and the client side interface (transmission) 50 are increased so that the expansion memories 80A and 80B can be connected. In the example of FIG. 13, the extended memory 80 </ b> A is connected to the network side interface (transmission) 40 and adjusts the delay difference based on the delay control information input from the selection unit 43. The extended memory 80 </ b> B is connected to the client side interface (transmission) 50 and adjusts the delay difference based on the delay control information input from the selection unit 53.

  The extended memory 80 includes an extended delay adjusting unit 82. By preparing the extended delay adjusting unit 82 corresponding to various delay times, it is possible to adjust a delay difference between a plurality of paths that are not initially assumed. To do. The expansion memory 80 can be expanded during operation, and the expansion memory can be used as an active system without interruption.

  For example, during the operation of the client side interface (transmission) 50, the expansion memory 80B is connected to the client side interface (transmission) 50. After the cross-connect unit 10 is switched so that the same signal is conducted to the expansion memory 80B, the selection unit 53 performs a delay adjustment unit 52 in the client side interface (transmission) 50 and an expansion delay adjustment unit in the expansion memory 80B. By adjusting the delay of 82B to eliminate the delay difference, the signal via the extended memory 80B can be made into the active system without interruption.

FIG. 14 shows a state in which an uninterrupted switching path is operated when this configuration example is used. The client side IF (RX) 30 of the left base A is the start point of the uninterruptible switching path, and the client IF (TX) 50 of the right base B is the end point of the uninterruptible switching path. At the site A on the left side, the client signal from the client device is accommodated in the ODU signal by the client side IF (RX) 30 and then branched into two and input to the XC unit 10. The XC unit 10 inputs _two signals to different NW-side IF (TX) 40 ₁ and 402 according to network settings. Signals from the NW side _{IF (TX) 40 1, 40} 2 is transmitted is transmitted through the path a and path b to the right of the base B. Here, it is assumed that the route a is shorter than the route b.

In the right base B, the two signals are respectively received by the NW-side IF (RX) 20 ₁ and 20 ₂ , and then input to the XC unit 10 and input to one client-side IF (TX) 50. Here, in the client-side IF (TX) 50, the selection unit 53 in the client-side IF (TX) 50 confirms the identity of the two signals and detects a delay difference. At this time, if the delay adjustment amount of the delay adjustment unit 52 in the client side IF (TX) 50 where the selection unit is present can compensate for the delay difference between the path a and the path b, the selection unit 53 performs the client side IF (TX ) When the delay adjusting unit 52 in 50 is used and it is recognized that there is not enough amount to compensate for the delay difference between the path a and the path b, the extended memory 80 is used (the dotted line in FIG. The case where it is used is illustrated.)

  Hereinafter, a case where the extended memory 80 is used will be described. The cross-connect unit 10 also inputs the same signal to the expansion memory 80, and the expansion delay adjustment unit 82 in the expansion memory 80 adjusts the delay based on the delay adjustment information from the selection unit 53, so that the path a and the path b Set the delay difference to zero. Since there is no delay difference between the two signals in the selection unit 53 in the client-side IF (TX) 50, it becomes possible to perform failure switching and plan switching without interruption.

  Although FIG. 14 shows a state where the uninterruptible switching path is operating at the end and end of the ODU path, FIG. 15 shows that a section in the middle of the ODU path is duplicated to enable uninterrupted switching. Show the state. The NW-side IF (RX) 20 of the left base A is the start point of duplexing, and the NW-side IF (TX) 40 of the right base B is the end point of duplexing. The extended memory 80 is used on the route a side of the right base B. Based on the delay control information from the NW-side IF (TX) 40, the delay adjusting unit 42 in the NW-side IF (TX) 40 and the extended delay adjusting unit 82 in the extended memory 80 determine the delays of the two paths a and b. Each is controlled to enable uninterrupted switching of the section.

[Fourth Embodiment]
In the present embodiment, an example in which an extended memory for performing delay adjustment is provided in the previous stage of the cross-connect unit 10 is shown.

  FIG. 16 shows a configuration of a digital cross-connect device according to the fourth embodiment of the present invention. In the figure, the same components as those of the first embodiment shown in FIG.

The configuration shown in FIG. 16 is a configuration in which the extended memory 80 can be connected to the network side interface (reception) 20. A branch unit 23 is provided between the framer / separator 22 and the delay adjustment unit 26 so that one of the branched signals can be output to the outside and connected to the expansion memory 80. The delay adjustment unit 26 of the network side interface (reception) 20 ₁ , 20 ₂ delays the signal input from the branch unit 23 according to the delay control information input from the selection unit 53 of the client side interface (transmission) 50. Make adjustments. Delay adjusting unit 26 of the network side interface (receiver) 20 _1, if it can compensate for the delay difference between the network side interface (receiver) 20 ₁ signal and the network side interface received in (receive) signal received by the 20 ₂ delay When the delay control is performed using the adjustment unit 26 and there is not enough amount to compensate for the delay difference, the expansion memory 80 is used. Thereby, expansion memory 80 performs delay adjustment signal input from the network side interface (receiver) 20 ₁ branches 23.

  FIG. 17 is similar to FIG. 14 except that the extended memory 80 is connected to the NW-side IF (RX) 20 and the delay control sent from the client-side IF (TX) 50 at the right base B Information is input to the delay adjustment unit 26 and the expansion memory 80 of the NW-side IF (RX) 20 at the same site, and the delay from the signal input from the branching unit 23 is adjusted by the expansion delay adjustment unit 82 of the expansion memory 80. This makes it possible to switch without interruption in the section. The configuration of FIG. 18 shows a state in which a section in the middle of the ODU path is duplicated to enable uninterrupted switching.

  The digital cross-connect devices in the following fifth, sixth, and seventh embodiments are all configured to use an extended memory, but are characterized in that any interface can be connected to the extended memory. .

[Fifth Embodiment]
In the present embodiment, an example is shown in which an extended memory for performing delay adjustment is provided in the subsequent stage of the cross-connect unit 10 and a switch unit for selecting an extended memory is further provided.

  FIG. 19 shows a configuration of a digital cross-connect device according to the fifth embodiment of the present invention. In the figure, the same components as those of the first embodiment shown in FIG.

  The configuration shown in FIG. 19 is similar to the configuration of FIG. 13 of the third embodiment, except that the switch unit 90 is provided between the expansion memories 80A and 80B and the selection unit 43 of the network side interface (transmission) 40. There is a point that the interface can use any extended memory. Appropriate expansion memories 80A and 80B can be used depending on the situation.

  For example, by installing a plurality of expansion memories 80A and 80B having different memory capacities (that is, different maximum delay adjustment times) and switching the switch unit 90, the most suitable expansion memory is selected according to the path length difference. Then, the delay control information output from the selection unit 43 can be input. When the extended memory is no longer used, the switch unit 90 disconnects the connection with the network side interface (transmission) 40 so that another interface can use the extended memory.

  Although not shown in the figure, the client side interface (transmission) 50 shown in FIG. 13 can also be connected to the expansion memories 80A and 80B, and the selection unit 53 may be connected to the switch unit 90.

[Sixth Embodiment]
In the present embodiment, an example in which an extended memory for performing delay adjustment is provided in the front stage of the cross-connect unit 10 and a switch unit is further provided.

  FIG. 20 shows a configuration of a digital cross-connect device according to the sixth embodiment of the present invention. In the figure, the same components as those of the first embodiment shown in FIG.

The digital cross-connect device shown in FIG. 20 is similar to the configuration of FIG. 16 in the fourth embodiment, but the difference is between the expansion memories 80A and 80B and the branch unit 23 of the network side interface (reception) 20. There are switch unit 90 having the same function as the fifth embodiment, the network-side interface (receiver) 20 ₁ is that it can use any extended memory.

The delay adjusting unit 26 of the network side interface (receiver) 20 _2, adjusting the delay of the ODU signals from the branch portion 23 in accordance with the delay control information inputted from the selection unit 43 of the network side interface (transmission) 40. If it can not compensate for the delay difference even in the delay adjusting unit 26 of the network side interface (receiver) 20 _1, extended memory 80A which is connected by the switch unit 90, using 80B. Thereby, expansion memory 80A, 80B performs delay adjustment ODU signals output from the network side interface (receiver) 20 ₁ branches 23.

  20 shows an example in which the network side interface (transmission) 40 is connected to the cross-connect unit 10, but a client side interface (transmission) 50 may be connected.

[Seventh Embodiment]
In the present embodiment, an example is shown in which a delay adjustment unit is provided in the subsequent stage of the cross-connect unit 10 and an expansion memory that performs delay adjustment is connected to the cross-connect unit 10.

  FIG. 21 shows the configuration of the digital cross-connect device in the seventh embodiment of the present invention. In the figure, the same components as those of the first embodiment shown in FIG.

  In the fifth and sixth embodiments, the switch 90 is newly provided to give flexibility to the connection relationship between the expansion memory and the interface. However, in the present embodiment, the cross-connect unit 10 is connected to the expansion memory 80A, It is used for switching the connection relationship between 80B and the interface. The setting of the cross-connect unit 10 is changed, and the expansion memories 80A and 80B can be used by conducting signals to the expansion memory as necessary.

  21 illustrates an example in which the network side interface (transmission) 40 is connected to the cross-connect unit 10 and the expansion memory 80, but a client side interface (transmission) 50 may be connected.

FIG. 22 shows a state in which an uninterrupted switching path is operated when this configuration example is used. The client side IF (RX) 30 of the left base A is the start point of the uninterruptible switching path, and the client IF (TX) 50 of the right base B is the end point of the uninterruptible switching path. At the site A on the left side, the client signal from the client device is accommodated in the ODU signal by the client side IF (RX) 30 and then branched into two and input to the XC unit 10. The XC unit 10 at the left site A inputs _two signals to different NW-side IF (TX) 40 ₁ and 40 ₂ according to the network settings. Signals from the NW side _{IF (TX) 40 1, 40} 2 is transmitted is transmitted through the path a and path b to the right of the base B. Here, it is assumed that the route a is shorter than the route b.

Two signals at the base B on the right side are respectively received by the NW side IF (RX) 20 ₁ and 20 ₂ , and then input to the XC unit 10 and input to one client side IF (TX) 50. Here, in the client-side IF (TX) 50, the selection unit 53 in the client-side IF (TX) 50 confirms the identity of the two signals and detects a delay difference. At this time, if the delay adjustment amount of the delay adjustment unit 52 in the client side IF (TX) 50 where the selection unit is present can compensate for the delay difference between the path a and the path b, the selection unit 53 performs the client side IF (TX ) When the delay adjusting unit 52 in 50 is used and it is recognized that there is not an amount that can compensate for the delay difference between the path a and the path b, delay control information is output to the extended memory 80 (the dotted line in the figure indicates the extended memory The case where it is used is illustrated.)

  Hereinafter, a case where the extended memory 80 is used will be described.

  The XC unit 10 also inputs the same signal to the expansion memory 80, and the expansion delay adjustment unit 82 in the expansion memory 80 adjusts the delay based on the delay adjustment information from the selection unit 53, so that the path a and the path b are adjusted. Set the delay difference to zero. In the selection unit 53 in the client-side IF (TX) 50, there is no difference in delay between the two signals, so that failure switching and plan switching can be performed without interruption.

  FIG. 22 shows a state in which the uninterruptible switching path is operating at the end and end of the ODU path, but FIG. 23 duplicates a section in the middle of the ODU path to enable uninterrupted switching. Show the state. The NW-side IF (RX) 20 of the left base A is the start point of duplexing, and the NW-side IF (TX) 40 of the right base B is the end point of duplexing. The extended memory 80 is used in the XC unit 10 on the route a side of the right base B. Based on the delay control information from the NW-side IF (TX) 40, the delay adjusting unit 42 in the NW-side IF (TX) 40 and the extended delay adjusting unit 82 in the extended memory 80 respectively control the delays of the two paths. To enable uninterrupted switching of the section.

[Eighth Embodiment]
In the present embodiment, an example in which a delay adjustment unit is provided in front of the cross-connect unit 10 and an extended memory that performs delay adjustment is connected to the cross-connect unit 10 is shown.

  FIG. 24 shows the configuration of the digital cross-connect device in the eighth embodiment of the present invention. In the figure, the same components as those of the first embodiment shown in FIG.

  The configuration of the digital cross-connect device shown in FIG. 24 is similar to that of FIG. 21 of the seventh embodiment, but the difference is that the delay adjustment unit 26 is included in the network side interface (reception) 20. The delay adjustment unit 26 adjusts the delay based on the delay control information output from the selection unit 43 of the network side interface (transmission) 40 and outputs the adjusted delay to the branch unit 23. Other operations are the same as those in the seventh embodiment.

  24 shows an example in which the network side interface (transmission) 40 is connected to the cross-connect unit 10, but the client side interface (transmission) 50 shown in FIG. 16 may be connected.

[Ninth Embodiment]
A specific operation flow of the digital cross-connect device shown in the seventh embodiment will be described with reference to FIGS.

  The process for relocating the ODU path without interruption is described below.

  As shown in Step 1 of FIG. 25, an example is shown in which an ODU path in operation between two bases (the left and right dotted frames indicate the respective bases) is transferred to another route without interruption.

In step 1, the client signal from the client device at the left base A is accommodated in the ODU signal by the client-side IF (RX) 30 and then only one of the two signals branched by the XC unit 10 is used as the first NW. are connected to the side IF (TX) 40 _1. Signal from the NW side IF (TX) 40 ₁ is transmitted to the right of the base B through a path a. After receiving a transmission signal in the NW side IF (RX) 20 ₁ in the right side of the site B, is input to the Client-side IF (TX) 50 via the XC 10. In the figure, the signal flow is indicated by dotted lines.

In step 2, in order to relocate this ODU path to route b, the setting of the cross-connect unit 10 on the left side A is changed, and the two output signals of the client-side IF (RX) 30 are not connected by the cross-connect. the signal so as to connect the second NW side IF (TX) 40 _2. Second NW side IF (TX) signal from 40 ₂ is transmitted through the path b is transmitted to the right of the base B. After the transmission signal is received by the second NW side IF (RX) 20 ₂ in the right side of the base B, and the first same signal path a of the Client-side IF (TX) 50 via the XC 10 It is input (thick dotted line in the figure). As a result, the client IF (TX) 50 receives signals transmitted through the two paths a and b. The client-side IF (TX) 50 confirms the identity of the two signals and detects the delay difference between them. This example shows a case where it is determined that the path b is longer than the path a and that an extended memory is necessary on the path a side.

In step 3, the signal of the route a is switched without interruption in such a way as to pass through the extended memory 80 at the base B on the right side. A signal towards the first NW side IF (RX) 20 ₁ in the right location B does not use one of the two signals that are output to the XC unit 10 via the XC unit 10 is connected to the expansion memory 80 (Dotted line h). The output of the expansion memory 80 is again connected to the XC unit 10, and the XC unit 10 inputs a signal to the client side IF (TX) 50. This Client-side IF (TX) 50 would have received a signal from the NW side IF 20 _1, signal via the extended memory 80, the three signals of the signals from the NW side IF 20 _2. The client-side IF (TX) 50 confirms the identity of the two signals from the _first NW-side IF (RX) 201, and then detects a delay time difference to generate delay control information. The delay control information is input to the delay adjusting unit 52 in the client IF (TX) 50 and the extended delay adjusting unit 82 in the extended memory 80 so that the delays of both are the same.

In Step 4, since the delay of the two signals from the _first NW-side IF (RX) 201 in Step 3 becomes the same, the signal on the dotted line e does not lose one bit in the Client-side IF (TX) 50. To the signal of the dotted line h.

  Next, in step 5, the delay of the two signals of the path a and the path b is adjusted. The selection unit in the client-side IF (TX) 50 of the right base B detects the delay difference by measuring the delay between the two signals from the route a and the route b after confirming the identity. In the present embodiment, since the path a is shorter than the path b, the delay time of the path a is increased by increasing the delay time of the extended delay adjustment unit 82 mounted in the extended memory 80, thereby reducing the delay difference between the two. To do. As a result, the delay difference between the signals of the dotted line h and the dotted line f is eliminated, so that switching without interruption is possible.

  This completes the path type change from an unduplicated ODU path (unprotected ODU) to a duplexed ODU path (hitless protected ODU) that can be switched without interruption.

  If the path is relocated without interruption, continue to the next step.

  Step 6 is shown in FIG. When the active system is switched to the signal of the route b in the state of step 5 without instantaneous interruption and the signal of the route a is abolished, the path uninterrupted transfer from the route a to the route b is completed.

  If the extended memory is used for the path in operation, the extended memory can be released by switching without interruption without reducing the delay.

[Tenth embodiment]
In the present embodiment, another example of a specific operation flow when the configuration of the seventh embodiment is used will be described.

  A flow of relocating an ODU path (hitless protected ODU) that can be switched without interruption will be described with reference to FIGS. 29 to 31.

  Consider a situation in which the left base A and the right base B are connected by three routes (routes a, b, and c) as shown in step 11 of FIG. At the site A on the left side, the client signal from the client device is accommodated in the ODU signal by the client IF (RX) 30 and then one of the two branched signals is transmitted on the route a, and the other is transmitted on the route b. Has been. At the base B on the right side, the received signal is input to the client IF (TX) 50 via the XC unit 10. In FIG. 29, the signal flow is shown by dotted lines h and f. Both are operated in a state in which the delay is adjusted and switching without interruption is possible. Assume that path a is the active system. In this state, it is assumed that the ODU path that can be switched without interruption between the route a and the route b is moved to the ODU path that can be switched without interruption through the route b and the route c.

  As shown in step 12 of FIG. 30, first, the active system is switched from the path a to the path b without interruption, and the path b is changed to the active system (dotted line f). After that, the setting of the XC unit 10 at the left and right bases A and B is changed, and the same signal is conducted to the path c (dotted line e). The client-side IF (TX) 50 at the right base B receives two signals (dotted line f and dotted line e), and the selection unit 53 in the client-side IF (TX) 50 receives the sameness and delay difference between the two signals. Is detected. It is detected that the path c is shorter than the path b, and it is determined that an extended memory is necessary (in this embodiment). The XC unit 10 is set so that the unused signal of the two signals to the XC unit 10 of the NW-side IF (RX) 20 at the right base B is connected to the expansion memory 80 (dotted line h). Then, within the right base B, the delay time difference between the dotted line e and the dotted line h is adjusted to make the delay difference zero, so that switching without interruption can be performed.

  As shown in step 13 of FIG. 31, the path is switched to the dotted line h without interruption. Next, the client-side IF (TX) 50 detects the delay time difference between the signal on the route b (dotted line f) and the signal on the route c (dotted line h), and by setting the delay difference between the two to 0, the route between the route b and the route c. Make the signal ready for uninterrupted switching.

  This completes the relocation of paths that can be switched without interruption. Further, both systems can be relocated by relocating the route b to another route such as a route d (not shown).

[Eleventh embodiment]
By relocating the path shown in the above embodiment, traffic can be rearranged. As shown in FIG. 32, signals can be transferred to different wavelengths on the same path or wavelengths on different paths without interruption, so that the usage and occupation of the wavelength can be freely changed without interrupting the service. Is possible.
[Twelfth embodiment]
33 and 34 show examples in which the number of connections between the cross-connect unit and each interface unit is changed from the previous embodiments. FIG. 33 corresponds to triple. FIG. 34 shows a configuration that can be connected to the triple memory and can be connected to an extended memory.

  In the above embodiment, the signal handled is OTN, but the present invention can be applied to other cases.

[Thirteenth embodiment]
An uninterruptible switching device according to a thirteenth embodiment of the present invention will be described with reference to FIGS. In the present embodiment, an uninterrupted system is configured between the active transmission system using the first transmission line and the standby transmission system using the second transmission line. In this system, before the start of the uninterruptible switching service, only the active system is operated, and it is not necessary to prepare the second transmission line in advance. Secure the road. According to this system, the delay difference between both systems can be adjusted without interrupting service.

  FIG. 35 shows the configuration of the uninterruptible switching device according to the thirteenth embodiment of the present invention. As shown in FIG. 35, the uninterruptible switching device 100 receives the signal from the first transmission line as the active system and simultaneously generates an IF circuit 102a that generates a clock signal, and a frame that performs frame processing on the received signal. It has a termination circuit 104a, a FIFO memory 106a for storing a signal after frame processing for phase adjustment, and a clock control circuit 108a, and receives a signal from the second transmission line as a standby system and simultaneously generates a clock signal. An IF circuit 102b that performs frame processing on the received signal, a FIFO memory 106b that stores the signal after termination processing for phase adjustment, and a clock control circuit 108b. The uninterruptible switching device 100 further measures the delay difference between the two systems by receiving and comparing the frame phase information detected by the frame termination circuits 104a and 104b, and uses the delay control amount calculated from the measurement result as the delay control information. As a phase difference detection circuit 110 that is transmitted to the clock control circuit, a switching circuit 112 that selects either one of the two signals after phase control and sends them to the client (downstream) side, and an error detection result or an operator And a switching control circuit 114 that issues a switching instruction to the switching circuit 112 based on the switching instruction.

  The signals transmitted through the first and second transmission paths are received by the IF circuits 102a and 102b, respectively, and then subjected to frame detection by the frame termination circuits 104a and 104b. The frame phase difference of the received signal reflects the delay difference of each transmission path, and the phase difference detection circuit 110 compares the detected frame phase to measure the delay difference between the two transmission paths. Determine how much to delay the phase. Specifically, the phase difference detection circuit 110 receives the frame phase of the signal transmitted through the first transmission path detected by the frame termination circuit 104a and the second transmission path detected by the frame termination circuit 104b. The frame phases of the transmitted signals are compared to determine which frame phase is delayed, and the delay difference between the two transmission paths. Based on the determination result, the phase difference detection circuit 110 typically has a relatively small delay with respect to the clock control circuits 108a and 108b of the system that controls the delay. Is given delay control information indicating a control amount corresponding to the delay difference. The clock control circuits 108a and 108b receive the clock signal generated from the reception signal by the IF circuits 102a and 102b, and generate write and read clocks for the FIFO memories 106a and 106b based on the clock signal. The signal data is written to the FIFO memories 106a and 106b with a write clock, and is read from the FIFO memories 106a and 106b with a read clock.

  When the phase difference detection circuit 110 determines that the system that adjusts (delays) a delay with a relatively small delay is the standby system, the data transmitted through the standby system is not sent to the client side, There is no need to consider disruption of communication. Data is written to the FIFO memory 106b using the transmission path clock, and the read clock is stopped until the data is accumulated in the FIFO memory 106b until the amount corresponding to the delay adjustment amount. By starting the read clock after accumulating a predetermined amount of data, adjustment for delaying the data phase can be performed.

  On the other hand, when the phase difference detection circuit 110 determines that the system that adjusts the delay with a relatively small delay is the active system, the data being communicated through the active system is sent to the client, Data disruption, code error, etc. are not permitted and do not affect the client, i.e., the phase of the active system within the range of frequency deviation that can maintain the communication provided to the client at or above the predetermined communication quality. It needs to be adjusted. More specifically, in this case, in the standby system that does not adjust the delay, a clock synchronized with the transmission path clock is used as the write and read clock. In the active system that adjusts the delay, the write clock is synchronized with the transmission line clock, but the read clock is continuously lowered in the range where the deviation from the write clock frequency does not affect the client. Later, by conversely increasing the frequency continuously, the frequency is returned to the frequency synchronized with the write clock.

  In the configuration of the present embodiment, as shown in the modification of FIG. 36, the connection order of the FIFO memories 106a and 106b and the frame termination circuits 104a and 104b may be switched. In this case, the same effect can be obtained.

  As shown in FIG. 9 described above, the delay adjustment unit that realizes the above-described delay adjustment includes the IF circuit 1, the FIFO memory 2, and the clock adjustment unit 3. The IF circuit 1 and the FIFO memory 2 in FIG. 9 may be the IF circuits 102a and 102b and the FIFO memories 106a and 106b. 9 may be included in the clock control circuits 108a and 108b described above, or may be provided independently of the clock control circuits 108a and 108b. When receiving the signal, the IF circuit 1 generates a clock signal and provides it to the clock adjustment unit 3. Based on the received clock signal and clock control signal, the clock adjustment unit 3 writes a data signal write clock frequency provided from the IF circuit 1 to the FIFO memory 2 and a data signal read clock frequency provided from the FIFO memory 2. And control.

  When receiving the clock control signal indicating that the delay time is adjusted, the clock adjustment unit 3 is configured to write the data signal to the FIFO memory 2 based on the clock received from the IF circuit 1 and / or from the FIFO memory 2. Adjust the read clock frequency of the data signal. For example, the clock adjustment unit 2 adjusts the write clock frequency and / or the read clock frequency by +/− X (ppm) with respect to the clock received from the IF circuit 1 (for example, +/− 1 ppm, etc.). As shown in FIG. 9B, when the delay is increased, the clock adjustment unit 3 sets the read clock frequency from the FIFO memory 2 to −1 ppm from the write clock frequency for a period corresponding to the delay time to be adjusted. The delay time can be increased by ΔD seconds. On the other hand, when reducing the delay (FIG. 9C), the clock adjustment unit 3 increases the read clock frequency from the FIFO memory 2 by +1 ppm from the write clock frequency for a period corresponding to the delay time to be adjusted. , The delay time can be reduced by ΔD. Note that the adjustment of the read clock frequency needs to be performed within a range in which a predetermined communication quality can be maintained, for example, the data signal provided to the client is not interrupted.

  As described above, by making the read clock frequency lower than the write clock frequency, the data stored in the FIFO memory 2 increases, and the data read is delayed by the frequency deviation, so that the data delay increases. The deviation must be controlled to return to the original frequency as soon as the phases of both systems are aligned. By the processing described above, the delay difference between the two systems can be made uniform by controlling the read clock frequency of the FIFO memory 2 to be slower than the write clock.

  After the phases of both systems are aligned, the switching control circuit 114 switches the switching circuit 112 from the active system to the standby system, thereby enabling switching without instantaneous interruption. The trigger for switching is assumed to be planned due to the occurrence of a code error in the current system or the transfer of trouble. Here, the signal to be transmitted assumes a frame format capable of wide-area transfer such as SDH (Synchronous Digital Hierarchy) and OTN (Optical Transport Network), and the signal sent to the client side is, for example, an Ethernet (registered trademark) signal, An SDH signal, an OTN signal, etc. are assumed. The frequency deviation with which the operation is guaranteed in the transmission apparatus varies depending on the frame format, SDH is ± 4.6 ppm, OTN is ± 20 ppm, and Ethernet (registered trademark) is ± 100 ppm. Thus, the allowable frequency deviation value varies depending on the type of device connected to the client side. In this embodiment, the frame is used as a unit for comparing the delay difference between the two systems. However, if the delay difference between the signals of both systems exceeds 1/2 of the frame length, the delay of either system is large. It becomes difficult to identify. For this reason, a plurality of frames may be concatenated and used as if they were a single long frame. Especially when a large transmission delay difference of several tens of kilometers or more is assumed, the use of the multiframe is effective. is there.

[Fourteenth embodiment]
Next, an uninterruptible switching device according to a fourteenth embodiment of the present invention will be described with reference to FIG. In the fourteenth embodiment, an upgrade from only one system to both systems that support uninterrupted switching is performed. That is, in the initial operation state, only one system operation is performed and uninterruptible switching is not supported.

FIG. 37 is a diagram showing the configuration of the uninterruptible switching device according to the fourteenth embodiment of the present invention. As shown in FIG. 37, the one-system operation package 200a includes an IF circuit 202a, two branch circuits 203a ₁ and 203a ₂ , a frame termination circuit 204a, a FIFO memory 206a, a clock control circuit 208a, and a switching circuit. 212 and a switching control circuit 214.

Data received by the IF circuit 202a is branched into two by the branching circuit 203a _1, one is connected to the IF connection port to upgrade package 200a ', the other is sent to the frame termination circuit 204a. Also the IF circuit 202a, a clock signal synchronized from received data is generated, after being branched by the branch circuit 203a _2, one for the clock control circuit 208a, is connected the other to an IF connection port to upgrade package 200a ' The

  The frame termination circuit 204a performs frame termination processing such as error detection / correction, alarm processing, and delay detection from the frame phase. The detected frame phase is connected to the IF connection port to the upgrade package 200a ′, and error detection information and other alarms are sent to the switching control circuit 214. The post-termination data is given a fixed delay in the FIFO memory 206a, and then sent to the client side via the switching circuit 212.

  An upgrade package 200a ′ is first added in order to make the active system compatible with uninterrupted switching from this initial state. The upgrade package 200a ′ includes a frame termination circuit 204a ′, a phase difference detection circuit 210a, a FIFO memory 206a ′, and a clock control circuit 208a ′. Typically, the FIFO memory 206a ′ has a relatively larger capacity than the FIFO memory 206a of the one-system operation package 200a.

Upgrade package 200a 'includes a data signal output from the IF connection port of the branch circuit 203a ₁ of one system operational package 200a, takes in a clock signal output from the branching circuit 203a _2, the data signal frame terminating circuit 204a' The termination process is performed by. The phase difference detection circuit 210a measures the delay difference between the frame phase detected by the frame termination circuit 204a ′ of the upgrade package 200a ′ and the frame phase detected by the frame termination circuit 204a of the one-system operation package 200a. Based on the measured delay difference, the data delay amount of the one-system operation package 200a is adjusted.

  Specifically, with respect to the write and read clocks of the FIFO memory 206a ′, the write clock is written at a frequency synchronized with the transmission path clock, but the read clock is provided within a frequency deviation range that does not affect the client, that is, provided to the client. After continuously reducing the frequency within the range of frequency deviation that can maintain the communication to be higher than the predetermined communication quality, the frequency is continuously increased so that the delay difference between the two signals becomes substantially equal, Return to the original frequency. This delay adjustment can be executed using the delay adjustment unit described with reference to FIG.

  When the delay amount of both signals becomes the same, the switching circuit 212 switches from the signal path of only the one-system operation package 200a to the signal path that returns to the one-system operation package 200a again via the upgrade package 200a '. It is done. By this signal path switching, the FIFO memory 206a ′ having a larger capacity can be used in the working system.

  Next, a standby package 200b that receives a signal transmitted through the second path is added. The standby system package 200b includes an IF circuit 202b, a frame termination circuit 204b, a FIFO memory 206b, a clock control circuit 208b, and a phase difference detection circuit 210b.

  The frame termination circuit 204b of the standby package 200b detects the frame phase at the same time as performing the frame termination of the signal of the backup path received from the IF circuit 202b. In the phase difference detection circuit 210b in the standby system package 200b, the delay difference between the frame phase detected in the frame termination circuit 204b and the frame phase detected in the frame termination circuit 204a ′ in the upgrade package 200a ′ is measured. . Based on the measured delay difference, the delay amount of the standby package 200b or the upgrade package 200a ′ is adjusted.

  When delaying the standby side, the data transmitted through the backup side is not sent to the client side, so there is no need to consider phase jumps and communication interruptions. For this reason, data is written to the FIFO memory 206b of the standby package 200b with a clock synchronized with the transmission signal generated by the IF circuit 202b, and the read clock is stored until the data is accumulated in the FIFO memory 206b until the delay adjustment amount is reached. Stop it. After data storage, data phase adjustment can be performed by starting reading using a clock synchronized with the transmission signal.

  On the other hand, when the active system side is delayed, in the clock control circuit 208a ′ for controlling the write clock and read clock of the FIFO memory 206a ′ in the upgrade package 200a ′, the write clock is a clock synchronized with the transmission signal generated by the IF circuit 202a. The read clock continuously reduces the frequency within the range of frequency deviation that does not affect the client, that is, within the range of frequency deviation that can maintain the communication provided to the client above the predetermined communication quality. After that, the frequency is continuously increased so that the delay difference between the two signals becomes substantially equal, and the original frequency is restored. This delay adjustment can be executed using the delay adjustment unit described with reference to FIG.

  Thereby, the delay amount of both signals can be made the same, and the preparation for the uninterruptible switching between the active system and the standby system is completed. By the above operation, it is possible to upgrade to an apparatus capable of switching without interruption by newly adding a package to a one-system operation system that was not initially switched without interruption. After that, switching without interruption is executed by detecting a code error or an alarm in the active system, or by switching the selection of the switching circuit 212 from the switching control circuit 214 using an instruction from the operator as a trigger. The phase adjustment amount when switching the signal path by adding the upgrade package 200a ′ to the one-system operation package 200a is about several meters at most because it is about the delay between packages in the apparatus. Therefore, the FIFO memory 206a mounted in the one-system operation package 200a may have a small capacity capable of storing about 130 bits per meter when the transmission rate is 40 Gbits, for example. On the other hand, the FIFO memories 206a 'and 206b mounted on the upgrade package 200a' and the standby system package 200b are for absorbing the delay difference of the transmission path. For example, assuming that the transmission speed is 40 Gbit and 80 km, it is equivalent to 10,560,000 bits. Therefore, a relatively large capacity is required. When switching without interruption is not necessary, use the single-system operation package 200a of such a small-capacity FIFO memory 206a, and add an upgrade package 200a 'with a large installed memory capacity when no interruption is required. do it. Thereby, an upgrade from single system operation to uninterrupted operation can be easily performed from an inexpensive configuration, and an uninterruptible switching device that is excellent in economy can be provided.

[Fifteenth embodiment]
Next, an uninterruptible switching device according to a fifteenth embodiment of the present invention will be described with reference to FIGS. As in the fourteenth embodiment, the fifteenth embodiment can be upgraded from the operation of only one system to both systems that support uninterrupted switching. It enables the reuse of packages used in the active system when system operation is used.

  38 to 42 show the configuration and processing of the uninterruptible switching device according to the fifteenth embodiment of the present invention. As shown in FIG. 38, the difference from the fourteenth embodiment is that the switching circuit 312 and the switching control circuit 314 in the one-system operation package 300a ′ are configured as independent switching packages 320, The switch 316 is added between the one-system operation package 300a, the upgrade package 300a ′, the standby system package 300b, and the switching package 320. In the following description, description of components having the same functions as those of the fourteenth embodiment will be omitted as appropriate.

  As shown in FIG. 39, the original system does not constitute a redundant system and does not support uninterrupted operation. That is, the system includes a one-system operation package 300a, a switch 316, and a switching package 320 during initial operation. The switch 316 is detachably connected to the one-system operation package 300a, the upgrade package 300a ′, and the standby package 300b, receives signals output from these packages, and outputs them to the switching package 320. By providing the switch 316 between each package and the switching package 320, the switching circuit can be configured independently. The FIFO memory 306a may have a relatively small capacity relative to the FIFO memory 306a ′ and the FIFO memory 306b, but can store data until frame termination processing (error detection, etc.) is completed. Capacity is needed. For example, the FIFO memory 306a may have a fixed delay. In the figure, the semi-transparent package indicates that the package is not mounted, and the semi-transparent signal line indicates that the signal is not conducted. If some of the blocks in the package are translucent, this means that the blocks have stopped operating.

  When upgrading to an uninterruptible system, as shown in FIG. 40, an upgrade package 300a ′ is first added. As shown in FIG. 41 from the signal path of the one-system operation package 300a → the switch 316 → the switching package 320 by the delay adjustment procedure using the FIFO memory 306a ′ and the clock frequency control similar to the fourteenth embodiment. The signal path is changed to one-system operation package 300a → upgrade package 300a ′ → switch 316 → switching package 320. By changing the path, it becomes possible to use the large-capacity FIFO memory 306a ′ mounted in the upgrade package 300a ′.

  Next, as shown in FIG. 42, the standby system package 300b is added, and the phase difference caused by the transmission line delay difference between the active system and the standby system is calculated using the phase difference detection circuit 310b in the standby system package 300b. To detect. When delaying the standby system to align the phases, the delay is adjusted by stopping the read clock of the FIFO memory 306b of the standby system package 300b for a certain period of time. On the other hand, when delaying the active system, the read clock frequency of the FIFO memory 306a ′ of the upgrade package 300a ′ is within a frequency deviation range that does not affect the client, that is, the communication provided to the client is maintained at a predetermined communication quality or higher. Adjust the delay by continuously decreasing the frequency within the range of possible frequency deviations, then increasing the frequency continuously so that the delay difference between the two signals is substantially equal, and then returning to the original frequency. To do.

  Through the above operation, it is possible to upgrade to a device capable of switching without interruption by newly adding a package to a system of one-system operation that was not originally switched without interruption. After that, switching between the switching control circuit 314 and the selection of the switching circuit 312 is performed by detecting a code error or an alarm in the active system, or by using an instruction from the operator as a trigger, thereby executing uninterruptible switching.

  In the present embodiment, when the system switching function is made independent as the switching package 320, for example, when it is desired to leave the second transmission line side when returning to the one-system operation from the uninterruptible system again, After switching to the system package 300b without interruption, the one-system operation package 300a and the upgrade package 300a ′ can be removed from the switch 316. The extracted package can be reused in another system, and the system can be operated economically. The switch 316 used in this system may be either an optical switch or an electrical switch as long as the interfaces between the packages are matched.

  In the illustrated embodiment, the switch 316 and the switching package 320 are provided as independent components, but the switch 316 and the switching package 320 may be integrated.

[Sixteenth embodiment]
Next, an uninterruptible switching device according to a sixteenth embodiment of the present invention will be described with reference to FIG. In the present embodiment, a system that has been operating without interruption is downgraded to single-system operation without interrupting communication. It is assumed that the system that has been temporarily switched to the standby system due to trouble relocation, etc. is switched back to the active system, or that the service without interruption is canceled by replacing the service that emphasizes reliability with the importance of economy. .

  When the current transmission line is the second transmission line, the first transmission line is first switched by uninterruptible switching. Hereinafter, the current operation is the same as in the case of the first transmission line. At this point, the standby system package 400b can be removed from the switch 416. Next, in order to operate only the one-system operation package 400a that does not support uninterruptible power, the in-device uninterruptible switching is executed, and the signal that has passed through the upgrade package 400a ′ is transmitted only through the one-system operation package 400a. Switch to However, since the upgrade package 400a ′ includes a large FIFO memory 406a ′ that absorbs the delay difference in the transmission path length, it is difficult to absorb the upgrade package 400a ′ using the small FIFO memory 406a of the initial package 400a.

  First, the write clock for the FIFO memory 406a ′ of the upgrade package 400a ′ is a clock synchronized with the transmission path. The read clock is continuously within a range in which predetermined communication quality can be maintained on the downstream side, for example, within a range in which the read clock frequency does not exceed the frequency deviation guaranteed for operation in the transmission apparatus so that no code error occurs. After increasing the frequency and reducing the amount of data stored in the FIFO memory 406a ′ to the amount of data that can be accommodated by the FIFO memory 406a, the frequency is continuously decreased so that the delay difference between the two signals becomes substantially equal. Then adjust the delay by returning to the original frequency. By switching the switching circuit 412 to select an input from the one-system operation package 400a in a state where the delays are aligned, it is possible to switch the signal path without causing a signal interruption. After the switching is completed, the upgrade package 400a ′ can be removed from the switch 416, and only the one-system operation package 400a can be left. The removed package can be reused, and an economical system can be constructed.

[Seventeenth embodiment]
Next, an uninterruptible switching device according to a seventeenth embodiment of the present invention will be described with reference to FIGS. In the present embodiment, in a system that is operating without interruption, a new path is added and the path is moved while continuing the uninterrupted service. As shown in FIG. 44, the system is initially operated with the first transmission path being the active system and the second transmission path being the standby system. From this state, as shown in FIG. 45, the third route is added, and then the active system is transferred from the first route to the third route, as shown in FIGS.

  First, as shown in FIG. 45, with respect to the initial system composed of the one-system operation package 500a, the upgrade package 500a ′, and the standby package 500b shown in FIG. The one-system operation package 500c is added.

  The phase difference detection circuit 510c of the second standby system package 500c measures the delay difference between the first transmission path and the third transmission path that are the active systems.

  When the delay of the third transmission path is larger than the delay of the first transmission path and it is necessary to increase the delay of the first transmission path, the following control is performed. That is, the read clock frequency of the FIFO memory of the first transmission line system is set within a range in which a predetermined communication quality can be maintained on the downstream side, for example, a frequency deviation that is guaranteed to operate in the transmission apparatus so that no code error occurs. After continuously lowering the frequency within a range not exceeding, the frequency is continuously increased so that the delay difference between the signal on the first transmission line and the signal on the third transmission line is substantially equal to the original frequency. To adjust the delay while continuing service. On the other hand, when the delay of the third transmission is smaller than the delay of the first transmission path, the delay of the third transmission path is increased. The read clock of the FIFO memory 506c of the third transmission path is stopped for a certain time, and data is accumulated in the FIFO memory 506c. When the delay of the first transmission line is met, the phase is adjusted by starting the read clock.

  When the delays of the first transmission path and the third transmission path are equal, as shown in FIG. 46, switching without interruption is performed from the first transmission path to the third transmission path. After the execution, the delay difference is measured between the third transmission line and the second transmission line, and the delay is adjusted by controlling the read clock of the FIFO memory by the same means. As shown in FIG. A new uninterrupted system is constructed between the two transmission lines and the third transmission line.

  Thereafter, as shown in FIG. 48, the one-system operation package 500a and the upgrade package 500a ′ may be removed from the switch 516 as necessary.

[Eighteenth embodiment]
Next, an uninterruptible switching device according to an eighteenth embodiment of the present invention will be described with reference to FIGS. The present embodiment is different from the seventeenth embodiment in that the third transmission path system package configuration includes a second single-system operation package 600c and a second upgrade package 600c ′.

  First, as shown in FIG. 49, an uninterruptible switching system is initially configured by the first transmission path (active system) and the second transmission path (standby system).

  Next, as shown in FIG. 50, a second single-system operation package 600c is added to the third transmission line system. The delay difference between the first transmission line and the third transmission line is measured by the phase difference detection circuit 610c of the second single-system operation package 600c.

  If it is determined that the memory capacity of the FIFO memory 606c mounted in the second one-system operation package 600c is sufficient for delay adjustment, the phase adjustment is performed as it is. When the delay of the first transmission path (active system) is increased, for example, a code error does not occur within a range in which the read clock of the FIFO memory 606a ′ of the upgrade package 600a ′ can maintain a predetermined communication quality on the downstream side. After continuously reducing the frequency within a range that does not exceed the frequency deviation guaranteed for the operation of the transmission device, the frequency is continuously increased so that the delay difference between the two signals becomes substantially equal. The delay is adjusted by returning to the frequency. On the other hand, when the delay of the third transmission path is increased, the read clock of the FIFO memory 606c of the second one-side operation package 600c is stopped for a certain time and data is accumulated in the memory, and the phases of both systems are aligned. Starts the read clock. When the delays of the first transmission line and the third transmission line are equal, as shown in FIG. 51, the instantaneous transmission switching is executed, and the third transmission line becomes a new working system. Thereafter, if necessary, as shown in FIG. 52, the one-system operation package 600a of the first transmission path is removed from the switch 614, and a new uninterrupted connection between the third transmission path and the second transmission path is performed. Configure the system.

  On the other hand, if it is determined that the memory capacity of the FIFO memory 606c mounted in the second one-system operation package 600c is insufficient for delay adjustment, a second upgrade package 600c ′ is further added as shown in FIG. By this addition, the signal of the system of the third transmission path is switched to be input to the switch 614 from the second single system operation package 600c via the second upgrade package 600c ′. After the switching, the phase adjustment between the first transmission path and the third transmission path is performed, and as shown in FIG. 54, uninterrupted switching is executed. After execution, if necessary, as shown in FIG. 55, the old working system package is removed from the switch 616, and a new uninterruptible switching system is constructed between the third transmission line and the second transmission line. To do.

[Nineteenth embodiment]
Next, an uninterruptible switching device according to a nineteenth embodiment of the present invention will be described with reference to FIGS. FIG. 56 shows the structure of the uninterruptible switching device according to the nineteenth embodiment of the present invention. As shown in FIG. 56, the uninterruptible switching device 700 receives a signal from the first transmission path as an active system, and simultaneously generates a clock signal on the line-side IF (Interface) circuit 702a, and receives the received signal. The first termination circuit 704a that performs frame processing, the first memory 706a and the second memory 706b that store the post-frame processing signal for phase adjustment, and the data storage amount of the first memory 706a and the second memory 706b are adjusted. A first clock control circuit 708a and a second clock control circuit 708b for receiving the signal from the second transmission line as a standby system and generating a clock signal at the same time, A second termination circuit 704b that performs frame processing on the signal, and a third memory 706c that stores the signal after termination processing to perform phase adjustment. And a third clock control circuit 708c for adjusting the amount of data accumulated in the third memory 706c. The uninterruptible switching device 700 further measures the delay difference between the two systems by receiving and comparing the frame phase information detected by the first termination circuit 704a and the second termination circuit 704b, and delay control calculated from the measurement result The phase difference detection circuit 710 that transmits the amount as delay control information to the first clock control circuit 708a, the second clock control circuit 708b, and the third clock control circuit 708c, and either the active or standby clock signal is selected. A first clock control circuit 708a, a switching circuit 712, a second clock control circuit 708b, a second memory 706b (read clock thereof), a client side IF circuit 702c, and a clock switching circuit 716 that outputs to the third clock control circuit 708c; Select one of the signals from both systems after phase control and send it to the client (downstream) side Having a switching circuit 712, a switching control circuit 714 for switching instruction to the switching circuit 712 and the clock switching circuit 716 based on the switching instruction from the error detection result and an operator to.

  The signals transmitted through the first and second transmission paths are received by the line-side IF circuits 702a and 702b, respectively, and then subjected to frame detection by the first termination circuit 704a and the second termination circuit 704b. The frame phase difference of the received signal reflects the delay difference of each transmission path, and the phase difference detection circuit 710 measures the delay difference between the two transmission paths by comparing the detected frame phases. Determine how much to delay the phase. Specifically, the phase difference detection circuit 710 includes the frame phase of the signal transmitted through the first transmission path detected by the first termination circuit 704a and the second transmission path detected by the second termination circuit 704b. Is compared with the frame phase of the signal transmitted through the network to determine which frame phase is delayed. Based on the determined result, the phase difference detection circuit 710 provides delay control information to the clock control circuit 708a or 708b of the system that controls the delay of the first clock control circuit 708a and the third clock control circuit 708c. . The clock control circuits 708a and 708b receive the clock signal generated from the reception signal by the line-side IF circuits 702a and 702b, and read the first memory 706a, the second memory 706b, and the third memory 706c based on the clock signal. Generate a clock. In each of the memories 706a, 706b, and 706c, signal data is written to the memory with a write clock and read from the memory with a read clock. When increasing the delay of the standby system, the data transmitted through the backup system is not sent to the client side, so there is no need to consider phase jumps and communication interruptions. Data is written to the third memory 706c with the transmission path clock, and the read clock is stopped until the data is accumulated in the third memory 706c until the amount corresponding to the delay adjustment amount. By starting the read clock after accumulating a predetermined amount of data, adjustment for delaying the phase of the standby data can be performed. On the other hand, when the delay of the standby system is reduced, data is written to the third memory 706c with the transmission path clock, and at the same time, the data is read from the third memory 706c with a clock whose frequency is higher than the transmission path clock frequency. Thus, the amount of data stored in the third memory 706c can be reduced, and adjustment can be performed to advance the phase of the standby data.

  On the other hand, when adjusting the delay of the active system, data that is being communicated via the active system is sent to the client, so phase jumps, data disruptions, code errors, etc. are not allowed, affecting the client. In such a state, it is necessary to adjust the phase of the working system. More specifically, when increasing the delay of the active signal, the first clock control circuit 708a and the second clock control circuit 708b are used to set the frequency of the read clock of the first memory 706a and the write clock of the second memory 706b. Lower than the transmission path clock. As a result, as shown in FIG. 57, the amount of data stored in the first memory 706a increases, and the amount of data stored in the second memory 706b decreases accordingly, so that the switching between the first memory 706a and the second memory 706b occurs. The input of the circuit 712 can be adjusted as if the delay of the working system has increased. On the other hand, when reducing the delay of the working signal, the first clock control circuit 708a and the second clock control circuit 708b are used to set the frequency of the read clock of the first memory 706a and the write clock of the second memory 706b. Since the data storage amount of the first memory 706a decreases and the data storage amount of the second memory 706b increases correspondingly by raising it from the transmission line clock, as shown in FIG. 58, the first memory 706a and the second memory 706b. In the input part of the switching circuit 712 between the two, the adjustment can be made as if the delay of the active system is reduced. In order to avoid the occurrence of memory slip, the output clock frequencies of the first clock control circuit 708a and the second clock control circuit 708b must always be controlled to be equal in any adjustment. This delay adjustment is an event that occurs between the first memory 706a and the second memory 706b, and gives an offset from the clock frequency in which the read clock of the first memory 706a and the write clock of the second memory 706b are synchronized with the transmission signal. Thus, the fact that the amount of data accumulated between the first memory 706a and the second memory 706b changes in a complementary manner is utilized. Since the sum of the data accumulation amounts of the first memory 706a and the second memory 706b is constant and the signal steadily arrives at the same clock frequency when viewed from the client side, the frequency deviation or delay is even during delay adjustment of the active system. You will not be informed of such fluctuations. With the delay control described above, the delay difference between the active system and the standby system can be adjusted, and a state in which uninterruptible switching can be executed can be achieved. At the time of switching, the signal selected in the switching circuit 712 is switched from the active system signal to the standby system signal by an instruction from the switching control circuit 714, and at the same time, the clock signal selected in the clock switching circuit 716 is switched from the active system clock to the standby system clock. . The clock switching circuit 716 selects the working clock before switching to the standby system, and uses the output of the clock switching circuit 716 as a read clock for the third memory 706c, thereby using the working system signal. Synchronize with the clock of the system signal. At the same time as the switching without interruption is performed and the switching circuit 712 switches to the standby system, the clock switching circuit 716 also switches to select the standby clock, and the read clock of the third memory 706c, the switching circuit 712, and the second memory Since the clock supplied to 706b is switched to a clock synchronized with the standby system signal, the signal output to the client side is a signal synchronized with the standby system clock. At this time, since the standby clock is also used as the read clock of the first memory 706a, the current system signal is synchronized with the clock of the standby system signal.

  Next, delay adjustment when switching from the standby system to the active system will be described. The active system delay adjustment is performed by controlling the read clock of the first memory 706a using the first clock control circuit 708a. In the standby delay adjustment, since the in-service signal is accumulated in the third memory 706c and the second memory 706b, the third memory 706c is used by using the third clock control circuit 708c and the second clock control circuit 708b. Is performed by controlling the read clock and the write clock of the second memory 706b. At this time, in order to avoid occurrence of memory slip, the output clock frequencies of the third clock control circuit 708c and the second clock control circuit 708b must always be controlled to be equal.

  Note that the write clock of the first memory 706a, the read clock of the second memory 706b, and the write clock of the third memory 706c are clocks synchronized with the frequency of the transmission signal in any case.

  In this embodiment, the delay of not only the standby system but also the working system can be adjusted in the service provision state, so that the standby system transmission line is secured after the operation with only one system initially. Delay control can be set flexibly when upgrading to an instantaneous interruption system. In addition, while providing services as an uninterruptible system, flexible delay control can be set when changing to a different route with a different length from the route that is currently set for the standby system. Can be improved.

  The signal transmitted in this apparatus assumes a frame format capable of wide-area transfer such as SDH and OTN, and the signal sent to the client side assumes, for example, an Ethernet (registered trademark) signal, an SDH signal, an OTN signal, etc. ing. In this embodiment, the frame is used as a unit for comparing the delay difference between the two systems. However, if the delay difference between the signals of both systems exceeds 1/2 of the frame length, the delay of either system is large. It becomes difficult to identify. Therefore, a multiframe may be used in which a plurality of frames are concatenated and handled as one long frame, and the use of a multiframe is effective particularly when a large transmission delay difference of several tens of kilometers or more is assumed.

  Further, in the configuration of the present embodiment, as shown in the modification of FIG. 59, the order of the first memory 706a and the first termination circuit 704a, and the third memory 706c and the second termination circuit 704b may be switched. In this case, the same effect is obtained.

  It will be apparent that this embodiment can be combined with the thirteenth through eighteenth embodiments. In other words, the configuration in which the memory is arranged in the subsequent stage of the switching circuit in order to keep the clock of the signal sent to the client side constant as in this embodiment can be easily applied to other embodiments.

[20th embodiment]
Next, an uninterruptible switching device according to a twentieth embodiment of the present invention will be described with reference to FIGS. FIG. 60 shows the structure of the uninterruptible switching device according to the twentieth embodiment of the present invention. In the twentieth embodiment, there are no first to third clock control circuits, and between the first memory and the switching circuit, between the third memory and the switching circuit, and between the switching circuit and the second memory. This is different from the nineteenth embodiment in that a bus width control circuit is arranged. Therefore, in the following description, overlapping descriptions are omitted.

  In the non-instantaneous switching device 800 according to the twentieth embodiment, assuming that the signal data rate is 10 Gbps and 16 parallel transfers are performed, the bit rate is 652 Mbps (= 10 Gbps / 16) per parallel. One bit is transferred from each bus every clock (625 MHz). Here, if the bus width is doubled (N = 2), the parallel number is 32, and if 1 bit is transferred from 32 parallel buses per 1 clock (625 MHz), the data rate is 20 Gbps, and the bus width is doubled. As a result, the data transfer rate can be doubled. As shown in FIG. 61, the data transfer rate is increased N times by changing the data bus width to N times (a positive integer) by the bus width control circuit 818, and the amount of data stored in the first memory 806a is reduced. Accordingly, the amount of data stored in the second memory 806b increases, so that the active system delay is adjusted at the input portion of the switching circuit 812 between the first memory 806a and the second memory 806b. be able to. However, in order to prevent memory slip, the bus width between the first memory 806a and the switching circuit 812 and between the switching circuit 812 and the second memory 806b must be simultaneously changed equally.

  On the other hand, when increasing the delay, as shown in FIG. 62, if N = 0 and no data is transferred from the first memory 806a, data writing to the first memory 806a and data from the second memory 806b are performed. Since data reading is continued at the data transfer rate, the amount of data stored in the first memory 806a increases and the amount of data stored in the second memory 806b decreases, so that the delay of the active system increases at the input portion of the switching circuit 812. Can be adjusted as if. If N = 1 at the same time as the delay adjustment is completed, the accumulated amounts of the first memory 806a and the second memory 806b do not change, so that the delay between the active system and the standby system can be maintained, and the transmission code can be maintained. It is possible to perform non-instantaneous switching by using an error, a failure, an instruction from an operator, or the like as a trigger.

  In addition, when it is necessary to adjust the delay of the standby system when switching back from the active system to the standby system and switching back to the active system without interruption, switching between the third memory 806c and the switching circuit 812 is performed. The delay can be adjusted by implementing a similar bus width adjustment between the circuit 812 and the second memory 806b.

  FIG. 63 shows another configuration of the uninterruptible switching device according to the twentieth embodiment. In the illustrated configuration, when the delay adjustment of the active system is performed, between the first memory 806a and the first termination circuit 804a, between the first termination circuit 804a and the switching circuit 812, and between the switching circuit 812 and the second memory. The bus width between 806b and 806b is changed at the same time and executed. When the standby delay adjustment is performed, the bus width adjustment between the third memory 806c and the second termination circuit 804b and between the second termination circuit 804b and the switching circuit 812 is simultaneously performed with the same change. In addition, when switching back to the active system again without instantaneous interruption after execution of switching to the standby system without instantaneous interruption, when adjusting the delay of the standby system, the third memory 806c and the second termination circuit 804b are connected to each other. The bus width between the 2-termination circuit 804b and the switching circuit 812 and between the switching circuit 812 and the second memory 806b is simultaneously changed to be equal.

  It will be apparent that this embodiment can be combined with the thirteenth through nineteenth embodiments. That is, as in the present embodiment, the delay is adjusted by adjusting the data transfer rate by controlling the bus width by using the bus width control circuit instead of the clock control circuit in the nineteenth embodiment. The configuration can be easily applied to other embodiments.

[Twenty-first embodiment]
An embodiment according to the present invention will be described with reference to FIG.

  FIG. 64 is a configuration diagram of the uninterruptible switching device according to the twenty-first embodiment of the present invention. Individual CDR (Clock and Data Recovery) 1010, FIFO memory 1020, frame detection unit 1030, one phase difference detection unit 1050, one selection unit 1040, clock generation for the active system, the standby system, and the rearrangement system Part 1100.

The clock generation unit 1100 includes switches (SW) 1110 _{1 to} 1110 ₃ , PLL (Phase Locked Loop) 1120 _{1 to} 1120 ₃ , CLK (clock) control units 1130 _{1 to} 1130 ₃ , SW 1140 _{1 to} 1140 ₃ , PLLs 11601 to 1160 ₃ , SW 1150, and PLL 1170.

The CDR 1010a, CDR 1010b, and CDR 1010c reproduce the clock signal from the received signals of each system, and identify and reproduce the signal. The output signal from each CDR 1010 is temporarily stored in each FIFO memory 1020a, FIFO memory 1020b, and FIFO memory 1020c. Thereafter, the signal is input to the frame detection unit 1030a, the frame detection unit 1030b, and the frame detection unit 1030c. Here, the frame portion of the signal is analyzed, and an identification signal representing a frame position or a multiframe position is detected. The detected frame position information is sent to the phase difference detection unit 1050. The phase difference detection unit 1050 receives the frame position information of the active system, the standby system, and the rearrangement system, and calculates the relative delay relationship of each system by comparing them. Based on the calculation result, control signals are sent to the CLK control units 1130 _{1 to} 1130 ₃ of the clock generation unit 1100. The CLK control units 1130 _{1 to} 1130 ₃ control the output frequencies of the PLLs 1120 _{1 to} 1120 ₃ based on the control signal. The SWs 1110 _{1 to} 1110 ₃ receive the clocks of each system, select one of them, and output it to the PLLs 1120 _{1 to} 1120 ₃ . The PLLs 1120 _{1 to} 1120 ₃ generate clocks synchronized with the clocks selected by the SWs 1110 _{1 to} 1110 ₃ as a reference. CLK control units 1130 _{1 to} 1130 ₃ control output frequencies of the PLLs 1120 _{1 to} 1120 ₃ . SWs 1140 _{1 to} 1140 ₃ receive the outputs of the respective PLLs 1120 _{1 to} 1120 ₃ and select one of them. The PLLs 1160 _{1 to} 1160 ₃ generate clocks synchronized with the clocks selected by the SWs 1140 _{1 to} 1140 ₃ as a reference. The SW 1150 receives the outputs of the PLLs 1120 _{1 to} 1120 ₃ and selects one of them. The PLL 1170 has a function of generating a clock synchronized with the clock selected by the SW 1150 as a reference.

First, a process of adding a standby system to a path operated only by the active system will be described. In the initial working system only, SW 1110 ₁ , SW 1110 ₂ , and SW 1150 of the clock generation unit 1100 select the working system. Also the SW1110 ₂ is the standby system of the standby system, SW1140 ₂ is to add. Standby system is selected auxiliary system (PLL1120 _2, first .CDR1010b the signal to the backup is inputted an output of the data and the clock The data is stored in the FIFO memory 1020b, and the clock is supplied from the SW 1110 ₂ of the clock generation unit 1100 through the PLL 1120 ₂ , SW 1140 ₂ , and PLL 1160 ₂ as a read clock of the FIFO memory 1020b. When frame synchronization of data is established, the frame position information is sent to the phase difference detection unit 1050, so that the delay difference between the active system and the standby system is calculated based on the calculation result. The control is performed so that there are four main types of control:
1. Increase the delay of the working system;
2. Reduce the delay of the working system;
3. Increase the standby delay;
4). Reduce standby delays;
There are four ways. In the case of 1 or 2, the output clock frequency of the active PLL 1120 ₁ may be made smaller (increase the delay) or increased (decrease the delay) than the input clock frequency. In the case of 3 or 4, the output frequency of the standby PLL 1120 ₂ may be made smaller (increase the delay) or increased (decrease the delay) than the input clock frequency. This frequency control is performed by the CLK controller 1130 _one or CLK controller 1130 _second clock generating unit 1100 an instruction from the phase difference detecting section 1050. The frequency control is performed so that the original frequency is restored when the delays of both systems are just aligned. After a delay of both systems are aligned, it performs switching to select the spare system SW1140 ₂ the working system (PLL1120 ₁ output) (instantaneous interruption due to switching at this time is smoothed by PLL1160 _2). Since the read clock of the FIFO memory 1020a and the FIFO memory 1020b by the switching becomes the same (PLL1120 ₁ output), or shift the transmission delay due to the difference in the path length of the working system and a standby system, the delay difference due to jitter error between the two systems Variations and the like are absorbed by the FIFO memory 1020, and the FIFO memory 1020 and later are exactly the same regardless of disturbances and variations. This completes an uninterruptible switching system between the active system and the standby system (FIG. 65 (a)). When a failure occurs in the unlikely event the active system, instantaneous interruption due to such switching (switching of this time the selector 1040 as switches SW1130 ₂ to select a frame detection section 1030b selects the auxiliary system (PLL1120 ₂₎ is smoothed by PLL1160 ₂ It is possible to switch from the active system to the standby system without data loss.

Next, the process of rearranging the working system to another path in a state where the delay between the working system and the standby system has been adjusted and switching without interruption can be described. The same data as the active system is transmitted to the relocation destination path. The data is received by CDR1010c, the output of the data and the clock is started from CDR1010c, data in the FIFO memory 1020c, the clock is sent to SW1110 ₃ of the clock generating unit 1100. SW 1110 ₃ selects a relocation destination clock, and SW 1130 ₃ also selects a relocation destination clock. Clock selected by SW1130 ₃ is used as a read clock for the FIFO memory 1020c via PLL1140 _3. As a result, data is supplied to the frame detection unit 1030c. When frame synchronization of data is established by the frame detection unit 1030c, frame position information is sent to the phase difference detection unit 1050, so that a delay difference between the active system (and the standby system) and the rearrangement destination system is calculated. Although control is performed so that the delay difference between the active system (and the standby system) and the rearrangement destination system becomes equal based on the calculation result, four types of control are mainly assumed. that is,
1. Increase the delay of the active system (and the standby system);
2. Reduce the delay of the active system (and the standby system);
3. Increase the relocation destination delay;
4). Reduce relocation delay;
There are four ways. (Since the standby system SW 1140 ₂ has selected the active system clock (PLL1120 ₁ ), if the PLL1120 ₁ is controlled to change the delay of the active system, the delay of the standby system also changes in synchronization.) 1 Alternatively, in the case of 2, the output clock frequency of the active PLL 1120 ₁ may be made smaller (increase the delay) or increased (decrease the delay) than the input clock frequency. In the case of 3 or 4, the output frequency of the PLL 1120 ₃ of the rearrangement destination system may be made smaller (increase the delay) or increased (decrease the delay) than the input clock frequency. This frequency control is performed by the CLK control unit 1130 ₁ or 1130 ₃ according to an instruction from the phase difference detection unit 1050. The frequency control is controlled so as to return to the original frequency when the delays of the active system (and the standby system) and the rearrangement destination system are just aligned (FIG. 65 (b)). When the delays of both systems are complete, the path is switched instantaneously from the active system to the relocation destination. Specifically, the selection unit 1040 selects the frame detection unit 1030c, the SW 1150 of the clock generation unit 1100 selects the relocation destination system (PLL1120 ₃ ), and the standby system SW 1140 ₂ selects the relocation destination system (PLL1120 ₃ ). select. As a result, path switching from the active system to the relocation destination system is executed, and the standby system that is subordinately synchronized to the active system is subordinately synchronized to the new active system that is the relocation destination. The original active system is released after the uninterruptible switching is completed, and is used for another path setting for path optimization (FIG. 65 (c)).

In addition, when a failure occurs in the relocation destination (new active system) in this state, it is switched to the standby system without interruption. Specifically, the selection unit 1040 selects the standby system (FIFO memory 1020b), and the SW 1140 ₂ switches to select the new working system (PLL1120 ₃ ). Instantaneous interruption due to switching is smoothed by PLL1160 _2.

[Twenty-second embodiment]
A twenty-second embodiment according to the present invention will be described with reference to FIG. In FIG. 66A, usable wavelengths are arranged in order from λ1 to λ8, of which λ1, λ2, λ6, λ7, and λ9 are in use, and λ3, λ4, λ5, and λ8 are unused. ing. In addition, λ6 and λ9 are an active system and a standby system of an uninterrupted path, respectively. When a 100 Gbps path setting request is generated in this state, 25 consecutive 4 wavelengths are required per wavelength, but in FIG. 66 (a), only 3 wavelengths from λ3 to λ5 are available at the maximum. Therefore, λ6 is rearranged to λ8, and four wavelengths of λ3 to 6 are secured by adding newly vacated λ5. λ6 is the working system of the non-instantaneous path and is adjusted so that the delay is equal to that of the standby system of λ9, but is not adjusted to the delay with the rearrangement destination λ8. Therefore, the delays of the active system of λ6 and the standby system of λ9 are adjusted at the same time so as to be equal to the delay of λ8. When the delays of λ6, λ8, and λ9 are aligned, the instantaneous λ6 path is switched to the rearrangement destination λ8 without interruption ((b) of FIG. 66). As a result, λ8 becomes a new working system, and a system without instantaneous switching is maintained with the standby system of λ9. After the switching is completed, the λ6 path is deleted, and a 100 Gbps path (25 Gbps × 4 wavelengths) is set using the four wavelengths λ3, λ4, λ5, and λ6 ((c) in FIG. 66).

  By adjusting the delays of λ6 and λ9 that constitute the uninterruptible switching system at the same time and executing the control to match the delay of λ9, which is the relocation destination, without interrupting the uninterruptible switching service Wavelength paths can be rearranged.

[Twenty-third embodiment]
The twenty-second embodiment described above relates to uninterrupted rearrangement of wavelength paths, but this embodiment relates to rearrangement of path capacity within a time slot. FIG. 67 is a diagram for explaining path rearrangement in a time slot. There are three OTU3s (Optical Transport Unit 3), in which 10G and 2.5G paths are set. When a 10G new path setting request is generated and the path setting status is referred to, there is no 10G capacity available. Therefore, the cost of the network is designed, and a decision is made to relocate the OTU3 1 2.5G path (uninterruptible active system) to OTU3 2 (FIG. 67 (a)). The delay of the 2.5G working path of OTU3 part 1 and the 2.5G standby path of OTU3 part 3 are simultaneously controlled to match the delay of the 2.5G relocation destination of OTU3 part 2, which is the relocation destination. After the delay adjustment is completed, the 2.5G uninterruptible active system path of OTU3 part 1 is switched to the 2.5G relocation destination path of OTU3 part 2 without interruption, and rearrangement is performed (FIG. 67 (b)). After the rearrangement is completed, the 2.5G path of OTU3 # 1 is deleted, and a new 10G path is set using the free 10G capacity (FIG. 67 (c)).

  The present invention is not limited to the above-described embodiment, and various modifications and applications can be made within the scope of the claims.

DESCRIPTION OF SYMBOLS 1 Interface part 2 FIFO memory 3 Clock adjustment part 10 Cross-connect part 20 Network side interface (reception)
21 receiving unit 22 framer / separating unit 23 branching unit 24 converting unit 26 delay adjusting unit 30 client side interface (receiving)
31 Client receiver 32 Mapping unit 33 Branch unit 34 Conversion unit 40 Network side interface (transmission)
41 conversion unit 42 delay adjustment unit 43 selection unit 44 framer / multiplexing unit 45 transmission unit 50 client side interface (transmission)
51 Conversion unit 52 Delay adjustment unit 53 Selection unit 54 Demapping unit 55 Client transmission unit 60 WDM (Wavelength Division Multiplexing) DEMUX
70 WDM MUX
80 Extended memory 81, 83 Conversion unit 82 Extended delay adjustment unit 100, 200, 300, 400, 500, 600, 700, 800 Uninterruptible switching device 200a, 300a, 400a, 500a, 600a Single system operation package 200a ', 300a ', 400a', 500a ', 600a' Upgrade packages 100b, 200b, 300b, 400b, 500b, 500b ', 600b, 600b' Preliminary package 102 IF (Interface) circuit 104 Frame termination circuit 106 FIFO memory 108 Clock control circuit 110 Phase difference detection circuit 112 Switching circuit 114 Switching control circuit 202, 302, 402, 502, 602 IF circuit 203, 303, 403, 503, 603 Branch circuit 204, 404, 504, 604 Frame termination circuit 206, 306, 406, 506, 606 FIFO memory 208, 308, 408, 508, 608 Clock control circuit 210, 310, 410, 510, 610, 710, 810 Phase difference detection circuit 212, 312, 412, 512, 612, 712, 812 Switching circuit 214 , 314, 414, 514, 614, 714 Switching control circuit 316, 416, 516, 616 Switch 320, 420, 520, 620 Switching package 500c, 600c Second single system operation package 600c 'Second upgrade package 702 Line side IF circuits 704a and 804a First termination circuits 704b and 804b Second termination circuits 706a and 806a First memories 706b and 806b Second memories 706c and 806c Third memory 708a First clock control circuit 708b Second clock control circuit 7 8c third clock control circuit 716,816 clock switching circuit 802a, 802b line side IF circuit 802c client IF circuit 818 bus width control circuit 1010 CDR
1020 FIFO memory 1030 Frame detection unit 1040 Selection unit 1050 Phase difference detection unit 1100 Clock generation unit 1110 Switch 1120, 1160, 1170 PLL
1130 Clock control units 1140 and 1150 switches

Claims (13)

An active transmission system for transmitting a signal received from the first transmission line;
A standby transmission system for transmitting the signal received from the second transmission line;
Non-instantaneous switching device for detecting a delay difference in signals between the active transmission system and the standby transmission system and adjusting a delay between the active transmission system and the standby transmission system based on the detected delay difference And an uninterruptible switching system,
The uninterruptible switching device is
An active memory and a standby memory for storing communication data extracted from signals received from the active transmission system and the standby transmission system, respectively;
Delay adjustment for equalizing the amount of delay between the active transmission system and the standby transmission system by continuously changing the read clock frequency of the active memory within a frequency deviation range in which predetermined communication quality can be maintained Means,
Having
Non-instantaneous switching system. The delay adjusting means is
The write clock frequency of the active memory and the spare memory is set to a clock frequency synchronized with the received signal, and the read clock frequency of the active memory and the spare memory is set to the write clock frequency according to the delay amount. 2. The uninterruptible switching system according to claim 1, further comprising means for increasing or decreasing the distance.   3. The uninterruptible switching system according to claim 1, wherein the active memory and the spare memory are first-in first-out (FIFO) memories. The working transmission system is
It further has an additional memory for storing communication data extracted from the received signal,
The delay adjusting means is
Means for controlling a delay amount of the active transmission system by continuously changing a read clock frequency of the active memory within a frequency deviation range in which predetermined communication quality can be maintained;
The working transmission system is
After the control of the delay adjusting means, non-instantaneous switching is performed on a signal path for writing and reading the communication data to and from the additional memory,
The uninterruptible switching system according to any one of claims 1 to 3, further comprising means for executing uninterrupted switching to the standby transmission system after the uninterrupted switching. 5. The uninterruptible switching system according to claim 4, wherein the additional memory has a storage capacity corresponding to the standby memory. A switch circuit detachably connected to the active transmission system and the standby transmission system;
A selection circuit that selectively outputs a signal output from the switch circuit;
The uninterruptible switching system according to any one of claims 1 to 5, further comprising: 7. The uninterruptible switching system according to claim 6, further comprising means for performing one-side operation by the active transmission system when the backup transmission system is removed from the switch circuit. A further transmission system for transmitting a signal received from the third transmission line;
2. The apparatus according to claim 1, further comprising means for switching from the active transmission system to the alternative transmission system without interruption and operating the standby transmission system as a standby transmission system of the alternative transmission system after switching. The uninterruptible switching system according to any one of 4 to 7. A switching circuit that switches the signal output from the active transmission system and the standby transmission system without interruption;
A post-stage memory that accumulates communication data extracted from the signal output from the switching circuit, and
The delay adjusting means is
2. The uninterruptible switching system according to claim 1, further comprising means for controlling a write clock frequency of the subsequent memory so as to be equal to a read clock frequency of the memory of the active transmission system. The delay adjusting means is
By controlling the bus width of the first bus that connects the active transmission system and the switching circuit and the bus width of the second bus that connects the switching circuit and the subsequent memory, writing to the subsequent memory 10. The uninterruptible switching system according to claim 9, further comprising means for controlling the clock frequency to be equal to the read clock frequency of the memory of the active transmission system. The delay adjusting means is
If uninterrupted switching was applied to the original path when performing path relocation,
2. The means according to claim 1, further comprising means for simultaneously controlling transmission delays of the active transmission system and the standby transmission system constituting the uninterruptible switching system so as to match the delay of the relocation destination path. Non-instantaneous switching system. An uninterruptible switching system that selects and outputs one of signals transmitted through a plurality of transmission paths,
Memory A that temporarily stores the data of the active transmission system,
Memory B that temporarily stores data of the standby transmission system,
Memory C that temporarily stores the data to be relocated,
Clock control means A for adjusting the read clock of the memory A,
Clock control means B for adjusting the read clock of the memory B,
A clock control means C for adjusting a read clock of the memory C;
Adjusting means for simultaneously adjusting the read clock of the memory A and the read clock of the memory B so that the delay of the data of the active transmission system and the data of the backup transmission system is equal to the delay of the data at the relocation destination; ,
A non-instantaneous switching system characterized by comprising: The clock control means A, the clock control means B, and the clock control means C are:
An active oscillator that oscillates on the basis of a clock synchronized with the data of the active transmission system;
A standby oscillator that oscillates on the basis of a clock synchronized with the data of the standby transmission system; and
A relocation destination oscillator that oscillates based on a clock synchronized with the data of the relocation destination;
An active switch for selecting one of the oscillators;
A backup switch for selecting one of the oscillators;
A relocation destination switch for selecting one of the oscillators;
An active oscillator for smoothing the output of the active switch;
A standby oscillator for smoothing the output of the standby switch;
A relocation destination oscillator for smoothing the output of the relocation destination switch;
13. The uninterruptible switching system according to claim 12.