JP2015016586A - Image processing system and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image processing system capable of shortening time required for drawing of image data to memory.SOLUTION: A drawing processing part 120, which has a circuit configuration configured as a circuit within a reconfigurable circuit, gets access to image memory 130 to draw an object, expressed in image data, into the image memory 130. An intermediate data generation part 110 interprets the image data to generate a command for instructing the drawing processing part 120 to continuously draw the different objects into the image memory 130.

Description

  The present invention relates to an image processing apparatus and a program.

  A technique for speeding up drawing of image data to a memory is known. For example, Patent Document 1 discloses an apparatus that selects a circuit attribute stored in a configuration storage unit according to the appearance frequency of an attribute of image information and configures the selected circuit in a dynamic circuit reconfiguration unit. Yes.

  Patent Document 2 discloses a reconfigurable circuit that efficiently holds and transfers circuit configuration information. The reconfigurable circuit includes a DRAM that stores a plurality of circuit configuration information and a secondary cache that caches the circuit configuration information loaded in the processing element, and the circuit configuration information to be loaded into the processing element is stored in the secondary cache. If not, the circuit configuration information is read from the DRAM to the secondary cache, and the circuit configuration information is loaded from the secondary cache to the processing element.

JP 2010-143040 A JP 2010-2986 A

  By the way, when the device that draws image data in the memory is configured with a reconfigurable circuit, the time required to generate circuit configuration information and the time required to load circuit configuration information into the reconfigurable circuit can be reconfigured. It may be longer than the time required for the drawing process by the circuit. In this case, the entire processing time may increase.

  An object of the present invention is to provide an image processing apparatus and program capable of reducing the time required for drawing image data in a memory.

  The invention according to claim 1 is configured as a reconfigurable circuit having a reconfigurable circuit configuration, and a circuit in the reconfigurable circuit, and by accessing an image memory, the object represented in the image data is Drawing processing means for drawing in an image memory; command generation means for generating a command for instructing the drawing processing means to continuously draw different objects in the image memory by interpreting the image data; An image processing apparatus comprising:

  According to a second aspect of the present invention, the command generation means includes a plurality of objects that are subjected to the same drawing process on the image memory and have a continuous drawing order among the plurality of objects represented in the image data. The image processing apparatus according to claim 1, wherein the command for instructing the drawing processing unit to continuously draw in the image memory is generated.

  According to a third aspect of the present invention, there is provided control means for generating circuit configuration information for causing the drawing processing means to realize a circuit for executing drawing processing, and for configuring a circuit in the drawing processing means based on the circuit configuration information. And when the drawing processing of a plurality of objects for which the same drawing processing is performed continues according to the command, the control means continues the drawing processing without changing the circuit of the drawing processing means. The image processing apparatus according to claim 1, wherein the image processing apparatus is executed by a processing unit.

  According to a fourth aspect of the present invention, there is provided an execution storage means for storing circuit configuration information for causing the drawing processing means to realize a first circuit for executing a first drawing process, and a second drawing after the first drawing process. Standby storage means for storing circuit configuration information for causing the drawing processing means to realize a second circuit for executing processing, and the control means includes a plurality of objects for which the same drawing processing is performed. When the drawing order is continuous, the first circuit is continuously configured in the drawing processing unit based on the circuit configuration information stored in the execution storage unit, and the drawing order of a plurality of objects in which the same drawing process is performed The circuit configuration information stored in the storage device for standby is loaded into the storage device for execution and the second circuit is configured in the drawing processing device if not continuously. Painting It is a processing apparatus.

  According to a fifth aspect of the present invention, when the drawing order of a plurality of objects for which the same drawing processing is performed is not continuous, the control means includes a circuit for executing the drawing processing of the plurality of objects as the drawing processing means. A plurality of circuit configuration information to be realized is generated on the main storage means, and each of the plurality of circuit configuration information is sequentially loaded from the main storage means to the standby storage means according to the drawing order, and the standby Loading the execution storage means to the execution storage means, the circuit configuration information stored in the execution storage means is changed according to the drawing order, the circuit of the drawing processing means is changed, and the same drawing processing is performed. When the drawing order of the plurality of objects is continuous, the control means does not change the circuit configuration information stored in the execution storage means, and the execution storage means Forming the circuit in the drawing processing means based on the stored circuit configuration information, it is an image processing apparatus according to claim 4, characterized in.

  According to a sixth aspect of the present invention, the command generating means generates intermediate data indicating a drawing process of each object based on the image data, and interprets the intermediate data, whereby the same drawing is performed on the image memory. A list indicating a plurality of objects that are processed and the drawing order is continuous is generated, and the drawing processing unit writes the continuous plurality of objects continuously in the image memory according to the list. An image processing apparatus according to any one of claims 1 to 5.

  The invention according to claim 7 is a reconfigurable circuit in which a circuit configuration is reconfigurable in a drawing processing circuit that draws an object represented by image data in the image memory by accessing the image memory to a computer. And a step of generating a command for instructing the drawing processing circuit to continuously draw different objects in the image memory by interpreting the image data. Is a program characterized by

  According to the first and seventh aspects of the present invention, it is possible to reduce the time required for drawing image data in the memory as compared with the case where the configuration of the present invention is not used.

  According to the second aspect of the present invention, a plurality of objects in which the same drawing process is performed and the drawing order is continuously written are continuously written in the image memory, and the image on the memory is compared with the case where the configuration of the present invention is not used. It is possible to reduce the time required for drawing data.

  According to the invention of claim 3, the circuit configuration is not changed when the drawing order of a plurality of objects for which the same drawing processing is performed is continuous, and the image for the memory is compared with the case where the configuration of the present invention is not used. It is possible to reduce the time required for drawing data.

  According to the fourth aspect of the present invention, in the apparatus for switching the circuit of the drawing processing means using the execution storage means and the standby storage means, when the drawing order of a plurality of objects on which the same drawing processing is performed continues, Compared to the case where the configuration of the invention is not used, it is possible to reduce the time required for drawing image data in the memory.

  According to the invention according to claim 5, when the drawing order of a plurality of objects for which the same drawing processing is performed is continuous, the number of times of loading the circuit configuration information is reduced, compared with the case where the configuration of the present invention is not used. Overall processing time is reduced.

  According to the invention of claim 6, by using the intermediate data, it is possible to shorten the time required for drawing the image data in the memory as compared with the case where the configuration of the present invention is not used.

It is a block diagram which shows an example of the system which concerns on embodiment. It is a block diagram which shows an example of the system which processes using a reconfigurable circuit. It is a block diagram which shows an example of the hardware constitutions of the image processing apparatus which concerns on embodiment. It is a schematic diagram for demonstrating an example of operation | movement of a reconstruction control part. It is a schematic diagram for demonstrating the drawing process which concerns on a reference example. It is a schematic diagram for demonstrating an example of the drawing process which concerns on embodiment. It is a figure which shows an example of the format of intermediate data. It is a figure which shows an example of the format of intermediate data. It is a figure which shows an example of the format of intermediate data. It is a figure which shows an example of the format of intermediate data. It is a schematic diagram for demonstrating an example of the drawing process which concerns on embodiment. It is a schematic diagram for demonstrating an example of operation | movement of the image processing apparatus which concerns on embodiment. 6 is a flowchart illustrating an example of an operation of the image processing apparatus according to the embodiment. 6 is a flowchart illustrating an example of an operation of the image processing apparatus according to the embodiment.

  FIG. 1 shows an example of a system according to an embodiment of the present invention. The system includes an image processing apparatus 100, an image memory 130, and a printing apparatus 140. The image processing apparatus 100 includes an intermediate data generation unit 110 and a drawing processing unit 120.

  For example, image data described in a page description language (PDL) is provided to the image processing apparatus 100 from an apparatus such as a computer. The page description language is a computer programming language for causing an information processing apparatus to execute print processing, display display processing, and the like. The image data described in the page description language includes position information, format information, color information, and the like of objects such as characters and graphics constituting the image to be printed.

  The intermediate data generation unit 110 is a command decoder, and generates and outputs intermediate data in which an image to be printed is described in an intermediate language by interpreting the image data. The intermediate data is data at a previous stage that is converted into drawing data that is finally output to the printing apparatus 140, and includes a command that represents a procedure for generating drawing data. A specific example of the intermediate data is a display list (DL), for example, but the present invention is not limited to this example. The intermediate data includes a drawing command representing a procedure for drawing each object that is a component of an image to be printed. Specifically, the intermediate data includes position information indicating the position of the object in the page, drawing order of the object (drawing command execution order), size information indicating the size of the object, and drawing contents of the object (for example, Drawing information indicating an image, a figure, a character, and the like) and color information indicating a color of the object (for example, how many colors the object is to be filled in). For example, the intermediate data of a certain page can be regarded as a set of commands indicating the drawing procedure of each object constituting the page.

  Further, the intermediate data generation unit 110 interprets the image data, and instructs the drawing processing unit 120 to continuously write a plurality of objects having the same drawing process to be executed and having a continuous drawing order to the image memory 130. New intermediate data (command) is generated. The intermediate data generation unit 110 corresponds to an example of a command generation unit.

  The drawing processing unit 120 (rasterizer) is, for example, a RIP (Raster Image Processor). The drawing processing unit 120 acquires intermediate data from the intermediate data generation unit 110, and generates drawing data that is compatible with the printing apparatus 140 and handled by the printing apparatus 140 according to the intermediate data. The drawing data is raster data including information (pixel value) for each pixel constituting the print image, for example, bitmap data or the like. The drawing processing unit 120 accesses the image memory 130 (frame memory) and writes the drawing data to the image memory 130, thereby storing the drawing data in the image memory 130. For example, the drawing processing unit 120 writes each object in the image memory 130 in order according to the drawing order (execution order) indicated by the intermediate data. When the drawing order of a plurality of objects having the same drawing process to be executed is continuous, the drawing processing unit 120 continuously writes the plurality of objects in the image memory 130 (object continuous processing). In this case, different objects are continuously written in the image memory 130.

  The printing apparatus 140 prints an image represented by the drawing data on a recording medium such as paper. For example, when drawing data for one page is written in the image memory 130, the drawing data is output to the printing apparatus 140, and an image represented by the drawing data is printed on a recording medium by the printing apparatus 140.

  In the image processing apparatus 100 described above, processing is executed by, for example, a DRP (Dynamic Reconfigurable Processor).

  FIG. 2 shows an example of a system that performs processing using DRP. As an example, this system includes a main CPU (central processing unit) 1, a main memory 2, a CPU bus-PCI bridge 3, a DRP accelerator 4, and an internal bus 50 for connecting them. The DRP accelerator 4 includes, for example, a plurality of DRP systems 5 and a PCI switch 6. A plurality of DRP systems 5 are connected to the PCI switch 6. The DRP system 5 includes a DRP 10 and a DDR memory 40. The DDR memory 40 stores data, programs, and the like for controlling the DRP 10.

  FIG. 3 shows an example of the hardware configuration of the image processing apparatus 100. In the example illustrated in FIG. 3, the image processing apparatus 100 is configured by the DRP 10.

  The DRP 10 is a processor that can dynamically change (reconfigure) the configuration of an internal logic circuit. The DRP 10 is, for example, a DAP / DNA architecture processor disclosed in Japanese Patent Application Laid-Open No. 2009-3765, but the present invention is not limited to this example, and may be composed of other circuits. . Hereinafter, an example of the DRP 10 will be described with reference to FIG.

  The DRP 10 includes a reconfiguration control unit 12 (RISC core module) called DAP (Digital Application Processor) and a reconfigurable circuit unit 14 (dynamic configurable data flow accelerator) called DNA (Distributed Network Architecture). Including. In addition to the reconfiguration control unit 12 and the reconfigurable circuit unit 14, the DRP 10 includes an interface 16 for direct input / output of the reconfigurable circuit unit 14, a PCI interface 18, an SDRAM interface 20, a DMA controller 22, and others. Peripheral devices 24 and an internal bus (high-speed switching bus) 26 for connecting them. The reconfiguration control unit 12 includes a debug interface 12a, a RISC core 12b, an instruction cache 12c, and a data cache 12d. The reconfigurable circuit unit 14 includes a PE matrix 14a and a configuration memory 14b. A plurality of processing elements PE (logic circuit elements) are two-dimensionally arranged in the PE matrix 14a. As an example, 376 processing elements PE are arranged in the PE matrix 14a. Configuration data 14c is stored in the configuration memory 14b. The configuration data 14c is data for reconfiguring the PE matrix 14a by changing the function and / or connection of the processing elements PE included in the PE matrix 14a and configuring a circuit in the PE matrix 14a.

  The reconfiguration control unit 12 is a module that performs operation control of the entire DRP 10 including the reconfigurable circuit unit 14, and is realized, for example, by executing a control program. The reconfiguration controller 12 configures a circuit for data processing in the PE matrix 14a by controlling the connection relationship of the processing elements PE in the PE matrix 14a. In addition, the reconfiguration control unit 12 performs control to supply data to a circuit configured in the PE matrix 14a and to output data from the circuit to another system.

  The configuration data 14c is data that defines the circuit configuration of the PE matrix 14a. Reconfiguration of the circuit in the PE matrix 14a is performed according to the configuration data 14c. A plurality of configuration data 14c is stored in the configuration memory 14b. When one of the plurality of configuration data 14c in the configuration memory 14b is selected and activated, a circuit configuration defined by the configuration data 14c is configured in the PE matrix 14a. As an example, the configuration memory 14b stores three configuration data 14c. However, the present invention is not limited to this example, and a number of configuration data 14c other than three may be stored in the configuration memory 14b.

  The configuration memory 14b will be described in detail. The configuration memory 14b has a configuration of a plurality of banks (a plurality of memories). For example, the configuration memory 14b includes an execution bank # 0 (execution memory), a bank # 1 (standby memory), and a bank # 2 (standby memory). The PE matrix 14a is configured and executed by the configuration data 14c stored in the execution bank # 0. Further, the second function or the third function is configured in the PE matrix 14a by the configuration data 14c stored in the bank # 1 or the bank # 2 as the background bank. Then, by switching the bank of the configuration memory 14b, the second function or the third function is reconfigured in the PE matrix 14a instead of the first function. The reconstruction of the PE matrix 14a is performed dynamically, for example, in one cycle (clock cycle). Thus, the PE matrix 14a is a reconfiguration unit including a plurality of processing elements PE for configuring a circuit and internal wirings for connecting these processing elements PE, and the processing elements PE are connected by the internal wirings. Is changed, the circuits included in the PE matrix 14a are reconfigured.

  Here, with reference to FIG. 4, a function switching process configured in the PE matrix 14 a will be described. For example, the reconstruction control unit 12 generates configuration data 14c for rendering each object in the image memory 130 on the DDR memory 40 according to the intermediate data (drawing command for each object) (DAP operation), and the configuration. The data 14c is loaded from the DDR memory 40 into the bank # 1 or the bank # 2 (DAP operation). Specifically, the reconstruction control unit 12 draws the object in the image memory 130 based on parameters (parameters defined in the intermediate data) such as object position information, size information, drawing contents, and color information. Configuration data 14c for the DDR memory 40 is generated. Then, the reconfiguration control unit 12 loads the configuration data 14c from the DDR memory 40 to the bank # 1 or the bank # 2, and further transfers the configuration data 14c from the bank # 1 or the bank # 2 to the execution bank # 0. By loading, the function corresponding to the configuration data 14c is configured in the PE matrix 14a (DAP operation). The PE matrix 14a executes the function configured by the configuration data 14c loaded in the execution bank # 0 (DNA operation). The DAP operation executed by the reconstruction control unit 12 corresponds to software processing, and the DNA operation executed by the PE matrix 14a corresponds to hardware processing.

  Next, an example of the drawing process according to the reference example will be described with reference to FIG. Here, the type of processing (drawing processing) for drawing drawing data on the image memory 130 will be described. Examples of the drawing processing include drawing commands such as “GRA”, “RAS-G”, and “RECT”. “GRA” is a drawing command indicating drawing between two designated points with a line segment. “RAS-G” is a drawing command indicating that a specified area is drawn in a format such as Bitmap. “RECT” is a drawing command indicating that a designated area is filled with a so-called solid. These drawing commands are defined in the intermediate data of each object.

  For example, the drawing processing unit 120 configured by the PE matrix 14 a draws each object in the image memory 130 according to the drawing order defined by the intermediate data. As an example, as illustrated in FIG. 5, the drawing process for the first object (lowercase “a”) is “RAS-G”, and the drawing process for the second object (lowercase “i”) is “GRA”. ”And the drawing process of the third object (capital“ B ”) is“ GRA ”. In this case, the reconfiguration control unit 12 uses the DDR memory 40 as the configuration data 14c for executing the drawing process “RAS-G” of the first object based on the intermediate data of the first object (“a”). The configuration data 14c generated above is loaded from the DDR memory 40 into the bank # 2, and the configuration data 14c is loaded from the bank # 2 into the execution bank # 0 (DAP operation). Thereby, a circuit for executing the drawing process “RAS-G” of the first object is configured in the PE matrix 14a. Then, the PE matrix 14a writes “first object (“ a ”)” to the image memory 130 by executing “RAS-G” on the first object (“a”) (DNA operation). .

  Further, the reconfiguration control unit 12 generates configuration data 14c on the DDR memory 40 for executing the drawing process “GRA” of the second object based on the intermediate data of the second object (“i”). Then, the configuration data 14c for “GRA” is loaded from the DDR memory 40 into the bank # 1 (DAP operation). For example, while the PE matrix 14a is executing the drawing process “RAS-G” for the first object, the reconstruction controller 12 sets the configuration data 14c for the drawing process “GRA” for the second object. Is loaded from the DDR memory 40 into the bank # 1 (DAP operation). That is, the DAP operation is performed in parallel with the DNA operation. When the rendering process “RAS-G” of the first object by the PE matrix 14a is completed, the reconstruction control unit 12 stores the configuration data 14c for the rendering process “GRA” of the second object in the bank # 1. To execution bank # 0 (DAP operation). Thus, a circuit for executing the drawing process “GRA” of the second object is configured in the PE matrix 14a. Then, the PE matrix 14a executes “GRA” on the second object (“i”) to write the second object (“i”) into the image memory 130 (DNA operation).

  Further, the reconfiguration control unit 12 generates, on the DDR memory 40, configuration data 14c for executing the drawing process “GRA” of the third object based on the intermediate data of the third object (“B”). Then, the configuration data 14c for “GRA” is loaded from the DDR memory 40 into the bank # 2 (DAP operation). For example, while the PE matrix 14a is executing the drawing process “GRA” of the second object, the reconstruction control unit 12 receives the configuration data 14c for the drawing process “GRA” of the third object DDR. The data is loaded from the memory 40 into the bank # 2 (DAP operation). When the drawing process “GRA” of the second object by the PE matrix 14a is completed, the reconstruction controller 12 executes the configuration data 14c for the drawing process “GRA” of the third object from the bank # 2. Load into bank # 0 (DAP operation). As a result, a circuit for executing the drawing process “GRA” of the third object is configured in the PE matrix 14a. Then, the PE matrix 14a executes “GRA” on the third object (“B”) to write the third object (“B”) into the image memory 130 (DNA operation).

  Similarly, for the fourth and subsequent objects, configuration data 14c for executing drawing processing of each object is generated on the DDR memory 40, and the configuration data 14c is stored in the bank # 1 or bank # 2 from the DDR memory 40. To be loaded. Configuration data 14c is alternately loaded from the DDR memory 40 into the banks # 1 and # 2. Then, the configuration data 14c is loaded from the bank # 1 or the bank # 2 to the execution bank # 0, and the drawing process is executed by the PE matrix 14a.

  In the drawing process according to the reference example shown in FIG. 5, the configuration data 14 c is once generated on the DDR memory 40 even when the drawing order of a plurality of objects having the same drawing process is continuous. The configuration data 14c is loaded from the DDR memory 40 into the bank # 1 or the bank # 2, and the configuration data 14c is loaded into the execution bank # 0. That is, the circuit configuration of the PE matrix 14a is changed every time the drawing process of each object is executed. The example shown in FIG. 5 will explain the configuration data for each object even though the drawing processing of the second object (“i”) to the Nth object (“x”) is “GRA”. 14c is generated once on the DDR memory 40, and the configuration data 14c for each object is loaded from the DDR memory 40 to the bank # 1 or the bank # 2, and further loaded from the bank # 1 or the bank # 2 to the execution bank # 0. doing. As described above, each time the drawing process of each object is performed, the configuration data 14c is generated for each object, and the configuration data 14c of each object is loaded from the DDR memory 40 to the bank. Generation time and load time increase, and the overall processing time may increase. For example, the drawing process by the PE matrix 14a is longer than the time required for generating the configuration data 14c and the time for loading the configuration data 14c from the DDR memory 40 to the bank (the time required for the DAP operation). When the time (time required for the DNA operation) is short, the generation and loading (DAP operation) of the configuration data 14c cannot catch up with the drawing process (DNA operation), and the entire processing time increases. That is, when the DAP operation and the DNA operation are executed in parallel, if the time required for the DAP operation becomes longer than the time required for the DNA operation, a waiting time for the DNA operation occurs and the overall processing time increases. Will do.

  In the present embodiment, when the drawing order of a plurality of objects having the same drawing process to be executed is continuous, the configuration data 14c is generated on the DDR memory 40 for each object, unlike the drawing process according to the reference example. Then, the plurality of objects are continuously drawn without being loaded into the bank. In this case, the PE matrix 14a continuously writes the plurality of consecutive objects in the image memory 130 without changing its circuit configuration.

  Here, an example of the drawing process according to the present embodiment will be described with reference to FIG. FIG. 6A shows an example of the drawing process according to this embodiment, and FIG. 6B shows an example of the drawing process according to the reference example. For example, as in the example illustrated in FIG. 5, the drawing process of the first object is “RAS-G”, the drawing process of the second object is “GRA”, and the third drawing process is “GRA”. The case where it is is demonstrated.

  With reference to FIG. 6A, a drawing process according to the present embodiment will be described. First, the reconfiguration control unit 12 generates configuration data 14 c for executing the drawing process “RAS-G” of the first object on the DDR memory 40, and stores the configuration data 14 c from the DDR memory 40 to the bank. Then, the configuration data 14c is loaded from the bank # 2 to the execution bank # 0 (DAP operation). Thereby, a circuit for executing the drawing process “RAS-G” of the first object is configured in the PE matrix 14a. Then, the PE matrix 14a executes “RAS-G” on the first object, thereby writing the first object into the image memory 130 (DNA operation).

  Further, the reconfiguration control unit 12 generates configuration data 14c for executing the drawing process “GRA” of the second object on the DDR memory 40, and the configuration data 14c is transferred from the DDR memory 40 to the bank # 1. (DAP operation). For example, the DAP operation is performed in parallel with the DNA operation. When the rendering process “RAS-G” of the first object by the PE matrix 14a is completed, the reconstruction control unit 12 stores the configuration data 14c for the rendering process “GRA” of the second object in the bank # 1. To execution bank # 0 (DAP operation). Thus, a circuit for executing the drawing process “GRA” of the second object is configured in the PE matrix 14a. Then, the PE matrix 14a executes “GRA” on the second object to write the second object into the image memory 130 (DNA operation).

  Since the drawing process of the third object is “GRA” and is the same as the drawing process of the second object, the reconfiguration control unit 12 stores the configuration data 14 c for the third object on the DDR memory 40. No configuration data 14c is loaded from the DDR memory 40 to the bank # 1 or the bank # 2. In this case, the PE matrix 14a obtains parameters (parameters defined in the intermediate data) such as position information, size information, and color information of the third object, and the circuit configuration of the PE matrix 14a itself is not changed. Then, only the parameter is changed, and the third object is written in the image memory 130 (object continuous processing). That is, the circuit for executing the drawing process “GRA” of the third object is already configured in the PE matrix 14a when the drawing process of the second object is executed. By using this, the third object is written in the image memory 130. In other words, the configuration data 14c loaded in the execution bank # 0 is not rewritten while the object continuous processing is executed, and a circuit for executing the same drawing processing is configured in the PE matrix 14a. It will be. On the other hand, when the object continuous process is not executed, the configuration data 14c loaded in the execution bank # 0 is rewritten, and the circuit configuration of the PE matrix 14a is changed. For example, when discontinuous processing continues, configuration data 14c stored in execution bank # 0 is rewritten by alternately loading configuration data 14c from bank # 1 or bank # 2 to execution bank # 0. Will be.

  For the fourth and subsequent objects, when the drawing order of a plurality of objects having the same drawing process to be executed is continuous, the PE matrix 14a continues the plurality of continuous objects without changing its circuit configuration. Are written in the image memory 130 (continuous object processing). In the example shown in FIG. 6A, since the drawing processes of the second to Nth objects are the same, the PE matrix 14a continues the second to Nth objects without changing the circuit configuration. Write to the image memory 130.

  While the object continuous processing is being performed, the reconfiguration control unit 12 generates, on the DDR memory 40, configuration data 14c for drawing processing that is executed after the object continuous processing, and the configuration data 14c is generated in the DDR memory 40. To bank # 1 or bank # 2. In the example shown in FIG. 6A, since the drawing process “RAS-G” is scheduled for the (N + 1) th object after the object continuous process “GRA”, the reconstruction control unit 12 Generates configuration data 14c for executing the rendering process “RAS-G” for the (N + 1) th object on the DDR memory 40, and loads the configuration data 14c from the DDR memory 40 to the bank # 2. To do. When the object continuous process “GRA” by the PE matrix 14a is completed, the reconfiguration control unit 12 loads the configuration data 14c for executing “RAS-G” from the bank # 2 to the execution bank # 0 ( DAP operation). As a result, the PE matrix 14a executes “RAS-G” to write the (N + 1) th object in the image memory 130 (DNA operation). The same applies to the subsequent objects, and when the drawing order of a plurality of objects having the same drawing process to be executed is continuous, the PE matrix 14a does not change its own circuit configuration, The data is continuously written in the image memory 130. On the other hand, when the drawing order of a plurality of objects having the same drawing process to be executed is not continuous, the reconfiguration control unit 12 generates, on the DDR memory 40, configuration data 14c for drawing processing for each non-continuous object. The configuration data 14c is loaded into bank # 1 or bank # 2.

  In the reference example shown in FIG. 6B, as in the reference example shown in FIG. 5, the DDR memory 40 is used even when the drawing order of a plurality of objects having the same drawing process to be executed is continuous. The configuration data 14c is once generated above, and the configuration data 14c is alternately loaded from the DDR memory 40 to the bank # 1 or the bank # 2.

  As described above, according to the present embodiment, when the drawing order of a plurality of objects having the same drawing process to be executed is continuous, the PE matrix 14a is already configured without changing the circuit of the PE matrix 14a. By using a circuit and continuously writing a plurality of continuous objects to the image memory 130, the overall processing time is shortened compared to the drawing processing according to the reference example. That is, in the present embodiment, when the drawing order of a plurality of objects having the same drawing process to be executed is continuous, the configuration data 14c is not generated on the DDR memory 40 for each object and loaded into the bank. By executing the object continuous processing, the time required to generate the configuration data 14c on the DDR memory 40 and the time required to load the configuration data 14c from the DDR memory 40 to the bank are reduced. . As a result, the overall processing time is shortened compared to the reference example. That is, since the number of times the configuration data 14c is generated and loaded is reduced, the overall processing time is shortened compared to the reference example.

  Next, a specific example of this embodiment will be described. First, the intermediate data generated by the intermediate data generation unit 110 will be described with reference to FIG. As an example, the intermediate data includes Stream0 (parameter information) and Stream1 (shape information). The intermediate data generation unit 110 generates Stream0 and Stream1 for each object represented in the image data, and lists the Stream0 and Stream1 of each object in the execution order (drawing order) of each object.

  The Stream 0 includes “Configuration ID (Configuration ID)”, “Data ID”, “Shape Top address”, “Shape Length”, “BitMask_ConstColor”, “Offset_Y_LSB, Offset_X_B, Offset_X_L”. Further, Stream1 includes “Config ID”, “Data ID”, and “Shape data”.

  “Config ID” is an ID of the configuration data 14 c and indicates the type of processing (drawing processing) for drawing an object on the image memory 130. The drawing commands such as “RAS-G”, “GRA”, and “REC” correspond to the drawing process. By referring to this “Config ID”, the drawing process of the object to be drawn is specified. “Data ID” is the series number of the Shape command of the image data, and indicates the drawing order of each object. “Shape Top address” indicates the start address of Stream1. “Shape Length” indicates the length of the Shape command and is defined in units of bytes. “BitMask_ConstColor” defines the value specified by the color command of the image data, and defines the color space, gradation, etc. of the image data as an example of the color attribute of the image data. “Offset_Y_LSB, Offset_X_LSB” indicates a position from the origin. “Bbox” is a boundary box that defines the drawing area of the object represented in the image data. For example, “Bbox” defines the position and size of a rectangular drawing area that circumscribes the object. As an example, “Bbox” is defined in the xy coordinate system and indicates the coordinates ((Lx, Ly), (Gx, Gy)) of the vertices on the diagonal line in the rectangular drawing region. “Shape data” is data of the Shape command, and indicates the shape of the object. “Shape data” has a variable length and, as an example, 0 data is filled so as to be a 256-byte burst unit. Note that the format of the intermediate data shown in FIG. 7 is an example, and the present invention is not limited to this example. As long as the position information, drawing order, size information, drawing information, color information, and the like of the object in the page are specified, the format of the intermediate data may be other than the format shown in FIG.

  In the present embodiment, the intermediate data generation unit 110 is not subject to a plurality of objects (a plurality of objects that are subject to object continuation processing) that have the same rendering process and that have a continuous rendering order, and object continuation processing. Differentiate between objects and generate different intermediate data. Hereinafter, the intermediate data of the object that is the object of the object continuous processing is referred to as “intermediate data for continuous processing”, and the intermediate data of the object that is not the target of the object continuous processing is referred to as “intermediate data for discontinuous processing”. I will do it.

  For example, the intermediate data generation unit 110 identifies the rendering process of each object by referring to “Config ID” included in the intermediate data of each object. When the specified drawing processes are the same and the drawing order of a plurality of objects is continuous, the intermediate data generation unit 110 generates “intermediate data for continuous processing” for the plurality of objects. On the other hand, when the drawing order of a plurality of objects for which the same drawing process is executed is not continuous, the intermediate data generation unit 110 generates “intermediate data for discontinuous processing” for the object.

  FIG. 8 shows an example of intermediate data for discontinuous processing. The intermediate data generation unit 110 adds information “Single Obj.” Indicating that the processing is not continuous processing to Stream0 (parameter information) of the intermediate data for discontinuous processing. Information other than “Single Obj.” Is the same as the information included in the original intermediate data shown in FIG.

  FIG. 9 shows an example of intermediate data for continuous processing. The intermediate data generation unit 110 adds information “Continue Obj.” Indicating continuous processing to the stream 0 (parameter information) of the intermediate data for continuous processing, and replaces “Shape Top address” with “Index Top address”. ”And“ Index Object address ”instead of“ Shape Length ”. “Index Top address” and “Index Object address” will be described later.

  Further, the intermediate data generation unit 110 adds “BitMask_ConstColor”, “Offset_Y_LSB, Offset_X_LSB”, and “Bbox” to Stream 1 (parameter / shape information) of the intermediate data for continuous processing. That is, the intermediate data generation unit 110 adds the position information and color information of the object to be continuously processed to the Stream1. As a result, the position information, the color information, and “Shape data” of the object are defined in Stream1.

  Further, the intermediate data generating unit 110 generates Stream2 (continuous processing information) based on Stream0 (parameter information) of the object to be continuously processed. This Stream2 (continuous processing information) defines the drawing order of each object to be continuously processed, and also defines the address of Stream1 (parameter / shape information) of each object on the memory. Specifically, the intermediate data generation unit 110 defines “Shape Top address” and “Shape Length” of each object to be continuously processed in the Stream 2 in the drawing order.

  Here, with reference to FIG. 10, the correspondence relationship between Stream0 and Stream2 will be described. In “Stream 2”, “Shape Top address” and “Shape Length” of objects # 1 to #N to be continuously processed are defined in units of 8 bytes in the drawing order. In addition, information “End of DNA continuous execute” indicating the end of continuous processing is defined at the end of the Stream2. Drawing processing of each object is performed in the order defined in Stream2. Details of the drawing process will be described later.

  “Index Top address” of Stream 0 indicates the start address of Stream 2. Since “Index Top address” is defined in Stream 0 of each object, the start address of Stream 2 is specified by referring to Stream 0 of each object. For example, “Index Top address” is defined for Stream0 of the first object # 1 among a plurality of objects to be continuously processed, and similarly, “Index Top address” is defined for Stream0 of the second object # 2. ing. “Index Top address” is also defined in Stream 0 of the third to Nth objects.

  In addition, “Index Object address” of Stream 0 of each object indicates an address in which “Shape Top address” of each object is defined in Stream 2. For example, since the object # 1 is the first object, the “Index Object address” of the object # 1 indicates the same address as the “Index Top address”. In addition, “Index Object address” of the object # 2 indicates an address in which “Shape Top address” of the object # 2 is defined in the Stream2. The same applies to other objects.

  As described above, in the present embodiment, before the drawing processing by the drawing processing unit 120, the intermediate data generation unit 110 generates new intermediate data, Stream0, Stream1, and Stream2.

  When the object continuous processing is performed, the PE matrix 14a acquires “Shape Top address” and “Shape Length” of the object # 1 as parameters by referring to the Stream2. Then, the PE matrix 14a refers to the Stream1, and the parameters of the object # 1 (“Shape data”, “BitMask_ConstColor”, and “Bbox”) defined in the memory area specified by “Shape Top address” and “Shape Length”. ), The object # 1 is written into the image memory 130. When the drawing process of the object # 1 is completed, the PE matrix 14a refers to the Stream2 and acquires the “Shape Top address” and the “Shape Length” of the object # 2 as parameters. Then, the PE matrix 14a refers to the stream 1, and the parameters of the object # 2 (“Shape data”, “BitMask_ConstColor”, “Bbox”) defined in the memory area specified by “Shape Top address” and “Shape Length”. ), The object # 2 is written into the image memory 130. Similar processing is performed for the objects # 3 to #N.

  FIG. 11 shows an example of the relationship between “Shape Top address” and “Shape Length” of each object on the memory. For example, the PE matrix 14a includes parameters of the object # 1 (“Shape data”, “BitMask_ConstColor”, and “Shape data”, which are defined in a memory area (for example, 64 bytes) specified by “Shape Top address” and “Shape Length” of the object # 1). According to “Bbox”), the object # 1 is written into the image memory 130. In addition, the PE matrix 14a includes parameters of the object # 2 (“Shape data”, “BitMask_ConstColor” and “Shape data”) defined in the memory area (for example, 128 bytes) specified by the “Shape Top address” and the “Shape Length” of the object # 2. According to “Bbox”), the object # 2 is written into the image memory 130. Similar processing is performed for the objects # 3 to #N.

  When the object continuous processing is not performed, the PE matrix 14a performs the object drawing processing with reference to the discontinuous processing Stream1.

  Next, with reference to FIG. 12, the drawing process executed based on the Streams 0, 1, and 2 will be described. First, the reconfiguration control unit 12 generates configuration data 14c for generating intermediate data on the DDR memory 40, loads the configuration data into the bank # 1, and further executes the bank # 1 from the execution bank # 1. Load 0 (DAP operation). Thereby, a circuit for realizing the function of the intermediate data generation unit 110 is configured in the PE matrix 14a. The intermediate data generation unit 110 generates Stream0, Stream1, and Stream2 by interpreting the image data.

  Then, the reconstruction control unit 12 refers to the Stream 0 and the Stream 2 and performs drawing processing control such as generation, loading, parameter setting, and confirmation / execution of DNA operation of the configuration data 14c for drawing processing.

  For example, a case will be described in which the drawing process of the first object is “RAS-G”, the drawing process of the second object is “GRA”, and the third drawing process is “GRA”.

  The reconfiguration control unit 12 specifies that the first object is not a target of continuous processing by referring to the first object Stream0, and further, based on the parameters defined in the Stream0, the first object Configuration data 14 c for executing the drawing process “RAS-G” is generated on the DDR memory 40. Since the first object is not a target of continuous processing, Stream 0 (intermediate data for discontinuous processing) shown in FIG. 8 is referred to by the reconfiguration control unit 12 to generate configuration data 14c. . Then, the reconfiguration control unit 12 loads the configuration data 14c from the DDR memory 40 to the bank # 2, and further loads the configuration data 14c from the bank # 2 to the execution bank # 0 (DAP operation). Thereby, a circuit for executing the drawing process “RAS-G” of the first object is configured in the PE matrix 14a. Then, the PE matrix 14a interprets Stream1 of the first object, and executes “RAS-G” on the first object according to “Shape Data” defined in Stream1. The object is written into the image memory 130 (DNA operation). Since the first object is not a target of continuous processing, Stream1 (intermediate data for discontinuous processing) shown in FIG. 8 is interpreted by the PE matrix 14a and drawing processing is performed.

  In addition, the reconstruction control unit 12 specifies that the second object is a target of continuous processing by referring to the Stream0 of the second object, and further draws the second object based on the Stream0. Configuration data 14 c for executing “GRA” is generated on the DDR memory 40. Since the second object is a target of continuous processing, Stream0 (intermediate data for continuous processing) shown in FIG. 9 is referred to by the reconfiguration control unit 12 to generate configuration data 14c. Then, the reconfiguration control unit 12 loads the configuration data 14c from the DDR memory 40 to the bank # 1 (DAP operation). For example, while the PE matrix 14a is executing the drawing process “RAS-G” for the first object, the reconstruction controller 12 sets the configuration data 14c for the drawing process “GRA” for the second object. Is loaded from the DDR memory 40 into the bank # 1. When the rendering process “RAS-G” of the first object by the PE matrix 14a is completed, the reconstruction control unit 12 stores the configuration data 14c for the rendering process “GRA” of the second object in the bank # 1. To execution bank # 0 (DAP operation). Thereby, a circuit for executing the drawing process “GRA” is configured in the PE matrix 14a.

  Then, the PE matrix 14a refers to Stream2 and Stream1 that are intermediate data for continuous processing, and executes “GRA” on the 2nd to Nth objects that are the targets of continuous processing, thereby obtaining 2 The Nth object is continuously written in the image memory 130 (DNA operation). As an example, a description will be given taking Stream2 shown in FIG. 10 as an example. The PE matrix 14a refers to Stream2, and acquires “Shape Top address” and “Shape Length” of the first consecutive object # 1 (second object shown in FIG. 12) as parameters. Then, the PE matrix 14a interprets the Stream1 and sets the parameters of the object # 1 (“Shape data”, “BitMask_ConstColor”) defined in the memory area specified by the “Shape Top address” and the “Shape Length” of the object # 1. In accordance with “Bbox”), the object # 1 is written in the image memory 130 by executing “GRA” on the object # 1 (DNA operation).

  Further, the PE matrix 14a acquires “Shape Top address” and “Shape Length” of the second consecutive object # 2 (the third object shown in FIG. 12) as parameters by referring to Stream2. Then, the PE matrix 14a interprets the Stream1 and sets the parameters of the object # 2 (“Shape data”, “BitMask_ConstColor”) defined in the memory area specified by the “Shape Top address” and the “Shape Length” of the object # 2. In accordance with “Bbox”), the object # 2 is written in the image memory 130 by executing “GRA” on the object # 2 (DNA operation). Since a circuit for executing the drawing process “GRA” is already configured in the PE matrix 14a, the PE matrix 14a writes the object # 2 to the image memory 130 while maintaining the circuit. That is, when performing the continuous processing, the configuration data 14c for executing the drawing process “GRA” of the object # 2 is not generated on the DDR memory 40 by the reconfiguration control unit 12, and the configuration data 14c to the bank is not generated. Is not executed.

  The PE matrix 14a writes continuously to the image memory 130 up to the Nth object. When the PE matrix 14a detects the end of continuous processing “End of DNA continuous execute” with reference to Stream 2, the continuous processing ends.

  While the continuous processing is being performed on the 2nd to Nth objects, the reconstruction control unit 12 refers to the Stream0 of the (N + 1) th object, so that the (N + 1) th object is not a target of continuous processing. Further, configuration data 14c for executing the drawing process “RAS-G” of the (N + 1) th object is generated on the DDR memory 40 based on the parameters defined in Stream0. Then, the reconfiguration control unit 12 loads the configuration data 14c from the DDR memory 40 to the bank # 2. When the drawing process of the Nth object is completed, the reconfiguration control unit 12 loads the configuration data 14c from the bank # 2 to the execution bank # 0 (DAP operation). Thus, a circuit for executing the drawing process “RAS-G” of the (N + 1) th object is configured in the PE matrix 14a. Then, the PE matrix 14a interprets Stream1 of the (N + 1) th object, and executes “RAS-G” on the (N + 1) th object according to “Shape Data” defined in Stream1. , (N + 1) th object is written in the image memory 130 (DNA operation). For the (N + 2) th and subsequent objects, the image processing apparatus 100 interprets the Streams 0, 1, and 2 to execute the object continuous processing or discontinuous processing.

  As described above, when stream 0, 1, and 2 are generated in advance as intermediate data before rendering processing, and the object continuous processing is executed by the PE matrix 14a interpreting Stream 2 and Stream 1, rendering is performed. The parameters necessary for the processing are set in the PE matrix 14a, and the drawing processing is executed. That is, the reconfiguration control unit 12 does not need to interpret the stream 0 of each object and generate the configuration data 14c for each object, and does not load the configuration data 14c for each object from the DDR memory 40 to the bank. That's it. That is, even if the DAP operation is not performed by the reconstruction control unit 12, the drawing process by the PE matrix 14a is executed. Thus, since the number of times the configuration data 14c is generated and the configuration data 14c is loaded by the reconfiguration controller 12 is reduced, the generation time and the load time of the configuration data 14c are reduced. Processing time is reduced. In other words, before the rendering process, in addition to the Streams 0 and 1, the Stream 2 that can be interpreted by the hardware PE matrix 14a is generated in advance, so that the object continuous process is a software process. The DAP operation is omitted, and a DNA operation (drawing process) that is a hardware process is executed. Since the DAP operation is thus omitted, the overall processing time is shortened.

  Next, an example of the operation of the image processing apparatus 100 will be described with reference to the flowcharts shown in FIGS.

  First, when an interrupt process (drawing request) occurs, an interrupt mask is set in the drawing processing unit 120 (S01), and thereafter, one of processes A, B, and C is executed according to the state of the drawing process (S02). ). Here, the process A is a process that is executed when the drawing process is started, and is a process that is executed when the configuration data 14c is not loaded in either the bank # 1 or the bank # 2. The process B is a process executed during the drawing process, and is executed when the configuration data 14c is loaded in both the bank # 1 and the bank # 2 and the drawing process is executed. The process C is a process executed when the drawing process is finished, and is a process executed when the last object drawing process is finished.

  First, a case where process A is executed will be described. In this case, a drawing process command is selected (S03), parameters for executing the drawing process are set, configuration data 14c is generated on the DDR memory 40 (S04), and the configuration data 14c is converted to DDR. The data is loaded from the memory 40 to the bank # 1 (S05). FIG. 14 shows the flow of this series of processing. First, the reconstruction control unit 12 selects a drawing processing command by interpreting Stream0 of the drawing target object (S20). Further, the reconstruction control unit 12 refers to the Stream0 of the object to be drawn, and specifies whether or not the object is a target for continuous processing. When the object is not a target of continuous processing, the reconfiguration control unit 12 refers to the stream 0 of the object, and stores the configuration data 14c for drawing the object on the DDR memory 40 according to the parameters defined in the stream 0. Generate (S21). On the other hand, when the object to be drawn is a target of continuous processing, the reconstruction control unit 12 refers to the stream 0 and stream 2 of the object, and configuration data for drawing the object according to the parameters defined in the stream 0 14c is generated on the DDR memory 40 (S22). Then, the reconfiguration control unit 12 loads the configuration data 14c from the DDR memory 40 to the bank # 1 (S23). Returning to FIG. 12, the reconfiguration control unit 12 loads the configuration data 14c from the bank # 1 to the execution bank # 0. Then, the PE matrix 14a executes the drawing process by executing the function configured by the configuration data 14c loaded in the execution bank # 0 (S06). Thereafter, similarly to the processing in steps S03 to S05, a drawing processing command is selected (S07), and configuration data 14c in which parameters for executing the drawing processing are set is generated on the DDR memory 40 (S08). ), The configuration data 14c is loaded from the DDR memory 40 into the bank # 2 (S09). Then, the process A ends (S10), the interrupt mask is released (S11), and the interrupt process ends. If a drawing process end command is detected in step S07, process A ends (S10).

  Next, a case where process B is executed will be described. In this case, when interrupt processing (drawing request) occurs, the reconfiguration control unit 12 stops processing of the PE matrix 14a (S12), and loads the configuration data 14c from the bank # 1 or bank # 2 to the execution bank # 0. To do. The PE matrix 14a executes the drawing process by executing the function configured by the configuration data 14c loaded in the execution bank # 0 (S13). Thereafter, similarly to the processing in steps S03 to S05, a drawing processing command is selected (S14), parameters for executing the drawing processing are set, and configuration data 14c is generated on the DDR memory 40 (S15). ), The configuration data is loaded from the DDR memory 40 into the bank # 1 or the bank # 2 (S16). Then, the interrupt mask is released (S11), and the interrupt process ends. If the drawing process end command is detected in step S14, the process B ends (S17).

  Next, a case where process C is executed will be described. In this case, since the drawing processing of the last object has been completed, the reconstruction controller 12 stops the processing of the PE matrix 14a (S18). Then, the interrupt mask is released (S11), and the interrupt process ends.

  As described above, the configuration data 14c is loaded into the execution bank # 0 and the drawing process is executed.

  10 DRP, 12 reconfiguration control unit, 14 reconfigurable circuit unit, 100 image processing device, 110 intermediate data generation unit, 120 drawing processing unit, 130 image memory, 140 printing device.

Claims (7)

A reconfigurable circuit whose circuit configuration is reconfigurable; and
A rendering processing unit configured as a circuit in the reconfigurable circuit and rendering an object represented by image data in the image memory by accessing the image memory;
Command generation means for generating a command for instructing the drawing processing means to continuously draw different objects in the image memory by interpreting the image data;
An image processing apparatus comprising: The command generation unit continuously draws, in the image memory, a plurality of objects in which the same drawing process is performed on the image memory and the drawing order is continuous among the plurality of objects represented in the image data. Generating the command to instruct the drawing processing means to
The image processing apparatus according to claim 1. Further comprising: control means for generating circuit configuration information for causing the drawing processing means to implement a circuit for executing the drawing processing, and for configuring the circuit in the drawing processing means based on the circuit configuration information;
In accordance with the command, when the drawing processing of a plurality of objects for which the same drawing processing is performed continues, the control means continues the drawing processing to the drawing processing means without changing the circuit of the drawing processing means. To execute,
The image processing apparatus according to claim 1 or 2, wherein Execution storage means for storing circuit configuration information for causing the drawing processing means to realize a first circuit for executing the first drawing processing;
Standby storage means for storing circuit configuration information for causing the drawing processing means to implement a second circuit that executes a second drawing process after the first drawing process;
Further comprising
The control means continues the first circuit to the drawing processing means based on the circuit configuration information stored in the execution storage means when the drawing order of a plurality of objects for which the same drawing processing is performed continues. If the drawing order of a plurality of objects configured and subjected to the same drawing process is not continuous, the circuit configuration information stored in the standby storage means is loaded into the execution storage means and the second circuit is drawn. Configure the processing means,
The image processing apparatus according to claim 3. When the drawing order of a plurality of objects on which the same drawing process is performed is not continuous, the control unit is configured to have a plurality of circuit configurations for causing the drawing processing unit to implement a circuit that executes the drawing process of each of the plurality of objects. Information is generated on the main storage means, and each of the plurality of circuit configuration information is sequentially loaded from the main storage means to the standby storage means according to the drawing order, and from the standby storage means to the execution storage By loading into the means, the circuit configuration information stored in the execution storage means is changed according to the drawing order to change the circuit of the drawing processing means, and the drawing order of a plurality of objects for which the same drawing processing is performed is changed. In the case of continuous operation, the control means does not change the circuit configuration information stored in the execution storage means, and the circuit configuration information stored in the execution storage means. Forming the circuit in the drawing processing means based on,
The image processing apparatus according to claim 4. The command generation means generates intermediate data indicating drawing processing of each object based on the image data, and interprets the intermediate data, whereby the same drawing processing is performed on the image memory, and the drawing order is continuous. Generate a list showing multiple objects
The drawing processing means continuously writes the plurality of consecutive objects to the image memory according to the list.
The image processing apparatus according to claim 1, wherein the image processing apparatus is an image processing apparatus. On the computer,
Configuring a drawing processing circuit that draws an object represented in image data in the image memory by accessing the image memory as a circuit in a reconfigurable circuit whose circuit configuration is reconfigurable;
Generating a command to instruct the drawing processing circuit to continuously draw different objects in the image memory by interpreting the image data;
A program characterized by having executed.

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