JP2015015701A5 - - Google Patents

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Publication number
JP2015015701A5
JP2015015701A5 JP2014103075A JP2014103075A JP2015015701A5 JP 2015015701 A5 JP2015015701 A5 JP 2015015701A5 JP 2014103075 A JP2014103075 A JP 2014103075A JP 2014103075 A JP2014103075 A JP 2014103075A JP 2015015701 A5 JP2015015701 A5 JP 2015015701A5
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JP
Japan
Prior art keywords
llr values
shortened
codeword
llr
values
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JP2014103075A
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Japanese (ja)
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JP2015015701A (ja
JP6367607B2 (ja
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Priority claimed from US13/934,999 external-priority patent/US9337865B2/en
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Publication of JP6367607B2 publication Critical patent/JP6367607B2/ja
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JP2014103075A 2013-07-03 2014-05-19 低密度パリティチェック（ｌｄｐｃ）復号器での対数尤度比（ｌｌｒ）減衰 Expired - Fee Related JP6367607B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/934,999 2013-07-03
US13/934,999 US9337865B2 (en) 2012-05-04 2013-07-03 Log-likelihood ratio (LLR) dampening in low-density parity-check (LDPC) decoders

Publications (3)

Publication Number Publication Date
JP2015015701A JP2015015701A (ja) 2015-01-22
JP2015015701A5 true JP2015015701A5 (https=) 2017-03-02
JP6367607B2 JP6367607B2 (ja) 2018-08-01

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ID=51167664

Family Applications (1)

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JP2014103075A Expired - Fee Related JP6367607B2 (ja) 2013-07-03 2014-05-19 低密度パリティチェック（ｌｄｐｃ）復号器での対数尤度比（ｌｌｒ）減衰

Country Status (5)

Country Link
EP (1) EP2822184B1 (https=)
JP (1) JP6367607B2 (https=)
KR (1) KR102155795B1 (https=)
CN (1) CN104283570B (https=)
TW (1) TWI619353B (https=)

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US9818488B2 (en) * 2015-10-30 2017-11-14 Seagate Technology Llc Read threshold voltage adaptation using bit error rates based on decoded data
KR102265220B1 (ko) * 2015-03-09 2021-06-16 에스케이하이닉스 주식회사 컨트롤러, 반도체 메모리 시스템 및 그것의 동작 방법
US9727416B2 (en) * 2015-07-01 2017-08-08 Xilinx, Inc. Variable code rate solid-state drive
US10268539B2 (en) * 2015-12-28 2019-04-23 Intel Corporation Apparatus and method for multi-bit error detection and correction
JP2018045387A (ja) 2016-09-13 2018-03-22 東芝メモリ株式会社 メモリシステム
US10222996B2 (en) 2017-02-07 2019-03-05 Western Digital Technologies, Inc. Read operation and soft decoding timing
US10269422B2 (en) * 2017-09-08 2019-04-23 Cnex Labs, Inc. Storage system with data reliability mechanism and method of operation thereof
KR102543059B1 (ko) 2017-11-22 2023-06-14 삼성전자주식회사 저밀도 패리티 체크 코드의 디코딩 방법, 이를 수행하는 디코더 및 시스템
US10884858B2 (en) * 2018-03-16 2021-01-05 SK Hynix Inc. LDPC decoding device, memory system including the same and method thereof
CN108683423B (zh) * 2018-05-16 2022-04-19 广东工业大学 一种多级闪存信道下的ldpc码动态串行调度译码算法及装置
US20190379399A1 (en) * 2018-06-08 2019-12-12 Goke Us Research Laboratory Log-likelihood-ratio (llr) generation algorithm for low-density-parity-check (ldpc) codes used in flash memory
US10715182B2 (en) * 2018-07-27 2020-07-14 Innogrit Technologies Co., Ltd. Systems and methods for decoding error correcting codes with self-generated LLR
KR102741031B1 (ko) * 2018-08-13 2024-12-11 에스케이하이닉스 주식회사 에러 정정 회로 및 이의 동작 방법
US10778248B1 (en) * 2020-01-30 2020-09-15 TenaFe, Inc. Low-density parity-check decoding with de-saturation

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7702986B2 (en) * 2002-11-18 2010-04-20 Qualcomm Incorporated Rate-compatible LDPC codes
JP2006238127A (ja) * 2005-02-25 2006-09-07 Sony Corp 復号装置および方法、並びにプログラム
CN101595700B (zh) * 2006-03-14 2014-04-16 高通股份有限公司 使用llr函数的分段线性逼近的对数似然比(llr)计算
US8873671B2 (en) * 2008-03-26 2014-10-28 Qualcomm Incorporated Method and system for LLR buffer reduction in a wireless communication modem
US8239734B1 (en) * 2008-10-15 2012-08-07 Apple Inc. Efficient data storage in storage device arrays
WO2011036864A1 (ja) * 2009-09-25 2011-03-31 パナソニック株式会社 符号化装置、復号装置、符号化方法、復号方法、及び通信システム
US8677218B2 (en) * 2010-01-27 2014-03-18 Sk Hynix Memory Solutions Inc. LDPC decoding with on the fly error recovery
US8458555B2 (en) * 2010-06-30 2013-06-04 Lsi Corporation Breaking trapping sets using targeted bit adjustment
KR20130012550A (ko) * 2011-07-25 2013-02-04 한양대학교 산학협력단 Ｌｄｐｃ 부호화 및 복호화 방법 및 그 방법을 사용하는 장치

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