JP2015006095A - Battery unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a battery unit which makes possible to suppress the mutual current backward flow between cell assemblies while reducing the loss of electric power by the cell assemblies.SOLUTION: A battery unit comprises: cell assemblies 10, 20, ... ,30 which are not directly connected in parallel, but connected in parallel with one another through switch parts respectively; a control part 2 capable of outputting an ON direction signal for turning on the switch parts thereto, and arranged to output the ON direction signal to any one of the switch parts selectively. When the control part 2 has output the ON direction signal to more than one switch part for some reason, the anti-concurrently-switch-on part nullifies the ON direction signals to all the switch parts, or leaves only the ON direction signal to any one of the switch parts effective. Concurrently turning on more than one of the switch parts is avoided in this way.

Description

  The present invention relates to a battery unit including a plurality of cell assemblies.

  A cell assembly in which a plurality of battery cells (hereinafter simply referred to as “cells”) are connected in series, in parallel or in series and parallel is connected in parallel, and power is supplied from one or more of the plurality of cell assemblies connected in parallel. There is a battery unit configured to supply power to a target load. As this type of battery unit, there are a configuration in which a plurality of cell assemblies are housed in a housing, and a configuration in which a plurality of cell assemblies can be individually attached and detached (see, for example, Patent Document 1). .

  In such a battery unit, when a plurality of cell assemblies are simply connected in parallel, current sneak (backflow) from one cell assembly to another due to a difference in electrical state between the cell assemblies or the like. ) May occur. Such a backflow caused by the difference in the electrical state between the cell assemblies is not very preferable for maintaining the quality of the battery. If an abnormality occurs in one cell assembly, an excessive sneak current (charging) from another cell assembly connected in parallel to the abnormal cell assembly may occur, and the state may deteriorate.

  On the other hand, Patent Document 1 is configured not to simply connect a plurality of batteries in parallel, but to connect a diode to the positive electrode of each battery and output a current from each battery to the load via the diode. An adapter is disclosed. According to this adapter, current wraparound between batteries connected in parallel is prevented by the diode.

JP 2011-218510 A

  However, the method for preventing the current from flowing between the batteries with the diode as described in Patent Document 1 has a large power loss due to the diode, and problems such as a decrease in power supplied to the load and heat generation due to the power loss. Invite.

  The present invention has been made in view of the above problems, and an object of the present invention is to suppress current wraparound between cell assemblies while suppressing power loss from each cell assembly.

  The battery unit of the present invention made to solve the above problems includes a plurality of cell assemblies, a positive electrode connection terminal, a negative electrode connection terminal, a switch unit provided for each cell assembly, a control unit, and a simultaneous on-blocking unit. With.

  The cell assembly includes an assembled battery in which a plurality of battery cells are connected in series, parallel, or series-parallel. The positive electrode connection terminal is connected to the positive electrode of each cell assembly. The negative electrode connection terminal is connected to the negative electrode of each cell assembly. The positive electrode of the cell assembly means the positive electrode of the assembled battery that the cell assembly has, and the negative electrode of the cell assembly means the negative electrode of the assembled battery that the cell assembly has.

  The switch unit is provided for each cell assembly, and is a member for conducting / interrupting the energization path between the positive electrode and the positive electrode connection terminal of the cell assembly. The control unit can individually output an on command signal for turning on each switch unit to make the energization path conductive for each switch unit, and selectively send an on command signal to any one of the switch units. It is configured to output. The simultaneous on-blocking unit validates only the on-command signal for any one of the plurality of switch units or outputs all of the on-command signals from the control unit to the plurality of switch units. By invalidating the ON command signal to the switch unit, the plurality of switch units are prevented from being turned ON simultaneously.

  In the battery unit configured as described above, the cell assemblies are not directly connected in parallel but are connected in parallel via a switch unit. Since the control unit selectively turns on one of the switches, the switch units are not normally turned on at the same time (as long as the control unit is normal). Are connected in parallel so that no current wraps between the cell assemblies. That is, in the present invention, current wraparound between the cell assemblies is suppressed by using a switch portion having a voltage drop (ON resistance) smaller than that of the diode without using a diode as in the prior art.

  However, the ON command signal may be output from the control unit to the plurality of switch units due to some factor such as an abnormality in the control unit. In consideration of the possibility that the ON command signal is output to the plurality of switch units as described above, the present invention includes a simultaneous ON blocking unit. Even if an ON command signal is output from the control unit to the plurality of switch units, the plurality of switch units are prevented from being simultaneously turned on by the simultaneous ON blocking unit.

Therefore, according to the battery unit of the present invention, it is possible to suppress current wraparound between the cell assemblies while suppressing power loss from each cell assembly.
The switch unit may include a first switch and a second switch connected in series. Specifically, one end of the second switch is connected to the positive electrode of the corresponding cell assembly, the other end is connected to one end of the first switch, and the other end of the first switch is connected to the positive electrode connection terminal. It may be.

  In this way, by configuring a switch unit using two switches connected in series, even if one of the two switches is short-circuited, as long as the other is normal, the other cell assembly Current wraparound can be suppressed. That is, current wraparound between the cell assemblies can be more effectively suppressed.

  Furthermore, a third switch, a switching control unit, and an abnormality determination unit may be provided to determine whether each switch unit is abnormal. The third switch is a switch provided individually for each switch unit, and one end thereof is connected to a connection unit between the first switch and the second switch. The switching control unit is provided for each third switch, and when the ON command signal is output to the corresponding switch unit, the third switch is turned OFF, and the ON command signal is not output to the corresponding switch unit. Turns on the third switch. That is, the third switch operates in reverse logic with respect to the ON command signal from the control unit, as compared with the first and second switches. The abnormality determining unit determines whether each switch unit is abnormal based on the electrical state of the other end of each third switch.

  If at least one of the first switch and the second switch in a certain switch unit has a short circuit failure, the third instruction is not transmitted to the switch unit via the short circuit failure switch even if the ON command signal is not output to the switch unit. There is a possibility that the other end of the switch is in an electrically abnormal state (a state different from the normal state). Therefore, according to the battery unit configured as described above, it is possible to detect a short circuit failure of the switch unit (that is, a short circuit failure of at least one of the first switch and the second switch).

  More specifically, the detection of the short circuit failure by the abnormality determination unit may be performed as follows. That is, the abnormality determination unit determines whether or not there is a short-circuit fault in the second switch based on the electrical state of the other end of each third switch when the ON command signal is not output from the control unit. May be.

  If the second switch connected to one of the cell assemblies has a short-circuit failure, the other end of the third switch is connected to the other end of the third switch even if no ON command signal is output from the control unit to the cell assembly. The voltage of the cell assembly appears directly or indirectly through the second switch and the third switch. Therefore, it is possible to detect a short-circuit failure of the second switch based on the electrical state (for example, voltage) of the other end of the third switch.

  More specifically, the detection of the short circuit failure by the abnormality determination unit may be performed as follows. That is, a constant voltage generation unit and a constant voltage application unit may be provided for short circuit failure detection. The constant voltage generator can apply a constant voltage having a predetermined voltage value to the other end of each first switch. The constant voltage application unit applies a constant voltage from the constant voltage generation unit to the other end of each first switch at a predetermined determination timing while the ON command signal is not output from the control unit. Then, the abnormality determination unit determines whether or not there is a short-circuit failure in the first switch based on the electrical state of the other end of each third switch when the constant voltage is applied by the constant voltage application unit. It may be.

  If the first switch connected to any one of the cell assemblies has a short circuit failure, the other end of the third switch is not connected to the other end of the third switch even if an ON command signal is not output from the control unit to the cell assembly. The constant voltage from the voltage generation unit appears directly or indirectly through the constant voltage application unit, the first switch, and the third switch. Therefore, it is possible to detect a short circuit failure of the first switch based on the electrical state (for example, voltage) of the other end of the third switch.

  The simultaneous on blocking unit may forcibly turn off all the switch units when an on command signal is output from the control unit to the plurality of switch units. According to such a configuration, since all the cell assemblies are forcibly disconnected from the positive electrode connection terminal, current wraparound between the plurality of cell assemblies is suppressed. Therefore, it is possible to improve the reliability of the battery unit with respect to occurrence of an abnormality of the ON command signal due to abnormality of the control unit.

  Alternatively, the simultaneous ON blocking unit outputs an ON command signal from the control unit to another switch unit while the ON command signal is output from the control unit to any one of the switch units. The transmission of the ON command signal to one switch unit to which the ON command signal has been output may be permitted as it is, and the transmission of the ON command signal to the other switch units may be blocked. Hereinafter, such a configuration is also referred to as an on-continuable configuration.

  In the case of the on-continuable configuration as described above, not all the switch units are forcibly turned off, but the switch units that have already been turned on continue to be in the on state, and the switch to which the on command signal is output later The switch unit is not turned on by invalidating the on command signal. Therefore, it is possible to continue the battery power supply (power supply to the outside through each connection terminal) via the switch part that has already been turned on, while suppressing the sneak current between the cell assemblies. can do.

  The battery unit having the above-described ON continuation configuration may be realized by providing a D-type flip-flop between the control unit and each switch unit. In this D-type flip-flop, an ON command signal for each switch unit output from the control unit is input as an input signal, and each output signal for each input signal is output to a corresponding switch unit. Further, the logical sum of each ON command signal from the control unit to each switch unit is input as a clock signal and a clear signal.

  Even if an ON command signal for a certain switch unit is output by this D-type flip-flop and an ON-command signal for another switch unit is output when the switch unit is ON, it is input to the D-type flip-flop. Since the clock signal to be output does not change, the ON command signal output later is not reflected as the output signal.

  Therefore, by transmitting the ON command signal from the control unit to each switch unit via the D-type flip-flop having the above-described configuration, the battery unit having the ON continuation configuration can be configured with a simple circuit. For this reason, the internal circuit of the battery unit can be reduced in size, and as a result, the entire battery unit can be reduced in size and cost.

  Each cell assembly may include a monitoring unit, and the battery unit may forcibly turn off a switch unit corresponding to the cell assembly having the monitoring unit when any monitoring unit detects an abnormality. . Specifically, each monitoring unit monitors the state of the corresponding assembled battery, and when an abnormality of the assembled battery is detected, outputs an error signal indicating that fact. When the error signal is output from the monitoring unit of any cell assembly, the forced-off unit forcibly turns off at least the switch unit corresponding to the cell assembly regardless of the presence or absence of the ON command signal.

  According to the battery unit configured in this manner, even when an abnormality occurs in the cell assembly itself, each switch unit is forcibly turned off, preventing parallel connection between the cell assemblies and each cell assembly. The positive connection terminal is disconnected. Therefore, even if an abnormality occurs in a certain cell assembly, the abnormality can be prevented from affecting other cell assemblies and the outside of the battery unit, and the reliability of the battery unit can be further improved.

It is a block diagram showing schematic structure of the electric tool of 1st Embodiment. It is a circuit diagram showing the electric constitution of the battery unit of 1st Embodiment. It is a flowchart of a cell block switching process. It is a flowchart of a self-check process. It is a block diagram showing schematic structure of the charging system of 2nd Embodiment. It is a circuit diagram showing the electric constitution of the battery unit of 2nd Embodiment.

  Preferred embodiments of the present invention will be described below with reference to the drawings. In addition, this invention is not limited to the specific means, structure, etc. which are shown by the following embodiment, In the range which does not deviate from the summary of this invention, various forms can be taken. For example, a part of the configuration of the following embodiment is replaced with a known configuration having a similar function, added to or replaced with the configuration of another embodiment, or omitted as long as the problem can be solved. May be. Moreover, you may comprise combining the following several embodiment suitably.

[First Embodiment]
(1) Structure of electric tool The electric tool of this embodiment is provided with the battery unit 1 and the tool main body 100, as shown in FIG. The battery unit 1 can be attached to and detached from the tool main body 100. When the battery unit 1 is mounted on the tool main body 100, both are physically and electrically connected. FIG. 1 shows a state where both are connected.

  The battery unit 1 includes a plurality (N) of cell assemblies 10, 20,..., A microcomputer (hereinafter simply referred to as “microcomputer”) 2, a positive electrode connection terminal 91, a negative electrode connection terminal 92, A first communication terminal 93 and a second communication terminal 94 are provided. The plurality of cell assemblies 10, 20,..., 30 all have the same configuration, and include cell blocks 11, 21,.

  That is, the first cell assembly 10 includes a cell block 11. The cell block 11 includes a plurality of secondary battery cells 16 connected in series. In addition, although the secondary battery cell of this embodiment is a lithium ion secondary battery, this is an example to the last and may be another kind of secondary battery cell. The positive electrode of the cell block 11 is connected to the positive electrode connection terminal 91 via the hardware interlock circuit A. The negative electrode of the cell block 11 is connected to the negative electrode connection terminal 92.

  Each of the other cell assemblies (second cell assembly 20,..., Nth cell assembly 30) has the same configuration as the first cell assembly 10. That is, the second cell assembly 20 includes a cell block 21 in which a plurality of secondary battery cells 26 are connected in series. The cell block 21 also has a positive electrode connected to the positive electrode connection terminal 91 via the hardware interlock circuit A and a negative electrode connected to the negative electrode connection terminal 92. The Nth cell assembly 30 also includes a cell block 31 in which a plurality of secondary battery cells 36 are connected in series. The cell block 31 also has a positive electrode connected to the positive electrode connection terminal 91 via the hardware interlock circuit A and a negative electrode connected to the negative electrode connection terminal 92.

  That is, the cell assemblies 10, 20,..., 30 are connected in parallel via the hardware interlock circuit A. The hardware interlock circuit A is a circuit for preventing a plurality of cell assemblies from being directly connected in parallel at the same time, and the detailed configuration and operation thereof will be described later.

  .., 31 (hereinafter also referred to as “cell block voltage”) have the same value in terms of specifications. However, in this embodiment, as will be described later, control is performed so that a plurality of cell assemblies are not directly connected in parallel at the same time. That is, in both discharge and charge, only any one cell assembly is permitted to be charged / discharged, and the cell assemblies permitted to be charged / discharged are sequentially switched. Therefore, in practice, each cell block voltage varies.

  Each of the cell blocks 11, 21,..., 31 can be charged by a charger 120 (see FIG. 5, details will be described later). In the following description, the voltage of the cell assembly means the voltage of the cell block that the cell assembly has, and the positive electrode of the cell assembly means the positive electrode of the cell block that the cell assembly has.

  The microcomputer 2 includes an I / O and a timer (not shown) in addition to the CPU 3a and the memory 3b. The positive electrode connection terminal 91 is connected to a positive electrode connection terminal to be mounted when the battery unit 1 is mounted on the tool body 100 or a charger 120 (see FIG. 5) described later. FIG. 1 shows a state where the positive electrode connection terminal 91 of the battery unit 1 and the positive electrode connection terminal 101 of the tool body 100 are connected.

  The negative electrode connection terminal 92 is connected to the negative electrode connection terminal to be mounted when the battery unit 1 is mounted on the tool body 100 or a charger 120 (see FIG. 5) described later. FIG. 1 shows a state where the negative electrode connection terminal 92 of the battery unit 1 and the negative electrode connection terminal 102 of the tool body 100 are connected.

  The first communication terminal 93 is connected to the communication terminal 103 of the tool body 100 when the battery unit 1 is attached to the tool body 100. The first communication terminal 93 of the battery unit 1 is connected to the microcomputer 2. The microcomputer 2 can perform various types of data communication with the microcomputer 111 of the tool body 100 via the first communication terminal 93 and the communication terminal 103 of the tool body 100.

  The second communication terminal 94 is connected to the communication terminal 124 of the charger 120 when the battery unit 1 is attached to the charger 120 (see FIG. 5). The second communication terminal 94 of the battery unit 1 is connected to the microcomputer 2. The microcomputer 2 can perform various data communications with the microcomputer 131 of the charger 120 via the second communication terminal 94 and the communication terminal 124 of the charger 120.

  Although not shown, the battery unit 1 includes a regulator that generates a constant voltage Vcc having a predetermined voltage value (for example, 5 V). This regulator generates a constant voltage Vcc from voltages input from the cell assemblies 10, 20,... That is, a diode is prepared for each cell assembly 10, 20,..., 30 and the anode of the corresponding diode is connected to the positive electrode of each cell assembly 10, 20,. . The cathodes of the diodes are commonly connected to the input terminal of the regulator. Each circuit in the battery unit 1, such as the microcomputer 2 and a self-diagnosis voltage supply circuit 3 (see FIG. 2) described later, operates using the constant voltage Vcc as a power source.

  As shown in FIG. 1, the tool body 100 includes a microcomputer 111, a motor 112, a drive circuit 113, a trigger switch 114, a positive electrode connection terminal 101, a negative electrode connection terminal 102, and a communication terminal 103. .

  The positive electrode connection terminal 101 is connected to one end of the motor 112 via the trigger switch 114. The negative electrode connection terminal 102 is connected to the other end of the motor 112 via the drive circuit 113. The motor 112 of this embodiment is a DC motor with a brush.

  The trigger switch 114 is turned on / off when the user operates a trigger (not shown) provided in the tool body 100. That is, it is turned on when the user pulls the trigger and turned off when the user releases the trigger. Information on ON / OFF of the trigger switch 114 is input to the microcomputer 111.

  The microcomputer 111 includes a CPU, a memory, and the like (not shown), and realizes various functions by the CPU executing various programs stored in the memory. When the trigger switch 114 is turned on, the microcomputer 111 starts energization from the battery unit 1 to the motor 112 by turning on the drive switch in the drive circuit 113, thereby operating the motor 112. When the trigger switch 114 is turned off, the microcomputer 111 stops energization from the battery unit 1 to the motor 112 by turning off the drive switch in the drive circuit 113.

  If an abnormal signal is input from the battery unit 1 via the communication terminal 103 while the battery unit 1 is energized to the motor 112, the microcomputer 111 forcibly stops energization of the motor 112.

  Although not shown, the tool body 100 includes a regulator that generates a constant voltage having a predetermined voltage value. This regulator generates a constant voltage by stepping down the voltage supplied from the battery unit 1 when the battery unit 1 is mounted on the tool body 100. The microcomputer 111 of the tool body 100 operates using this constant voltage as a power source.

(2) Configuration of Battery Unit 1 A more specific configuration of the battery unit 1 will be described with reference to FIG. As shown in FIG. 2, the battery unit 1 includes a plurality of (N) switch circuits 40, 50,..., 60 provided for each cell assembly 10, 20,. A diagnostic voltage supply circuit 3 and a NOR circuit 5 are provided. A plurality (N) of switch circuits 40, 50,..., 60 constitute the hardware interlock circuit A shown in FIG.

  The first cell assembly 10 includes a cell monitoring circuit 12 for monitoring the cell block 11 in the first cell assembly 10. The cell monitoring circuit 12 is an integrated circuit (IC) for monitoring the cell block 11. The cell monitoring circuit 12 has a function of detecting the voltage of the cell block 11 and the voltage (cell voltage) of each cell 16 and outputting the detection result from the data terminal to the microcomputer 2. In addition, the cell monitoring circuit 12 monitors the cell voltage of each cell 16 and when any one of the cell blocks 11 is in an overvoltage state, such as when the cell voltage is overvoltage, a cell error signal (High (H ) Level signal) is output from the error terminal to the NOR circuit 5. When no error has occurred in the cell block 11, the error terminal output is at the Low (L) level.

  Each of the other cell assemblies 20,..., 30 also includes a cell monitoring circuit having the same configuration and function as the first cell assembly 10. That is, the second cell assembly 20 includes a cell monitoring circuit 22 for monitoring the cell block 21, and the Nth cell assembly 30 includes a cell monitoring circuit 32 for monitoring the cell block 31.

  Of the plurality of switch circuits 40, 50,..., 60, the first switch circuit 40 is provided for the first cell assembly 10. That is, the first switch circuit 40 is provided between the positive electrode of the first cell assembly 10 and the positive electrode connection terminal 91.

  The first switch circuit 40 includes a high-side switch 41, a low-side switch 42, a self-diagnosis switch 43, an AND circuit 44, two inverters 45 and 46, and a diode D1.

  The high side switch 41 has one end connected to the positive electrode connection terminal 91 and the other end connected to one end of the low side switch 42 and one end of the self-diagnosis switch 43. The other end of the low side switch 42 is connected to the positive electrode of the first cell assembly 10 (the positive electrode of the cell block 11). That is, the cell block 11 of the first cell assembly 10 is connected to the positive electrode connection terminal 91 via the low side switch 42 and the high side switch 41 connected in series. Hereinafter, the high-side switch 41 and the low-side switch 42 are also collectively referred to as a “switch unit”.

  The switch unit is turned on / off by an output signal from the AND circuit 44. Specifically, when the output signal from the AND circuit 44 is L level, the switch unit is turned off, and when the output signal from the AND circuit 44 is H level, the switch unit is turned on.

  One permission input inverter 45 of the two inverters 45, 46 logically inverts the first charge / discharge permission signal input from the microcomputer 2 and outputs it to the inverting input terminal of the AND circuit 44. The other self-diagnosis inverter 46 logically inverts the output signal from the AND circuit 44 and outputs it to the self-diagnosis switch 43.

  The self-diagnosis switch 43 has one end connected to a connection point between the high-side switch 41 and the low-side switch 42 and the other end connected to the self-diagnosis error signal input terminal of the microcomputer 2 and the NOR circuit 5 via the diode D1. . The self-diagnosis switch 43 is turned off when the output signal from the AND circuit 44 is at the H level, and is turned on when the output signal from the AND circuit 44 is at the L level.

  Note that the two switches 41 and 42 and the self-diagnosis switch 43 constituting the switch unit are actually semiconductor switches, and more specifically, MOSFETs in the present embodiment.

  The high side switch 41 and the low side switch 42 constituting the switch unit are actually both P-channel MOSFETs. The drains of these two MOSFETs are connected to each other and to the self-diagnosis switch 43. A circuit for inverting the output signal from the AND circuit 44 is connected to the gates of these two MOSFETs. Thus, these two MOSFETs are turned off when the output signal from the AND circuit 44 is at L level, and turned on when the output signal from the AND circuit 44 is at H level.

  The AND circuit 44 receives an individual charge / discharge permission signal for each of the switch circuits 40, 50,..., 60 output from the microcomputer 2 and an output signal of the NOR circuit 5. However, each charge / discharge permission signal is input to the inverting input terminal of the AND circuit 44. In addition, among the charge / discharge permission signals, the # 1 charge / discharge permission signal corresponding to the first switch circuit 40 (corresponding to the first cell assembly 10) is logically inverted by the permission input inverter 45 to be AND circuit 44. Is input to the inverting input terminal.

  AND circuit 44 further logically inverts the logic inversion signal of # 1 charge / discharge permission signal input via permission input inverter 45, and each charge / discharge permission signal (#) other than # 1 charge / discharge permission signal. 2 charge / discharge permission signal,..., #N charge / discharge permission signal) are also logically inverted, and the logical product of each logically inverted input signal and the output signal from the NOR circuit 5 is calculated.

  The second switch circuit 50 is provided for the second cell assembly 20. That is, the second switch circuit 50 is provided between the positive electrode of the second cell assembly 20 and the positive electrode connection terminal 91.

  The second switch circuit 50 has the same configuration as the first switch circuit 40 except for a part (connection position of the permission input inverter 55). That is, the second switch circuit 50 includes a high-side switch 51, a low-side switch 52, a self-diagnosis switch 53, an AND circuit 54, two inverters 55 and 56, and a diode D2.

  In the second switch circuit 50, the # 1 charge / discharge permission signal corresponding to the first cell assembly 10 among the charge / discharge permission signals from the microcomputer 2 is an inverter. Is input to the inverting input terminal of the AND circuit 54 as it is.

  In the second switch circuit 50, the # 2 charge / discharge permission signal corresponding to the second switch circuit 50 (corresponding to the second cell assembly 20) is input to the permission input inverter 55, and this # 2 charge / discharge permission is received. The signal is logically inverted by the permission input inverter 55 and input to the inverting input terminal of the AND circuit 54.

  The AND circuit 54 further inverts the logic inversion signal of the # 2 charge / discharge permission signal input via the permission input inverter 55 and also performs other charge / discharge permission signals other than the # 2 charge / discharge permission signal. Each of these is logically inverted, and the logical product of each logically inverted input signal and the output signal from the NOR circuit 5 is calculated.

  The Nth switch circuit 60 also has the same configuration as the first switch circuit 40 except for a part (connection position of the permission input inverter 65). That is, the Nth switch circuit 60 includes a high side switch 61, a low side switch 62, a self-diagnosis switch 63, an AND circuit 64, two inverters 65 and 66, and a diode D3.

  In the N-th switch circuit 60, other charge / discharge permission signals other than the N-th charge / discharge permission signal are included in the N-th switch circuit 60. The signal is directly input to the inverting input terminal of the AND circuit 64 without going through the inverter.

  In the Nth switch circuit 60, the #N charge / discharge permission signal corresponding to the Nth switch circuit 60 (corresponding to the Nth cell assembly 30) is input to the permission input inverter 65. The signal is logically inverted by the permission input inverter 65 and input to the inverting input terminal of the AND circuit 64.

  The AND circuit 64 further inverts the logic inversion signal of the #N charge / discharge permission signal input via the permission input inverter 65 and also performs other charge / discharge permission signals other than the #N charge / discharge permission signal. Each of these is logically inverted, and the logical product of each logically inverted input signal and the output signal from the NOR circuit 5 is calculated.

  The self-diagnosis voltage supply circuit 3 includes a resistor R0, a diode D0, and a constant voltage supply switch 4. The resistor R0 has one end connected to the positive electrode connection terminal 91 and the other end connected to the cathode of the diode D0. The anode of the diode D0 is connected to one end of the constant voltage supply switch 4. A constant voltage Vcc from a regulator (not shown) is applied to the other end of the constant voltage supply switch 4.

  The constant voltage supply switch 4 is turned on / off by a self-check signal from the microcomputer 2. That is, the constant voltage supply switch 4 is turned off while the self-check signal from the microcomputer 2 to the constant voltage supply switch 4 is at L level, and the constant voltage supply switch 4 is turned on when the self-check signal becomes H level. When the constant voltage supply switch 4 is turned on, the constant voltage Vcc is supplied to the switch circuits 40, 50,.

  The microcomputer 2 selectively changes any one of the charge / discharge permission signals to the switch circuits 40, 50,..., 60 to the H level, thereby changing the charge / discharge permission signal to the H level. The switch part of the corresponding switch circuit is turned on to connect the positive electrode of the corresponding cell assembly to the positive electrode connection terminal 91. That is, the microcomputer 2 does not simultaneously turn on the switch portions of the plurality of different switch circuits (so that the plurality of cell assemblies are not directly connected in parallel to each other), and the voltage of any one cell assembly is applied to the positive electrode connection terminal 91. The switch circuits 40, 50,..., 60 are controlled so as to be applied and output.

  For example, in order to allow the first cell assembly 10 to charge / discharge the cell block 11, the microcomputer 2 sets the # 1 charge / discharge permission signal to H level and all other charge / discharge permission signals to L level. . In this case, in the first switch circuit 40, the # 1 charge / discharge permission signal is logically inverted to the L level by the permission input inverter 45 and input to the inverting input terminal of the AND circuit 44, and on the input side in the AND circuit 44 Further, the logic is inverted. The other charge / discharge permission signals are input to the inverting input terminal of the AND circuit 44 as they are (while being at the L level), and are logically inverted on the input side in the AND circuit 44.

  The output signal from the NOR circuit 5 is also input to the AND circuit 44. If the battery unit 1 is normal, each input signal to the NOR circuit 5 is at L level. Becomes H level. That is, the AND circuit 44 normally receives an H level signal from the NOR circuit 5 (unless there is an abnormality).

  Therefore, the output signal from the AND circuit 44 becomes H level, the switch section (the high-side switch 41 and the low-side switch 42) is turned on, and the self-diagnosis switch 43 is turned off. As a result, the cell block voltage of the first cell assembly 10 is applied to the positive electrode connection terminal 91 via the switch unit, so that the cell block voltage can be supplied to the outside as the voltage of the battery unit 1 (battery voltage). It becomes.

  On the other hand, for each of the switch circuits 50,..., 60 other than the first switch circuit 40, the switch part is turned off, and the corresponding cell assemblies 20,. 91 is cut off.

  For example, in the second switch circuit 50, the # 1 charge / discharge permission signal is input to the inverting input terminal of the AND circuit 54 while maintaining the H level, and is logically inverted to the L level on the input side in the AND circuit 54. Also, since the # 2 charge / discharge permission signal corresponding to the second switch circuit 50 is at the L level, the L level # 2 charge / discharge permission signal is logically inverted to the H level by the permission input inverter 55 and the AND circuit. 54 is input to the inverting input terminal 54 and logically inverted to the L level again on the input side in the AND circuit 54. For this reason, the output of the AND circuit 54 becomes L level, and therefore the switch sections (the high side switch 51 and the low side switch 52) are turned off.

  The microcomputer 2 sequentially turns on the switch portions of the switch circuits 40, 50,..., 60 from the first switch circuit 40 at the time of discharging and charging, so that the cell assemblies 10, 20, ..., 30 are sequentially charged and discharged (connected to the positive electrode connection terminal 91) one by one.

  For example, at the time of discharging, the microcomputer 2 first turns on the switch portion of the first switch circuit 40 by setting the # 1 charge / discharge permission signal to the H level to permit the discharge from the first cell assembly 10. Then, when a switching condition for switching the cell assembly to which discharge is permitted (for example, a discharge completion state is caused by a decrease in the cell block voltage), the first cell is set by setting the # 1 charge / discharge permission signal to L level. The discharge from the assembly 10 is stopped. Then, by setting the # 2 charge / discharge permission signal to the H level, the switch part of the second switch circuit 50 is turned on, and the discharge from the second cell assembly 20 is permitted. In this way, the microcomputer 2 sequentially switches the cell assemblies to be discharged.

  Further, for example, during charging by the charger 120 (see FIG. 5), the microcomputer 2 first turns on the switch section of the first switch circuit 40 by setting the # 1 charge / discharge permission signal to the H level, and the first switch circuit 40 is turned on. The charging of the cell assembly 10 is permitted. When the switching condition for switching the cell assembly to be charged (for example, when the cell block voltage is fully charged, the charging is completed), the # 1 charge / discharge permission signal is set to the L level. As a result, the charging of the first cell assembly 10 is stopped. Then, by setting the # 2 charge / discharge permission signal to the H level, the switch portion of the second switch circuit 50 is turned on, and the charging of the second cell assembly 20 is permitted. In this way, the microcomputer 2 sequentially switches the cell assemblies subject to charge permission even during charging.

  Further, the microcomputer 2 determines whether or not each switch part of each switch circuit 40, 50,..., 60 has a short circuit failure at a predetermined timing when all charge / discharge permission signals are at the L level. Make a diagnosis.

  Specifically, the microcomputer 2 determines the voltage of the self-diagnosis voltage supply circuit 3 at the timing of switching the cell assembly that permits charging / discharging, for example, when all the charging / discharging permission signals become L level during the switching process. The constant voltage supply switch 4 is turned on for a predetermined time by setting the self-check signal to the voltage supply switch 4 to the H level. Then, during the ON period, the presence / absence of a short circuit failure in each switch unit is determined (self-diagnosis) based on a signal input from each switch circuit 40, 50,..., 60 to the self-diagnosis error signal input terminal. .

  If all the switch sections are normal, when all the charge / discharge permission signals are at the L level, the output signals of the AND circuits 44, 54,. Is also turned off. Therefore, although the self-diagnosis switches 43, 53,..., 63 are all turned on, the diodes D1, D2,..., D3 of the switch circuits 40, 50,. All signals inputted to the self-diagnosis error signal input terminal of the microcomputer become L level. In this case, the microcomputer 2 recognizes that each switch unit is normal.

  On the other hand, when a short circuit failure occurs in any of the switch units, an H level signal (self-diagnosis error signal) is input to the self-diagnosis error signal input terminal of the microcomputer 2. That is, for example, when the high-side switch 41 among the two switches 41 and 42 constituting the switch unit of the first switch circuit 40 is short-circuited, the constant voltage Vcc from the self-diagnosis voltage supply circuit 3 is short-circuited. The high-side switch 41, the self-diagnosis switch 43, and the diode D1 are input to the microcomputer 2 as an H-level self-diagnosis error signal.

  Further, for example, when the low-side switch 42 in the first switch circuit 40 is short-circuited, the cell block voltage of the first cell assembly 10 is passed through the low-side switch 42, the self-diagnosis switch 43, and the diode D1 that are short-circuited. , And is input to the microcomputer 2 as an H level self-diagnosis error signal.

  When the microcomputer 2 receives the self-diagnosis error signal, the microcomputer 2 determines that any one of the switch parts is short-circuited. In addition, the self-diagnosis error signal from each switch circuit 40, 50, ..., 60 is input not only to the microcomputer 2 but also to the NOR circuit 5. For this reason, when an H level self-diagnosis error signal is output from any of the switch circuits, the output signal of the NOR circuit 5 becomes L level. The L level output signal from the NOR circuit 5 is input to the error signal input terminal of the microcomputer 2 as an error signal, and the microcomputer 2 can detect the occurrence of an abnormality also by this error signal.

  In the NOR circuit 5, when each switch part is normal and each cell assembly 10, 20,..., 30 is also normal, all the input signals are L level, and therefore the output signal is H level. . This H level output signal is input to the error signal input terminal of the microcomputer 2 and is also input to the AND circuits 44, 54,. From this H level output signal, the microcomputer 2 recognizes that the battery unit 1 is normal.

  On the other hand, an abnormality occurs in one of the cell assemblies, and an H level cell error signal is input to the NOR circuit 5 from the cell monitoring circuit, or a short circuit fault occurs in any one of the switch units, and this corresponds to the self-diagnosis. When an H level self-diagnosis error signal is input to the NOR circuit 5 from the switch circuit, the output of the NOR circuit 5 becomes L level.

  This L level output signal is input to the error signal input terminal of the microcomputer 2 as an error signal, whereby the microcomputer 2 recognizes that one of the cell assemblies is abnormal or a short circuit failure of the switch unit has occurred.

  Further, when an L level error signal is output from the NOR circuit 5, the error signal is also input to each AND circuit 44, 54,..., 64 of each switch circuit 40, 50,. The For this reason, the output signals of the AND circuits 44, 54,..., 64 are forcibly set to the L level, thereby forcibly turning off each switch unit.

  By the way, as described above, the microcomputer 2 outputs a charge / discharge permission signal to any one of the switch circuits so that a plurality of cell assemblies are not connected in parallel at the same time, thereby turning on the switch portion of the switch circuit. Charge / discharge is allowed only for the cell assembly corresponding to the circuit.

  However, there is a possibility that a plurality of charge / discharge permission signals from the microcomputer 2 become H level for some reason such as abnormality of the microcomputer 2. On the other hand, the battery unit 1 according to the present embodiment has an interlock function for preventing a plurality of switch units from being turned on at the same time even if a plurality of charge / discharge permission signals become H level from the microcomputer 2 due to some abnormality. Is provided. Specifically, in the present embodiment, when a plurality of charge / discharge permission signals become H level, charge / discharge from all cell assemblies is prohibited. This interlock function is realized by a hardware interlock circuit A comprising the switch circuits 40, 50,.

  That is, for example, it is assumed that the microcomputer 2 sets the # 1 charge / discharge permission signal to the H level in order to permit the charge / discharge of the first cell assembly 10. At this time, the output of only the AND circuit 44 of the first switch 40 becomes the H level, and the outputs of the AND circuits 54,..., 64 of the other switches 50,. . Therefore, only the switch part (the high side switch 41 and the low side switch 42) of the first switch is turned on, and only the first cell assembly 10 can be charged / discharged.

  From this state, it is assumed that, for example, an abnormality occurs in the microcomputer 2 and not only the # 1 charge / discharge permission signal but also the # 2 charge / discharge permission signal becomes H level. At this time, since the H level # 2 charge / discharge permission signal is input to the AND circuit 44 of the first switch circuit 40, the state of the # 1 charge / discharge permission signal is set by the H level # 2 charge / discharge permission signal. Regardless, the output signal of the AND circuit 44 is forced to L level. Therefore, both the high side switch 41 and the low side switch 42 in the first switch circuit 40 are forcibly turned off.

  The AND circuits 54,..., 64 of the switch circuits 50,..., 60 other than the first switch circuit 40 are all output when the # 1 charge / discharge signal is already at the H level. The signal is at L level. Therefore, even if the # 2 charge / discharge permission signal becomes H level, the output signal remains at L level, so that the switch parts of the other switch circuits 50,..., 60 remain off. is there.

  As described above, the battery unit 1 of the present embodiment has an interlock function, so that if the charge / discharge permission signal is erroneously output from the microcomputer 2 (that is, the microcomputer 2 erroneously outputs two or more cell blocks). (When charging / discharging is simultaneously performed), all the switch units are turned off, and charging / discharging of all the cell blocks is prohibited.

  In addition to the sequential switching of the cell assemblies subject to discharge and the self-diagnosis function, the microcomputer 2 states the cell assemblies 10, 20,..., 30 from the cell monitoring circuits 12, 22,. A function that acquires (cell block voltage, voltage of each cell, etc.) and monitors these states, or when an error signal is input from the NOR circuit 5 or a self-diagnosis error signal is input from any switch circuit A function of performing a protection operation of the device, a function of performing various data communications with the tool body 100, and a second communication with the microcomputer 131 (see FIG. 5) of the charger 120 when the charger 120 is mounted. A function of performing various data communications via the terminal 94 is also provided. Examples of the protective operation include setting all charge / discharge permission signals to the L level, and outputting abnormal signals from the first communication terminal 93 and the second communication terminal 94. Various functions including the above-described functions of the microcomputer 2 are realized mainly by the CPU 3a executing various programs stored in the memory 3b.

  Note that the function of the microcomputer 2 is not necessarily realized by a microcomputer, and can be realized in various forms such as an IC formed of various logic circuits. The same applies to the microcomputer 111 of the tool body 100 and the microcomputer 131 of the charger 120 described later.

(3) Explanation of Cell Block Switching Process Among various processes executed by the microcomputer 2 of the battery unit 1, a cell block switching process including a self-diagnosis function for controlling switching of a discharge-permitted cell assembly will be described with reference to FIG. I will explain. Note that the cell block switching process includes a process for the self-diagnosis function (self-check process).

  In the microcomputer 2 of the battery unit 1, when the operation starts, the CPU 3a reads the program for the cell block switching process of FIG. 3 from the memory 3b and repeatedly executes it. When starting the cell block switching process of FIG. 3, the CPU 3a sets a cell block designation variable n to 1 in S110. In S120, a self-check process is executed. The details of the self-check process are as shown in FIG.

  That is, in S121, all charge / discharge permission signals are turned off (that is, set to L level). In S122, a self-check signal is output to the constant voltage supply switch 4 of the self-diagnosis voltage supply circuit 3, thereby turning on the constant voltage supply switch 4. In S123, it is determined whether there is any error input. Specifically, at least one of an error signal (L level signal) from the NOR circuit 5 and a self-diagnosis error signal (H level signal) from each switch circuit 40, 50,. Judge whether or not.

  If there is no error input, the output of the self-check signal is stopped in S124. In S125, normal determination (determination that the self-check (self-diagnosis) result is normal) is performed, and the process proceeds to the next S130. If there is an error input in S123, the output of the self-check signal is stopped in S126, an abnormality determination (determination that the self-check (self-diagnosis) result is abnormal) is performed in S127, and the process proceeds to the next S130. .

  Returning to FIG. 3, in S130, it is determined whether or not the self-check result in the self-check process in S120 is normal. If the self-check result is abnormal, charging / discharging of all the cell blocks is prohibited in S200, and this cell block switching process is terminated. That is, in S200, all charge / discharge permission signals are turned off (L level).

  If the result of the self-check is normal in S130, it is determined in S140 whether there is any error input. The determination process in S140 is the same as S123 in FIG. If there is any error input, the process proceeds to S200, but if there is no error input, the process proceeds to S150.

  In S150, the #n charge / discharge permission signal is turned on (H level). For example, when n = 1, the # 1 charge / discharge permission signal corresponding to the first cell assembly 10 is turned on, so that the cell block of the first cell assembly 10 can be charged / discharged.

  In S160, it is determined whether or not a cell block switching condition for which charging / discharging is permitted is satisfied. That is, it is determined whether or not the voltage of the n-th cell assembly is in a charging completion state during charging, and whether or not the voltage of the n-th cell assembly is in a discharging completion state except during charging.

  If the cell block switching condition is not satisfied, the process returns to S140. If the cell block switching condition is satisfied, the charge / discharge of the cell block of the nth cell assembly is inhibited by turning off the #n charge / discharge permission signal (L level) in S170. At this time, the cell blocks of all the cell assemblies are temporarily prohibited from being charged / discharged.

  In S180, it is determined whether the cell block designation variable n matches the total number N of cell assemblies. If the cell block designation variable n does not match the total number N of cell assemblies, the cell block designation variable n is incremented by 1 in S190, and the process returns to S120. If the cell block designation variable n matches the total number N of cell assemblies in S180, this cell block switching process is terminated.

(4) Effects of First Embodiment As described above, in the battery unit 1 of the present embodiment, only the switch part (high side switch and low side switch) of any one switch circuit is charged / discharged from the microcomputer 2. This is selectively turned on by the permission signal, so that only one cell assembly whose switch is turned on can be charged / discharged.

  Based on such a configuration, a hardware interlock function is further provided. If charge / discharge permission signals to a plurality of switch circuits are simultaneously turned on due to abnormality of the microcomputer 2, any charge / discharge is performed. The permission signal is also invalidated and all cell blocks are prohibited from being charged / discharged. That is, the hardware interlock function has a configuration in which a plurality of switch units cannot be turned on simultaneously (in other words, a configuration in which a plurality of cell assemblies are not connected in parallel). Therefore, the reliability of the battery unit 1 is improved with respect to the abnormality (multiple simultaneous ON) of the charge / discharge permission signal caused by the abnormality of the microcomputer 2 or the like.

  Therefore, according to the battery unit 1 of the present embodiment, the power loss from each cell assembly is compared to the conventional method of suppressing the current wrapping between the cell assemblies by connecting the diode to the charge / discharge path. Can be suppressed. Further, current wraparound between cell assemblies (and thus unintentional charging due to the sneak current) can be suppressed while suppressing power loss from each cell assembly.

  In addition, current wraparound between cell assemblies is suppressed by using a switch (high-side switch and low-side switch) with a voltage drop (ON resistance) smaller than that of the diode, so that the conventional circuit configuration using a diode is used. In comparison, it is possible to reduce the heat generation, suppress the reduction in power supplied to the load, and reduce the size of the entire unit.

  Moreover, each switch part of each switch circuit 40, 50, ..., 60 is comprised by two switches (a high side switch and a low side switch) connected in series. For this reason, even if one of the two switches is short-circuited, it is possible to suppress current wraparound from other cell assemblies as long as the other is normal. That is, current wraparound (unintended charging) between the cell assemblies can be more effectively suppressed.

  In particular, in the present embodiment, semiconductor switches (MOSFETs) are used as the high side switch and the low side switch. The MOSFET has a parasitic diode between the source and the drain. For this reason, if the switch unit is composed of only one MOSFET, even if it is turned off, current wraparound may occur via the parasitic diode. On the other hand, in this embodiment, two MOSFETs are connected in series with a drain common, and both parasitic diodes are connected in series in opposite directions. Therefore, bidirectional current is cut off in the switch section while the two MOSFETs are turned off. That is, the influence of the parasitic diode can be suppressed by connecting the two MOSFETs in series to form the switch unit.

  Further, by providing the switch circuits 40, 50,..., 60 with self-diagnosis switches 43, 53,. (That is, a short circuit failure of at least one of the high-side switch and the low-side switch) can be detected.

  Specifically, for a short-circuit failure in the low-side switch, the voltage of the cell block connected to the low-side switch is output from the self-diagnostic switch to the microcomputer 2 via the diode as an H-level self-diagnosis error signal. It can be detected. On the other hand, a short circuit failure of the high side switch can be detected by applying a constant voltage Vcc from the self-diagnosis voltage supply circuit 3.

  In addition, each cell assembly 10, 20,..., 30 includes cell monitoring circuits 12, 22,. When an abnormality is detected in any of the cell monitoring circuits, an L level error signal is input from the NOR circuit 5 to the microcomputer 2 and also to each AND circuit in each switch circuit. As a result, the output signal of each AND circuit is forcibly set to L level, and each switch section is forcibly turned off.

  Therefore, even when an abnormality occurs in the cell assembly itself, each switch unit is forcibly turned off, preventing parallel connection between the cell assemblies and blocking each cell assembly and the positive electrode connection terminal 91 from each other. Therefore, even if an abnormality occurs in a certain cell assembly, it is possible to suppress the abnormality from affecting other cell assemblies and the outside of the battery unit 1, and the reliability of the battery unit 1 can be further improved.

  Note that it is not essential to forcibly turn off all the switch sections when an abnormality occurs in a cell assembly. At least the switch section corresponding to the cell assembly in which the abnormality has occurred is forcibly turned off. Also good.

[Second Embodiment]
Next, the charging system of 2nd Embodiment is demonstrated using FIG. As shown in FIG. 5, the charging system of the present embodiment includes a battery unit 70 and a charger 120. The battery unit 70 can be attached to and detached from the charger 120. When the battery unit 70 is attached to the charger 120, both are physically and electrically connected. FIG. 5 shows a state where both are connected.

  The battery unit 70 differs from the battery unit 1 of the first embodiment in the number of cell assemblies and a part of the configuration of the hardware interlock circuit B. Other than that, the battery unit 70 is basically the same as that of the first embodiment. The configuration is the same as that of the battery unit 1.

  The battery unit 70 of the present embodiment includes three cell assemblies 10, 20, and 30. The cell assemblies 10, 20,..., 30 are connected in parallel via a hardware interlock circuit B. Similar to the hardware interlock circuit A of the first embodiment, the hardware interlock circuit B is a circuit for preventing a plurality (three in this example) of cell assemblies from being directly connected in parallel at the same time. It is.

  Note that the battery unit 70 of the present embodiment can be mounted on the tool body 100 of the first embodiment and can supply power to the tool body 100. In addition, the charger 120 of the present embodiment can also be charged with the battery unit 1 of the first embodiment.

  As shown in FIG. 5, the charger 120 includes a microcomputer 131, a charging power supply circuit 132, a positive connection terminal 121, a negative connection terminal 122, and a communication terminal 124. The charging power supply circuit 132 includes a rectification circuit and a switching power supply circuit inside, and rectifies and transforms an alternating voltage supplied from an alternating current (AC) power supply such as a commercial power supply to generate a direct current voltage for charging the battery unit 1. Generate.

  The microcomputer 131 includes a CPU, a memory, and the like, like the microcomputer 6 in the battery unit 1. The microcomputer 131 can perform data communication with the microcomputer 6 of the battery unit 1 via the communication terminal 124. When the battery unit 1 is attached to the charger 120, the microcomputer 131 controls the charging power supply circuit 132 to supply the charging DC voltage to the battery unit 1 to charge the battery unit 1. When the microcomputer 131 receives a charge completion signal from the microcomputer 6 of the battery unit 1 via the communication terminal 124 after the start of charging, the microcomputer 131 stops charging. If the microcomputer 131 receives an abnormal signal from the microcomputer 6 of the battery unit 1 via the communication terminal 124 during charging, the microcomputer 131 forcibly stops charging.

  More specifically, the battery unit 70 is configured as shown in FIG. As shown in FIG. 2, the battery unit 70 of the present embodiment is also provided with a switch circuit for each cell assembly. That is, the first cell assembly 10 is connected to the positive electrode connection terminal 91 via the first switch circuit 71, and the second cell assembly 20 is connected to the positive electrode connection terminal 91 via the second switch circuit 72. 30 is connected to the positive electrode connection terminal 91 via the third switch circuit 73.

  The configuration of each switch circuit 71, 72, 73 is the same as that of each switch circuit 40, 50,..., 60 of the first embodiment except that the configuration of the AND circuit is partially different. In the present embodiment, since the number of cell assemblies is three, each of the AND circuits 76, 77, 78 receives three charge / discharge permission signals corresponding to these three cell assemblies 10, 20, 30. It is configured as follows. However, in each of the AND circuits 76, 77, 78, the charge / discharge permission signal corresponding to itself among the three charge / discharge permission signals is logically inverted and input by the permission input inverter as in the first embodiment. .

  As for the NOR circuit 7 as well, since the number of cell assemblies is three in this embodiment, a cell error signal is input from each of the cell monitoring circuits 12, 22, 32 of the three cell assemblies 10, 20, 30. It is configured.

  The biggest difference between the battery unit 70 of this embodiment and the battery unit 1 of the first embodiment is that a D-type flip-flop 81 and two OR circuits 82 and 83 are provided. That is, the three charge / discharge permission signals from the microcomputer 6 are not directly input to the switch circuits 71, 72, 73 but are input via the D-type flip-flop 81.

  That is, in this embodiment, the hardware interlock circuit B is configured by the three switch circuits 71, 72, 73, the D-type flip-flop 81, the two OR circuits 82, 83, and the like. In the first embodiment, when a plurality of charge / discharge permission signals are turned on (H level), charge / discharge of all cell blocks is prohibited. On the other hand, the hardware interlock circuit B according to the present embodiment includes the D-type flip-flop 81, so that when any one cell block is permitted to be charged / discharged, the hardware interlock circuit B may be different due to an abnormality of the microcomputer 6 or the like. If the charging / discharging permission signal for the cell block is erroneously turned on, the charging / discharging permission signal that was turned on normally is still valid and the charging / discharging permission is disabled. Let it continue.

  That is, the D-type flip-flop 81 includes three input terminals D1, D2, and D3, three output terminals Q1, Q2, and Q3, a clock terminal CK, and a clear terminal CLR. Three charge / discharge permission signals are input to the three input terminals D1, D2, and D3, respectively.

  The output terminal Q1 for the input terminal D1 to which the # 1 charge / discharge permission signal is input is connected to the permission input inverter 45 of the corresponding first switch circuit 71 and each AND circuit of the other switch circuits 72 and 73. 77 and 78 are also connected. The output terminal Q2 for the input terminal D2 to which the # 2 charge / discharge permission signal is input is connected to the permission input inverter 55 of the corresponding second switch circuit 72 and each AND circuit of the other switch circuits 71 and 73. 76 and 78 are also connected. The output terminal Q3 for the input terminal D3 to which the # 3 charge / discharge permission signal is input is connected to the permission input inverter 65 of the corresponding third switch circuit 73 and each AND circuit of each of the other switch circuits 71 and 72. 76 and 77 are also connected.

  Of the two OR circuits 82 and 83, three charge / discharge permission signals are input to the clear OR circuit 82. Then, the logical sum of the three charge / discharge permission signals is input from the clear OR circuit 82 to the clear terminal CLR of the D-type flip-flop 81 as a clear signal.

  Of the two OR circuits 82 and 83, three charge / discharge permission signals are input to the clock OR circuit 83. Then, the logical sum of the three charge / discharge permission signals is input from the clock OR circuit 83 to the clock terminal CK of the D-type flip-flop 81 as a clock signal.

  In the D flip-flop 81, when the clear signal is at the L level, all the outputs of the output terminals Q1, Q2, and Q3 are cleared and become the L level. At the rising edge of the clock signal, the input signals to the input terminals D1, D2, and D3 at that time are output from the corresponding output terminals Q1, Q2, and Q3, respectively.

  Therefore, for example, when the first charge / discharge permission signal is turned on (H level) from the state where all the charge / discharge permission signals are off (L level), the input terminal D1 of the D-type flip-flop 81 has the H level 1 Charging / discharging permission signal is input. Further, the two OR circuits 82 and 83 both change from the L level to the H level by the first charge / discharge permission signal. That is, the clock signal rises. Therefore, the output signal Q1 corresponding to the first charge / discharge permission signal among the three output signals is at the H level. Thereby, the switch part (the high-side switch 41 and the low-side switch 42) of the 1st switch circuit 71 turns on, the positive electrode of the cell block 11 of the 1st cell assembly 10 is connected to the positive electrode connection terminal 91, and charging / discharging is possible. It becomes.

  In this state, it is assumed that the second charge / discharge permission signal is also turned on (H level) due to abnormality of the microcomputer 6 or the like. Even if the second charge / discharge permission signal becomes H level while the first charge / discharge permission signal is already at H level, the clock signal remains at H level and does not change. That is, the rising edge of the clock signal does not occur. Therefore, the fact that the second charge / discharge permission signal has become H level is not transmitted to the output terminal side and becomes invalid. The first charge / discharge permission signal that is already at the H level continues to function effectively, so that the charge / discharge permission state of the first cell assembly 10 is continued.

  As described above, the battery unit 70 of the present embodiment is configured such that each charge / discharge permission signal from the microcomputer 6 is output to each switch circuit 71, 72, 73 via the D-type flip-flop 81. . Therefore, even if the charge / discharge permission signal to the other switch circuit becomes H level when the switch part of one switch circuit is turned on, the transmission of the charge / discharge permission signal is blocked. In other words, only the switch parts that are already turned on are kept on (permitted), and the charge / discharge permission signals for the other switch parts are invalidated.

  For this reason, it is possible to continuously supply battery power through one switch circuit that is already turned on, and to suppress current wraparound between the plurality of cell assemblies.

  Such a function is realized with a simple configuration using the D-type flip-flop 81 and the two OR circuits 82 and 83. Therefore, the internal circuit of the battery unit 70 can be reduced in size while having the above functions, and thus the entire battery unit 70 can be reduced in size and cost.

[Other Embodiments]
(1) In the above embodiment, the switch unit is configured by two switches (a high-side switch and a low-side switch), but the switch unit may be configured by one switch or three or more switches. However, when an element that generates a parasitic diode, such as a MOSFET, is used as the switch, it is desirable that a plurality of switches be connected in series so that no current wraparound occurs through the parasitic diode.

  (2) The high-side switch and low-side switch that constitute the switch unit, and the self-diagnosis switch may be semiconductor switches other than MOSFETs, or other switches (for example, relays) other than semiconductor switches. Also good.

  (3) In the above embodiment, the hardware interlock circuit is configured using a plurality of switch circuits. However, such a configuration is merely an example, and various specific configurations of the hardware interlock circuit are conceivable.

In addition, regarding the specific configuration of each switch circuit, the circuit configurations shown in FIGS. 2 and 6 are merely examples, and the switch circuits may be realized by other circuit configurations.
(4) In the second embodiment, the D-type flip-flop 81 is used so that charging / discharging of other cell blocks can be prohibited while continuing charging / discharging permission of one cell block. Instead of using the D-type flip-flop 81, other various logic circuits may be used.

  (5) In the above embodiment, when a cell error signal is output from the cell monitoring circuit of any cell assembly, the outputs of all AND circuits are set to L level and charging / discharging of all cell blocks is prohibited. Although it was a structure, it is not necessary to prohibit charging / discharging of all the cell blocks. For example, when an error is detected in the cell monitoring circuit of any one cell assembly, charging / discharging of only the cell block of that cell assembly may be prohibited.

(6) Each cell assembly may be configured to be individually detachable from the battery unit.
(7) The number of cells constituting the cell block and the connection form may be different from those in the above embodiment. That is, the cell block may have a configuration in which a plurality of cells are connected in parallel as well as a configuration in which a plurality of cells are connected in series as in the above embodiment, or a configuration in which a plurality of cells are connected in series and parallel. It may be.

  (8) If a display element is appropriately arranged in the battery unit and an error is detected in each cell monitoring circuit, or if any of the switch parts of each switch circuit is short-circuited, an abnormality occurs in the battery unit. You may make it alert | report that it has generate | occur | produced using a display element.

  In that case, the user may be notified so that the user can know the part where the abnormality has occurred, such as which cell assembly is abnormal and which switch part is short-circuited. Specifically, for example, a cell assembly in which an abnormality has occurred by arranging a 7-segment LED in the battery unit to display a number corresponding to the cell assembly in which an abnormality has occurred, or by arranging a plurality of display elements A method of informing using the number of display elements corresponding to the above is conceivable.

  By adopting a configuration that can notify the occurrence of an abnormality and its location in this way, when an abnormality occurs in the battery unit, the user of the battery unit, the repair operator, etc. can easily recognize the occurrence location of the abnormality. Can be maintained quickly.

  DESCRIPTION OF SYMBOLS 1,70 ... Battery unit, 2, 6, 111, 131 ... Microcomputer, 3 ... Self-diagnosis voltage supply circuit, 3a, 6a ... CPU, 3b, 6b ... Memory, 4 ... Constant voltage supply switch, 5, 7 ... NOR Circuit, 10, 20, 30 ... cell assembly, 11, 21, 31 ... cell block, 12, 22, 32 ... cell monitoring circuit, 16, 26, 36 ... secondary battery cell, 40, 50, 60, 71, 72 , 73 ... switch circuit, 41, 51, 61 ... high side switch, 42, 52, 62 ... low side switch, 43, 53, 63 ... self-diagnosis switch, 44, 54, 64 ... AND circuit, 45, 55, 65 ... Inverter for permission input, 46, 66, 76 ... Inverter for self-diagnosis, 81 ... D-type flip-flop, 82 ... OR circuit for clear, 83 ... OR circuit for clock, 91, 10 , 121 ... Positive connection terminal, 92, 102, 122 ... Negative connection terminal, 93 ... First communication terminal, 94 ... Second communication terminal, 100 ... Tool body, 103, 124 ... Communication terminal, 112 ... Motor, 113 ... Drive Circuit 114, trigger switch 120, charger 132, power supply circuit for charging A, B ... hardware interlock circuit, D0, D1, D2, D3 ... diode, R0 ... resistor.

Claims (9)

A plurality of cell assemblies each having an assembled battery in which a plurality of battery cells are connected in series, in parallel or in series,
A positive electrode connection terminal to which a positive electrode of each cell assembly is connected;
A negative electrode connection terminal to which a negative electrode of each cell assembly is connected;
A switch unit provided for each cell assembly, for conducting / interrupting the energization path between the positive electrode of the cell assembly and the positive electrode connection terminal;
An ON command signal for turning on each of the switch units and conducting the energization path can be individually output for each switch unit, and the ON command signal can be selectively output to any one of the switch units. A controller configured to output
When the ON command signal is output from the control unit to the plurality of switch units, only the ON command signal for any one of the plurality of switch units is validated or all the A simultaneous on-blocking unit that blocks the plurality of switch units from being turned on simultaneously by disabling the on-command signal to the switch unit;
A battery unit comprising: The battery unit according to claim 1,
The switch unit includes a first switch and a second switch connected in series,
One end of the second switch is connected to the positive electrode of the corresponding cell assembly, the other end is connected to one end of the first switch, and the other end of the first switch is connected to the positive electrode connection terminal. A battery unit characterized by The battery unit according to claim 2,
A switch provided individually for each of the switch units, a third switch having one end connected to a connection between the first switch and the second switch;
Provided for each of the third switches, when the ON command signal is output to the corresponding switch unit, the third switch is turned OFF, and the ON command signal is not output to the corresponding switch unit A switching control unit for turning on the third switch,
An abnormality determination unit that determines the presence or absence of an abnormality in each switch unit based on the electrical state of the other end of each third switch;
A battery unit comprising: The battery unit according to claim 3,
The abnormality determination unit determines whether or not there is a short circuit failure in the second switch based on an electrical state of the other end of each of the third switches when the ON command signal is not output from the control unit. A battery unit characterized by The battery unit according to claim 3 or claim 4,
A constant voltage generator capable of applying a constant voltage having a predetermined voltage value to the other end of each of the first switches;
A constant voltage application unit that applies the constant voltage from the constant voltage generation unit to the other end of each first switch at a predetermined determination timing while the on command signal is not output from the control unit;
With
The abnormality determination unit determines whether or not there is a short circuit failure in the first switch based on an electrical state of the other end of each of the third switches when the constant voltage is applied by the constant voltage application unit. A battery unit characterized by judging. The battery unit according to any one of claims 1 to 5,
The simultaneous on blocking unit forcibly turns off all the switch units when the on command signal is output from the control unit to the plurality of switch units. The battery unit according to any one of claims 1 to 5,
While the ON command signal is being output from the control unit to any one of the switch units, the simultaneous ON blocking unit also outputs the ON command signal from the control unit to the other switch units. Is output, the transmission of the ON command signal to one of the switch units to which the ON command signal has been output is allowed as it is, and the transmission of the ON command signal to the other switch unit is blocked. A battery unit characterized by The battery unit according to claim 7,
A D-type flip-flop is provided between the control unit and each switch unit,
In the D-type flip-flop, the ON command signal for each switch unit output from the control unit is input as an input signal, and each output signal for each input signal is output to the corresponding switch unit, A battery unit, wherein a logical sum of each ON command signal from the control unit to each switch unit is input as a clock signal and a clear signal. The battery unit according to claim,
Each of the cell assemblies has a monitoring unit configured to monitor a state of the corresponding assembled battery and output an error signal indicating that when an abnormality of the assembled battery is detected,
Furthermore,
When the error signal is output from the monitoring unit of any one of the cell assemblies, at least the switch unit corresponding to the cell assembly is forcibly turned off regardless of the presence of the on command signal. A battery unit comprising: