JP2014511039A5 - - Google Patents
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- JP2014511039A5 JP2014511039A5 JP2014502583A JP2014502583A JP2014511039A5 JP 2014511039 A5 JP2014511039 A5 JP 2014511039A5 JP 2014502583 A JP2014502583 A JP 2014502583A JP 2014502583 A JP2014502583 A JP 2014502583A JP 2014511039 A5 JP2014511039 A5 JP 2014511039A5
- Authority
- JP
- Japan
- Prior art keywords
- conductor pad
- conductor
- pad
- solder
- gap
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 239000004020 conductor Substances 0.000 claims 32
- 229910000679 solder Inorganic materials 0.000 claims 14
- 238000001465 metallisation Methods 0.000 claims 10
- 238000002161 passivation Methods 0.000 claims 9
- 239000004065 semiconductor Substances 0.000 claims 9
- 238000004519 manufacturing process Methods 0.000 claims 7
- 230000001808 coupling Effects 0.000 claims 6
- 238000010168 coupling process Methods 0.000 claims 6
- 238000005859 coupling reaction Methods 0.000 claims 6
- 229920000642 polymer Polymers 0.000 claims 6
- 239000000758 substrate Substances 0.000 claims 2
- 238000000034 method Methods 0.000 claims 1
Claims (24)
第２の導体パッドを、前記パッシベーション構造上であって前記第１の導体パッドの周囲に、間隙を残すように前記第１の導体パッドと物理的に接触することなく形成するステップと、
前記第１の導体パッドと電気的に接触するアンダーバンプメタライゼーション構造を形成するステップと、を含み、
前記アンダーバンプメタライゼーション構造は、前記第２の導体パッドと上下に重なる部分を有しており、
前記第２の導体パッドは、前記重なる部分によって与えられる応力から、前記パッシベーション構造の一部を保護するように動作する、
製造方法。 A step of Ru provided a semiconductor chip having a first conductor pad formed beneath the path Sshibeshon structure,
Forming without the second conductor pad, to said even on passivation structure around the first conductor pads, the first conductive pad to leave between gap in physical contact When,
Forming an under bump metallization structure in electrical contact with the first conductor pad;
The under bump metallization structure has a portion that overlaps with the second conductive pad,
The second conductor pad operates to protect a portion of the passivation structure from stress imparted by the overlapping portion;
Production method.
前記間隙の近くの前記パッシベーション構造の一部を保護するために、第３の導体パッドを、前記間隙の近くの前記高分子膜上に形成するステップとを備える、請求項１に記載の製造方法。 Forming a polymer film on the semiconductor chip;
To protect some near the passivation structure of the gap, the third conductor pad, and a step of forming on near the polymer film of the gap, prepared as described in claim 1 Method.
はんだ構造を前記アンダーバンプメタライゼーション構造に結合するステップと、
前記はんだ構造を前記回路基板に結合するステップと、
を含む方法。 A passivation structure, the first conductor pad, a semiconductor chip and a second conductor pad near the first conductor pads, the first conductive pad is below the passivation structure is formed on the first conductor pads and second contact pads are separated by a polymeric film so as to leave a gap, said first conductor pad, the second conductor pad Although extends over overlaps vertically with the second contact pad, wherein the polymer film in electrical contact with the under bump metallization structure that more separated and the second conductor pad, the semiconductor chip circuits a method for coupling the base plate,
Coupling a solder structure on the under bump metallization structure,
Coupling the solder structure to the circuit board;
Including methods.
前記パッシベーション構造上であって前記第１の導体パッドの周囲に、間隙を残すように前記第１の導体パッドと物理的に接触することなく存在する第２の導体パッドと、
前記第１の導体パッドと電気的に接触するアンダーバンプメタライゼーション構造と、を備え、
前記アンダーバンプメタライゼーション構造は、前記第２の導体パッドと上下に重なる部分を有しており、
前記第２の導体パッドは、前記重なる部分によって与えられる応力から、前記パッシベーション構造の一部を保護するように動作する、
装置。 A semiconductor chip having a first conductor pad formed beneath the path Sshibeshon structure,
Around the first conductor pads be over the passivation structure, the second conductive pad that exists without the first conductor pads in physical contact so as to leave between gap,
An under bump metallization structure in electrical contact with the first conductor pad;
The under bump metallization structure has a portion that overlaps with the second conductive pad,
The second conductor pad operates to protect a portion of the passivation structure from stress imparted by the overlapping portion;
apparatus.
前記間隙の近くの前記パッシベーション構造の一部を保護するために、前記間隙の近くの前記高分子膜上に存在する第３の導体パッドとを備える、請求項１７に記載の装置。 A polymer film on the semiconductor chip;
To protect some near the passivation structure of the gap, and a third conductor pad present on proximate the polymer film of the gap, according to claim 17.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/072,554 | 2011-03-25 | ||
| US13/072,554 US8647974B2 (en) | 2011-03-25 | 2011-03-25 | Method of fabricating a semiconductor chip with supportive terminal pad |
| PCT/US2012/027631 WO2012134710A1 (en) | 2011-03-25 | 2012-03-03 | Semiconductor chip with supportive terminal pad |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2014511039A JP2014511039A (en) | 2014-05-01 |
| JP2014511039A5 true JP2014511039A5 (en) | 2015-02-12 |
| JP5764256B2 JP5764256B2 (en) | 2015-08-19 |
Family
ID=45992817
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2014502583A Active JP5764256B2 (en) | 2011-03-25 | 2012-03-03 | Semiconductor chip having support terminal pads |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US8647974B2 (en) |
| EP (1) | EP2689455B1 (en) |
| JP (1) | JP5764256B2 (en) |
| KR (1) | KR101508669B1 (en) |
| CN (1) | CN103460379A (en) |
| TW (1) | TWI517273B (en) |
| WO (1) | WO2012134710A1 (en) |
Families Citing this family (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7749885B2 (en) * | 2006-12-15 | 2010-07-06 | Micron Technology, Inc. | Semiconductor processing methods, methods of forming contact pads, and methods of forming electrical connections between metal-containing layers |
| US9978656B2 (en) * | 2011-11-22 | 2018-05-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Mechanisms for forming fine-pitch copper bump structures |
| US9224688B2 (en) | 2013-01-04 | 2015-12-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Metal routing architecture for integrated circuits |
| US10242142B2 (en) * | 2013-03-14 | 2019-03-26 | Coventor, Inc. | Predictive 3-D virtual fabrication system and method |
| US9793231B2 (en) * | 2015-06-30 | 2017-10-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Under bump metallurgy (UBM) and methods of forming same |
| US9818711B2 (en) | 2015-06-30 | 2017-11-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Post-passivation interconnect structure and methods thereof |
| KR102410018B1 (en) * | 2015-09-18 | 2022-06-16 | 삼성전자주식회사 | Semiconductor package |
| US9929112B2 (en) | 2015-09-25 | 2018-03-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method of manufacture |
| US10165682B2 (en) | 2015-12-28 | 2018-12-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Opening in the pad for bonding integrated passive device in InFO package |
| US9704832B1 (en) * | 2016-02-29 | 2017-07-11 | Ixys Corporation | Die stack assembly using an edge separation structure for connectivity through a die of the stack |
| KR102663140B1 (en) | 2016-06-24 | 2024-05-08 | 삼성디스플레이 주식회사 | display device |
| MY192389A (en) * | 2016-07-01 | 2022-08-18 | Intel Corp | Systems, methods, and apparatuses for implementing a pad on solder mask (posm) semiconductor substrate package |
| US10290584B2 (en) * | 2017-05-31 | 2019-05-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Conductive vias in semiconductor packages and methods of forming same |
| DE102017210654B4 (en) * | 2017-06-23 | 2022-06-09 | Infineon Technologies Ag | An electronic device comprising a redistribution layer pad comprising a cavity |
| US10665559B2 (en) * | 2018-04-11 | 2020-05-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Device, semiconductor package and method of manufacturing semiconductor package |
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| US3615913A (en) | 1968-11-08 | 1971-10-26 | Westinghouse Electric Corp | Polyimide and polyamide-polyimide as a semiconductor surface passivator and protectant coating |
| US4034469A (en) | 1976-09-03 | 1977-07-12 | Ibm Corporation | Method of making conduction-cooled circuit package |
| JPH06163629A (en) | 1992-11-26 | 1994-06-10 | Sanyo Electric Co Ltd | Bonding pad structure for semiconductor integrated circuit |
| JP3138159B2 (en) * | 1994-11-22 | 2001-02-26 | シャープ株式会社 | Semiconductor device, semiconductor device package, and semiconductor device replacement method |
| JPH09134934A (en) * | 1995-11-07 | 1997-05-20 | Sumitomo Metal Ind Ltd | Semiconductor package and semiconductor device |
| US6118180A (en) * | 1997-11-03 | 2000-09-12 | Lsi Logic Corporation | Semiconductor die metal layout for flip chip packaging |
| KR100306842B1 (en) * | 1999-09-30 | 2001-11-02 | 윤종용 | Redistributed Wafer Level Chip Size Package Having Concave Pattern In Bump Pad And Method For Manufacturing The Same |
| DE10122324A1 (en) * | 2001-05-08 | 2002-11-14 | Philips Corp Intellectual Pty | Flexible integrated monolithic circuit |
| CN1225778C (en) * | 2002-05-27 | 2005-11-02 | 联华电子股份有限公司 | Technique for repairing salient point and memory by using laser |
| US7547623B2 (en) * | 2002-06-25 | 2009-06-16 | Unitive International Limited | Methods of forming lead free solder bumps |
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| JP4708148B2 (en) * | 2005-10-07 | 2011-06-22 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
| JP5017872B2 (en) | 2006-02-06 | 2012-09-05 | 富士通セミコンダクター株式会社 | Semiconductor device and manufacturing method thereof |
| JP4247690B2 (en) * | 2006-06-15 | 2009-04-02 | ソニー株式会社 | Electronic parts and manufacturing method thereof |
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| US7790501B2 (en) | 2008-07-02 | 2010-09-07 | Ati Technologies Ulc | Semiconductor chip passivation structures and methods of making the same |
| US8030781B2 (en) | 2008-09-19 | 2011-10-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | Bond pad structure having dummy plugs and/or patterns formed therearound |
| US8058108B2 (en) * | 2010-03-10 | 2011-11-15 | Ati Technologies Ulc | Methods of forming semiconductor chip underfill anchors |
-
2011
- 2011-03-25 US US13/072,554 patent/US8647974B2/en active Active
-
2012
- 2012-03-03 JP JP2014502583A patent/JP5764256B2/en active Active
- 2012-03-03 WO PCT/US2012/027631 patent/WO2012134710A1/en active Application Filing
- 2012-03-03 CN CN201280014892XA patent/CN103460379A/en active Pending
- 2012-03-03 KR KR1020137025186A patent/KR101508669B1/en active IP Right Grant
- 2012-03-03 EP EP12715748.5A patent/EP2689455B1/en active Active
- 2012-03-08 TW TW101107851A patent/TWI517273B/en active
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