JP2014241699A - Switching regulator, power supply circuit device, semiconductor device and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a switching regulator that has a smaller packaging area than before, keeps a voltage of an input terminal in continuity with an output terminal in a standby state, and protectively limits a short circuit current even if an output is short-circuited.SOLUTION: The switching regulator includes: an element with an inductance component connected to the input terminal; a switching transistor; a synchronous rectification transistor; a switching control circuit for controlling the switching transistor and the synchronous rectification transistor to convert an input voltage to a predetermined output voltage for outputting; a through switch circuit connected in parallel with the synchronous rectification transistor or with a series circuit of the synchronous rectification transistor and the element with the inductance component; and a through switch control circuit for turning on the through switch circuit to output the input voltage to the output terminal in a standby state of the switching regulator.

Description

  The present invention relates to a switching regulator, a power supply circuit device including the same, a semiconductor device, and an electronic device, and more particularly to a switching regulator that causes an input terminal to conduct to an output terminal in a standby state, and a power supply circuit device including the same, a semiconductor device, And electronic devices.

  2. Description of the Related Art Conventionally, a health care product that is driven by a DC power source such as a battery, such as a blood pressure monitor, includes a booster circuit. For example, the booster circuit boosts the power supply voltage so that the sphygmomanometer operates in a normal operation state (hereinafter referred to as an active state) for blood pressure measurement. In general, a sphygmomanometer operates in an operation state (hereinafter, referred to as a standby state) in which only a minimum component such as a microcomputer operates in order to wait for an operation in an active state. In order for the sphygmomanometer to operate in the standby state, it is only necessary to obtain a power supply voltage capable of operating only the minimum components such as a microcomputer, and therefore there is no need for boosting.

  At present, a diode rectification type boost DC / DC converter is mainly used as a boost circuit. In many cases, in a stand-by state, in a diode rectification step-up DC / DC converter, an input terminal to which a power supply voltage is applied is conducted to an output terminal to which a load is connected. However, the diode rectification step-up DC / DC converter requires an external diode, and therefore has a large mounting area and a low mounting area compared with a synchronous rectification step-up DC / DC converter incorporating a synchronous rectification transistor. Power conversion efficiency. Therefore, the use of a synchronous rectification boost DC / DC converter having a small mounting area and high power conversion efficiency compared to a diode rectification boost DC / DC converter is increasing.

  For example, Patent Document 1 discloses a configuration for turning on a synchronous rectification transistor step by step for the purpose of preventing an inrush current at startup. Patent Document 2 discloses a configuration in which a synchronous rectification transistor is operated at a constant current within a certain time period after startup for the purpose of preventing inrush current at startup. Further, in Patent Document 3, a current limiting transistor having a high on-resistance is provided in parallel with the synchronous rectification transistor for the purpose of preventing an inrush current at the start-up, and the synchronous rectification transistor is in a predetermined time at the start-up. A configuration that is turned on only for a period of time is disclosed.

  However, each of the above Patent Documents 1 to 3 is means for preventing an inrush current in the active state, and is not configured to prevent an inrush current in the standby state. In the diode rectification step-up DC / DC converter, the power supply voltage can be conducted from the input terminal to the output terminal in the standby state. However, when the output terminal is short-circuited, a large current corresponding to the driving capability of the diode is obtained. Flows, leading to destruction of the device. In order to prevent destruction of the element at the time of a short circuit, for example, it is necessary to provide a protection circuit having a fuse. When such a protection circuit is used, there is a problem that a mounting area increases.

  An object of the present invention is to provide a switching regulator that solves the above-described problems and has a mounting area reduced as compared with the conventional example, and can provide protection in a short-circuit state in a standby state. .

A switching regulator according to one embodiment of the present invention includes an element having an inductance component having one end connected to an input terminal;
A switching transistor connected between the other end of the element having an inductance component and the ground and driven by the first control signal inputted;
A synchronous rectification transistor connected between a connection point between the element having the inductance component and the switching transistor and the output terminal and driven by the input second control signal;
A switching control circuit that controls the switching transistor and the synchronous rectification transistor so that the input voltage input through the input terminal is converted into a predetermined output voltage and output from the output terminal;
A through switch circuit connected in parallel with a synchronous rectification transistor, or a series circuit of a synchronous rectification transistor and an element having an inductance component, and controlled by an input third control signal;
And a slew switch control circuit for controlling the slew switch circuit so that the slew switch circuit is turned on and the input voltage is output to the output terminal in a standby state of the switching regulator.

  The switching regulator according to the present invention has a reduced mounting area compared to the conventional example, and when the power supply voltage applied to the input terminal is conducted to the output terminal even in the standby state, when the output terminal is short-circuited. A switching regulator having protection can also be provided.

1 is a circuit diagram showing a configuration of a switching regulator 1A according to Embodiment 1 of the present invention. It is a circuit diagram which shows the structure of switching regulator 1B which is a modification of switching regulator 1A of FIG. 1A. 1B is a table for explaining operations in an active state and a standby state of the switching regulator 1A of FIG. 1A. 3 is a timing chart showing temporal changes of (a) a gate signal VG2 of the synchronous rectification transistor 13 and (b) a gate signal VG3 of a PMOS transistor 17Aa in the active state of FIG. 3 is a timing chart showing temporal changes in (a) the gate signal VG2 of the synchronous rectification transistor 13 and (b) the gate signal VG3 of the PMOS transistor 17Aa in the standby state of FIG. Changes in time of (a) gate signal VG2, (b) gate signal VG3, and (c) enable signal EN when the operating state of switching regulator 1A in FIG. 1A transitions from the active state to the standby state at time t1. It is a timing chart which shows. FIG. 1A shows time variations of the power supply voltage VDD, (b) power supply current IVDD, and (c) output voltage VOUT when the power supply is turned on at time t2 and when the load is short-circuited at time t3. It is a timing chart. It is a circuit diagram which shows the structure of 1C of switching regulators concerning Embodiment 2 of this invention. It is a circuit diagram which shows the structure of switching regulator 1D which is a modification of switching regulator 1C of FIG. 7A.

  Hereinafter, embodiments according to the present invention will be described with reference to the drawings. In addition, in each following embodiment, the same code | symbol is attached | subjected about the same component.

Embodiment 1. FIG.
FIG. 1A is a circuit diagram showing a configuration of a switching regulator 1A according to Embodiment 1 of the present invention. In FIG. 1A, the through switch circuit 17A includes a PMOS transistor 17Aa having a current driving capability smaller than that of the synchronous rectification transistor 13. When the through switch control circuit 18 makes the through switch circuit 17A conductive in the standby state, the through switch circuit 17A outputs the input voltage, which is the power supply voltage VDD to the input terminal 21, to the output terminal 22.

  In FIG. 1A, a switching regulator 1A is a coil 11, a switching transistor 12 which is an N-channel MOS field effect transistor (hereinafter referred to as NMOS transistor), and a P-channel MOS field effect transistor (hereinafter referred to as PMOS transistor). And a synchronous rectification transistor 13. The switching regulator 1A further includes a switching control circuit 14, switching transistors 15a and 15b, a back gate control circuit 16, a through switch circuit 17A, and a through switch control circuit 18. Here, the switching control circuit 14 performs on / off control of the switching transistor 12 and the synchronous rectification transistor 13. Each of the switching transistors 15a and 15b is a PMOS transistor. The back gate control circuit 16 controls the voltage output to the back gate of the synchronous rectification transistor 13 via the switching transistors 15a and 15b. The through switch circuit 17A includes PMOS transistors 17Aa, 17Ab, and 17Ac. The through switch control circuit 18 controls on / off of the through switch circuit 17A by controlling on / off of the PMOS transistor 17Aa. The switching regulator 1A of FIG. 1A is provided in a booster circuit of a sphygmomanometer, for example. The switching regulator 1A may be mounted as an integrated circuit device.

  A DC power supply voltage VDD is applied to the input terminal 21 of FIG. 1A from a DC power supply (not shown) such as a battery. The input terminal 21 is connected via the coil 11 to the drain of the switching transistor 12, the drain of the synchronous rectification transistor 13, and the drain of the switching transistor 15b. The input terminal 21 is connected to the drains of the PMOS transistors 17Aa and 17Ac via the coil 11. The source of the switching transistor 12 is grounded. The source of the synchronous rectification transistor 13 is connected to the source of the switching transistor 15a, the sources of the PMOS transistors 17Aa and 17Ab, and the output terminal 22. The back gate of the synchronous rectification transistor 13 is connected to the drain of the switching transistor 15a and the source of the switching transistor 15b. The back gate of the PMOS transistor 17Aa is connected to the drain of the PMOS transistor 17Ab and the source of the PMOS transistor 17Ac.

  The switching control circuit 14 in FIG. 1A controls the switching transistor 12 to be turned off by outputting a low level gate signal VG1 to the gate which is the control terminal of the switching transistor 12. Further, the switching control circuit 14 controls the switching transistor 12 to be turned on by outputting a high-level gate signal VG1 to the gate of the switching transistor 12.

  Further, the switching control circuit 14 controls the synchronous rectification transistor 13 to be turned on by outputting a low-level gate signal VG2 to the gate which is a control terminal of the synchronous rectification transistor 13. The switching control circuit 14 controls the synchronous rectification transistor 13 to be turned off by outputting a high level gate signal VG2 to the gate of the synchronous rectification transistor 13.

  The back gate control circuit 16 in FIG. 1A controls the voltage applied to the back gate of the synchronous rectification transistor 13 via the switching transistors 15a and 15b. The back gate control circuit 16 controls the bias state so that the parasitic diode of the synchronous rectification transistor 13 becomes non-conductive by changing the potential of the back gate of the synchronous rectification transistor 13. The back gate control circuit 16 controls the voltage applied to the back gate of the PMOS transistor 17Aa via the PMOS transistors 17Ab and 17Ac. The back gate control circuit 16 controls the bias state so that the parasitic diode of the PMOS transistor 17Aa becomes non-conductive by changing the potential of the back gate of the PMOS transistor 17Aa.

  In FIG. 1A, the enable signal EN is input to the through switch control circuit 18 via an enable signal input terminal 23 from an external circuit such as an external controller. Further, the power supply voltage VDD and the output voltage VOUT are input to the through switch control circuit 18. The through switch control circuit 18 outputs the high level gate signal VG3 to the gate of the PMOS transistor 17Aa in response to the high level (EN = H) enable signal EN so as to turn off the through switch circuit 17A. Control. The through switch control circuit 18 controls the through switch circuit 17A to be turned on by outputting a low level gate signal VG3 to the gate of the PMOS transistor 17Aa. Here, the through switch control circuit 18 changes the control to turn on the through switch circuit 17A into a low level (EN = L) enable signal EN and a through switch control circuit signal including signals of the power supply voltage VDD and the output voltage VOUT. Execute in response.

  The through switch control circuit 18 controls the through switch circuit 17A so that the conduction direction of the through switch circuit 17A is only in the direction from the input terminal 21 to the output terminal 22. Specifically, the through switch control circuit 18 controls the through switch circuit 17A to turn on when EN = L and VDD ≧ VOUT, and to turn off when EN = H or VDD <VOUT. .

  The operation of the switching regulator 1A configured as described above in the active state and the standby state will be described below.

  FIG. 2 is a table showing operations in the active state and the standby state of the switching regulator 1A of FIG. 1A.

  FIG. 3 is a timing chart showing temporal changes in (a) the gate signal VG2 of the synchronous rectification transistor 13 and (b) the gate signal VG3 of the PMOS transistor 17Aa in the active state of FIG.

  As shown in FIGS. 2 and 3B, in the active state, the enable signal EN of high level (EN = H) is input to the enable signal input terminal 23, whereby the through switch circuit 17A is turned off.

  As shown in FIG. 3A, the gate signal VG2 of the synchronous rectification transistor 13 is switched between a high level and a low level at a predetermined time interval. In synchronization with the switching of the gate signal VG2, the synchronous rectification transistor 13 is switched between on and off.

  In the active state, the output voltage VOUT changes in synchronization with, for example, the switching operation between on and off of the synchronous rectification transistor 13. For example, the output voltage VOUT changes so as to be switched between a voltage of about 0 V and a voltage substantially equal to the output voltage VOUT or the power supply voltage VDD with respect to the ground potential (GND) in synchronization with the switching operation.

  FIG. 4 is a timing chart showing temporal changes of (a) the gate signal VG2 of the synchronous rectification transistor 13 and (b) the gate signal VG3 of the PMOS transistor 17Aa in the standby state of FIG.

  As shown in FIGS. 2 and 4B, in the standby state, a low level gate signal VG3 corresponding to the low level (EN = L) enable signal EN is input to the gate of the PMOS transistor 17Aa. The through switch circuit 17A is turned on. As shown in FIGS. 2 and 4A, in the standby state, the high-level gate signal VG2 is input to the gate of the synchronous rectification transistor 13, whereby the synchronous rectification transistor 13 is turned off.

  In the standby state, when the through switch circuit 17A is turned on, for example, an output voltage VOUT having substantially the same level as the power supply voltage VDD is output from the output terminal 22.

  As described above, in the standby state, the synchronous rectification transistor 13 is turned off and the through switch circuit 17A is turned on. Therefore, the power supply current IVDD does not flow through the synchronous rectification transistor 13 and its parasitic diode, but flows through a path from the source of the synchronous rectification transistor 13 to the output terminal 22 via the PMOS transistor 17Aa of the through switch circuit 17A.

  FIG. 5 shows the time of (a) gate signal VG2, (b) gate signal VG3 and (c) enable signal EN when the operating state of switching regulator 1A in FIG. 1A transitions from the active state to the standby state at time t1. It is a timing chart which shows each change.

  In FIG. 5, in the time period before time t1, the switching regulator 1A operates in the active state of FIG. When the enable signal EN is switched from the high level to the low level at time t1, the switching regulator 1A operates in the standby state of FIG.

  Contrary to the case of FIG. 5, when the enable signal EN is switched from the low level to the high level, the switching regulator 1A operates in the active state of FIG.

  FIG. 6 shows (a) the power supply voltage VDD, (b) the power supply current IVDD, and (c) the output voltage VOUT at the time when the power is turned on at time t2 and at the time when the load is short-circuited at time t3. It is a timing chart which shows each change. The initial operating state of the switching regulator 1A after power-on at time t2 is a standby state.

  In FIG. 6, the power supply voltage VDD applied to the input terminal 21 is 0 V in the time period before time t2. Therefore, in this time period, the power supply current IVDD is 0 A, and the output voltage VOUT is 0 V.

  At time t2, when a predetermined power supply voltage VDD is applied to the input terminal 21 as shown in FIG. 6A, the switching regulator 1A starts operating in a standby state. At time t2, the power supply current IVDD rises and flows through the coil 11 and the through switch circuit 17A that is turned on. The power supply current IVDD further flows as an inrush current from the output terminal 22 to the load capacity of the load connected to the output terminal 22.

  In the standby state, the back gate control circuit 16 controls the switching transistors 15 a and 15 b so as to prevent an inrush current from flowing between the drain and source of the synchronous rectification transistor 13. Therefore, the power supply current IVDD does not substantially flow between the drain and source of the synchronous rectification transistor 13.

  Further, as shown in FIG. 6B, the PMOS transistor 17Aa of the through switch circuit 17A has a current driving capability smaller than the current driving capability of the synchronous rectification transistor 13. Therefore, for example, a power supply current IVDD of about 10 mA at most flows after time t2, and a large current of 1-2 A, for example, does not flow. After the power supply current IVDD rises after time t2, the power supply current IVDD decreases stepwise at a speed based on the time constant corresponding to the load capacity of the load connected to the output terminal 22, and then the load It becomes the current according to.

  As the power supply current IVDD decreases stepwise, the output voltage VOUT at the output terminal 22 increases stepwise at a speed based on the time constant corresponding to the load capacity of the load, as shown in FIG. To do.

  After the power supply current IVDD and the output voltage VOUT are changed after the power is turned on, in the standby state of the switching regulator 1A, for example, the output voltage VOUT that substantially matches the power supply voltage VDD is output from the output terminal 22 as in the case of FIG. Is done.

  At time t3 in FIG. 6, when the load connected to the output terminal 22 is short-circuited while the switching regulator 1A is operating in the standby state, the output terminal 22 is grounded. As shown in FIG. 6C, the output voltage VOUT becomes 0 V with respect to the ground potential (GND). For this reason, the power supply voltage VDD is applied to both ends of the through switch circuit 17A. Further, as shown in FIG. 6B, the power supply current IVDD flows to the load connected to the output terminal 22 via the coil 11 and the PMOS transistor 17Aa of the through switch circuit 17A.

  However, as described above, the PMOS transistor 17Aa has a current driving capability smaller than that of the synchronous rectification transistor 13. For this reason, after time t3 after the load is short-circuited, as shown in FIG. 6B, for example, only a power supply current IVDD of about 10 mA at most flows, for example, a large current of 1-2 A does not flow. . Therefore, the through switch circuit 17A can limit the short-circuit current that flows when the load is short-circuited, as compared with the case where the configuration according to the conventional example is used, and prevents the destruction of the device associated with the subsequent stage. Can do. As a result, the through switch circuit 17A operates to limit and protect the short-circuit current. When a short circuit occurs, a large current flows, so that it is possible to prevent destruction of subsequent elements, to suppress battery consumption, and to prevent a sudden drop in battery voltage due to an inrush current.

  The switching regulator 1A according to the embodiment of the present embodiment configured as described above includes the coil 11 having one end connected to the input terminal 21, the switching transistor 12, and the synchronous rectification transistor 13. Here, the switching transistor 12 is connected between the other end of the coil 11 and the ground, and is controlled so as to be driven by a gate signal VG1 which is a control signal. The synchronous rectification transistor 13 is connected between a connection point between the coil 11 and the switching transistor 12 and the output terminal 22, and is controlled to be driven by a gate signal VG2 which is a control signal. The switching regulator 1A includes a switching control circuit 14, a through switch circuit 17A connected in parallel with the synchronous rectification transistor 13, and a through switch control circuit 18. Here, the switching control circuit 14 controls the switching transistor 12 and the synchronous rectification transistor 13 so that the power supply voltage VDD input via the input terminal 21 is converted into a predetermined output voltage VOUT and output from the output terminal 22. To do. The through switch control circuit 18 operates in response to the enable signal EN and the through switch control circuit signal. Specifically, the through switch control circuit 18 controls the through switch circuit 17A so that the through switch circuit 17A is turned on and the power supply voltage VDD is output to the output terminal 22 in the standby state of the switching regulator 1A. The through switch circuit 17A is controlled by a gate signal VG3 generated by the through switch control circuit 18.

  According to this configuration, when the switching regulator 1A is operating in the standby state, when the load connected to the output terminal 22 is short-circuited, the power supply current IVDD passes through the PMOS transistor 17Aa of the through switch circuit 17A. Flow to the load. Here, the through switch circuit 17 has a current drive capability smaller than the current drive capability of the synchronous rectification transistor 13. For this reason, the power supply current IVDD is smaller than the current flowing between the drain and source of the synchronous rectification transistor 13 when the synchronous rectification transistor 13 is turned on. Therefore, according to the switching regulator 1 which concerns on this invention, it has the mounting area reduced compared with the diode rectification product of the prior art example. Further, when compared with a synchronous rectification switch of a synchronous rectification product, protection at the time of a short circuit is possible. Furthermore, the current flowing through the output terminal 22 in the standby state can be reduced.

  For example, even when the switching regulator 1A is operating in the standby state after the transition from the active state in FIG. 5, the above-described effect is obtained in that the current flowing through the load connected to the output terminal 22 is reduced. Further, even when the switching regulator 1A is operating in the standby state after power-on in FIG.

  Further, the back gate control circuit 16 applies a voltage signal applied to the back gate of the synchronous rectification transistor 13 via the switching transistors 15a and 15b so that the synchronous rectification transistor 13 is turned off when the through switch circuit 17A is turned on. Control. When the back gate control circuit 16 controls the bias state of the synchronous rectification transistor 13, the parasitic diode of the synchronous rectification transistor 13 becomes non-conductive. As a result, in the standby state of the switching regulator 1A, not only the synchronous rectification transistor 13 but also its parasitic diode is turned off.

  Further, in the first embodiment of the present invention, the through switch control circuit 18 switches the gate signal VG3 between on and off when the enable signal EN is switched. However, the present invention is not limited to this, and the through switch control circuit 18 outputs to the through switch circuit 17A the gate signal VG3 that gradually changes between the high level and the low level when the enable signal EN is switched. You may comprise.

  Furthermore, in the above embodiment, the through switch control circuit 18 controls the through switch circuit 17A to be turned on when EN = L and VDD ≧ VOUT. However, the present invention is not limited to this, and the slew switch control circuit 18 controls the slew switch circuit 17A by adding an offset to the above relationship between the power supply voltage VDD and the output voltage VOUT due to circuit variations or intentionally. May be. For example, the through switch control circuit 18 may control the through switch circuit 17A to turn on the through switch circuit 17A when EN = L and VDD ≧ VOUT + 100 mV.

  In the above embodiment, the coil 11 is provided in the switching regulator 1A. However, the present invention is not limited to this, and an element having at least an inductance component may be provided in the switching regulator 1A.

  FIG. 1B is a circuit diagram showing a configuration of a switching regulator 1B which is a modification of the switching regulator 1A of FIG. 1A. In FIG. 1B, the switching regulator 1B is different from the switching regulator 1A in FIG. 1A in that a through switch circuit 17B is provided instead of the through switch circuit 17A in FIG. 1A. The through switch circuit 17B includes PMOS transistors 17Ba and 17Bb each having a current drive capability lower than that of the synchronous rectification transistor 13.

  In FIG. 1B, the drain of the PMOS transistor 17Bb is connected to the drain of the synchronous rectification transistor 13. The source of the PMOS transistor 17Bb is connected to the drain of the PMOS transistor 17Ba. The source of the PMOS transistor 17Ba is connected to the output terminal 22.

  The through switch control circuit 18 in FIG. 1B outputs the low level gate signals VG3a and VG3b to the gates of the PMOS transistors 17Ba and 17Bb to turn on the PMOS transistors 17Ba and 17Bb, thereby turning on the through switch circuit 17B. The through switch control circuit 18 outputs the high-level gate signals VG3a and VG3b to the gates of the PMOS transistors 17Ba and 17Bb to turn off the PMOS transistors 17Ba and 17Bb, thereby turning off the through switch circuit 17B.

  The through switch control circuit 18 in FIG. 1B controls the through switch circuit 17B so that the conduction direction of the through switch circuit 17B is only in the direction from the input terminal 21 to the output terminal 22. Specifically, the through switch control circuit 18 turns on the through switch circuit 17B when EN = L and VDD ≧ VOUT, and turns off the through switch circuit 17B when EN = H or VDD <VOUT. Control.

  The switching regulator 1B of FIG. 1B according to the modified example configured as described above also has the same operational effects as the switching regulator 1A of FIG. 1A.

Embodiment 2. FIG.
FIG. 7A is a circuit diagram illustrating a configuration of a switching regulator 1C according to the second embodiment.

  In FIG. 7A, the switching regulator 1C according to the second embodiment is different from the switching regulator 1A in FIG. 1A in that the drains of the PMOS transistors 17Aa and 17Ac are connected to the input terminal 21 without passing through the coil 11. Different.

  According to the switching regulator 1C according to this embodiment configured as described above, the coil 11 having one end connected to the input terminal 21 and the switching connected between the other end of the coil 11 and the ground. The transistor 12 and the synchronous rectification transistor 13 are provided. Here, the switching transistor 12 is driven by the gate signal VG1, and the synchronous rectification transistor 13 is connected between the connection point between the coil 11 and the switching transistor 12 and the output terminal 22, and by the input gate signal VG2. Driven. The switching regulator 1 </ b> C includes a switching control circuit 14. Here, the switching control circuit 14 controls the switching transistor 12 and the synchronous rectification transistor 13 so that the power supply voltage VDD input via the input terminal 21 is converted into a predetermined output voltage VOUT and output from the output terminal 22. To do. Further, the switching regulator 1A is connected in parallel with the series circuit of the synchronous rectification transistor 13 and the coil 11, and is controlled by a through switch circuit 17A controlled by an input gate signal VG3 and through switch control for controlling the through switch circuit 17A. Circuit 18. Here, the through switch control circuit 18 controls the through switch circuit 17A so that the through switch circuit 17A is turned on and the power supply voltage VDD is output to the output terminal 22 in the standby state of the switching regulator 1A.

  This embodiment has the same function and effect as the first embodiment.

  FIG. 7B is a circuit diagram showing a configuration of a switching regulator 1D which is a modification of the switching regulator 1C of FIG. 7A. 7B, the switching regulator 1D is different from the switching regulator 1C in FIG. 7A in that a through switch circuit 17B in FIG. 1B is provided instead of the through switch circuit 17A in FIG. 7A. Here, in FIG. 7B, the through switch control circuit 18 performs on / off control of the through switch circuit 17B in the same manner as the through switch control circuit 18 in FIG. 1B.

  The switching regulator 1D configured as described above also has the same operational effects as the switching regulator 1C of FIG. 7A.

  In the first and second embodiments of the present invention, the switching regulators 1A to 1D are provided in the booster circuit. However, the present invention is not limited to this, and the switching regulators 1A to 1D are used in power supply circuit devices such as a step-down circuit and a step-up / down circuit. It may be provided.

  In the first and second embodiments, the switching regulators 1A to 1D are mounted as integrated circuit devices. However, the present invention is not limited to this, and the switching regulators 1A to 1D may be provided in a semiconductor device such as a semiconductor integrated circuit. .

  Further, in the first and second embodiments, the switching regulators 1A to 1D are provided in the blood pressure monitor. However, the present invention is not limited to this, and the switching regulators 1A to 1D may be provided in the electronic device. Here, the electronic device includes a health device such as a blood pressure monitor, a health device, an MP3 player, a mobile phone, a smartphone, a digital camera, a GPS device, and the like. Further, the power supply circuit device or the semiconductor device including the switching regulators 1A to 1D may be provided in the electronic device.

1A to 1D ... switching regulator,
11 ... Coil,
12 ... switching transistor,
13 ... Synchronous rectification transistor,
14 ... switching control circuit,
15a, 15b ... switching transistors,
16: Back gate control circuit,
17A, 17B: Through switch circuit,
17Aa-17Ac, 17Ba, 17Bb ... PMOS transistors,
18: Through switch control circuit.

JP 2010-081748 A JP 2010-068566 A JP 2010-130826 A

Claims (9)

An element having an inductance component having one end connected to the input terminal;
A switching transistor connected between the other end of the element having the inductance component and the ground and driven by the input first control signal;
A synchronous rectification transistor connected between a connection point between the element having the inductance component and the switching transistor and an output terminal, and driven by an input second control signal;
A switching control circuit that controls the switching transistor and the synchronous rectification transistor so that an input voltage input via the input terminal is converted into a predetermined output voltage and output from the output terminal;
A through switch circuit connected in parallel to the synchronous rectification transistor or a series circuit of the synchronous rectification transistor and the element having the inductance component, and controlled by an input third control signal;
A switching circuit comprising: a through switch control circuit for controlling the through switch circuit so that the through switch circuit is turned on and the input voltage is output to the output terminal in a standby state of the switching regulator. regulator.   2. The switching regulator according to claim 1, wherein the through switch circuit has a current driving capability smaller than that of the synchronous rectification transistor.   3. The switching regulator according to claim 1, wherein the through switch control circuit performs on / off control of the through switch circuit based on a third control signal input from an external circuit.   3. The switching regulator according to claim 1, wherein the through switch control circuit controls a voltage applied to a control terminal of the through switch circuit based on a third control signal input from an external circuit. .   2. A back gate control circuit for controlling a voltage applied to a back gate of the synchronous rectification transistor so that the synchronous rectification transistor is turned off when the through switch circuit is turned on. The switching regulator as described in any one of -4.   A power supply circuit device comprising the switching regulator according to claim 1.   A semiconductor device comprising the switching regulator according to claim 1.   An electronic apparatus comprising the power supply circuit device according to claim 6.   An electronic apparatus comprising the semiconductor device according to claim 7.

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