JP2014230410A - Gate control device of semiconductor element for electric power - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a gate control device of an IEGT, capable of reducing total loss of both of the IEGT turned on and a diode facing the IEGT independently of an operation condition and capable of suppressing a peak current.SOLUTION: The gate control device is comprised of PWM control means 40 and gate driving means 10N. The PWM control means 40 gives delay time corresponding to a PWM signal and an output current value of an inverter to the gate driving means 10N. The gate driving means 10N is comprised of: first driving means for inputting the PWM signal; current detection means 15 for detecting a collector current of an IEGT; comparison means 16 which when the current reaches a threshold, outputs a trigger signal; delay means 17 which when the PWM signal is a turn-on signal, delays the trigger signal by delay time; second driving means for supplying a gate voltage to the IEGT by an output from the delay means 17; and combination means 14 composed of a plurality of resistors or a plurality of resistors and a diode and combines an output from the first driving means with an output from the second driving means.

Description

  The present invention relates to a gate control device for a power semiconductor element having an insulated gate.

  As high-voltage insulated gate semiconductor elements, IGBTs and IEGTs (Injection Enhanced Gate Transistors) are widely used. IGBTs and IEGTs are power semiconductor elements having an insulated gate and capable of controlling high power, and are widely used in electric vehicles, hybrid vehicles, industrial equipment, electric motor drive, and the like.

  In the case of a general gate control device for these power semiconductor elements, for example, a configuration is adopted in which the gate voltage is raised or lowered by a combination of a P-channel MOSFET and an N-channel MOSFET, and the signal to the gate terminal of each MOSFET is: It is usual to receive one gate control signal given through an optical fiber or the like and obtain it through a level shifter or the like. In such a conventional gate control device, a free-wheeling diode (hereinafter simply referred to as “opposing diode”) connected in reverse parallel to the IGBT / IEGT having the same switching leg as the IGBT / IEGT that is turned on and off. ) During reverse recovery, the gate current was controlled by a gate resistance having a fixed resistance value. For this reason, the charge amount of the gate electrode cannot be finely controlled during that time. That is, the transiently changing gate voltage VGE flows into and out of the gate electrode a current other than the current value determined by Ohm's law by the potential difference between the positive gate power supply voltage VGG or the negative gate power supply voltage -VGG and the gate resistance. In particular, the transient operation of power semiconductors could not be finely controlled.

  Several proposals have been made for such problems. For example, by having two pairs of gate drive circuits and delaying the drive timing of one by a predetermined delay time, it is intended to prevent both malfunctions and solve both high dV / dt and high dI / dt problems during switching. (For example, refer to Patent Document 1).

  In addition, a proposal has been made to have an auxiliary circuit for driving the gate, and to capture the characteristic points of the collector voltage and the gate voltage at the time of switching and to operate the auxiliary circuit to reduce the gate resistance value equivalently ( For example, see Patent Document 2).

Japanese Patent Laying-Open No. 2006-340579 (page 9-12, FIG. 1) JP 2009-54639 A (page 3-4, FIG. 3)

  Even in consideration of the above prior art, problems remain for the following reasons. Generally, it is necessary to reduce the gate current to suppress the peak of the collector current at the turn-on (that is, the peak of the reverse recovery current of the opposite diode), but conversely, the collector voltage tail is shortened to reduce the loss. For this purpose, it is necessary to increase the gate current. However, both requirements are incompatible. For this reason, in the conventional proposal, there is not necessarily an effect of reducing the total loss of both the IGBT / IEGT and the opposing diode, and depending on the driving timing of the auxiliary circuit or the like, an excessive current flows to the opposing diode, and the diode is destroyed. There is a risk of inviting. For example, in the method disclosed in Patent Document 1, since the delay time is fixed, the diode may be destroyed due to an increase in the peak current during reverse recovery of the diode relative to the IGBT depending on the operating conditions. Further, according to the technique disclosed in Patent Document 2, the auxiliary circuit cannot be driven except for the above feature points. Therefore, depending on the operating conditions, the total loss including the turn-on loss of IGBT / IEGT and the reverse recovery loss of the opposite diode increases, and it becomes difficult to realize optimal gate driving.

  The present invention has been made in view of the above circumstances, and is a power semiconductor device capable of reducing the total loss of both diodes opposed to IGBT / IEGT at the time of turn-on and suppressing the peak current without depending on the operating conditions. An object is to provide a gate control device.

  In order to achieve the above object, a gate control device for a power semiconductor element according to the present invention includes a PWM control means for generating PWM signals for a plurality of power semiconductor elements constituting an inverter, and each of the power semiconductor elements. A gate control device comprising a plurality of gate driving means for driving the gate of the PWM control means, wherein the PWM control means outputs the PWM signal and a delay time signal corresponding to an output current value or an output current command value of the inverter. Supplying to the gate driving means, each of the gate driving means receives the PWM signal, and detects the collector current of the power semiconductor element and the first driving means for supplying the gate voltage to the power semiconductor element. Current detecting means for performing, a comparing means for outputting a trigger signal when the instantaneous current detected by the current detecting means reaches a predetermined current threshold value, When the WM signal is a turn-on signal, a delay means for outputting a continuous signal delayed from the trigger signal by the delay time, and a second voltage for supplying a gate voltage to the power semiconductor element by using the output of the delay means as inputs. The driving means comprises a plurality of resistors or a plurality of resistors and diodes, and coupling means for coupling the output of the first driving means and the output of the second driving means.

  According to the present invention, it is possible to provide a gate control device for a power semiconductor element capable of reducing the total loss of both diodes facing the IGBT / IEGT at the time of turn-on and suppressing the peak current regardless of the operating conditions. It becomes possible.

The circuit block diagram of the gate control apparatus of the semiconductor element for electric power which concerns on one Example of this invention. The operation | movement timing chart of the gate control apparatus of the semiconductor element for electric power which concerns on one Example of this invention. The internal block diagram which shows an example of the delay means in FIG. The circuit block diagram which shows the example of a drive object of the gate control apparatus of the semiconductor element for electric power which concerns on one Example of this invention. Operation | movement explanatory drawing (collector voltage, collector current, and delay time) of the gate control apparatus of the semiconductor element for electric power which concerns on one Example of this invention. Operation | movement explanatory drawing (inverter electric current command value and delay time) of the gate control apparatus of the semiconductor element for electric power which concerns on one Example of this invention. Operation | movement explanatory drawing (collector voltage and delay time) of the gate control apparatus of the semiconductor element for electric power which concerns on one Example of this invention. The simulation result of the delay time and switching loss of the gate control apparatus of the semiconductor element for electric power which concerns on one Example of this invention. The simulation result of the delay time and peak current of the gate control apparatus of the semiconductor element for electric power which concerns on one Example of this invention. Example of experimental results of collector current peak value and turn-on loss with respect to delay time.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a circuit diagram of a gate control device for a power semiconductor device according to an embodiment of the present invention. In the illustration of the signal system in FIG. 1, the level shifter, the ground side wiring, and the like are omitted. The gate control device shown in FIG. 1 includes a PWM control circuit 40 and a gate drive device 10N, and drives the gate of the power semiconductor element 1N on and off. As will be described in detail later, the PWM control circuit 40 generates a PWM signal 1 for PWM control of the inverter and supplies it to the gate drive device 10N, and at the same time a delay time tdelay setting signal corresponding to the output current value of the inverter. Is generated and supplied to the gate driving device 10N. Here, the PWM control circuit 40 may be considered to include some or all of the main control unit that controls the entire inverter. The inverter output current value may be a current actually detected or a current command value.

  In the gate drive device 10N, the PWM signal 1 is given to the MOSFET drivers 12A and 12B via the on / off discrimination means 11. The outputs of the MOSFET drivers 12A and 12B are connected to the gates of the P-channel MOSFET 13A and the N-channel MOSFET 13B, respectively, to drive the power semiconductor elements. The P-channel MOSFET 13A and the N-channel MOSFET 13B are connected in series, the collector of the P-channel MOSFET 13A is connected to the positive gate power supply, and the emitter of the N-channel MOSFET 13B is connected to the negative gate power supply. Then, the gate of IEGT1N, which is a driving target power semiconductor element, is driven through the gate resistance Rg1 in the coupling circuit 14 from the connection point between the P-channel MOSFET 13A and the N-channel MOSFET 13B.

  The collector current of IEGT1N is detected by the current detection means 15, and the output is given to the comparison means 16. In this embodiment, a current is detected using a Rogowski coil or a current transformer, and in some cases, a signal is sent to the comparison means 16 via a noise filter. In FIG. 1, the current on the emitter side is detected. Since the emitter current and the collector current are basically the same, they are collectively referred to as the collector current. The comparison means 16 is constituted by a circuit using an operational amplifier, and determines whether or not the detected instantaneous current is greater than or equal to a predetermined threshold value. Give a signal. The delay unit 17 receives this trigger signal, the on / off determination signal from the on / off determination unit 11 and the delay time tdelay setting signal. When the PWM signal 1 is an on-gate signal (turn-on signal), a predetermined tdelay 1 time from the trigger signal. A continuous signal is given to the MOSFET driver 18 at a delayed timing. Since the output of the MOSFET driver 18 is connected to the gate of the P-channel MOSFET 19, the P-channel MOSFET 19 is driven by this output. The collector of the P-channel MOSFET 19 is connected to the positive gate power supply, and the emitter is connected to the gate of IEGT1N, which is the element to be driven, via the gate resistance Rg2 in the coupling circuit 14.

  Details of the operation will be described below with reference to an operation timing chart of the gate control device shown in FIG. 2 and an internal configuration diagram showing an example of the delay means shown in FIG. 2A is a timing chart of each signal in the PWM control circuit 40, FIG. 2B is a timing chart of each signal in the gate drive device 10N, and FIG. 2C is a collector voltage of the IEGT 1N. The waveform of collector current is shown. Further, in the first half of the timing chart of FIG. 2, when the collector current command value of IEGT1N is predetermined Ic0 at time t = t01, the latter half of the timing chart of IEGT1N has a predetermined Ic0 at time t = t02. The timing chart when ΔIc increases more is shown. Since the operations of the first half and the second half are basically the same, the operation of the first half will be described below.

  The PWM signal 0 in FIG. 2A is a reference PWM signal, which rises at t = t01 and is a command signal that turns on the IEGT 1N in FIG. 1 by the pulse width of w1. Then, the PWM signal 1 delayed by the wait time with respect to the PWM signal 0 is transmitted to the gate drive device 10N. In addition, a delay time tdelay setting signal set by the PWM control circuit 40 by an operation to be described later is transmitted to the gate driving device 10N at a timing t = t01 as illustrated. Here, the wait time is set by the PWM control circuit 40 by adding a slight margin time to the delay time tdelay1.

  The PWM signal 1 transmitted from the PWM control circuit 40 arrives at the gate drive device 10N with a delay of the transmission delay time flt1, and becomes a drive signal for the MOSFET 13A as shown in FIG. Similarly, the delay time tdelay setting signal arrives at the gate drive device 10N with a delay of the transmission delay time flt1 and is provided to the integrator 171 of the delay means 17 in FIG. 3 as the setting signal of the delay time tdelay. The integrator 171 starts integration simultaneously with the rise of the tdelay setting signal, performs integration for tdelay 1 time, stops the integration, and holds it. The held voltage value is given to the negative terminal of the comparator 173 as ref1. 1 is given as an IEGT ON detection signal to the integrator 172 of the delay means 17, and the integrator 172 integrates during the ON command period of IEGT1N, that is, during the ON period of the MOSFET 13A. I do. The output of the integrator 172 is integrated until the integrator 172 is saturated. The output of the integrator 172 is input to the + side terminal of the comparator 173. When this value reaches the ref1 voltage, the comparator 172 outputs a Hi level, which is given to one input terminal of the AND circuit 174. If the integrator 171 and the integrator 172 have the same integration characteristic, the time from when the trigger signal is given until the output of the integrator 172 reaches the ref1 voltage is tdelay1 time. Since the discrimination signal of the on / off discrimination means 11 is given to the other input terminal of the AND circuit 174, the output of the AND circuit 174 becomes like the drive signal of the MOSFET 19 in FIG. That is, it is possible to obtain a second-stage drive signal that is turned off at the same time as the drive signal of the first-stage MOSFET 13A is turned off by detecting the ON state of IEGT1N and rising after a delay time tdelay1. The transition of the gate voltage of IEGT1N is shown at the bottom of FIG.

  FIG. 4 shows an example of a conversion circuit to which IEGT to be driven is applied. In this example, a single-phase inverter is configured by connecting two sets of switching legs 31 and 32 in parallel with the DC power supply 5. The switching leg 31 has a configuration in which IEGT1P and IEGT1N are connected in series. Diodes 3P and 3N for reflux are connected in reverse parallel to IEGT1P and IEGT1N, respectively. Similarly, the switching leg 32 has a configuration in which IEGT2P and IEGT2N are connected in series, and diodes 4P and 4N for reflux are connected in antiparallel to IEGT2P and IEGT2N, respectively. A load 6 is connected between the midpoints of both switching legs.

  IEGTs 1P, 1N, 2P, and 2N are driven by gate driving devices 10P, 10N, 20P, and 20N, respectively. These gate driving devices are abbreviated as GDM, and the illustration of the PWM control device 40 is omitted. Here, since FIG. 1 shows the gate drive device 10N, the drive target is the IEGT 1N, and the opposing diode is the diode 3P.

  FIG. 5 is a diagram for explaining the operation of the gate driving device for a power semiconductor device according to one embodiment of the present invention, and shows the waveforms of the collector voltage and the collector current at turn-on. Here, Vc0 indicates the voltage of the DC power supply 5, and Ic0 indicates the magnitude of the command value of the inverter output current. Note that Vc is the collector-emitter voltage of IEGT1N, and it may be considered that Vc = Vc0 during a period when IEGT1N is not switching (except for a switching transient period). Similarly, although Ic is the output current of the inverter, it may be considered that Ic = Ic0 is controlled during a period in which IEGT1N is not switching (except for a switching transient period). When a turn-on signal (that is, an on signal of PWM signal 1) is input to the gate drive device 10N shown in FIG. 1, the P-channel MOSFET 13A is turned on via the MOSFET driver 12A, and the MOS of IEGT1N via the gate resistor Rg1. Start charging the gate. When the gate voltage reaches the gate threshold voltage after time Δt0, the conduction of IEGT1N starts. Thereafter, the collector current rises at a substantially constant dIc / dt. In other words, the parasitic inductance L of the circuit composed of the IEGT 1N, the opposing diode 3P, and the DC power source 5, and the value obtained by subtracting the voltage applied to the IEGT from the collector voltage (Vc0 = L · dIc / dt). Due to dt, the collector current increases at a constant dIc / dt. At this time, dIc / dt is substantially proportional to the collector voltage.

  This increase in collector current at a constant di / dt continues beyond the current command value Ic0 to the peak. This is because in order to discharge the charge accumulated in the diode 3P, a recovery current in the direction opposite to the conduction direction of the diode 3P needs to flow temporarily. At this time, if the ratio of the peak value of the collector current to the current command value Ic0 is expressed by α, it is 1.5 to 2.5 for a silicon PN junction diode, and 1.0 to 2.5 for silicon carbide (SiC). 1.2. The reason why SiC has a smaller value of α than that of a silicon diode is that SiC uses a Schottky barrier instead of a PN junction because of material characteristics. In other words, the Schottky barrier diode is a unipolar element, and the charge due to the discharge of the main junction capacitance flows in the reverse direction, but the Schottky barrier diode does not exist in principle in the accumulated carriers in the silicon PN junction diode that is a bipolar element. It is.

In FIG. 5, if the time from the rise of the collector current to the peak value is Δt1,
Δt1 = Ic0 · α / (dIc / dt) (1)
It becomes. Assuming that the current detection threshold in the comparison means 16 is Icth, the time from the current rising detection (excluding detection delay and noise removal time) to the peak current is calculated from the equation (1) as follows.
tdelay = (Ic0 · α−Icth) / (dIc / dt) (2)
It becomes. As will be described later, the timing for turning on the P-channel MOSFET 19 as the second stage gate driving means is preferably in the vicinity of the timing when the collector current by the first stage gate driving means reaches the peak. Therefore, in this embodiment, if the time delay from the detection of the rise of the collector current to the trigger output is ignored, the delay time tdelay until the P-channel MOSFET 19 is turned on is basically given by the above equation (2). However, if there is a time delay that cannot be ignored on the circuit, it is necessary to determine the delay time by subtracting the time delay.

  From the above description, it can be understood that the PWM control circuit 40 can give the delay time tdelay1 to the gate drive device 10N by performing the calculation of the equation (2) for the current command value that changes every moment.

  Next, when the collector voltage Vc is constant (that is, the voltage Vc0 of the DC power supply 5 in FIG. 2 is constant), the waveforms of the collector voltage and the collector current at the turn-on when the current command value Ic0 is changed are shown in FIG. As shown in the figure, it can be seen that when the current command value Ic0 increases, the time when the collector current Ic reaches the peak gradually becomes T1, T2, and T3. Here, since the current command value Ic0 in the equation (2) is the output current of the switching leg 31 to which IEGT1N belongs, that is, the current flowing in the load 6, instead of using the current command value Ic0, the detected value of the output current, that is, the inverter output current Ic As described above, can be used. The inverter output current Ic used here is not an instantaneous value but a current magnitude.

  FIG. 7 shows the waveforms of the collector voltage and collector current at turn-on when the collector voltage Vc0 is changed when the current command value Ic0 is constant. As shown in the figure, when the collector voltage Vc decreases (that is, when the voltage Vc0 of the DC power supply 5 in FIG. 4 decreases), the time at which the collector current Ic reaches the peak is also gradually delayed to T1, T2, T3. = L · dIc / dt. Therefore, if there are operating conditions that change the collector voltage, it is necessary to consider this. Since the normal voltage type inverter device feeds back the DC voltage to the control side and is controlled to be constant, the calculation can be performed by using the DC feedback value.

  FIG. 8 shows the above operation studied by simulation. The simulation conditions are a DC voltage Vc0 = 2250V, a collector current Ic per chip = 30 A, a gate resistance Rg1 = 100Ω, and Rg2 = 2Ω. FIG. 8A shows the delay time for turning on the P-channel MOSFET 19 on a schematic diagram of the waveform of the collector current (the waveform when the delay time is not shown in the figure), FIG. 8B Is a graph of each loss of diode 3P relative to IEGT1N versus delay time, and the sum of these losses as turn-on loss. The numbers plotted in FIG. 8 (a) correspond to the numbers shown in FIG. 8 (b).

  From FIG. 8 (b), it is understood that the turn-on loss of the IEGT decreases and the reverse recovery loss of the diode increases as the timing at which the ON signal is input to the P-channel MOSFET 19 as the second stage gate driving means. Further, it can be seen that the sum of losses decreases as the timing is earlier, but is almost flat when the delay time is about 1.75 us.

  FIG. 9 shows a collector current waveform when the delay time is 1.85 us, 1.90 us, and further 1.95 us. When the timing for turning on the P-channel MOSFET 19 is before the collector current peak (1.85 us), the collector current peak increases and at the same time the reverse recovery current of the diode increases. There is a risk of inducing a phenomenon. For this reason, it is desirable to turn on the P-channel MOSFET 19 after the peak of the collector current.

  Note that by making the gate resistance Rg2 equal to or smaller than the Rg1 with respect to the gate resistance Rg1, the collector voltage can be quickly lowered, and as a result, the IEGT loss can be further reduced.

  FIG. 10 is an experimental result showing the relationship between the turn-on loss of IEGT and the peak value of the collector current with respect to the timing (delay time) at which the P-channel MOSFET 19 is turned on. The conditions in this case are a DC voltage Vc0 = 1000 V, a collector current Ic0 = 30 A per chip, a gate resistance Rg1 = 100Ω, and Rg2 = 30Ω. According to this result, it is understood that when the timing of the gate driving means at the second stage is shifted backward, the peak value of the collector current rapidly decreases, but immediately after that the optimum timing point is obtained. Before this point, the IEGT loss further decreases, but the collector current peak increases, which may cause breakdown, and if shifted further back, the collector current peak value decreases but the turn-on loss increases. Therefore, it is not desirable as a timing for turning on the P-channel MOSFET 19.

  Although the embodiment of the present invention has been described above, this embodiment is presented as an example and is not intended to limit the scope of the invention. The novel embodiment can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  For example, although it has been described in FIG. 1 that the delay time tdelay setting signal is set on the PWM control circuit 40 side and transmitted to the gate driving device 10N, it may be set on the gate driving device 10N side. In this case, it is necessary to give the output current value or output current command value of the inverter to each gate driving device. Further, when the tdelay setting signal is set on the gate drive device 10N side, instead of the output current value or the output current command value of the inverter, the diode immediately before reverse recovery of the opposing diode that occurs simultaneously with the turn-on of the IEGT Even if this current is detected, the same effect can be obtained.

  In addition, although the circuit configuration to which the IEGT to be driven in FIG. 4 is applied is shown as a single-phase inverter, this may be a multi-phase of three or more phases, or a multi-level inverter of two or more levels. Also good. The opposing diode in the case of a multilevel inverter may be a diode through which a reverse recovery current flows when IEGT is turned on.

  Further, although the coupling circuit in FIG. 1 is shown only with a resistor, for example, in applications where the gate resistance at turn-on and the gate resistance at turn-off are changed, a configuration in which a plurality of resistors and diodes are combined may be used.

1P, 1N, 2P, 2N IEGT
3P, 3N, 4P, 4N Diode 5 DC power supply 10P, 10N, 20P, 20N Gate drive device 11 On / off discrimination means 12A, 12B MOSFET driver 13A P-channel MOSFET
13B N-channel MOSFET
14 coupling circuit 15 current detection means 16 comparison means 17 delay means 18 MOSFET driver 19 P-channel MOSFET
31, 32 Switching leg 40 PWM control circuit 171, 172 Integrator 173 Comparator 174 AND circuit

Claims (8)

A gate control device comprising PWM control means for generating PWM signals for a plurality of power semiconductor elements constituting an inverter, and a plurality of gate drive means for driving each gate of the power semiconductor elements,
The PWM control means includes
Supplying the PWM signal and a delay time signal corresponding to the output current value or output current command value of the inverter to the gate driving means;
Each of the gate driving means includes
First driving means for receiving the PWM signal and supplying a gate voltage to the power semiconductor element;
Current detecting means for detecting a collector current of the power semiconductor element;
Comparison means for outputting a trigger signal when the instantaneous current detected by the current detection means reaches a predetermined current threshold;
When the PWM signal is a turn-on signal, delay means for outputting a continuous signal delayed from the trigger signal by the delay time;
Second driving means for taking the output of the delay means as an input and supplying a gate voltage to the power semiconductor element;
A gate of a power semiconductor device comprising a plurality of resistors, or a coupling means comprising a plurality of resistors and a diode and coupling the output of the first driving means and the output of the second driving means Drive device. A gate control device comprising PWM control means for generating PWM signals for a plurality of power semiconductor elements constituting an inverter, and a plurality of gate drive means for driving each gate of the power semiconductor elements,
Each of the gate driving means includes
First driving means for receiving the PWM signal and supplying a gate voltage to the power semiconductor element;
Current detecting means for detecting a collector current of the power semiconductor element;
Comparison means for outputting a trigger signal when the instantaneous current detected by the current detection means reaches a predetermined current threshold;
Delay means for delaying the trigger signal by a delay time corresponding to the output current value or output current command value of the inverter and outputting a continuous signal when the PWM signal is a turn-on signal;
Second driving means for taking the output of the delay means as an input and supplying a gate voltage to the power semiconductor element;
A gate of a power semiconductor device comprising a plurality of resistors, or a coupling means comprising a plurality of resistors and a diode and coupling the output of the first driving means and the output of the second driving means Drive device. A gate control device comprising PWM control means for generating PWM signals for a plurality of power semiconductor elements constituting an inverter, and a plurality of gate drive means for driving each gate of the power semiconductor elements,
Each of the gate driving means includes
First driving means for receiving the PWM signal and supplying a gate voltage to the power semiconductor element;
Current detecting means for detecting a collector current of the power semiconductor element;
Comparison means for outputting a trigger signal when the instantaneous current detected by the current detection means reaches a predetermined current threshold;
When the PWM signal is a turn-on signal, the trigger signal is delayed by a delay time corresponding to the current value of the diode facing the power semiconductor element immediately before the power semiconductor element is turned on, and a continuous signal is output. Delay means;
Second driving means for taking the output of the delay means as an input and supplying a gate voltage to the power semiconductor element;
A gate of a power semiconductor device comprising a plurality of resistors, or a coupling means comprising a plurality of resistors and a diode and coupling the output of the first driving means and the output of the second driving means Drive device.   4. The gate drive of a power semiconductor device according to claim 1, wherein the delay time is changed according to a change in a collector voltage of the power semiconductor device. 5. apparatus.   The delay time is obtained by dividing a value obtained by subtracting a predetermined current threshold value from a value obtained by multiplying the output current value or output current command value of the inverter by a constant α by a value proportional to the DC voltage of the inverter. 3. The gate drive device for a power semiconductor device according to claim 1, wherein the gate drive device is obtained by:   The delay time is a value obtained by subtracting a predetermined current threshold value from a value obtained by multiplying a current value of a diode facing the power semiconductor element of the inverter immediately before the power semiconductor element is turned on by a constant α. 4. The gate drive device for a power semiconductor element according to claim 3, wherein the value is obtained by dividing by a value proportional to a DC voltage of the inverter.   The power semiconductor element according to claim 5 or 6, wherein when the diode facing the power semiconductor element is a silicon diode, the constant α is in the range of 1.5 to 2.5. Gate drive device.   The power semiconductor element according to claim 5 or 6, wherein when the diode facing the power semiconductor element is a SiC diode, the constant α is in the range of 1.0 to 1.2. Gate drive device.

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