JP2014229327A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which improves a current supply capability of a memory cell transistor in a structure that uses a vertical structure transistor as a memory cell transistor.SOLUTION: A semiconductor device includes: a global bit line; a plurality of local bit lines that are selectively connected to the global bit line; a common source line; a plurality of memory cells each of which is provided between the common source line and the plurality of local bit lines and includes a resistance change element and memory cell transistor which are connected in series between the common source line and the plurality of local bit lines; and a word line that is connected in common to a plurality of gates of a plurality of memory cell transistors in a plurality of memory cells; and a plurality of control transistors, to each of whose gates the word line is connected in common and which is constituted so as to form a channel between either sources or drains of respectively corresponding two memory cell transistors which are adjacent to each other.

Description

  The present invention relates to a semiconductor device. In particular, the present invention relates to a semiconductor device including a memory element.

  In Patent Document 1, a resistance change type memory using a vertical transistor is disclosed. As disclosed in Patent Document 1, resistance change type memories such as PRAM (Phase change RAM), ReRAM (Resistance Random Access Memory), and STTRAM (Spin Transfer Torque RAM) are used as resistance change elements (resistance change type memory elements). The information is stored by changing the resistance value according to the flowing current. That is, since data is written by passing a current through the resistance change element, a certain current supply capability is required for the memory cell transistor connected to the resistance change element.

JP2012-080100A

  The disclosure of the above prior art document is incorporated herein by reference. The following analysis was made by the present inventors.

  As described above, the memory cell transistor used in the resistance change type memory is required to have a constant current supply capability. On the other hand, in order to meet the demand for miniaturization of semiconductor memories, the size of memory cell transistors is steadily decreasing. As a result, it is difficult to ensure the current supply capability required for the memory cell transistor.

  According to a first aspect of the present invention, a global bit line, a plurality of local bit lines selectively connected to the global bit line, a word line, the word line, and the plurality of local bit lines A plurality of memory cells each including a memory cell transistor each having a resistance change element connected to a main electrode and a word line connected to a control electrode. A semiconductor device is provided in which the body portions are connected to each other in adjacent memory cell transistors so that the channel portions are connected to each other when the word line is in an active state.

  According to one aspect of the present invention, there is provided a semiconductor device that contributes to improving the current supply capability of a memory cell transistor in a structure using a vertical transistor as a memory cell transistor.

2 is a diagram illustrating an example of an internal configuration of a memory cell array 11 according to the first embodiment. FIG. 1 is a diagram illustrating an example of a configuration of a semiconductor device 10 according to a first embodiment. FIG. 8 is a layout diagram in which the memory cells 32-1 to 32-8 shown in FIG. 1 and their peripheral circuit configurations are formed by so-called planar type transistors. FIG. 8 is a structural diagram in which the memory cells 32-1 to 32-8 shown in FIG. 1 and their peripheral circuit configurations are formed by so-called vertical transistors, and a cross section in the word line WL direction of the memory cells 32-1 to 32-8 is shown. FIG. 3 is a diagram showing an example of another internal configuration of the memory cell array 11. FIG.

  An outline of one embodiment will be described. As shown in FIG. 1, the semiconductor device includes a global bit line (for example, global bit line GBL0) and a plurality of local bit lines (for example, local bit lines LBL0 to LBL7) selectively connected to the global bit line. The common source line (for example, the common source line SL) is provided between the common source line and the plurality of local bit lines, and each is connected in series between the common source line and the plurality of local bit lines. A plurality of memory cells (for example, reference numeral 32 in FIG. 1) each including a variable resistance element (for example, reference numeral 34 in FIG. 1) and a memory cell transistor (for example, reference numeral 35 in FIG. 1), and a plurality of memory cells And a word line (for example, word line WL0) connected in common to a plurality of gates of the plurality of memory cell transistors, and A plurality of control transistors (for example, as shown in FIG. 1) are connected in common, and are formed to form a channel between one of the sources and drains of two adjacent memory cell transistors corresponding to each other. Reference numeral 33).

  In the semiconductor device according to the embodiment, the memory cell transistors that constitute the memory cells sharing the global bit line among the plurality of memory cells have channels formed in the memory cell transistors in response to activation of the word lines. It has a configuration to connect. Of the plurality of memory cells sharing the global bit line, one memory cell is selected by the word line and is to be accessed. In other words, among the memory cells that share the global bit line, memory cells that are not selected by the word line are excluded from access targets. Therefore, in the semiconductor device according to the embodiment, not only the memory cell transistor included in the memory cell to be accessed, but also the memory cell transistor included in the memory cell that is excluded from the access target is used. Current is passed through the change element. That is, the current supply capability of the memory cell transistor when writing data to the variable resistance element can be increased.

  Hereinafter, specific embodiments will be described in more detail with reference to the drawings.

[First Embodiment]
The first embodiment will be described in detail with reference to the drawings.

  FIG. 2 is a diagram illustrating an example of the configuration of the semiconductor device 10 according to the first embodiment. A memory cell array 11 shown in FIG. 2 includes a plurality of resistance change memory cells arranged two-dimensionally. Each memory cell includes a resistance change element (reference numeral 34 shown in FIG. 1) and a memory cell transistor (reference numeral 35 shown in FIG. 1). Each resistance change element stores either a high resistance state “0” or a low resistance state “1”, and functions as a nonvolatile memory element.

  The semiconductor device 10 selects a memory cell and performs three operations: SET writing for changing the high resistance state to the low resistance state, RESET writing for changing the low resistance state to the high resistance state, and reading of the resistance state. In FIG. 2, blocks other than the memory cell array 11 control the above three operations for the memory cell array 11.

  The address input circuit 12 inputs an address ADD of a memory cell to be accessed. The address latch circuit 13 latches the input address ADD and separates it into a row address ADD_ROW and a column address ADD_COLUMN.

  The address latch circuit 13 outputs the row address ADD_ROW to the row control circuit 14 and the column address ADD_COLUMN to the column control circuit 15. The address latch circuit 13 may receive the row address ADD_ROW and the column address ADD_COLUMN in a time division manner.

  The row control circuit 14 includes a row decoder (not shown) and decodes a row selection signal from the row address ADD_ROW. Of the plurality of word lines WL, the word line WL selected by the row selection signal is activated.

  The column control circuit 15 includes a column decoder (not shown), and decodes the column selection signal YJ from the column address ADD_COLUMN. The column control circuit 15 outputs a column selection signal YJ to the memory cell array 11. The bit line BL selected by the column selection signal YJ is activated.

  The clock input circuit 16 receives complementary external clock signals CK and / CK supplied to the semiconductor device 10 from the outside, and generates an internal clock ICLK. The clock input circuit 16 supplies the generated internal clock ICLK to the timing generator 17.

  The timing generator 17 generates various timing signals necessary for the operation of the semiconductor device 10 based on the internal clock ICLK, and supplies the various timing signals to each unit (not shown). In this specification, the signal name “/” indicates that the signal is active at a low level.

  The data input / output terminal DQ is connected to the input / output circuit 18, and the write data is taken into the input / output circuit 18 in response to the write data being input to the data input / output terminal DQ. The input / output circuit 18 is connected to a read / write amplifier (RWAMP) 19. The read / write amplifier 19 outputs write data to the global bit line GBL that extends the memory cell array 11. The read / write amplifier 19 inputs data read from the memory cell via the global bit line GBL, amplifies the data, and outputs the amplified data to the input / output circuit 18. The input / output circuit 18 outputs the data amplified by the read / write amplifier 19 from the data input / output terminal DQ.

  The command input circuit 20 inputs a row address strobe signal / RAS, a column address strobe signal / CAS, a write enable signal / WE, and the like as control signals.

  The command decode circuit 21 decodes these control signals and outputs control signals necessary for executing the decoded command to each unit in the semiconductor device 10. The command decode circuit 21 supplies a program (write) command signal PROG or a read command signal READ to the row control circuit 14 and the column control circuit 15 based on the decoding result of the control signal.

  The row control circuit 14 and the column control circuit 15 select a memory cell to be accessed by an address signal (row address ADD_ROW, column address ADD_COLUMN) supplied together with the program command signal PROG or the read command signal READ. At the time of data programming, data amplified by the read / write amplifier 19 is written into the selected memory cell via the global bit line GBL and the local bit line LBL. On the other hand, when reading data, data read from the memory cell is read after being amplified by the read / write amplifier 19 via the local bit line LBL and the global bit line GBL.

  The internal power supply generation circuit 22 receives power supply VDD and VSS supplied from the outside, generates voltages VPP, VREAD, VSET, VRESET, VSL, VPERI and the like necessary for each part in the semiconductor device 10 and supplies them to each part. .

  The voltage VREAD is used when a sense amplifier (not shown) applies a predetermined voltage to the selected bit line BL and reads the resistance change of the resistance change element. The voltage VSET is supplied to the read / write amplifier 19 and used during SET writing. The voltage VRESET is supplied to the read / write amplifier 19 and used at the time of RESET writing. The voltage VSL is used when precharging the global bit line GBL and the local bit line LBL via the common source line SL. The voltage VPERI is used as a power source for peripheral circuits of the memory cell array 11.

  Next, the internal configuration of the memory cell array 11 will be described.

  FIG. 1 is a diagram illustrating an example of the internal configuration of the memory cell array 11. Referring to FIG. 1, the memory cell array 11 includes a plurality of Y switch circuits 30-1 to 30-8, a plurality of precharge circuits 31-1 to 31-8, and a plurality of memory cells 32-1 to 32-8. And a plurality of coupled transistors 33-1 to 33-7. In the following description, when there is no particular reason for distinguishing the Y switch circuit, it is expressed as “Y switch circuit 30”. The same notation is applied to the precharge circuit, the memory cell, the connection transistor, the resistance change element, and the memory cell transistor.

  Each memory cell 32 included in the memory cell array 11 is selected by a word line WL and a bit line BL. The bit line BL used for selecting the memory cell 32 is hierarchized into a global bit line GBL and a local bit line LBL. For example, in FIG. 1, one of the local bit lines LBL0 to LBL7 is selected and connected to the global bit line GBL0.

  As described above, in the memory cell array 11, a plurality of global bit lines GBL are wired, and any one of the plurality of local bit lines LBL is selectively connected to each global bit line GBL.

  The Y switch circuit 30 is a switch circuit provided between the global bit line GBL and the plurality of local bit lines LBL. The Y switch circuit 30 functions as a switch that switches connection between the global bit line GBL and the plurality of local bit lines LBL. The Y switch circuit 30 is composed of, for example, an N-channel MOS transistor or the like, and receives a column selection signal YJ at its gate terminal (control electrode). For example, in FIG. 1, if the column selection signal YJ0 is in the active state and the column selection signals YJ1 to YJ7 are in the inactive state, the Y switch circuit 30-1 is turned on and the global bit line GBL0 and the local bit line LBL0 are connected. The In this way, each Y switch circuit 30 is turned on in response to the column selection signal YJ that switches connection of the plurality of local bit lines LBL to the global bit line GBL. The column selection signals YJ corresponding to the respective Y switch circuits 30 are independent selection signals.

  The precharge circuit 31 is a circuit connected to each of the plurality of local bit lines LBL. The precharge circuit 31 is a circuit that precharges the potential of the global bit line GBL and the local bit line LBL to the voltage VSL. The precharge circuit 31 is configured by, for example, an N-channel MOS transistor and receives a precharge signal YB at its gate terminal. Each precharge circuit 31 connects the global bit line GBL and the local bit line LBL by connecting the local bit line LBL and the common source line SL that supplies the voltage VSL in response to the activation of the precharge signal YB. Precharge to voltage VSL. The precharge signal YB is a signal that is activated when the column selection signal YJ is inactive (when the Y switch circuit 30 is not selected). That is, the precharge circuit 31 becomes conductive when any of the Y switch circuits 30 is not selected.

  In FIG. 1, the word line WL and the local bit line LBL are selected by various control signals generated by the row control circuit 14 and the column control circuit 15. Memory cells 32 are respectively provided between the word line WL and the plurality of local bit lines LBL. After the word line WL and the local bit line LBL are selected, the memory cell 32 located at the intersection is accessed. It becomes.

  The memory cell 32 includes a resistance change element 34 and a memory cell transistor 35. The first main electrode (one of the source terminal and the drain terminal) of the memory cell transistor 35 is connected to the resistance change element 34, the second main electrode (the other one of the source terminal and the drain terminal) is connected to the common source line SL, and the control electrode ( Gate terminals) are respectively connected to the word lines WL. As described above, the memory cells 32 are provided between the common source line SL and the plurality of local bit lines LBL, respectively, and are connected in series between the common source line SL and the plurality of local bit lines LBL. A resistance change element 34 and a memory cell transistor 35 are provided.

  When writing data in each memory cell 32, the word line WL corresponding to the memory cell 32 to which data is to be written is selected, so that the memory cell transistor 35 is turned on. Further, a write operation is performed by applying a write voltage between the common source line SL and the local bit line LBL and causing a current to flow through the resistance change element 34.

  More specifically, when data “0” is written in the memory cell 32, a low-potential voltage VRESET is applied to the global bit line GBL. On the other hand, when writing data “1” in the memory cell, a high-potential voltage VSET is applied to the global bit line GBL. Note that when data is written to the memory cell, the voltage applied to the global bit line GBL is switched by controlling the read / write amplifier 19. The read / write amplifier 19 receives the voltages VRESET and VSET, and changes the voltage supplied to the global bit line GBL corresponding to the data to be written.

  Further, the voltage VREAD is applied to the resistance change element 34, and the resistance state (low resistance state or high resistance state) of the resistance change element 34 is determined by the current flowing at that time, thereby reading data from the memory cell 32.

  The connection transistor 33 is a transistor for connecting the body portions of the memory cell transistors 35 included in the adjacent memory cells 32 to each other. For example, the connection transistor 33-1 connects the body part of the memory cell transistor 35-1 and the body part of the memory cell transistor 35-2. As described above, the connection transistor 33 functions as a connection portion that connects the body portions of the memory cell transistors 35 included in the adjacent memory cells 32.

  The range of the memory cells 32 to which the coupling transistor 33 is connected is limited to a plurality of memory cells 32 that can be selected by a specific global bit line GBL and a specific word line WL. In other words, the body portions of the memory cell transistors 35 included in the memory cells 32 sharing the global bit line GBL and the word line WL among the plurality of memory cells 32 are connected to each other. For example, the memory cells 32-1 to 32-8 are connected to each other by the connecting transistors 33-1 to 33-7, but are not connected to other memory cells (for example, the memory cell 32-9). That is, the body portions of the memory cell transistors included in the memory cell 32 that does not share the global bit line GBL and the word line WL among the plurality of memory cells 32 are not connected to each other.

  The gate terminal of each connection transistor 33 is connected to the corresponding word line WL. Therefore, when the corresponding word line WL is activated, the connection transistor 33 becomes conductive. That is, when the corresponding word line WL is activated, a channel is formed in the body portion of the connection transistor 33. Further, when the word line WL is activated, a channel is also formed in the body portion of the memory cell transistor 35. Furthermore, as will be described later, the body portion (silicon pillar) of the memory cell transistor 35 included in the plurality of memory cells 32 sharing the global bit line GBL and the word line WL is formed as one pillar. Accordingly, the body portion in each memory cell transistor 35 can be regarded as connecting memory cell transistors 35 adjacent to each other so that the channel portions are connected when the word line WL is in an active state. In FIG. 1, when the word line WL0 is activated, the connection transistors 33-1 to 33-7 are turned on to connect the body portions of the memory cell transistors 35.

  In this way, each of the connection transistors 33 has a common word line WL connected to each gate, and a channel between one of the sources and drains of the two adjacent memory cell transistors 35 corresponding thereto. Configured to form. Therefore, one of the source and the drain in the two memory cell transistors 35 adjacent to each other is electrically connected to each other via the channel of the connection transistor 33 when the word line WL is in an active state, and the word line WL is in an inactive state. At this time, the connection transistor 33 becomes electrically independent depending on the fact that the channel is not formed. If the corresponding word line WL is in an inactive state, the connecting transistor 33 is not conducted, and the body portions of the memory cell transistors 35 in the memory cell 32 are not connected to each other.

  Note that not only the bit lines BL but also the word lines WL may be hierarchized. In that case, the word line WL is hierarchized into a main word line and a sub word line, and the memory cell 32 is selected using a main word driver (not shown) or a sub word driver (not shown).

  FIG. 3 is a layout diagram in which the memory cells 32-1 to 32-8 shown in FIG. 1 and their peripheral circuit configurations are formed of so-called planar type transistors. In this configuration, the source, channel, and drain of each transistor are arranged so as not to overlap in a plane. The present invention can be configured using such a planar type transistor.

  On the other hand, FIG. 4 is a structural diagram in which the above circuit configuration is formed by so-called vertical transistors, and is a diagram showing a cross section in the word line WL direction in the memory cells 32-1 to 32-8 shown in FIG. In this configuration, the source, channel (and body), and drain of each memory cell transistor 35 overlap in a plane and are arranged in a direction perpendicular to the semiconductor substrate. Further, the connection transistor 33 is formed so as to form a channel between one of the source and drain of two memory cell transistors 35 adjacent to each other, that is, like a planar type transistor. Note that in FIG. 3 and FIG. 4, circuit symbols of transistors are illustrated for easy understanding.

  Referring to FIG. 3, the N-type diffusion layer 102 forming the memory cell transistor 35 is electrically connected to one end of the variable resistance element 34 through the first contact 103. Furthermore, the other end of the resistance change element 34 is electrically connected to the local bit line LBL. The N-type diffusion layer 101 forming the memory cell transistor 35 is electrically connected to the common source line SL via the second contact 104. Further, the gate terminal of the memory cell transistor 35 is electrically connected to the corresponding word line WL. Note that a channel is formed in a region sandwiched between the N-type diffusion layers 101 and 102. Further, a connection transistor 33 is formed between nodes on the local bit line LBL side adjacent to each other of each memory cell transistor 35. In this way, each transistor in FIG. 3 is arranged in a plane.

  Referring to FIG. 4, each memory cell transistor is formed in a direction perpendicular to the semiconductor substrate, and the body portion of the memory cell transistor 35 is mutually connected by the connecting transistor 33 formed between the N-type diffusion layers 102 as a part of each memory cell transistor. It is formed so as to be electrically connected. That is, the N-type diffusion layer 101 is stacked on the substrate 106, and the silicon pillar 107 is formed as one pillar common to each memory cell transistor 35. On the silicon pillar 107, a plurality of N-type diffusion layers 102 are formed corresponding to the plurality of resistance change elements 34, respectively, and the silicon pillar 107 is formed so that the upper surface of the body portion is substantially flat. . As a result, the body portion is shared via the connection transistor 33 between the plurality of memory cell transistors 35 sharing the global bit line GBL and the word line WL. A gate electrode (not shown) is disposed on both sides of the silicon pillar 107 with a predetermined interval (via a gate oxide film), and is electrically connected to the corresponding word line WL0. Although the formation difficulty in the process is high, the size of the semiconductor device can be reduced by forming in this way.

  Note that the body parts of the memory cell transistors 35 are connected to only the memory cell transistor 35 that shares the global bit line GBL and the word line WL, and does not share either the global bit line GBL or the word line WL. The memory cell transistors 35 are not connected to each other. In other words, one of the source and drain of the memory cell transistors 35 arranged adjacent to each other (for example, the memory cell transistor 35 connected to the word line WL0) and another memory cell transistor 35 having a different word line WL connected thereto. One of the source and the drain of the memory cell transistor 35 (for example, the memory cell transistor 35 connected to a word line WL other than the word line WL0) is electrically independent regardless of which word line WL is activated.

  Next, the operation of the semiconductor device 10 will be described with reference to FIG. Here, an operation when data “1” is written in the memory cell 32-4 shown in FIG. 1 will be described.

  First, the row decoder included in the row control circuit 14 activates the word line WL to which the memory cell 32 to be accessed is connected based on the row address ADD_ROW supplied from the address latch circuit 13. Here, since the memory cell 32-4 is a memory cell to be accessed, the word line WL0 changes to the active state. When the word line WL0 is activated, the memory cell transistors 35-1 to 35-8 and the connection transistors 33-1 to 33-7 connected to the word line WL0 are turned on.

  Next, the column decoder included in the column control circuit 15 decodes the column selection signal YJ from the column address ADD_COLUMN supplied from the address latch circuit 13. Here, the column selection signal YJ3 is activated, and the other column selection signals YJ remain inactive. When the column selection signal YJ3 is activated and the other column selection signals YJ are deactivated, the Y switch circuit 30-4 is turned on and the other Y switch circuits 30 are turned off.

  Thereafter, the voltage VSET is supplied to the global bit line GBL in order to write the data “1”. Here, the voltage VSET is supplied to the global bit line GBL0. Since the Y switch circuit 30-4 is conductive, a current flows through the resistance change element 34-4 via the global bit line GBL0 and the local bit line LBL3. At that time, the connection transistors 33-1 to 7-3 are turned on in response to the activation of the word line WL0. That is, a current flows through the resistance change element 34-4 not only through the memory cell transistor 35-4 but also through the connection transistors 33-1 to 3-7 and the other memory cell transistors 35-1 to 35-3, 5-8. . Thus, by making many memory cell transistors 35 into a conduction | electrical_connection state, sufficient electric current for changing the resistance state of the resistance change element 34 (here resistance change element 34-4) is securable.

  As described above, the semiconductor device 10 according to the first embodiment pays attention to the fact that one local bit line LBL is selected for one global bit line GBL, and the unselected local bit line LBL. The current supply capability of the memory cell transistors corresponding to the above is aggregated to improve the current supply capability.

  Note that when data “0” is written to the memory cell 32, the basic operation is the same, only the direction of current flow is reversed compared to when data “1” is written. Therefore, further explanation is omitted.

  Here, in order to increase the amount of current flowing through the resistance change element 34, the configuration of the memory cell array 11 may be as shown in FIG. Each memory cell 32 shown in FIG. 5 has a configuration in which the memory cells 32 are connected to each other without the connection transistor 33. In FIG. 5, the same components as those in FIG. 1 are denoted by the same reference numerals, and the description thereof is omitted.

  Here, in the configuration of the memory cell array 11 shown in FIG. 5, there is a possibility of current sneaking through the memory cells 32 belonging to the non-selected word line WL. The design of the memory cell array 11 and the resistance change element 34 Although it is employed only in a range where there is no problem in characteristics, in the configuration shown in FIG. 1, current wraparound can be prevented by the connecting transistor 33 provided between the memory cells 32.

  For example, in the configuration of FIG. 5, a case where the word line WL0 and the column selection signal YJ3 are in the active state is considered as in the case described above. In this case, the current flowing from the global bit line GBL0 to the local bit line LBL3 is also transmitted to the local bit line LBL2 via the memory cells 32-10 and 32-11. On the other hand, in the configuration shown in FIG. 1, since the connection transistor 33-8 formed between the memory cell 32-10 and the memory cell 32-11 is not conducted, no current flows into the local bit line LBL2.

  The disclosure of the cited patent document is incorporated herein by reference. Within the scope of the entire disclosure (including claims) of the present invention, the embodiments and examples can be changed and adjusted based on the basic technical concept. Various disclosed elements (including each element of each claim, each element of each embodiment or example, each element of each drawing, etc.) within the scope of the claims of the present invention, Selection is possible. That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea. In particular, with respect to the numerical ranges described in this document, any numerical value or small range included in the range should be construed as being specifically described even if there is no specific description.

DESCRIPTION OF SYMBOLS 10 Semiconductor device 11 Memory cell array 12 Address input circuit 13 Address latch circuit 14 Row control circuit 15 Column control circuit 16 Clock input circuit 17 Timing generator 18 Input / output circuit 19 Read / write amplifier (RWAMP)
20 Command input circuit 21 Command decode circuit 22 Internal power supply generation circuit 30, 30-1 to 30-8 Y switch circuit 31, 31-1 to 31-8 Precharge circuit 32, 32-1 to 32-11 Memory cell 33, 33-1 to 33-8 connected transistor 34, 34-1 to 34-8 variable resistance element 35, 35-1 to 35-8 memory cell transistor 101, 102 N-type diffusion layer 103 first contact 104 second contact 105 field 106 Substrate 107 Silicon pillar

Claims (8)

Global bit lines,
A plurality of local bit lines selectively connected to the global bit line;
A common source line;
A resistance change element and a memory cell transistor, each provided between the common source line and the plurality of local bit lines, each connected in series between the common source line and the plurality of local bit lines; A plurality of memory cells;
A word line commonly connected to a plurality of gates of the plurality of memory cell transistors in the plurality of memory cells;
A plurality of controls configured to form a channel between one of the sources and drains of two adjacent memory cell transistors corresponding to each other, the word line being commonly connected to each gate. A semiconductor device comprising: a transistor;   2. One of the source and drain of the two adjacent memory cell transistors is electrically connected to each other through a channel of the control transistor when the word line is in an active state. Semiconductor device.   One of the source and drain in the two memory cell transistors adjacent to each other is electrically independent when the word line is in an inactive state according to the fact that the channel of the control transistor is not formed. The semiconductor device according to claim 2. Other resistance change elements and other memories provided between the common source line and the plurality of local bit lines, each connected in series between the common source line and the plurality of local bit lines. A plurality of other memory cells comprising cell transistors;
Another word line commonly connected to a plurality of gates of the plurality of other memory cell transistors in the plurality of other memory cells;
The other word line is commonly connected to each gate, and a channel is formed between one of the sources and drains of the two other memory cell transistors adjacent to each other. The semiconductor device according to claim 1, further comprising a plurality of other control transistors.   One of the source and drain of the memory cell transistor and one of the source and drain of the other memory cell transistor arranged adjacent to each other is activated when the word line is activated or the other word line is activated. 5. The semiconductor device according to claim 4, wherein the semiconductor device is electrically independent in any case.   6. The plurality of memory cell transistors are vertical structure transistors formed such that the sources and drains are arranged in a direction substantially perpendicular to a substrate, respectively. Semiconductor device. A plurality of switch circuits provided respectively between the global bit line and the plurality of local bit lines;
The semiconductor device according to claim 1, wherein the plurality of switch circuits are turned on according to selection signals corresponding to each other. A plurality of precharge circuits respectively connected to the plurality of local bit lines;
8. The semiconductor device according to claim 7, wherein the plurality of precharge circuits are turned on when all of the plurality of switch circuits are not selected.

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