JP2014216363A - Field effect transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress falling, at a high temperature, of a drain current of a depletion type field effect transistor that uses a nitride semiconductor.SOLUTION: A field effect transistor includes a first barrier wall layer 102 comprising a second nitride semiconductor in which a main surface is a (0001) surface, a second barrier wall layer 105 and a third barrier wall layer 106 which have a layer thickness of 1.5-5 nm, and are formed on the first barrier wall layer 102 of a source formation region 122 and a drain formation region 123 which sandwich a gate formation region 121, being made from a third nitride semiconductor having a larger band gap energy than the seconde nitride semiconductor, and a fourth barrier wall layer 107 and a fifth barrier wall layer 108 which are formed over them and made from the second nitride semiconductor containing an impurity introduction region 171 and an impurity introduction region 181 on its lower side. The layer thickness of the first barrier wall layer 102 of the gate formation region 121 is a thickness to form a secondary electron in the first barrier wall layer 102 of the gate formation region 121.

Description

  The present invention relates to a depletion type field effect transistor using a nitride semiconductor.

  An example of a field effect transistor (FET) using a nitride semiconductor is a heterostructure field effect transistor (HFET). This nitride semiconductor FET is very promising as a next-generation high-temperature / high-output / high-voltage high-frequency transistor, and is actively researched for practical use. Nitride semiconductor FETs are usually formed in the + c plane ((0001) plane) direction, which is the polar plane direction, and since there is a large polarization charge at the hetero interface, doping processing for supplying carriers is generally performed. Even if not, carriers contributing to conduction are induced in the channel as channel electrons (two-dimensional electrons).

  The nitride semiconductor FET having such a feature has an advantageous aspect that a large current is easily obtained. On the other hand, as a device operation, in general, a so-called depletion type (or no-node) having a negative threshold value is used. Suitable for device operation of (Mary-on type). That is, even when no voltage is applied to the gate electrode (that is, when the gate voltage is zero), the drain current flows by applying the drain voltage, and by applying a negative voltage to the gate electrode, the drain current becomes zero. This is suitable for the transistor operation of becoming (that is, pinching off).

  For this reason, a so-called enhancement-type (normally-off type) device operation with a positive threshold, which is a device operation contrary to this, can be realized in a GaN-based heterostructure field effect transistor (HFET) ( As a general nitride semiconductor FET, it is not easy to realize and disadvantageous in this respect.

M. A. Khan et al., "Enhancement and depletion mode GaN / AlGaN heterostructure field effect transistors", Appl. Phys. Lett., Vol.68, no.4, pp.514-516, 1996. N. MAEDA et al., "Superior Pinch-Off Characteristics at 400 ℃ in AlGaN / GaN Heterostructure Field Effect Transistors", Jpn. J. Appl. Phys., Vol. 38, pp. L987-L989, 1999. N. MAEDA et al., "High-Temperature Characteristics in Normally Off AlGaN / GaN Heterostructure Field-Effect Transistors with Recessed-Gate Enhanced-Barrier Structures", Appl. Phys. Express, vol.5, 084201, 2012.

  By the way, one of the attractions of nitride semiconductor devices is that they can be used in high-temperature environments because of the heat resistance characteristics of nitride semiconductors. However, since the electron mobility decreases at high temperatures, there is a disadvantage in device operation that the drain current is greatly decreased (Non-patent Document 2). For this reason, in field effect transistors using nitride semiconductors, it has been strongly desired to develop a device with a small decrease in drain current even at high temperatures.

  The present invention has been made to solve the above-described problems, and is intended to suppress a decrease in the drain current of a depletion type field effect transistor using a nitride semiconductor at a high temperature. Objective.

  The field effect transistor according to the present invention includes a channel layer made of a first nitride semiconductor having a main surface of (0001) plane and a second nitride semiconductor having a band gap energy larger than that of the first nitride semiconductor. A first barrier layer formed thereon, a gate electrode formed on the first barrier layer via a gate insulating layer, and a source formation region and a drain formation region sandwiching the gate formation region in which the gate electrode is formed A second barrier layer and a third barrier layer formed of a third nitride semiconductor having a band gap energy larger than that of the second nitride semiconductor and having a thickness of 1.5 to 5 nm. A fourth barrier layer and a fifth barrier layer made of a second nitride semiconductor formed on the second barrier layer and the third barrier layer and having an n-type impurity introduced on the second barrier layer and third barrier layer sides; barrier And a source electrode and a drain electrode formed on the fourth barrier layer and the fifth barrier layer, and the layer thickness of the first barrier layer in the gate formation region is two-dimensional in the first barrier layer in the gate formation region. The thickness is such that electrons are formed.

  In the field effect transistor, the thickness of all barrier layers in the source formation region and the drain formation region may be in the range of 10 nm to 100 nm, and the gate insulating layer may have a thickness of 2 nm to 100 nm.

In the field effect transistor, the combination of the semiconductor material of the second nitride semiconductor / first nitride semiconductor is Al _X Ga _1-X N / GaN (0 <X <1), Al _X1 Ga _1-X1 N / In. _{X2 Ga 1-X2 N (0} <X1 <1,0 ≦ X2 ≦ 1), Al X1 Ga 1-X1 N / Al X2 Ga 1-X2 N (0 <X1 <1,0 ≦ X2 <1, X1> _{X2), GaN / In X Ga} 1-X N (0 <X ≦ 1), In X1 Ga 1-X1 N / In X2 Ga 1-X2 N (0 ≦ X1 <1,0 <X2 ≦ 1, X1 < _{X2), In X Al 1-} X N / GaN (0 ≦ X <0.5), In X1 Al 1-X1 N / Al X2 Ga 1-X2 N (0 ≦ X1 <0.5,0 ≦ X2 < 1, X1 + X2 <1), In _X1 Al _{1 -X1} N / In _X2 Ga _{1 -X2} N (0 ≦ X1 <1, 0 ≦ X2 ≦ 1) may be used.

In the field effect transistor, the combination of the third nitride semiconductor / second nitride semiconductor is Al _X1 Ga _{1 -X1} N / Al _X2 Ga _{1 -X2} N (0 <X1 ≦ 1, 0 ≦ X2 <1, X1 _{> X2), In X1 Al 1} -X1 N / Al X2 Ga 1-X2 N (0 ≦ X1 <0.5,0 ≦ X2 <1, X1 + X2 <1), Al X Ga 1-X N / GaN (0 <X ≦ 1), In _X Al _1-X N / GaN (0 ≦ X <0.5), Al _X1 Ga _1-X1 N / In _X2 Ga _1-X2 N (0 <X1 ≦ 1, 0 ≦ X2 ≦ 1), GaN / In _X Ga _1-X N (0 <X ≦ 1), In _X1 Ga _1-X1 N / In _X2 Ga _1-X2 N (0 ≦ X1 <1, 0 <X2 ≦ 1, X1 <X2), In _X1 Al _1-X1 N / In _X2 Ga _1-X2 N (0 ≦ X1 <1, 0 ≦ X2 ≦ 1), In _X1 Al _1-X1 N / In _X2 Al _1-X2 N (0 ≦ X1 <X2 ≦ 1) It is sufficient to.

  As described above, according to the present invention, it is possible to obtain an excellent effect that a decrease in drain current at a high temperature of a depletion type field effect transistor using a nitride semiconductor can be suppressed.

FIG. 1 is a cross-sectional view showing a configuration of a field effect transistor according to an embodiment of the present invention. FIG. 2 is an explanatory diagram showing potential shapes and electron distribution states in the source formation region 122 and the gate formation region 121. FIG. 3 is a band diagram showing a band gap state in a field effect transistor having a recessed gate structure. FIG. 4 is an explanatory diagram showing the potential shape and the electron distribution at a high temperature in the source formation region 122 and the gate formation region 121. FIG. 5 is a cross-sectional view showing a configuration example of an enhancement type field effect transistor using a nitride semiconductor.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view showing a configuration of a field effect transistor according to an embodiment of the present invention. This field effect transistor includes a channel layer 101 made of a first nitride semiconductor having a main surface of (0001) plane, and a channel layer 101 made of a second nitride semiconductor having a larger band gap energy than the first nitride semiconductor. The first barrier layer 102 formed on the first barrier layer 102 and the gate electrode 104 formed on the first barrier layer 102 with the gate insulating layer 103 interposed therebetween.

  The field effect transistor is formed on the first barrier layer 102 in the source formation region 122 and the drain formation region 123 across the gate formation region 121 where the gate electrode 104 is formed, and is larger than the second nitride semiconductor. A second barrier layer 105 and a third barrier layer 106 made of a third nitride semiconductor having a band gap energy and having a layer thickness of 1.5 to 5 nm are provided.

  The field effect transistor includes a fourth barrier layer 107 and a fifth barrier layer 108 made of a second nitride semiconductor formed on the second barrier layer 105 and the third barrier layer 106, and a fourth barrier layer 107. And a source electrode 109 and a drain electrode 110 formed on the fifth barrier layer 108. Here, in the embodiment, the fourth barrier layer 107 and the fifth barrier layer 108 include an impurity introduction region 171 in which an n-type impurity is introduced on the second barrier layer 105 and the third barrier layer 106 side, and an impurity introduction. A region 181 is provided.

  The layer thickness of the first barrier layer 102 in the gate formation region 121 is set to a thickness at which two-dimensional electrons are formed in the first barrier layer 102 in the gate formation region 121. Therefore, this field effect transistor is a so-called depletion type (normally on type). In the embodiment, the thickness of the first barrier layer 102 in the gate formation region 121 is equal to or less than the thickness of the first barrier layer 102 in the source formation region 122 and the drain formation region 123, and a so-called recess gate structure is employed.

  In the field effect transistor according to the above-described embodiment, as shown in FIG. 2, the electron transport includes a process exceeding the potential step formed at the boundary between the source formation region 122 and the gate formation region 121. Become. FIG. 2 is an explanatory diagram showing potential shapes and electron distribution states in the source formation region 122 and the gate formation region 121. In FIG. 2, the boundary between the source formation region 122 and the gate formation region 121 is illustrated as an example, and although not illustrated, the same is true between the gate formation region 121 and the drain formation region 123.

  As a result of the layer thickness of the first barrier layer 102 being different in the two regions, the channel potential position of the source formation region 122 becomes lower than the channel potential position of the gate formation region 121, and the two-dimensional electrons of the source formation region 122 The concentration is higher than the two-dimensional electron concentration in the gate formation region 121. In FIG. 2, reference numerals 201 and 202 indicate the correspondence between the potential change and the conduction band position. As described above, a potential step is formed in the channel at the boundary between the source formation region 122 and the gate formation region 121 of the recessed gate structure.

  Therefore, the electron transport in the recessed gate structure includes a process exceeding the potential step formed at the boundary between the source forming region 122 and the gate forming region 121, and this process is added as one of the resistances. The channel potential position and the two-dimensional electron concentration in the gate formation region 121 can be changed by applying a gate voltage. At this time, the position of the potential of the source formation region 122 at the boundary between the source formation region 122 and the gate formation region 121 also changes due to the influence of the electric field due to the gate voltage application. Therefore, there is a step in the channel potential at the boundary between the source formation region 122 and the gate formation region 121 even when a gate voltage is applied.

  Therefore, at any gate voltage, electron transport includes a process exceeding the potential step formed at the boundary between the source formation region 122 and the gate formation region 121, and this process is added as one of the resistances. Will be. At a high temperature, the process of electrons exceeding the above-described potential step is thermally accelerated. However, for example, at a high temperature of about 400 ° C., the effect is not very significant, and a resistance due to the potential step exists significantly.

  Next, potential shapes and electron distributions in the channel layer and the barrier layer of the field effect transistor will be described with reference to FIG. 3A shows the case where the fourth barrier layer 107 is not doped, and FIG. 3B shows the case where the fourth barrier layer 107 includes the impurity introduction region 171. The presence of the impurity introduction region 171 changes the potential shape. FIG. 3 mainly shows the state of the source formation region 122, but the same applies to the drain formation region 123.

  Further, when the fourth barrier layer 107 is not doped, as shown in FIG. 3A, the electrons 301 are transferred to the channel layer even at a high temperature (about 400 ° C.) as at room temperature (about 25 ° C.). 101 exists. On the other hand, when the impurity introduction region 171 is provided, the electrons 302 are also present under the second barrier layer 105 in a high temperature state as shown in FIG.

  Next, potential shapes and electron distribution at high temperatures in the source formation region 122 and the gate formation region 121 will be described with reference to FIGS. FIG. 4 is an explanatory diagram showing the potential shape and the electron distribution at a high temperature in the source formation region 122 and the gate formation region 121. In FIG. 4, reference numerals 401, 402, and 403 indicate correspondence relationships between potential changes and conduction band positions. In the source formation region 122, electrons 411 exist in the channel layer 101, electrons 412 exist under the second barrier layer 105, and in the gate formation region 121, electrons 413 exist in the channel layer 101. It shows that.

  As described with reference to FIG. 2, in the electron transport in the recessed gate structure, the potential step formed in the channel layer 101 at the boundary between the source formation region 122 and the gate formation region 121 from 401 to 402 is expressed as follows. This process is added as one of the resistances.

  On the other hand, according to the present invention, at a high temperature, at the same time, at the boundary between the source formation region 122 and the gate formation region 121, the negative barrier layer semiconductor of the source formation region 122 and the channel layer 101 of the gate formation region 121 are negative. An energetically favorable process from 403 to 401 that goes through the potential step is included. This process is a process in which electrons flow from the first barrier layer 102 into the channel layer 101 along the step side surface of the recess gate structure in real space.

  Accordingly, the process from reference numeral 403 to reference numeral 401 reduces the resistance in electron transport that exists in the boundary between the source formation region 122 and the gate formation region 121 in the recess gate structure. As a result, an increase in channel resistance due to a decrease in electron mobility at a high temperature is offset. As described above, according to the present invention, in the depletion type field effect transistor using the nitride semiconductor formed on the normal polarity plane (that is, in the c-axis direction), the decrease in the drain current is greatly suppressed even at high temperatures. Even when the temperature is high, a state in which the decrease in the drain current is small is realized, and the decrease in the drain current at the high temperature can be suppressed.

[Example]
Next, a description will be given using an example. First, the manufacturing method will be briefly described.

First, a substrate made of c-plane sapphire, a substrate made of SiC, or a substrate made of Si is prepared. Next, on the prepared substrate, first, a channel layer 101 made of GaN having a layer thickness of 2 μm, a first barrier layer 102 made of Al _0.3 Ga _0.7 N having a layer thickness of 4 nm, and Al _0.5 Ga _0.5 N having a layer thickness of 2 nm. Layers (second barrier layer 105 and third barrier layer 106) are formed. Further, an Al _0.3 Ga _0.7 N layer (fourth barrier layer 107 and fifth barrier layer 108) having a thickness of 20 nm is formed on the Al _0.5 Ga _0.5 N layer. In the formation of an Al _0.3 Ga _0.7 N layer having a layer thickness of 20 nm, silicon was doped at a concentration of about 2 × 10 ¹⁹ cm ^{−3 in the} initial stage of deposition (lower 10 nm). These may be grown by a crystal growth method such as a well-known metal organic vapor phase epitaxy (MOVPE).

Next, a gate formation region 121 is formed from an Al _0.3 Ga _0.7 N layer having a thickness of 20 nm to a part of the first barrier layer 102 by using a mask pattern formed by a known lithography technique and by a dry etching method using a chlorine-based gas. Grooves (recesses) were formed. In the gate formation region 121, the first barrier layer 102 remains in a state where the layer thickness is 4 nm. By this patterning, the second barrier layer 105, the third barrier layer 106, the fourth barrier layer 107, and the fifth barrier layer 108 are formed. In addition, the impurity introduction region 171 and the impurity introduction region 181 are formed in the fourth barrier layer 107 and the fifth barrier layer 108.

Next, the fourth barrier layer 107 and the fifth barrier layer 108 are formed on the fourth barrier layer 107 by vapor deposition of an electrode metal material, and the drain electrode 110 is formed on the fifth barrier layer 108. Next, the gate insulating layer 103 is formed. For example, the gate insulating layer 103 may be formed by depositing Al ₂ O ₃ with a thickness of about 25 nm by a well-known deposition method such as atomic layer deposition (ALD). Next, the gate electrode 104 is formed on the gate insulating layer 103 in the gate formation region 121 by evaporating a predetermined electrode metal or the like. As a result, the field effect transistor described with reference to FIG. 1 is obtained.

  When the static characteristics of the field effect transistor in the example manufactured as described above were evaluated, a depletion type device operation having a threshold value of −4 V was confirmed, and a drain of 1.2 A / mm at room temperature was confirmed. Although the current density was obtained, the amount of decrease in the drain current described above was at most 10% even at a high temperature of 300 ° C.

  By the way, the layer thickness of the second barrier layer 105 and the third barrier layer 106 needs to be 1.5 nm or more in order to be able to form two-dimensional electrons immediately under high temperature, but the layer thickness is large. Then, since the resistance when electrons are injected from the source electrode 109 is increased, it is not desirable to exceed the layer thickness of 5 nm. Therefore, the thicknesses of the second barrier layer 105 and the third barrier layer 106 are 1.5 nm or more and 5 nm or less. This range shifts in the direction of increasing the thickness as a whole because the impurity introduction region 171 and the impurity introduction region 181 doped with impurities exist in the upper layer.

  Further, the total thickness of all the barrier layers in the source formation region 122 and the drain formation region 123 is generally required to be 10 nm or more in order to induce high-concentration two-dimensional electrons in the channel of the region. On the other hand, the two-dimensional electron concentration is generally saturated when the thickness of all layers is 100 nm or less. Therefore, the total thickness of all the barrier layers in the source formation region 122 and the drain formation region 123 is 10 nm to 100 nm.

  In order for the first barrier layer 102 in the gate formation region 121 to operate as a depletion type device, a layer thickness of 4 nm or more is necessary in order for two-dimensional electrons in the region to exist. On the other hand, if the thickness of the first barrier layer 102 in this region increases, the mutual conductance decreases, so it is better not to exceed the layer thickness of 20 nm. Therefore, the thickness of the first barrier layer 102 in the gate formation region 121 may be 4 nm or more and 20 nm or less.

  The layer thickness of the gate insulating layer 103 under the gate electrode 104 needs to be 2 nm or more in order to obtain the effects of increasing the gate breakdown voltage and reducing the gate leakage current. The above effect increases as the layer thickness increases. On the other hand, the gain of the field effect transistor decreases at the same time. Therefore, the layer thickness of the insulating film is 100 nm or less from the condition for obtaining a practical field effect transistor gain. As good as

In the present embodiment, the semiconductor material of the first nitride layer constituting the first barrier layer 102, the fourth barrier layer 107, and the fifth barrier layer 108, and the first nitride semiconductor constituting the channel layer 101 is used. As a combination of the above, a structure in which Al _0.3 Ga _0.7 N is used as the second nitride semiconductor and GaN is used as the first nitride semiconductor is used, but the combination is not limited thereto.

The combination of the semiconductor material of the second nitride semiconductor / first nitride semiconductor is Al _X Ga _1-X N / GaN (0 <X <1), Al _X1 Ga _1-X1 N / In _X2 Ga _1-X2 N (0 <X1 <1, 0 ≦ X2 ≦ 1), Al _X1 Ga _{1 -X1} N / Al _X2 Ga _{1 -X2} N (0 <X1 <1, 0 ≦ X2 <1, X1> X2), GaN / In _{X Ga 1-X N (0} <X ≦ 1), In X1 Ga 1-X1 N / In X2 Ga 1-X2 N (0 ≦ X1 <1,0 <X2 ≦ 1, X1 <X2), In X Al _1-X N / GaN (0 ≦ X <0.5), In _X1 Al _1-X1 N / Al _X2 Ga _1-X2 N (0 ≦ X1 <0.5, 0 ≦ X2 <1, X1 + X2 <1) In _X1 Al _{1 -X1} N / In _X2 Ga _{1 -X2} N (0 ≦ X1 <1, 0 ≦ X2 ≦ 1), the second nitride semiconductor is more preferable than the first nitride semiconductor. The band gap is large, and the effect of the present invention Can be obtained.

In this embodiment, as a combination of the third nitride semiconductor composing the second barrier layer 105 and the third barrier layer 106 and the semiconductor material of the second nitride semiconductor, Al _0.5 Ga _{0.5 is used} as the third nitride semiconductor. N, the structure of Al _0.3 Ga _0.7 N was used as the second nitride semiconductor, but the structure is not limited to this.

As a combination of the third nitride semiconductor / second nitride semiconductor, Al _X1 Ga _{1 -X1} N / Al _X2 Ga _{1 -X2} N (0 <X1 ≦ 1, 0 ≦ X2 <1, X1> X2), In _X1 Al _{1 -X 1} N / Al _{X 2} Ga ₁ -X ₂ N (0 ≦ X1 <0.5, 0 ≦ X2 <1, X1 + X2 <1), Al _X Ga _1-X N / GaN (0 <X ≦ 1), In _X Al _1-X N / GaN (0 ≦ X <0.5), Al _X1 Ga _1-X1 N / In _X2 Ga _1-X2 N (0 <X1 ≦ 1, 0 ≦ X2 ≦ 1), GaN / _{In X Ga 1-X N (} 0 <X ≦ 1), In X1 Ga 1-X1 N / In X2 Ga 1-X2 N (0 ≦ X1 <1,0 <X2 ≦ 1, X1 <X2), In X1 Al _1-X1 N / In _X2 Ga _1-X2 N (0 ≦ X1 <1, 0 ≦ X2 ≦ 1), In _X1 Al _1-X1 N / In _X2 Al _1-X2 N (0 ≦ X1 <X2 ≦ 1) ), The third nitride semiconductor is the second nitride. Larger band gap than the conductor, it is possible to obtain the effect of the present invention.

In this embodiment, the gate insulating layer 103 is made of Al ₂ O _3. However, the present invention is not limited to this, and the gate insulating layer 103 may be made of various materials such as SiN, SiO ₂ , AlN, ZrO ₂ , and HfO _2. It can be made of any insulating material.

  As described above, according to the present invention, the barrier layer has a three-layer structure including the first barrier layer, the second barrier layer, the third barrier layer, the fourth barrier layer, and the fifth barrier layer. Since the second barrier layer and the third barrier layer have a larger band gap energy than the other barrier layers, a decrease in the drain current of the depletion type field effect transistor using a nitride semiconductor at a high temperature is suppressed. become able to.

  According to the present invention, at a high temperature of, for example, 300 ° C., electrons that are thermally excited in the second barrier layer on both sides of the gate formation region and the first barrier layer under the third barrier layer exist in the gate formation region. It is transported energetically favorably to the channel layer. As a result, the resistance at the boundary between the gate forming region and the gate forming region is reduced, the decrease in drain current due to the decrease in electron mobility at high temperature is greatly reduced, and the decrease in drain current is suppressed even at high temperatures. Become.

  The present invention is not limited to the embodiment described above, and many modifications and combinations can be implemented by those having ordinary knowledge in the art within the technical idea of the present invention. It is obvious.

  By the way, a structure in which a thin layer made of a nitride semiconductor having a band gap energy larger than that of the barrier layer is sandwiched between the barrier layers can be applied to an enhancement type field effect transistor using a nitride semiconductor. This case will be described below with reference to FIG.

  This field effect transistor includes a channel layer 501 made of a first nitride semiconductor having a main surface of (0001) plane, and a channel layer 501 made of a second nitride semiconductor having a larger band gap energy than the first nitride semiconductor. A first barrier layer 502 formed on the first barrier layer 502 and a gate electrode 504 formed on the first barrier layer 502 with a gate insulating layer 503 interposed therebetween.

  The field effect transistor is formed on the first barrier layer 502 in the source formation region 522 and the drain formation region 523 across the gate formation region 521 in which the gate electrode 504 is formed, and is larger than the second nitride semiconductor. A second barrier layer 505 and a third barrier layer 506 made of a third nitride semiconductor having a band gap energy and having a layer thickness of 1.5 to 5 nm are provided.

  The field effect transistor includes a fourth barrier layer 507 and a fifth barrier layer 508 made of a second nitride semiconductor formed on the second barrier layer 505 and the third barrier layer 506, and a fourth barrier layer 507. And a source electrode 509 and a drain electrode 510 formed on the fifth barrier layer 508. The fourth barrier layer 507 and the fifth barrier layer 508 include an impurity introduction region 571 and an impurity introduction region 581 into which an n-type impurity is introduced on the second barrier layer 505 and the third barrier layer 506 side.

  Note that the thickness of the first barrier layer 502 in the gate formation region 521 is set such that two-dimensional electrons are depleted in the first barrier layer 502 in the gate formation region 521. For example, the gate formation region 521 may have no barrier layer 502. Therefore, this field effect transistor is a so-called enhancement type (normally off type). Also in this field effect transistor, the thickness of the first barrier layer 502 in the gate formation region 521 is equal to or less than the thickness of the first barrier layer 502 in the source formation region 522 and the drain formation region 523, and a so-called recess gate structure is formed. .

Next, a manufacturing method will be described. First, a substrate made of c-plane sapphire, a substrate made of SiC, or a substrate made of Si is prepared. Next, on the prepared substrate, first, a channel layer 501 made of GaN having a layer thickness of 2 μm, a first barrier layer 502 made of Al _0.3 Ga _0.7 N having a layer thickness of 4 nm, and Al _0.5 Ga _0.5 N having a layer thickness of 2 nm. Layers (second barrier layer 505 and third barrier layer 506) are formed. Note that the first barrier layer 502, the second barrier layer 505, and the third barrier layer 506 are formed by doping silicon with about 2 × 10 ¹⁹ cm ⁻³ .

Further, an Al _0.3 Ga _0.7 N layer (fourth barrier layer 507 and fifth barrier layer 508) having a thickness of 10 nm is formed on the Al _0.5 Ga _0.5 N layer. In the formation of an Al _0.3 Ga _0.7 N layer having a layer thickness of 10 nm, silicon was doped at a concentration of about 2 × 10 ¹⁹ cm ^{−3 in the} initial stage of deposition (lower 6 nm). These may be grown by a crystal growth method such as a well-known metal organic chemical vapor deposition method.

Next, a gate formation region 521 is formed from an Al _0.3 Ga _0.7 N layer having a thickness of 10 nm to a part of the first barrier layer 502 by using a mask pattern formed by a known lithography technique and by a dry etching method using a chlorine-based gas. Grooves (recesses) are formed. In the gate formation region 521, the first barrier layer 502 is in a state where the layer thickness remains 3 nm. By this patterning, the second barrier layer 505, the third barrier layer 506, the fourth barrier layer 507, and the fifth barrier layer 508 are formed. Further, the impurity introduction region 571 and the impurity introduction region 581 are formed in the fourth barrier layer 507 and the fifth barrier layer 508.

Next, the fourth barrier layer 507 and the fifth barrier layer 508 are formed on the fourth barrier layer 507, and the drain electrode 510 is formed on the fifth barrier layer 508 by vapor deposition of an electrode metal material. Next, the gate insulating layer 503 is formed. For example, the gate insulating layer 503 may be formed by depositing Al ₂ O ₃ with a thickness of about 25 nm by a well-known deposition method such as atomic layer deposition. Next, a gate electrode 504 is formed on the gate insulating layer 503 in the gate formation region 521 by depositing a predetermined electrode metal or the like. Thus, an enhancement type field effect transistor can be obtained (see Non-Patent Document 3).

  When the static characteristics of the enhancement type field effect transistor fabricated as described above were evaluated, an enhancement type device operation having a threshold of +5 V was confirmed, and a drain current of 0.6 A / mm at room temperature. Although the density was obtained, the amount of decrease in the drain current described above was at most 5% even at a high temperature of 300 ° C.

  By the way, the layer thickness of the second barrier layer 505 and the third barrier layer 506 needs to be 1.5 nm or more in order to be able to form two-dimensional electrons immediately under high temperature, but the layer thickness is large. Then, since the resistance when electrons are injected from the source electrode 509 is increased, it is not desirable to exceed the layer thickness of 5 nm. Therefore, the thicknesses of the second barrier layer 505 and the third barrier layer 506 may be 1.5 nm or more and 5 nm or less.

  Further, the total thickness of all the barrier layers in the source formation region 522 and the drain formation region 523 generally needs to be 10 nm or more in order to induce high-concentration two-dimensional electrons in the channel of the region. On the other hand, the two-dimensional electron concentration is generally saturated when the thickness of all layers is 100 nm or less. Therefore, the total layer thickness of all the barrier layers in the source formation region 522 and the drain formation region 523 may be 10 nm or more and 100 nm or less.

  The first barrier layer 502 in the gate formation region 521 has a layer thickness of 10 nm or less for depletion of two-dimensional electrons in the region in order to perform enhancement type device operation, and the layer thickness is 0 It may be.

  In addition, the layer thickness of the gate insulating layer 503 under the gate electrode 504 needs to be 2 nm or more in order to obtain the effects of increasing the gate breakdown voltage and reducing the gate leakage current. The above effect increases as the layer thickness increases. On the other hand, the gain of the field effect transistor decreases at the same time. Therefore, the layer thickness of the insulating film is 100 nm or less from the condition for obtaining a practical field effect transistor gain. As good as

In the enhancement-type field effect transistor described above, the second nitride semiconductor constituting the first barrier layer 502, the fourth barrier layer 507, and the fifth barrier layer 508, and the first nitride semiconductor constituting the channel layer 501 are included. As a combination of the semiconductor materials, a structure in which Al _0.3 Ga _0.7 N is used as the second nitride semiconductor and GaN is used as the first nitride semiconductor is used, but the combination is not limited thereto.

The combination of the semiconductor material of the second nitride semiconductor / first nitride semiconductor is Al _X Ga _1-X N / GaN (0 <X <1), Al _X 1Ga _1-X1 N / In _X2 Ga _1-X2 N (0 <X1 <1, 0 ≦ X2 ≦ 1), Al _X1 Ga _{1 -X1} N / Al _X2 Ga _{1 -X2} N (0 <X1 <1, 0 ≦ X2 <1, X1> X2), GaN / In _{X Ga 1-X N (0} <X ≦ 1), In X1 Ga 1-X1 N / In X2 Ga 1-X2 N (0 ≦ X1 <1,0 <X2 ≦ 1, X1 <X2), In X Al _1-X N / GaN (0 ≦ X <0.5), In _X1 Al _1-X1 N / Al _X2 Ga _1-X2 N (0 ≦ X1 <0.5, 0 ≦ X2 <1, X1 + X2 <1) In _X1 Al _{1 -X1} N / In _X2 Ga _{1 -X2} N (0 ≦ X1 <1, 0 ≦ X2 ≦ 1), the second nitride semiconductor is more preferable than the first nitride semiconductor. As a result, the band gap becomes large.

In this embodiment, in the field effect transistor described with reference to FIG. 1, the combination of the third nitride semiconductor constituting the second barrier layer 505 and the third barrier layer 506 and the semiconductor material of the second nitride semiconductor. As the third nitride semiconductor, a structure having Al _0.5 Ga _0.5 N as the second nitride semiconductor and Al _0.3 Ga _0.7 N as the second nitride semiconductor is used, but the structure is not limited to this.

As a combination of the third nitride semiconductor / second nitride semiconductor, Al _X1 Ga _{1 -X1} N / Al _X2 Ga _{1 -X2} N (0 <X1 ≦ 1, 0 ≦ X2 <1, X1> X2), In _X1 Al _{1 -X 1} N / Al _{X 2} Ga ₁ -X ₂ N (0 ≦ X1 <0.5, 0 ≦ X2 <1, X1 + X2 <1), Al _X Ga _1-X N / GaN (0 <X ≦ 1), In _X Al _1-X N / GaN (0 ≦ X <0.5), Al _X1 Ga _1-X1 N / In _X2 Ga _1-X2 N (0 <X1 ≦ 1, 0 ≦ X2 ≦ 1), GaN / _{In X Ga 1-X N (} 0 <X ≦ 1), In X1 Ga 1-X1 N / In X2 Ga 1-X2 N (0 ≦ X1 <1,0 <X2 ≦ 1, X1 <X2), In X1 Al _1-X1 N / In _X2 Ga _1-X2 N (0 ≦ X1 <1, 0 ≦ X2 ≦ 1), In _X1 Al _1-X1 N / In _X2 Al _1-X2 N (0 ≦ X1 <X2 ≦ 1) ), The third nitride semiconductor is the second nitride. Band gap becomes larger state than conductors.

Further, although the gate insulating layer 503 is made of Al ₂ O ₃ , it is not limited to this, and can be made of various insulating materials such as SiN, SiO ₂ , AlN, ZrO ₂ , and HfO ₂ .

  DESCRIPTION OF SYMBOLS 101 ... Channel layer, 102 ... 1st barrier layer, 103 ... Gate insulating layer, 104 ... Gate electrode, 105 ... 2nd barrier layer, 106 ... 3rd barrier layer, 107 ... 4th barrier layer, 108 ... 5th barrier layer , 109 ... source electrode, 110 ... drain electrode, 171 ... impurity introduction region, 181 ... impurity introduction region, 121 ... gate formation region, 122 ... source formation region, 123 ... drain formation region.

Claims (4)

A channel layer made of a first nitride semiconductor having a main surface of (0001) plane;
A first barrier layer made of a second nitride semiconductor having a larger band gap energy than the first nitride semiconductor and formed on the channel layer;
A gate electrode formed on the first barrier layer via a gate insulating layer;
The third nitride semiconductor is formed on the first barrier layer in the source formation region and the drain formation region sandwiching the gate formation region where the gate electrode is formed, and has a larger band gap energy than the second nitride semiconductor. A second barrier layer and a third barrier layer having a layer thickness of 1.5 to 5 nm,
A fourth barrier made of the second nitride semiconductor formed on the second barrier layer and the third barrier layer and having an n-type impurity introduced on the second barrier layer and the third barrier layer side. A layer and a fifth barrier layer;
A source electrode and a drain electrode formed on the fourth barrier layer and the fifth barrier layer,
The field effect transistor according to claim 1, wherein a thickness of the first barrier layer in the gate formation region is a thickness at which two-dimensional electrons are formed in the first barrier layer in the gate formation region. The field effect transistor of claim 1, wherein
The thickness of all barrier layers in the source formation region and the drain formation region is in the range of 10 nm to 100 nm,
The gate insulating layer has a layer thickness of 2 nm to 100 nm. The field effect transistor according to claim 1 or 2,
The combination of the semiconductor material of the second nitride semiconductor / first nitride semiconductor is Al _x Ga _1-x N / GaN (0 <X <1), Al _x1 Ga _1-x1 N / In _x2 Ga _{1- X2 N (0 <X1 <1,0} ≦ X2 ≦ 1), Al X1 Ga 1-X1 N / Al X2 Ga 1-X2 N (0 <X1 <1,0 ≦ X2 <1, X1> X2), GaN _{/ In X Ga 1-X N} (0 <X ≦ 1), In X1 Ga 1-X1 N / In X2 Ga 1-X2 N (0 ≦ X1 <1,0 <X2 ≦ 1, X1 <X2), In _X Al _1-X N / GaN (0 ≦ X <0.5), In _X1 Al _1-X1 N / Al _X2 Ga _1-X2 N (0 ≦ X1 <0.5, 0 ≦ X2 <1, X1 + X2 < 1) A field effect transistor having a combination selected from In _X1 Al _{1 -X1} N / In _X2 Ga _{1 -X2} N (0 ≦ X1 <1, 0 ≦ X2 ≦ 1). The field effect transistor according to any one of claims 1 to 3,
The combination of the third nitride semiconductor / second nitride semiconductor is Al _X1 Ga _{1 -X1} N / Al _X2 Ga _{1 -X2} N (0 <X1 ≦ 1, 0 ≦ X2 <1, X1> X2), In _X1 Al _1-X1 N / Al _X2 Ga _1-X2 N (0 ≦ X1 <0.5, 0 ≦ X2 <1, X1 + X2 <1), Al _X Ga _1-X N / GaN (0 <X ≦ 1) ), In _X Al _1-X N / GaN (0 ≦ X <0.5), Al _X1 Ga _1-X1 N / In _X2 Ga _1-X2 N (0 <X1 ≦ 1, 0 ≦ X2 ≦ 1), _{GaN / In X Ga 1-X} N (0 <X ≦ 1), In X1 Ga 1-X1 N / In X2 Ga 1-X2 N (0 ≦ X1 <1,0 <X2 ≦ 1, X1 <X2), In _X1 Al _1-X1 N / In _X2 Ga _1-X2 N (0 ≦ X1 <1, 0 ≦ X2 ≦ 1), In _X1 Al _1-X1 N / In _X2 Al _1-X2 N (0 ≦ X1 <X2 ≦ 1) is a combination selected from The field effect transistor.