JP2014216033A - Testing method, testing apparatus, and semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve PASS/FAIL test accuracy of an erase test for an entire block.SOLUTION: A testing apparatus 100 determines whether each of representative cells rc has succeeded in erasure in order after an erase pulse is applied to each cell in a block B. Upon discovery of one cell that fails in erasure, the testing apparatus 100 halts the determination, stores information indicating the cell determined to fail in a storage unit, applies an erase pulse to each cell in the block B, and determines whether only the cells other than the failed cell have succeeded in erasure. When the erasure pulse is applied to each cell (n+2) times, the testing apparatus 100 determines that each of the cells other than the cell indicated by last stored information has succeeded in erasure. The testing apparatus 100 determines the number of applied erasure pulses in an erasure test for the entire block on the basis of the number of applied erasure pulses when determining that erasure is successful.

Description

  The present invention relates to a test method, a test apparatus, and a semiconductor memory device.

  Conventionally, in a nonvolatile memory such as a flash memory or an EEPROM (Electrically Erasable Programmable Read-Only Memory), an erase pulse is applied a plurality of times to erase data stored in a cell. Therefore, in the nonvolatile memory test, an erase test is performed to determine whether data stored in the cell is erased by applying a plurality of erase pulses (for example, Patent Documents 1 to 5 below). reference.).

  For example, in the erase test, a technique is known in which the number of erase pulses applied when testing cells in the entire block is determined by the number of erase pulses applied to erase data stored in some cells in the block. ing. Here, “block” means an erase unit of the memory cell array. When the flash memory is erased, an erase pulse is simultaneously applied to all cells in the block, and erase is performed in units of blocks. In some cases, “sector” is displayed instead of “block”. For example, when testing a cell of the entire block, a cell that has been successfully erased by the erase pulse of the determined number of application times is judged as good, and a cell that has not successfully erased the data by the determined number of erase pulses is: Defect is judged.

JP-A-8-17200 JP 2001-273792 A JP 2002-93193 A JP-A-8-249895 JP 2000-207897 A

  However, if there is a cell in which the number of times of erasing pulses applied for erasing data is specifically large, there is a problem that a cell that is originally determined to be defective is judged good in an erasing test in the entire block.

  In one aspect, an object of the present invention is to provide a test method, a test apparatus, and a semiconductor memory device that can improve the accuracy of good / bad determination in an erase test for an entire block.

  According to an aspect of the present invention, the applying unit applies an erasing pulse for erasing data stored in each cell in the block of the storage device to each cell in the block. The counting unit counts the number of times that the erasing pulse is applied to each cell in the block by the applying unit. The first control process for applying the erase pulse to each cell in the block by the application unit is executed, and whether erase by the erase pulse has succeeded for each of a plurality of cells in the block. The first determination process for determining whether or not in order is executed, and when it is determined that the first determination process is not successful, the first determination process is interrupted, and information indicating a cell determined to be unsuccessful A second control process for storing in the storage unit and applying the erase pulse to each cell in the block by the application unit is performed, and after executing the second control process, among the plurality of cells, For each cell other than the cell indicated by the information stored last in the storage unit, a second determination process for sequentially determining whether or not the erasure has succeeded is performed, and in the second determination process, If it is determined that it has not succeeded, the second determination process is interrupted, information indicating a cell that has been determined to have not been successfully erased is stored in the storage unit, and the erase pulse is transmitted by the applying unit to the block After applying to each cell in the block, when the third control process for executing the second determination process is executed and it is determined that all of the second determination processes are successful, in the erasure test of the block A test method, a test apparatus, and a semiconductor memory device that execute a determination process for determining the number of times of application of the erase pulse based on the number of times counted by the counter are proposed.

  According to one embodiment of the present invention, the accuracy of good / bad determination can be improved in an erasure test on the entire block.

FIG. 1 is an explanatory diagram of an operation example of the test apparatus according to the embodiment. FIG. 2 is an explanatory diagram illustrating an example of a semiconductor memory device. FIG. 3 is an explanatory diagram showing a block example. FIG. 4 is a block diagram illustrating a functional configuration example of the test apparatus. FIG. 5 is an explanatory diagram of an operation example of the test apparatus according to the first embodiment. FIG. 6 is an explanatory diagram of an example of defect detection by the test apparatus according to the first embodiment. FIG. 7 is an explanatory diagram of an operation example of the test apparatus according to the second embodiment. FIG. 8 is a flowchart (part 1) illustrating an example of a test procedure by the test apparatus. FIG. 9 is a flowchart (part 2) illustrating an example of a test procedure by the test apparatus.

  Exemplary embodiments of a test method, a test apparatus, and a semiconductor memory device according to the present invention will be explained below in detail with reference to the accompanying drawings.

  FIG. 1 is an explanatory diagram of an operation example of the test apparatus according to the embodiment. The test apparatus 100 is an apparatus capable of determining the number of erase pulses applied in a block B erase test of the storage device. The test apparatus 100 can control the application unit 101 and can access the erase pulse number counting unit 102. The application unit 101 applies an erase pulse for erasing data stored in each cell in the block B to each cell in the block B. The erase pulse number counting unit 102 counts the number of times the erase pulse is applied by the applying unit 101.

  First, the test apparatus 100 executes a first control process in which the application unit 101 applies an erase pulse to each cell in the block B. Next, the test apparatus 100 executes a first determination process for sequentially determining whether or not the erase by the erase pulse is successful for each of some of the plurality of cells in the block B. Some of the plurality of cells are referred to as representative cells rc. In the example of FIG. 1, the representative cell rc is assumed to be eight cells for the sake of simplicity of explanation. In the example of FIG. 1, the test apparatus 100 determines in order from the upper left cell in the representative cell rc toward the lower right cell.

  When the test apparatus 100 determines that the first determination process is not successful, the test apparatus 100 interrupts the first determination process, stores information indicating the cell determined to be unsuccessful in the storage unit, and erases it by the application unit 101 A second control process for applying a pulse to each cell in block B is executed. The information indicating the cell is, for example, an address indicating the cell. When the number of times of application by the application unit 101 is n, the test apparatus 100 determines that the third cell has failed.

  The test apparatus 100 executes a second determination process for determining whether or not erasure has succeeded for each of the representative cells rc other than the cell indicated by the information stored last in the storage unit. In the example of FIG. 1, the test apparatus 100 determines whether erasure has succeeded in order from the fourth cell. In the (n + 1) th time, the test apparatus 100 determines that the fifth cell has failed. When the test apparatus 100 determines that the second determination process is not successful, the test apparatus 100 executes the third control process. The third control process interrupts the second determination process, causes the storage unit to store information indicating a cell determined to have not been successfully erased, and applies an erase pulse to each cell in the block B by the application unit 101. This is a process for executing the second determination process after the application. As a result, in the (n + 1) th time, the sixth cell to the eighth cell and the first cell to the third cell are newly determined without determining whether or not the erasure is successful. An erase pulse is applied. Therefore, the number of determinations is reduced.

  In the (n + 2) th time, the test apparatus 100 determines whether erasure has succeeded in order from the sixth cell. In the example of FIG. 1, the test apparatus 100 determines that erasing has succeeded from the sixth cell to the eighth cell, and then returns to the first cell and sequentially determines up to the fourth cell. The cell indicated by the information stored last in the storage unit is the fifth cell. In the (n + 2) th time, since the test apparatus 100 determines that the cells other than the fifth cell among the representative cells rc have succeeded, the test apparatus 100 executes the determination process. The determination process is a process of determining the number of erase pulses applied in the erase test of block B based on the number of times counted by the erase pulse number counting unit 102. As a result, the number of erase pulses in which the failure to erase one cell is allowed is detected, and the number of erase pulses in the erase test of the cells in the block becomes excessive due to the cells that are difficult to erase specifically in the representative cell. Can be avoided. Therefore, according to the test apparatus, the accuracy of good / bad determination can be improved. Further, according to the test apparatus 100, it is possible to detect a state in which only one cell has failed to be erased with a small number of determinations.

(Semiconductor memory device)
FIG. 2 is an explanatory diagram illustrating an example of a semiconductor memory device. The semiconductor memory device 200 includes a memory core 201, a command control circuit 202, a test mode / BIST (Built In Self Test) control circuit 203, an output data determination circuit 208, a redundancy control circuit 207, and a data input / output circuit 209. ,have.

  The memory core 201 includes an X address control circuit 213, a Y address control circuit 214, a bus control circuit 212, a memory cell array 211, and a redundant memory cell array 215. The memory cell array 211 has a plurality of cells and is divided into a plurality of blocks B. The redundancy memory cell array 215 is a memory cell for replacing a memory cell determined to be defective among the memory cells in the memory cell array 211. The replacement of the memory cell is performed by the redundancy control circuit 207 after the erase test for the entire block B is completed.

  The X address control circuit 213 controls the word line of the memory cell array 211. The Y address control circuit 214 controls the bit lines of the memory cell array 211. The bus control circuit 212 controls the data bus line of the memory cell array 211.

  The command control circuit 202 identifies a command according to a combination of values of signals input from the input terminal CEX, the input terminal OEX, the input terminal CLK, and the input terminal ADDR. For example, commands for writing, erasing, reading, and testing are input. For example, when receiving a test command, the command control circuit 202 sets the flag TM to a value indicating a test and outputs it to the test mode / BIST control circuit 203.

  The test mode / BIST control circuit 203 controls the test mode according to the values of the flag TM and the flag DOP / F.

  The operation control circuit 204 controls the internal voltage generation circuit 206 and the address control circuit 205 on the basis of an instruction from the command control circuit 202 or control by the test mode / BIST control circuit 203, so that various commands are processed. Control the behavior. For example, the operation control circuit 204 controls the operation for the erase test in the representative cell rc in the block B. Next, the operation control circuit 204 controls the operation for the erase test in the entire block B based on the result of the erase test in the representative cell rc. Then, the operation control circuit 204 performs redundancy control based on the result of the erase test in the entire block B. The operation control circuit 204 controls the internal voltage generation circuit 206 and the address control circuit 205 to perform writing to each cell in the target block B. The operation control circuit 204 controls the internal voltage generation circuit 206 and the address control circuit 205 to apply an erase pulse to each cell in the target block B. The operation control circuit 204 controls the internal voltage generation circuit 206, the address control circuit 205, and the output data determination circuit 208 to read data stored in the target cell. The operation control circuit 204 controls the internal voltage generation circuit 206, the address control circuit 205, and the output data determination circuit 208 to read out data stored in the target cell for an erasure test. Do.

  The address control circuit 205 controls the X address control circuit 213 and the Y address control circuit 214 by a combination of the address control by the operation control circuit 204 and the value of the signal input from the input terminal ADDR. Specifically, the address control circuit 205 notifies the X address control circuit 213 and the Y address control circuit 214 of the address of the target block B and the addresses of the cells in the block B. The internal voltage generation circuit 206 generates a voltage to be used during read, write, and erase operations by internal voltage control by the operation control circuit 204.

  The output data determination circuit 208 determines Pass / Fail according to the memory core control by the operation control circuit 204 and the set determination condition, and sets the value of the flag DOP / F based on the determination result. Output. Specifically, the output data determination circuit 208 determines 1 or 0 by comparing the voltage value output from the bus control circuit 212 with a threshold value. The threshold value is set according to operations such as reading, writing, and erasing test reading, and is determined when the semiconductor memory device 200 is designed. In the erase test according to the present embodiment, the output data determination circuit 208 determines whether or not the erase is successful by comparing the voltage value output from the bus control circuit 212 with the threshold value for the erase test. To do.

  The data input / output circuit 209 outputs a signal input from the input terminal DI to the bus control circuit 212 as data. The data input / output circuit 209 outputs the value of each cell determined by the output data determination circuit 208 to the output terminal DO.

  FIG. 3 is an explanatory diagram showing a block example. In the block B shown in FIG. 3, the column Column has 0 to 1023, and the data line D0 has 0 to 31. Further, the block B includes ele0 and ele1 as the redundant memory cell array 215. For example, a diagonal cell is used as the representative cell rc described above.

(Example of functional configuration of test apparatus 100)
FIG. 4 is a block diagram illustrating a functional configuration example of the test apparatus. The test apparatus 100 includes a first control unit 401, a second control unit 402, a third control unit 403, a first determination unit 404, and a second determination unit 405. The test apparatus 100 includes an application unit 101, an address sequencer 406, an erase pulse number counting unit 102, a FAIL address storage unit 407, a FAIL number counting unit 409, and a determination unit 410.

  The test apparatus 100 may be included in the semiconductor memory device 200 shown in FIG. For example, the first control unit 401, the second control unit 402, the third control unit 403, the erase pulse number counting unit 102, the FAIL number counting unit 409, and the FAIL address storage unit 407 are realized by the operation control circuit 204. The address sequencer 406 is realized by the address control circuit 205. The application unit 101 is realized by an internal voltage generation circuit 206 and an address control circuit 205. The first determination unit 404 and the second determination unit 405 are realized by the operation control circuit 204 and the output data determination circuit 208.

  In addition, the test apparatus 100 may not be included in the semiconductor storage device 200 illustrated in FIG. 2, but the application unit 101 and the address sequencer 406 are included in the semiconductor storage device 200. The FAIL number counting unit 409 and the erasing pulse number counting unit 102 from the first control unit 401 include, for example, a negative logic circuit, a logical product circuit, a negative logical product circuit, a logical sum circuit, a negative logical sum circuit, an exclusive logical sum, It is formed by standard cells such as flip-flops. Further, the FAIL number counting unit 409 and the erasing pulse number counting unit 102 from the first control unit 401 define functions by description such as Verilog-HDL (Hardware Description Language), and logically synthesize the description to generate FPGA ( (Field Programmable Gate Array). Further, the processing from the first control unit 401 to the FAIL number counting unit 409 and the erase pulse number counting unit 102 may be coded in a program, for example, and the processor may execute the program. Accordingly, the FAIL number counting unit 409 and the erase pulse number counting unit 102 may be realized from the first control unit 401. Further, the program may be distributed via a network such as the Internet.

  The erase pulse number counting unit 102 erases each cell in the block B by controlling one of the first control unit 401, the second control unit 402, and the third control unit 403. Count the number of pulses applied, pulse_cnt.

  Here, the present embodiment will be described in detail using Example 1 and Example 2. In the first embodiment, a case where one cell that is specifically delayed is allowed will be described. In the second embodiment, a case where a plurality of cells that are specifically delayed is allowed is described. The FAIL number counting unit 409 is used in the second embodiment.

Example 1
FIG. 5 is an explanatory diagram of an operation example of the test apparatus according to the first embodiment. In the first embodiment, a case where up to one specifically slow cell is allowed will be described. FIG. 5 illustrates a case where there is one specifically slow cell.

  The first control unit 401 performs a first control process in which the application unit 101 applies an erase pulse to each cell in the block B. Next, the first determination unit 404 performs a first determination process for sequentially determining whether or not the erase by the erase pulse is successful for each of the representative cells rc. Specifically, as shown in (a), the first determination unit 404 determines whether the address sequencer 406 has succeeded in erasing from the cell indicated by the address 1st addr to the cell indicated by the address last addr in order. . The order is, for example, the order indicated by the traveling direction. The address sequencer 406 sequentially changes the target address by incrementing or decrementing the target address indicating the target cell.

  When it is determined that the first determination process by the first determination unit 404 is not successful, the second control unit 402 interrupts the first determination process and displays information indicating the cell determined to be unsuccessful as FAIL. A second determination process stored in the address storage unit 407 is performed. The information indicating a cell is, for example, an address indicating a cell. For example, the address stored in the FAIL address storage unit 407 is represented as ADDR. In FIG. 5B, it is determined that the third cell from the left is not successful, and an address 3rd addr indicating the third cell from the left is stored in the FAIL address storage unit 407.

  For each representative cell rc, the second determination unit 405 performs a second determination process for determining whether or not erasure has succeeded in the order in which the cell indicated by the address ADDR stored last in the FAIL address storage unit 407 is last. Do. The order here is the order from the cell indicated by the address 4th addr in the traveling direction. In FIG. 5C, the second determination unit 405 determines that the cell indicated by the address 5th addr is not successful.

  If the third control unit 403 determines that the second determination process by the second determination unit 405 is not successful, the third control unit 403 executes the third control process. The third control process interrupts the second determination process, causes the FAIL address storage unit 407 to store information indicating a cell determined to have not been successfully erased, and applies an erase pulse to each cell in the block B by the application unit 101. Is a process for executing the second determination process after being applied to. Here, the address ADDR stored in the FAIL address storage unit 407 is overwritten, and one address ADDR is stored in the FAIL address storage unit 407. In FIG. 5C, the third control unit 403 overwrites the address 5th addr in the FAIL address storage unit 407 and applies an erase pulse to each cell in the block B by the application unit 101. 2nd judgment processing by 2 judgment part 405 is performed.

  In FIG. 5D, the second determination unit 405 determines whether erasing has succeeded in order from the cell indicated by the address next to the address 5th addr which is the address ADDR. As shown in FIG. 5D, the second determination unit 405 sequentially determines in the traveling direction. More specifically, for example, after determining that the cell indicated by the address last addr has been successfully erased, the second determination unit 405 determines whether the cell indicated by the address 1st addr has been successfully erased.

  In FIG. 5D, when it is determined that the second determination process by the second determination unit 405 is not successful, the third control unit 403 executes the third control process. As a result, the second determination process by the second determination unit 405 is interrupted, and the address 3rd addr is overwritten in the FAIL address storage unit 407. Then, the erasing pulse is applied to each cell in the block B by the application unit 101, and the second determination process by the second determination unit 405 is executed again.

  Further, the second determination unit 405 determines whether all the cells other than the cell indicated by the address ADDR among the representative cells rc have succeeded. Specifically, each time the address sequencer 406 changes the address, the second determination unit 405 determines whether the cell indicated by the address ADDR matches the next target address.

  When the cell indicated by the address ADDR matches the next target address indicated by the address sequencer 406, the second determination unit 405 determines that the cells other than the cell indicated by the address ADDR have been successfully erased. If the cell indicated by the address ADDR and the next target address indicated by the address sequencer 406 do not match, the second determining unit 405 determines that the erasure determination of cells other than the cell indicated by the address ADDR has not been completed. To do. In FIG. 5E, since the address ADDR is 3rd addr and the next target address is 3rd addr, the second determination unit 405 determines that cells other than the cell indicated by the address ADDR have been successfully erased. to decide.

  When it is determined that all the determination processes by the second determination unit 405 are successful, the determination unit 410 counts the number of times of application of the erase pulse in the erase test of block B as the number of times counted by the erase pulse number counting unit 102. Determine based on. Specifically, the determination unit 410 determines the number of times of application in the erase test of the block B by multiplying the number of times counted by the erase pulse number counting unit 102 by a coefficient. The coefficient is determined in advance by the designer of the test apparatus 100, for example.

  FIG. 6 is an explanatory diagram of an example of defect detection by the test apparatus according to the first embodiment. FIG. 6 illustrates a case where there are two specifically slow cells when, for example, up to one specifically slow cell is allowed. Since (a) to (c) in FIG. 6 are the same as (a) to (c) in FIG. 5, detailed description thereof is omitted.

  Next, FIG. 6D will be described. The second determination unit 405 determines whether erasing has succeeded in order from the cell next to the cell indicated by the address ADDR stored in (c). In FIG. 6D, the second determination unit 405 determines that the cell indicated by the address 3rd addr has not been successfully erased. The third control unit 403 performs a third control process. As a result, the determination process by the second determination unit 405 is interrupted, the address 3rd addr is overwritten in the FAIL address storage unit 407, and the erasing pulse is applied to each cell in the block B by the application unit 101. 2nd judgment processing by 2 judgment part 405 is performed.

  In FIG. 6E, the second determination unit 405 determines that the cell indicated by the address 5th addr has not been successfully erased. Therefore, the third control unit 403 executes the third control process. As a result, the determination process by the second determination unit 405 is interrupted, and the address 5th addr is overwritten in the FAIL address storage unit 407. Thereafter, (d) in FIG. 6 and (e) in FIG. 6 are repeated, so that the number of times pulse_cnt is counted up each time.

  The generation unit 408 generates and outputs information indicating that the block B is defective when the number of times pulse_cnt reaches a predetermined number. Specifically, the generation unit 408 generates and outputs information indicating error determination. The predetermined number of times may be set in advance in a register or the like by the designer of the test apparatus 100, or may be input from the outside of the test apparatus 100. The predetermined number of times is the maximum number of application times estimated by the designer of the semiconductor memory device 200 that cell data can be erased.

  Thereby, it is possible to identify a defective block B with a small number of determinations. Therefore, it is possible to increase the test speed of the semiconductor memory device 200.

(Example 2)
In the second embodiment, a case where a plurality of cells that are specifically delayed is allowed is described. As a result, it is possible to avoid an excessive number of erase pulses applied in the erase test of the entire block B due to a plurality of cells that are difficult to erase specifically in some cells. In the second embodiment, the same description as in the first embodiment is omitted.

  FIG. 7 is an explanatory diagram of an operation example of the test apparatus according to the second embodiment. The first control unit 401 causes the application unit 101 to apply an erase pulse to each cell in the block B. Next, the first determination unit 404 sequentially determines whether or not the erase by the erase pulse has succeeded for each of the representative cells rc.

  When it is determined that the first determination process by the first determination unit 404 is not successful, the FAIL number counting unit 409 counts the number of times FAIL_cnt determined not to be successful. The second control unit 402 does not perform the second control process when the number of times FAIL_cnt is less than the determination number of 2 or more that is smaller than the number of representative cells rc. The number of determinations may be set in advance in a register included in the test apparatus 100 by the designer of the test apparatus 100, or may be input from the outside of the test apparatus 100. In the example of FIG. 7, the number of determinations is 3. In FIG. 7B, the number of times FAIL_cnt is 1, and in FIG. 7C, the number of times FAIL_cnt is 2, so the second control process is not performed.

  When the number of times FAIL_cnt is the determination number, the second control unit 402 resets the number of times FAIL_cnt and performs the second control process. In FIG. 7D, since the number of times FAIL_cnt is 3, the second control unit 402 performs the second control process. In FIG. 7D, the address ADDR is the address 5th addr, and when the number of times FAIL_cnt reaches 3, the address ADDR is reset to 0.

  Next, the second determination unit 405 determines, for each representative cell, whether or not erasure has succeeded in the order in which the cell indicated by the address ADDR is last. The FAIL number counting unit 409 counts the number of times FAIL_cnt determined that the second determination process by the second determination unit 405 is not successful.

  In the second determination process performed by the second determination unit 405, the third control unit 403 determines that the third control process 403 does not succeed after the last information is stored in the FAIL address storage unit 407. Do not execute. Specifically, the third control unit 403 determines that the number of times FAIL_cnt counted by the FAIL number counting unit 409 is less than the determination number after it is determined that the second determination process by the second determination unit 405 is not successful. The third control process is not executed. For example, in FIG. 7E, since the number of times FAIL_cnt is 1, the third control unit 403 does not execute the third control process.

  In addition, when the third control unit 403 determines that the number of determinations has not succeeded since the information was last stored in the FAIL address storage unit 407 in the second determination processing by the second determination unit 405, the third control processing is performed. Run. Specifically, the third control unit 403 determines that the number of times FAIL_cnt counted by the FAIL number counting unit 409 after determining that the second determination process by the second determination unit 405 is not successful is a determination number. The third control process is executed. In FIG. 7F, it is determined that the cell indicated by the address 3rd addr has not been successfully erased, and the number of times FAIL_cnt is 2. In FIG. 7F, it is determined that the cell indicated by the address 4th addr has not been successfully erased, and the number of times FAIL_cnt is 3. When the number of times FAIL_cnt becomes 3, the third control unit 403 resets the number of times FAIL_cnt and executes the third control process. As a result, the number of times FAIL_cnt becomes 0, the address ADDR becomes 4th addr, and the erasing pulse is applied to each cell in the block B by the applying unit 101.

  Next, in (g) of FIG. 7, the second determination unit 405 determines whether or not erasure has succeeded for each of the representative cells rc other than the cell indicated by the address ADDR. In FIG. 7G, it is determined that the cell indicated by the address 5th addr has not been successfully erased, and the number of times FAIL_cnt is 1. In FIG. 7G, the third control unit 403 does not execute the third control process.

  In FIG. 7H, it is determined that the cell indicated by the address 3rd addr has not been successfully erased, and the number of times FAIL_cnt is 2.

  The second determination unit 405 determines whether all the cells other than the determination number of cells including the cell indicated by the address ADDR are successfully erased in the representative cell rc. Specifically, the second determination unit 405 determines whether or not the address indicated by the cell that is next determined as to whether or not the erasure is successful among the representative cells rc is the same as the address ADDR. If the address indicated by the cell that determines whether or not the erasure has succeeded is the same as the address ADDR, the second determination unit 405 erases cells other than the determination number of cells including the cell indicated by the address ADDR. Judge that everything is successful.

  In FIG. 7H, the address FAIL_cnt is 2 when the address ADDR is 4th addr and it is determined that the cell indicated by the address 3rd addr has not been successfully erased. Therefore, the second determination unit 405 determines that erasing of all cells other than the determination number of cells including the cell indicated by the address ADDR is successful. The determination unit 410 determines the number of times of application of the erase pulse in the block B erase test. Specifically, the determination unit 410 determines the number of times of application based on the number of times counted by the erase pulse number counting unit 102. Since the specific determination method by the determination part 410 is the same as Example 1, detailed description is abbreviate | omitted.

(Example of test procedure using test apparatus 100)
8 and 9 are flowcharts showing an example of a test procedure by the test apparatus. Here, Example 2 will be described. First, the test apparatus 100 sets Taddr = 1st addr (step S801). The test apparatus 100 sets the number of times FAIL_cnt = the number of determinations (step S802). The test apparatus 100 sets ADDR = last addr (step S803). The test apparatus 100 determines whether or not Taddr = ADDR (step S804). When Taddr = ADDR is not satisfied (step S804: No), the test apparatus 100 determines whether the erasure is successful (step S805).

  Next, when the erasure is successful (step S805: PASS), the test apparatus 100 determines whether or not Taddr = last addr (step S806). When Taddr = last addr (step S806: Yes), the test apparatus 100 sets Taddr = 1st addr (step S807), and proceeds to step S804. If Taddr = last addr is not satisfied (step S806: No), the test apparatus 100 sets Taddr = Taddr + 1 (step S808), and proceeds to step S804.

  If the erasure is not successful (step S805: FAIL), the test apparatus 100 determines whether or not the number of times FAIL_cnt = the number of determinations (step S901). When the number of times FAIL_cnt = the number of determinations (step S901: Yes), the test apparatus 100 sets ADDR = Taddr (step S902). The test apparatus 100 sets the number of times FAIL_cnt = 0 (step S903), and proceeds to step S905. If the number of times FAIL_cnt = not the number of determinations (step S901: No), the test apparatus 100 sets the number of times FAIL_cnt = number of times FAIL_cnt + 1 (step S904), and proceeds to step S905.

  The test apparatus 100 applies an erase pulse (step S905). The test apparatus 100 sets number pulse_cnt = number pulse_cnt + 1 (step S906). The test apparatus 100 determines whether or not the number pulse_cnt <the predetermined number of times (step S907). If the number pulse_cnt <the predetermined number of times is not satisfied (step S907: NO), the test apparatus 100 generates information indicating a failure (step S908), and ends the series of processes.

  When the number pulse_cnt <the predetermined number of times (step S907: Yes), the process returns to step S806. If Taddr = ADDR in step S804 (step S804: Yes), the test apparatus 100 determines the number of erase pulses applied in the erase test of block B based on the number pulse_cnt (step S809), and performs a series of processes. finish.

  In the present embodiment, the example in which the semiconductor memory device 200 has the test apparatus 100 has been described. However, the present invention is not limited to this, and the apparatus may be different from the semiconductor memory device 200.

  As described above, the test apparatus 100 suspends the determination when it finds one cell that has failed to be erased in the determination of whether the erasure is correct after applying the erase pulse for the representative cell. Determine the cell. As a result, the number of erase pulses in which the failure to erase one cell is allowed is detected, and the number of erase pulses in the erase test of the cells in the block becomes excessive due to the cells that are difficult to erase specifically in the representative cell. Can be avoided. Therefore, according to the test apparatus, the accuracy of good / bad determination can be improved. Further, according to the test apparatus 100, it is possible to detect a state in which only one cell has failed to be erased with a small number of determinations.

  In addition, the test apparatus 100 interrupts the determination when it finds the determination number of cells that have failed to be erased in the determination of whether the erasure is correct after applying the erase pulse for the representative cell, and next time, the cell other than the cell found last Judging. As a result, the number of erase pulses in which the failure of erasure of the determined number of cells is allowed is detected, and the number of erase pulses in the erase test of the cells in the block is excessive due to the cells that are difficult to erase specifically in the representative cell. Can be avoided. Therefore, according to the test apparatus, the accuracy of good / bad determination can be improved. Further, according to the test apparatus 100, it is possible to detect a state where only the determination number of cells has failed to be erased with a small number of determinations.

  Further, the test apparatus 100 outputs information indicating that the block is defective when the erase pulse is applied a predetermined number of times or more in the test for the representative cell. Thereby, it is possible to identify a defective block with a small number of determinations. Therefore, it is possible to increase the test speed of the semiconductor memory device 200.

  The following additional notes are disclosed with respect to each of the embodiments described above.

(Appendix 1) An application unit that applies an erasing pulse for erasing data stored in each cell in the block of the storage device to each cell in the block can be controlled, and the erasing is performed by the application unit. A test device accessible to a counting unit that counts the number of times a pulse is applied to each cell in the block,
Performing a first control process for applying the erase pulse to each cell in the block by the application unit;
After executing the first control process, for each of some of the cells in the block, execute a first determination process for sequentially determining whether or not the erase by the erase pulse is successful,
When it is determined that the first determination process is not successful, the first determination process is interrupted, information indicating a cell determined to be unsuccessful is stored in a storage unit, and the erase pulse is transmitted by the application unit. Executing a second control process to be applied to each cell in the block;
After executing the second control process, it is sequentially determined whether or not the erasure is successful for each of the cells other than the cell indicated by the information stored last in the storage unit among the plurality of cells. The second determination process is executed,
When it is determined that the second determination process is not successful, the second determination process is interrupted, and information indicating a cell that is determined not to be successfully erased is stored in the storage unit. After applying the erase pulse to each cell in the block, performing a third control process to execute the second determination process;
If it is determined that all of the second determination process is successful, a determination process for determining the number of times of application of the erase pulse in the erase test of the block based on the number of times counted by the counting unit is executed.
A test method characterized by the above.

(Appendix 2) The test apparatus is
If it is determined that the number of determinations less than the plurality of cells is not successful in the first determination process, the second control process is not executed, and it is determined that the number of determinations is not successful in the first determination process. The second control process is executed,
In the second determination process, when it is determined that less than the determination number has not succeeded since the information was last stored in the storage unit, the third control process is not executed, and the storage is performed in the second determination process. If it is determined that the number of determinations has not been successful since the information was last stored in the unit, the third control process is executed,
In the second determination process, when it is determined that a cell other than the determination number of cells including the cell indicated by the information stored last in the storage unit is successful among the plurality of cells, the determination process is performed. The test method according to appendix 1, wherein the test method is performed.

(Supplementary Note 3) In the second determination process, it is not determined whether or not the erasure is successful for the cell indicated by the information stored last in the storage unit among the plurality of cells. The test method according to Supplementary Note 1 or 2.

(Appendix 4) The test apparatus is
Additional information 1 to 3, wherein when the number of times counted by the counting unit reaches a predetermined number of times, information indicating that the block is defective is generated without executing the third control process. The test method as described in any one of these.

(Supplementary Note 5) An application unit that applies an erasing pulse for erasing data stored in each cell in the block of the storage device to each cell in the block can be controlled, and the erasing is performed by the application unit. A test apparatus accessible to a counting unit for counting the number of times a pulse is applied to each cell in the block,
A first control unit for applying the erase pulse to each cell in the block by the application unit;
A first determination unit that sequentially determines whether or not erasing by the erasing pulse has succeeded for each of some of the plurality of cells in the block after performing the first control processing by the first control unit;
When it is determined that the first determination process by the first determination unit is not successful, the first determination process is interrupted, information indicating a cell determined to be unsuccessful is stored in a storage unit, and the application A second control unit for applying the erase pulse to each cell in the block by a unit;
After executing the second control process by the second control unit, is the erasure successful for each of the cells other than the cell indicated by the information stored last in the storage unit among the plurality of cells? A second determination unit for sequentially determining whether or not,
When it is determined that the second determination process by the second determination unit is not successful, the second determination process is interrupted, and information indicating a cell determined to have not been successfully erased is stored in the storage unit A third control unit that causes the second determination unit to execute the second determination process after the erase pulse is applied to each cell in the block by the application unit;
A determination unit that determines the number of times of application of the erase pulse in the erase test of the block based on the number of times counted by the counting unit when it is determined that all of the second determination processes are successful;
A test apparatus characterized by comprising:

(Additional remark 6) It has a judgment number counting part which counts the frequency | count that it judged that it was not successful each time the said 1st judgment process or the said 2nd judgment process was performed,
The second controller is
When the determination number counting unit is less than the determination number less than the plurality of cells, the second control process is not performed, and when the determination number counting unit is the determination number, the second control process is performed. ,
The third control unit
When the determination number counting unit is less than the determination number, the third control process is not performed. When the determination number counting unit is the determination number, the third control process is performed,
The determination unit
In the second determination process, when it is determined that cells other than the determination number of cells including the cell indicated by the information stored last in the storage unit among the plurality of cells are successful, the number of times of application is determined. The test apparatus according to appendix 5, which is determined.

(Appendix 7) Blocks,
An application unit for applying an erase pulse for erasing data stored in each cell in the block to each cell in the block;
A counter for counting the number of times the erase pulse is applied to each cell in the block by the application unit;
A first control unit for applying the erase pulse to each cell in the block by the application unit;
A first determination unit that sequentially determines whether or not erasing by the erasing pulse has succeeded for each of some of the plurality of cells in the block after performing the first control processing by the first control unit;
When it is determined that the first determination process by the first determination unit is not successful, the first determination process is interrupted, information indicating a cell determined to be unsuccessful is stored in a storage unit, and the application A second control unit for applying the erase pulse to each cell in the block by a unit;
After executing the second control process by the second control unit, is the erasure successful for each of the cells other than the cell indicated by the information stored last in the storage unit among the plurality of cells? A second determination unit for sequentially determining whether or not,
When it is determined that the second determination process by the second determination unit is not successful, the second determination process is interrupted, and information indicating a cell determined to have not been successfully erased is stored in the storage unit A third control unit that causes the second determination unit to execute the second determination process after the erase pulse is applied to each cell in the block by the application unit;
A determination unit that determines the number of times of application of the erase pulse in the erase test of the block based on the number of times counted by the counting unit when it is determined that all of the second determination processes are successful;
A semiconductor memory device comprising:

DESCRIPTION OF SYMBOLS 100 Test apparatus 101 Application part 102 Erase pulse number counting part 200 Semiconductor memory device 401 1st control part 402 2nd control part 403 3rd control part 404 1st judgment part 405 2nd judgment part 406 Address sequencer 407 FAIL address memory | storage part 409 FAIL number counting unit 410 determining unit rc representative cell B block

Claims (6)

An application unit that applies an erase pulse for erasing data stored in each cell in the block of the storage device to each cell in the block can be controlled, and the erase pulse is applied to the block by the application unit. A test device accessible to a counting unit that counts the number of times applied to each cell in the
Performing a first control process for applying the erase pulse to each cell in the block by the application unit;
After executing the first control process, for each of some of the cells in the block, execute a first determination process for sequentially determining whether or not the erase by the erase pulse is successful,
When it is determined that the first determination process is not successful, the first determination process is interrupted, information indicating a cell determined to be unsuccessful is stored in a storage unit, and the erase pulse is transmitted by the application unit. Executing a second control process to be applied to each cell in the block;
After executing the second control process, it is sequentially determined whether or not the erasure is successful for each of the cells other than the cell indicated by the information stored last in the storage unit among the plurality of cells. The second determination process is executed,
When it is determined that the second determination process is not successful, the second determination process is interrupted, and information indicating a cell that is determined not to be successfully erased is stored in the storage unit. After applying the erase pulse to each cell in the block, performing a third control process to execute the second determination process;
If it is determined that all of the second determination process is successful, a determination process for determining the number of times of application of the erase pulse in the erase test of the block based on the number of times counted by the counting unit is executed.
A test method characterized by the above. The test apparatus is
If it is determined that the number of determinations less than the plurality of cells is not successful in the first determination process, the second control process is not executed, and it is determined that the number of determinations is not successful in the first determination process. The second control process is executed,
In the second determination process, when it is determined that less than the determination number has not succeeded since the information was last stored in the storage unit, the third control process is not executed, and the storage is performed in the second determination process. If it is determined that the number of determinations has not been successful since the information was last stored in the unit, the third control process is executed,
In the second determination process, when it is determined that a cell other than the determination number of cells including the cell indicated by the information stored last in the storage unit is successful among the plurality of cells, the determination process is performed. The test method according to claim 1, wherein the test method is performed. The test apparatus is
The information indicating that the block is defective is generated without executing the third control process when the number of times counted by the counting unit reaches a predetermined number. 2. The test method according to 2. An application unit that applies an erase pulse for erasing data stored in each cell in the block of the storage device to each cell in the block can be controlled, and the erase pulse is applied to the block by the application unit. A test device accessible to a counting unit for counting the number of times applied to each cell in the cell;
A first control unit for applying the erase pulse to each cell in the block by the application unit;
A first determination unit that sequentially determines whether or not erasing by the erasing pulse has succeeded for each of some of the plurality of cells in the block after performing the first control processing by the first control unit;
When it is determined that the first determination process by the first determination unit is not successful, the first determination process is interrupted, information indicating a cell determined to be unsuccessful is stored in a storage unit, and the application A second control unit for applying the erase pulse to each cell in the block by a unit;
After executing the second control process by the second control unit, is the erasure successful for each of the cells other than the cell indicated by the information stored last in the storage unit among the plurality of cells? A second determination unit for sequentially determining whether or not,
When it is determined that the second determination process by the second determination unit is not successful, the second determination process is interrupted, and information indicating a cell determined to have not been successfully erased is stored in the storage unit A third control unit that causes the second determination unit to execute the second determination process after the erase pulse is applied to each cell in the block by the application unit;
A determination unit that determines the number of times of application of the erase pulse in the erase test of the block based on the number of times counted by the counting unit when it is determined that all of the second determination processes are successful;
A test apparatus characterized by comprising: Each time the first determination process or the second determination process is executed, a determination number counting unit that counts the number of times the first determination process or the second determination process is determined to be unsuccessful;
The second controller is
When the determination number counting unit is less than the determination number less than the plurality of cells, the second control process is not performed, and when the determination number counting unit is the determination number, the second control process is performed. ,
The third control unit
When the determination number counting unit is less than the determination number, the third control process is not performed. When the determination number counting unit is the determination number, the third control process is performed,
The determination unit
In the second determination process, when it is determined that cells other than the determination number of cells including the cell indicated by the information stored last in the storage unit among the plurality of cells are successful, the number of times of application is determined. The test apparatus according to claim 4, wherein the test apparatus is determined. Block,
An application unit for applying an erase pulse for erasing data stored in each cell in the block to each cell in the block;
A counter for counting the number of times the erase pulse is applied to each cell in the block by the application unit;
A first control unit for applying the erase pulse to each cell in the block by the application unit;
A first determination unit that sequentially determines whether or not erasing by the erasing pulse has succeeded for each of some of the plurality of cells in the block after performing the first control processing by the first control unit;
When it is determined that the first determination process by the first determination unit is not successful, the first determination process is interrupted, information indicating a cell determined to be unsuccessful is stored in a storage unit, and the application A second control unit for applying the erase pulse to each cell in the block by a unit;
After executing the second control process by the second control unit, is the erasure successful for each of the cells other than the cell indicated by the information stored last in the storage unit among the plurality of cells? A second determination unit for sequentially determining whether or not,
When it is determined that the second determination process by the second determination unit is not successful, the second determination process is interrupted, and information indicating a cell determined to have not been successfully erased is stored in the storage unit A third control unit that causes the second determination unit to execute the second determination process after the erase pulse is applied to each cell in the block by the application unit;
A determination unit that determines the number of times of application of the erase pulse in the erase test of the block based on the number of times counted by the counting unit when it is determined that all of the second determination processes are successful;
A semiconductor memory device comprising:

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