JP5127078B2 - MRAM testing - Google Patents

Description

  The present disclosure relates generally to MRAM. More particularly, it relates to a method for testing an MRAM.

  Magnetoresistive random access memory (MRAM) has been found to be advantageous for use as a memory because the MRAM is non-volatile and performs high speed operations in both reading and writing. One approach to MRAM that has been effective so far is to operate the MRAM as a toggle memory. In such a case, the state of the MRAM cell is determined by leaving the cell in its current state because the current state of the cell is the desired state, or by changing the memory state to the current logic state. By switching to the opposite logic state, a desired logic state can be obtained. It has been found that operating the MRAM as a toggle memory provides a more reliable operation than the approach of directly writing the cell state. When writing the logic state of an MRAM cell directly, it has been found that the write disturb problem arises because other cells along the bit line are very often illegally written to the same logic state. Toggle writing has been found to be much less susceptible to write disturb than direct writing. In order to effectively perform toggle writing, it is necessary to read the logic state of the cell and determine whether it is necessary to switch the state. The time required for this is added to the time required for the write operation. Even when an extra read operation is performed, the write operation is performed on the order of tens of nanoseconds, whereas a normal floating gate nonvolatile memory is used. (NVM) requires time on the order of milliseconds for writing. The use of flash type floating gate NVM has become widespread. While the benefits of MRAM are obvious, there continues to be a general preference for flash as an NVM, at least in part because of the deep understanding of flash reliability.

  Therefore, it would be advantageous to establish a situation where the MRAM could be a highly reliable device and would be such a device as expected.

  The MRAM is tested by performing continuous state switching of adjacent cell groups adjacent to the cell to be tested with respect to the write disturb in order to counter the write disturb problem. In one example, it has been found that a write disturb can occur when performing a state switch of one adjacent cell on the same word line, followed by a state switch of one adjacent cell on the same bit line. This type of test can be performed more completely by not only further switching the state of other adjacent memory cell groups, but also by repeatedly switching the state of adjacent cell groups.

It is a circuit diagram of a part of MRAM. FIG. 2 is a block diagram of a system that uses the MRAM of FIG. 1. FIG. 3 is a block diagram of a portion of the system of FIG. FIG. 4 is a part of the block diagram shown in FIG. 3 in detail. 6 is a flowchart describing a method for testing an MRAM according to one embodiment.

  The present invention is illustrated through examples and is not limited by the accompanying figures, in which like reference symbols refer to like components. The components in these figures are shown for simplicity and clarity of illustration and are not necessarily drawn to scale.

  FIG. 1 shows an MRAM cell 12, an MRAM cell 14, an MRAM cell 16, an MRAM cell 18, an MRAM cell 20, an MRAM cell 22, an MRAM cell 24, an MRAM cell 26, and an MRAM cell. 28, a part of the memory 10. The MRAM cells 22, 14, 24 are arranged along a row connected to the word line 30. The MRAM cells 20, 12 and 16 are arranged along a row connected to the word line 32. The MRAM cells 26, 18, 28 are arranged along a row connected to the word line 34. The MRAM cells 22, 20 and 26 are arranged along a column connected to the bit line 36. The MRAM cells 14, 12, and 18 are arranged along a column connected to the bit line 38. The MRAM cells 24, 16 and 28 are arranged along a column connected to the bit line 40. In the example where the MRAM cell 12 is a cell under test (CUT), the MRAM cells 14, 18 are adjacent to the MRAM cell 12 and are aligned along the same bit line as the MRAM cell 12. It is a cell adjacent to the cell 12. MRAM cells 20 and 16 are also adjacent cells of MRAM cell 12 because these cells are adjacent to MRAM cell 12 and are aligned along the same word line as MRAM cell 12. MRAM cells 22, 24, 26 and 28 are not considered adjacent cells of MRAM cell 12 because these cells are not located on the same word line or the same bit line as MRAM cell 12.

  Write disturb is related to the case of switching the state of an adjacent cell group when one adjacent cell is located on the same word line as the cell under test (CUT) and the other adjacent cell is located on the same bit line as the CUT. It turns out to be a more serious problem. Therefore, in order to ensure high reliability, the MRAM cell 12 has an adjacent cell group that performs continuous state switching during the test.

  Shown in FIG. 2 is a system 50 that includes a memory 10, a built-in self test (BIST) circuit 52, a processor 54, a module group 56, an interface circuit 58, and a bus 60. The memory 10 is connected to the BIST circuit 52, the interface circuit 58, and the bus 60. The BIST circuit 52 is further connected to the interface circuit 58. The processor 54 is connected to the interface circuit 58 and the bus 60. The module group 56 is connected to the processor 54, the interface circuit 58, and the bus 60. The interface circuit 58 further has inputs / outputs for external connection to the system 50, which can be a single integrated circuit. Module group 56 may be a plurality of circuit functions such as peripheral controls, memory, or another processor. The BIST circuit 52 enables the memory 10 to be tested. In this test, each memory cell is tested by continuously switching the state of adjacent cell groups. This test can be performed by responding to an external source via interface circuit 58. The processor 54 controls the memory 10 as other operations, and controls the module group 56 at least to some extent. The system 50 can include other circuits in addition to the circuits shown. Testing of the memory 10 can also be performed under the control of the processor 54 or via the interface 58.

  FIG. 3 shows details of the BIST circuit 52 and the memory 10. There are also means for connecting to other circuit groups between the BIST circuit 52 and the memory 10, and these other circuits are not shown in the drawing for the sake of simplicity. The BIST circuit 52 includes other BIST logic 62, a configuration storage circuit 64, and a forced switching logic circuit 66. The memory 10 includes a memory controller 68 and a memory array 70. The other BIST logic 62 and the forced switching logic circuit 66 instruct the test of the memory array 70 based on the input from the configuration storage circuit 64 via the memory controller 68, and the input is a CUT (test target cell). ) Includes a sequence or a sequence group for switching the state of a specific adjacent cell in the adjacent cell group. Another signal, a forced switching indicator, is generated by the forced switching logic circuit 66 to notify that a forced state switch is scheduled. Forcible state switching is state switching that ensures that cell state switching is performed regardless of the cell contents. The contents of the configuration storage circuit 64 are read out via another BIST logic 62.

  FIG. 4 shows details of the configuration storage circuit 64. The configuration storage circuit 64 can be a register, which provides information about the CUT (cell under test) and how it is going to test the CUT. The configuration storage circuit 64 includes a field 72, a field 74, a field 76, a field 78, a field 80, and a field 82. Field 76 is a location that can be the address of neighbor cell 0. Field 78 is a location that can be the address of adjacent cell 1. Field 80 is a location that can be the address of adjacent cell 2. The field 82 is a location that can be the address of the adjacent cell 3. In the example where the MRAM cell 12 is a CUT (test target cell), the fields 76-82 identify the locations of the memory cells 14, 16, 18, and 20 in the order desired for testing the CUT. In field 72, the final field to be used is specified from among the fields 76 to 82, and this final field indicates which of the adjacent cells is to be subjected to state switching in the sequence. It has the effect that it can be specified. For example, since the sequence includes only two neighboring cells, the last neighboring cell is the second neighboring cell whose state is switched in the sequence. Even if there are only two neighboring cells in the sequence, the sequence can be executed multiple times. A field 74 indicates a count of the number of times of addition after the first time when a sequence for switching the state of the adjacent cell group is executed. The fields in the configuration storage circuit 64 can be arranged in any order relative to each other, and one embodiment of this order is shown in FIG.

  Shown in FIG. 5 is a flow diagram 100 for performing a test of a CUT that can be an MRAM cell 12. In step 102, the CUT is written to bring the cell into a known state, which is accomplished by reading and subsequently performing state switching as necessary. By reading the CUT in step 104, the writing in step 102 is verified. Steps 102 and 104 are executed when the final steps 128 and 130 are executed according to the instructions of the other BIST logic 62. The other steps are performed according to instructions from the configuration storage circuit 64 and the forced switching logic circuit 66. In step 106, the state of the adjacent cell specified in the field 76 is switched. In the case of the MRAM cell 12, the adjacent cell can be any one of the memory cells 14, 16, 18, and 20. In step 108, it is determined whether or not the neighboring cell whose state is to be switched is the final neighboring cell specified in the field 72. If it is determined that the cell is the last adjacent cell, it is determined in step 110 whether or not the state switching is to be repeated based on the field 74. If there are more iterations to perform, the next step is step 106. The letter “A” is used to indicate a return to step 106. If it is determined in step 110 that there are no more iterations to be performed, the CUT is read in step 128 to verify that the CUT has not changed state and therefore no write disturb has occurred. To do. Whenever step 128 is performed, the next cell must be selected as the next CUT at step 130, so the process will resume from step 102 with the newly selected CUT.

  If it is determined in step 108 that the neighboring cell whose state has been switched in step 106 is not the final neighboring cell that is to undergo state switching, in the next step, the state switching of the neighboring cell specified in field 78 is performed. To do. As a result, any one of the four neighboring cells of the CUT can be specified. Although the neighbor cell is shown as neighbor cell 1 in step 112, the neighbor cell may be the same as the neighbor cell identified in field 76 and whose state is switched in step 106. After switching the state of the adjacent cell 1, it is determined in step 114 whether or not the adjacent cell is the final adjacent cell specified in the field 72. If the neighbor cell is the last neighbor cell, a determination is made at step 116 as to whether additional iterations have not yet been performed based on field 74. If no additional iterations are to be performed, at step 128, the CUT is read to determine if a write disturb has occurred. If additional iterations are to be performed, the next step is step 106. If the neighbor cell 1 is not the final neighbor cell, the state of the neighbor cell, that is, the neighbor cell 2 specified in the field 80, is switched at step 118. This adjacent cell may be any one of the four adjacent cells including either the adjacent cell 0 or the adjacent cell 1. In step 120, it is determined whether adjacent cell 2 is the last adjacent cell. If neighbor cell 2 is the last neighbor cell, it is determined in step 122 whether additional iterations are performed based on field 74. If no additional iterations are performed, at step 128, the CUT is read to determine if a write disturb has occurred. If additional iterations are performed, the next step is step 106. If the adjacent cell 2 is not the final adjacent cell, the state of the adjacent cell specified as the adjacent cell 3 in the field 82 is switched in step 124. In the same manner as for neighbor cells 0, 1, and 2, neighbor cell 3 may be any neighbor cell of the four neighbor cells of the CUT. After switching the state of the cell specified as the neighbor cell 3 in step 124, it is determined in step 126 whether another repetition to be performed based on the field 74 remains. If there is another iteration to perform, the next step is step 106 and the process continues. If there is no other iteration to be performed, the CUT is read at step 128 to determine if a write disturb has occurred.

  Flowchart 100 thus shows that various options for switching states of neighboring cell groups can be used. In one example, the state is simply switched between two neighboring cells, where one neighboring cell is in the same column as the CUT and the other neighboring cell is in the same row as the CUT. Yes.

  This two-cell sequence can be repeated. In fact, the two cell sequence can be repeated as many times as indicated in field 74. In such a case, continuous state switching of one column adjacent cell and one row adjacent cell is performed, and then this continuous state switching is repeated as desired. Moreover, you may perform continuous state switching of the same adjacent cell. This can be done by identifying the same neighboring cell in both fields 76 and 78. This continuous state switching can be repeated as desired and / or repeated by adding another cell or group of cells to the sequence. By using this flowchart to test, not only can one cell be checked for reliability, but it can also be used to switch states that pose the greatest danger of causing a write disturb. Different combinations of can be analyzed. This can be useful not only to confirm future margin tests, but also to identify potential areas of improvement for establishing MRAM as a reliable device.

  As shown in FIG. 1, the MRAM cell is drawn as an ellipse, where the major axis makes an angle of 45 degrees with the rows and columns. The most serious problem with write disturb occurs when the long axes of two adjacent cells are aligned. Thus, if MRAM cell 12 is a CUT, the most dangerous combination with respect to write disturb is the continuous state switching of MRAM cells 20 and 14 or MRAM cells 16 and 18. Therefore, it is a great advantage to simply switch states of adjacent cells with the long axis closest to a straight line, test the write disturb, and then move to the next CUT.

  From the foregoing, it should be understood that a method for testing a toggle MRAM having a plurality of cells has been provided. In this method, a cell to be tested is selected from the plurality of cells. The method further writes the first state to the cell. The method further verifies the first state by reading from the cell. In the method, the state of the first neighboring cell of the cell and the state of the second neighboring cell of the cell are continuously switched according to a predetermined neighboring cell sequence. In this case, the first neighboring cell of the cell Adjacent to the cell, and the second adjacent cell of the cell is adjacent to the cell, and the predetermined adjacent cell sequence is an order in which the state of the first adjacent cell and the state of the second adjacent cell should be continuously switched. Indicates. In the method, after the step of switching continuously, the cell is read to determine whether a change from the first state to the second state has occurred. The switching of the state of the first adjacent cell is not performed in response to reading of the first adjacent cell, and the switching of the state of the second adjacent cell is performed in response to reading of the second adjacent cell. There is no. The method further does not read out the first adjacent cell immediately before switching the state of the first adjacent cell, and reads out the second adjacent cell immediately before switching the state of the second adjacent cell. It is characterized by not. The method can further obtain a predetermined neighbor cell sequence from the configuration storage circuit. The method is further characterized in that the configuration storage circuit notifies the last neighbor cell in a predetermined neighbor cell sequence. The method further includes a repeat indicator in the configuration storage circuit, using the repeat indicator to determine the number of times to repeat a predetermined neighbor cell sequence, reading from the cell, and from the first state to the second state. Before determining whether or not a change has occurred, continuous switching of the first and second neighboring cells is repeated a number of times determined using a repeat indicator according to a predetermined neighboring cell sequence. The method is further characterized in that the first adjacent cell is aligned along the same bit line as the cell and the second adjacent cell is aligned along the same word line as the cell. The method further indicates that the predetermined neighbor cell sequence indicates that the first neighbor cell follows the second neighbor cell, and the state of the first neighbor cell of the cell, and the state of the second neighbor cell of the cell. The step of continuously switching is performed such that the state of the second adjacent cell is changed earlier than the state of the first adjacent cell.

  A data processing system having an MRAM array having a plurality of cells, an MRAM controller connected to the MRAM array, and test logic are provided. The test logic is connected to the MRAM controller and includes a configuration storage circuit that stores a predetermined sequence of at least two adjacent cell locations, and when testing each cell of the plurality of cells, the test logic is configured to store at least two of the predetermined sequence. The state of the adjacent cell group of the cell being tested is continuously switched as indicated by the two adjacent cell locations. The data processing system is further characterized in that the MRAM array, the MRAM controller, and the test logic are provided on a single integrated circuit. The data processing system is further characterized in that the configuration storage circuit stores a last neighbor cell indicator indicating the end of the predetermined sequence. The data processing system further stores a repeat indicator in the configuration storage circuit, wherein the repeat indicator is the number of times the test logic continuously switches between a series of at least two adjacent cells of the cell being tested as indicated by the predetermined sequence. It is characterized by showing. The data processing system is further characterized in that the switching is not performed in response to reading of the adjacent cell to be switched.

  A method for testing a toggle MRAM having a plurality of cells is also described. In this method, a cell to be tested is selected from a plurality of cells. The method further writes the first state to the cell. The method further verifies the first state by reading from the cell. In the method, the state of the first adjacent cell of the cell and the state of the second adjacent cell of the cell are continuously switched according to a predetermined adjacent cell sequence, and the first adjacent cell of the cell is adjacent to the cell. And the second neighboring cell of the cell is adjacent to the cell, and the predetermined neighboring cell sequence should continuously switch the state of the first neighboring cell and the state of the second neighboring cell. Indicates the order. In the method, after the step of continuously switching, reading from the cell is performed to determine whether or not a change from the first state to the second state has occurred. The switching of the state of the first adjacent cell is not performed in response to reading of the first adjacent cell, and the switching of the state of the second adjacent cell is performed by the second adjacent cell. It is not performed in response to reading of. Furthermore, in the method, the reading of the first adjacent cell is not performed immediately before the switching of the state of the first adjacent cell, and the reading of the second adjacent cell is performed by the second adjacent cell. It is not performed immediately before the switching of the state. The method further acquires the predetermined neighbor cell sequence from the configuration storage circuit. The method is further characterized in that the configuration storage circuit further indicates the last neighbor cell in the predetermined neighbor cell sequence. In this method, the configuration storage circuit further includes a repeat indicator, and using the repeat indicator, the number of times of repeating the predetermined adjacent cell sequence is obtained, reading from the cell is performed, and from the first state Prior to determining whether the change to the second state has occurred, a continuous state switch of the first and second neighboring cells is determined using the repeat indicator according to the predetermined neighboring cell sequence. It is characterized by repeating for the number of times. The method is further characterized in that the first adjacent cells are aligned along the same bit line as the cell, and the second adjacent cells are aligned along the same word line as the cell. The method further includes that the predetermined neighbor cell sequence indicates that the first neighbor cell follows the second neighbor cell, and the state of the first neighbor cell of the cell, and the first of the cell. The continuous switching of the state of the two adjacent cells is performed such that the state of the second adjacent cell is switched earlier than the state of the first adjacent cell.

  A data processing system is further provided, the data processing system including an MRAM array having a plurality of cells, an MRAM controller connected to the MRAM array, and test logic. The test logic is connected to the MRAM controller and includes a configuration storage circuit that stores a predetermined sequence of at least two adjacent cell locations. When testing each cell of the plurality of cells, the test logic includes: The state of neighboring cell groups of the cell to be tested is continuously switched as indicated by at least two neighboring cell locations in the predetermined sequence. The data processing system is further characterized in that the MRAM array, the MRAM controller, and the test logic are provided in a single integrated circuit. The data processing system is further characterized in that the configuration storage circuit stores a last adjacent cell indicator indicating the end of the predetermined sequence. The data processing system further includes the configuration storage circuit storing a repeat indicator, wherein the repeat indicator is a series of at least two adjacent cells of the cell, the test logic being tested as indicated by the predetermined sequence. The number of times of continuous state switching is indicated. The data processing system is further characterized in that the state switching is not performed in response to the reading of the neighboring cell that performs the state switching.

  In addition, a method for testing a toggle MRAM having a plurality of cells is described. In this method, a test target cell is selected from the plurality of cells. The method further writes the first state to the cell. The method further verifies the first state by reading from the cell. The method further determines a first adjacent cell of the cell adjacent to the cell as indicated by a predetermined adjacent cell sequence. The method further switches the state of the first adjacent cell of the cell, and the switching of the state of the first adjacent cell is not performed in response to reading of the first adjacent cell. The method further determines a second adjacent cell of the cell adjacent to the cell as indicated by the predetermined adjacent cell sequence. The method further switches the state of the second adjacent cell of the cell, and the switching of the state of the second adjacent cell is not performed in response to reading of the second adjacent cell. In the method, after the switching of the state of the second adjacent cell, reading from the cell is performed to determine whether or not a change from the first state to the second state has occurred. The method further selects the next cell of the plurality of cells to be tested after performing the reading from the cell to determine whether the change from the first state to the second state has occurred. To do. The method further determines that the first neighboring cell is not the last neighboring cell of the predetermined sequence after the switching of the state of the first neighboring cell of the cell. The method further determines whether the change from the first state to the second state has occurred after the switching of the state of the second neighboring cell of the cell and after the reading from the cell. Before determining, it is determined that the second adjacent cell is the final adjacent cell of the predetermined sequence. The method further determines whether or not the repetition of the predetermined sequence is instructed after determining that the second adjacent cell is the final adjacent cell of the predetermined sequence. The method further includes selecting the next cell and then writing the third state to the next cell; reading from the next cell to verify the third state; adjacent to the next cell The third neighbor cell of the next cell is determined as indicated by the predetermined neighbor cell sequence; the state of the third neighbor cell of the next cell is determined as the state of the third neighbor cell of the next cell. Is switched in response to reading of the third adjacent cell of the next cell; the fourth adjacent cell of the next cell adjacent to the next cell is changed to the predetermined cell The state of the fourth neighbor cell of the next cell is changed as the state of the fourth neighbor cell of the next cell is changed to the state of the fourth neighbor cell of the next cell. Row in response to cell read Switching from the third state to the fourth state by performing a read from the next cell after the switching of the state of the fourth neighboring cell of the next cell. Determine whether or not The method is further characterized in that the second state is one of a logical state and an intermediate state. Further, the method is characterized in that the first adjacent cell and the second adjacent cell are not arranged along the same word line or the same bit line.

  Since the apparatus embodying the present invention is in most cases composed of electronic components and circuits known to those skilled in the art, circuit details are considered necessary as indicated above. It is intended to be able to understand and evaluate the underlying concepts of the present invention, never to explain more than is possible, and to make the suggestion of the present invention unclear or ambiguous. I don't want to end up.

  Some of the embodiments described above can be implemented using a variety of different information processing systems depending on the application. For example, while FIG. 1 and the description of FIG. 1 describe an exemplary information processing architecture, this exemplary architecture provides a useful reference architecture for describing various aspects of the present invention. It is only presented as such. Of course, the description of the architecture has been simplified for ease of explanation, and the architecture is merely one of many different types of suitable architectures that can be used in accordance with the present invention. Absent. For those skilled in the art, the boundaries of the logic block groups are merely exemplary, and in another embodiment, the logic block groups or circuit element groups can be integrated or separated. Can be added to various logic blocks or circuit elements.

  Although the invention has been described with reference to particular embodiments, various modifications and changes can be made without departing from the scope of the invention as set forth in the claims below. For example, in the flow chart of FIG. 5, boxes 116, 122, and 126 can be deleted, and the YES output from boxes 114 and 120, and the output of box 124 can all be connected to the input of box 110. The specification and drawings are accordingly to be regarded in an illustrative rather than a restrictive sense, and all such variations are considered to be within the scope of the invention. All effects, advantages, and technical solution (s) described herein with respect to particular embodiments are claimed in any claim, or on all essential, necessary, or basic of these claims. Should not be taken as a unique feature or element.

The term “coupled” as used herein is not limited to a direct connection or a mechanical connection.
Further, as used herein, the term “a” or “an” is defined as “one” or “more than one”. Also, the use of prefixes such as “at least one” and “one or more” in a claim group does this by placing the indefinite article “a” or “an” in front of another claim element. Any claim that contains a claim element with an indefinite article must always contain the indefinite article such as "a or or one" and the prefix "one or more" or "at least one" In any case, it should not be construed to mean that it is limited to an invention containing only one such element. The same interpretation applies for the use of definite articles.

  Unless otherwise noted, terms such as “first” and “second” are used to arbitrarily distinguish between the groups of elements described by such terms. Thus, these terms are not necessarily used to refer to the temporal priority or other priorities of such elements.

Claims (20)

In a method for testing a toggle MRAM having a plurality of cells,
Selecting a cell to be tested among the plurality of cells;
Writing a first state to the cell;
Reading from the cell to verify the first state;
Continuously switching a state of a first neighboring cell of the cell and a state of a second neighboring cell of the cell according to a predetermined neighboring cell sequence, wherein the first neighboring cell of the cell is adjacent to the cell And the second neighboring cell of the cell is adjacent to the cell, and the predetermined neighboring cell sequence continuously switches the state of the first neighboring cell and the state of the second neighboring cell. Continuously switching to indicate a power sequence;
After the step of switching continuously, performing a read from the cell to determine whether a change from the first state to the second state has occurred. The switching of the state of the first neighboring cell is not performed in response to reading of the first neighboring cell, and the switching of the state of the second neighboring cell is performed by the second neighboring cell. The method of claim 1, wherein the method is not performed in response to reading of. The reading of the first neighboring cell is not performed immediately before the switching of the state of the first neighboring cell, and the reading of the second neighboring cell is performed in the state of the second neighboring cell. The method of claim 1, wherein the method is not performed immediately before switching. The method of claim 1, further comprising obtaining the predetermined neighbor cell sequence from a configuration storage circuit. The method of claim 4, wherein the configuration storage circuit further indicates a final neighbor cell in the predetermined neighbor cell sequence. The configuration storage circuit includes a repeat indicator, and the repeat indicator is used to determine the number of times to repeat the predetermined adjacent cell sequence, and the reading from the cell is performed, and the second state is changed from the first state to the second state. The number of times the continuous state switching of the first and second neighboring cells is determined using the repeat indicator according to the predetermined neighboring cell sequence before determining whether the change to The method of claim 4, wherein the method is repeated only. The method of claim 1, wherein the first adjacent cells are aligned along the same bit line as the cells, and the second adjacent cells are aligned along the same word line as the cells. The predetermined neighbor cell sequence indicates that the first neighbor cell follows the second neighbor cell, and the state of the first neighbor cell of the cell and the second neighbor cell of the cell The method of claim 1, wherein the continuous switching of states is performed such that the state of the second neighboring cell switches faster than the state of the first neighboring cell. An MRAM array having a plurality of cells;
An MRAM controller connected to the MRAM array;
A test logic connected to the MRAM controller, the test logic comprising a configuration storage circuit for storing a predetermined sequence of at least two adjacent cell locations, and testing each cell of the plurality of cells; The data processing system, wherein the test logic continuously switches the state of adjacent cell groups of the cell being tested as indicated at at least two adjacent cell locations in the predetermined sequence. The data processing system of claim 9, wherein the MRAM array, the MRAM controller, and the test logic are provided in a single integrated circuit. The data processing system according to claim 9, wherein the configuration storage circuit stores a last adjacent cell indicator indicating the end of the predetermined sequence. The configuration storage circuit stores a repeat indicator that repeats a continuous state switch of a series of at least two neighboring cells of the cell, where the test logic is tested as indicated by the predetermined sequence. The data processing system of claim 9, wherein the data processing system indicates the number of times to perform. The data processing system according to claim 9, wherein the state switching is not performed in response to reading of the adjacent cell that performs state switching. In a method for testing a toggle MRAM having a plurality of cells,
Selecting a cell to be tested from the plurality of cells;
Writing a first state to the cell;
Reading from the cell to verify the first state;
Determining a first neighbor cell of the cell adjacent to the cell as indicated by a predetermined neighbor cell sequence;
Switching the state of the first neighboring cell of the cell so that the switching of the state of the first neighboring cell is not performed in response to reading of the first neighboring cell;
Determining a second adjacent cell of the cell adjacent to the cell as indicated by the predetermined adjacent cell sequence;
Switching the state of the second neighboring cell of the cell so that switching of the state of the second neighboring cell is not performed in response to reading of the second neighboring cell;
After the switching of the state of the second adjacent cell, reading from the cell to determine whether a change from the first state to the second state has occurred;
Selecting the next cell of the plurality of cells to be tested after performing the reading from the cell and determining whether the change from the first state to the second state has occurred. ,Method. 15. The method of claim 14, wherein after the switching of the state of the first neighbor cell of the cell, the method further comprises determining that the first neighbor cell is not the last neighbor cell of the predetermined sequence. Method. After the switching of the state of the second neighboring cell of the cell and before performing the reading from the cell to determine whether the change from the first state to the second state has occurred, 16. The method of claim 15, further comprising determining that the second neighbor cell is the last neighbor cell of the predetermined sequence. 17. After the step of determining that the second neighbor cell is the last neighbor cell of the predetermined sequence, the method further comprises determining whether repetition of the predetermined sequence is indicated. The method described in 1. After the step of selecting the next cell, further
Writing a third state to the next cell;
Reading from the next cell to verify the third state;
Determining a third neighbor cell of the next cell adjacent to the next cell as indicated by the predetermined neighbor cell sequence;
The state of the third neighbor cell of the next cell is switched, and the switch of the state of the third neighbor cell of the next cell is in response to reading of the third neighbor cell of the next cell Steps to prevent it from happening,
Determining a fourth neighbor cell of the next cell adjacent to the next cell as indicated by the predetermined neighbor cell sequence;
The state of the fourth neighbor cell of the next cell is switched, and the switching of the state of the fourth neighbor cell of the next cell is in response to reading of the fourth neighbor cell of the next cell Steps to prevent it from happening,
After the switching of the state of the fourth adjacent cell of the next cell, reading from the next cell to determine whether a change from the third state to the fourth state has occurred; 15. The method of claim 14, comprising. The method of claim 14, wherein the second state is one of a logical state or an intermediate state. The method of claim 14, wherein the first adjacent cell and the second adjacent cell are not aligned along the same word line or the same bit line.

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