JP2014204146A - Logic circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a logic circuit and a method of drive thereof which are highly tamper-proof and can iteratively provide logic many times.SOLUTION: A logic circuit includes: first and second ferroelectric capacitor groups; an evaluation circuit for detecting an amount of charge read out from the first ferroelectric capacitor group, and evaluating a result of predetermined logic synthesis depending on a charge retention state stored in the first ferroelectric capacitor group; a first transfer circuit for transferring a charge depending on the charge read out from the first ferroelectric capacitor group to the second ferroelectric capacitor group to write to the second ferroelectric capacitor group; and a second transfer circuit for transferring a charge depending on a charge read out from the second ferroelectric capacitor group to the first ferroelectric capacitor group to write to the first ferroelectric capacitor group.

Description

  The present invention relates to a logic circuit using a ferroelectric capacitor and a driving method thereof.

  In recent years, the necessity of storing programs and codes in a semiconductor chip and the necessity of storing confidential information such as passwords are increasing, and realization of a logic circuit with higher tamper resistance is required. As a logic circuit considering tamper resistance, a dynamic field programmable logic is known. The dynamic field programmable logic is a logic circuit with improved tamper resistance by programming a CMOS logic circuit using a data signal of a nonvolatile latch such as a ferroelectric memory.

Japanese Patent Laid-Open No. 06-275790 Japanese Patent Application Laid-Open No. 07-106528 JP-T-08-511895 JP 2002-246487 A

  However, in the above-described conventional logic circuit, when a data signal is input to the CMOS logic circuit, a CMOS amplitude signal is once output, so that the function may be copied by hacking the signal. Further, since the memory information is destroyed by reading, the ferroelectric memory can be used only once. For this reason, it has been desired to realize a logic circuit that has higher tamper resistance and can repeatedly perform logic.

  An object of the present invention is to provide a logic circuit having high tamper resistance and capable of repeatedly taking logic as many times as possible and a driving method thereof.

  According to one aspect of the embodiment, the first and second ferroelectric capacitor groups and the charge connected to the first ferroelectric capacitor group and read from the first ferroelectric capacitor group An evaluation circuit for detecting a quantity and evaluating a result of a predetermined logic synthesis in accordance with a charge holding state stored in the first ferroelectric capacitor group; the first ferroelectric capacitor group; and the second ferroelectric capacitor group; Connected to the second ferroelectric capacitor group, and transfers a charge corresponding to the read charge from the first ferroelectric capacitor group to the second ferroelectric capacitor group so as to transfer the second ferroelectric capacitor group. A first transfer circuit for writing into the body capacitor group; and a read circuit connected to the first ferroelectric capacitor group and the second ferroelectric capacitor group for reading from the second ferroelectric capacitor group The charge corresponding to the charge is changed to the first strong A logic circuit and a second transfer circuit is transferred to the collector capacitor group written in the first ferroelectric capacitor group are provided.

  According to another aspect of the embodiment, the amount of charge read from the first ferroelectric capacitor group is detected, and the charge holding state stored in the first ferroelectric capacitor group is determined. A method of driving a logic circuit for evaluating a result of a predetermined logic synthesis, wherein a read charge from the first ferroelectric capacitor group is determined when reading the first ferroelectric capacitor group By transferring the charge to the second ferroelectric capacitor group, the charge retention state is backed up by the second ferroelectric capacitor group, the second ferroelectric capacitor group is read, and the second ferroelectric capacitor group is read out. The charge retention state backed up is transferred to the first ferroelectric capacitor by transferring a charge corresponding to a read charge from the second ferroelectric capacitor group to the first ferroelectric capacitor group. The driving method of a logic circuit to write back to the group is provided.

  According to the disclosed logic circuit and the driving method thereof, logic synthesis is performed according to the charge holding state written in the ferroelectric capacitor, so that it is possible to prevent the logic from being analyzed from the layout pattern. Thereby, a logic circuit with high tamper resistance can be realized. In addition to the ferroelectric capacitor for evaluation, a backup ferroelectric capacitor is provided, and writing is performed after reading out the ferroelectric capacitor for evaluation. Therefore, the charge holding state of the ferroelectric capacitor for evaluation is changed. Can be maintained. Further, since reading and writing back of the ferroelectric capacitor can be realized only by charge transfer, the tamper resistance can be improved as compared with the case of operating at the CMOS level.

FIG. 1 is a diagram showing the principle of a logic circuit using a ferroelectric capacitor. FIG. 2 is a circuit diagram showing an example of a method for detecting a composite charge in a logic circuit using a ferroelectric capacitor. FIG. 3 is a diagram illustrating a method of evaluating a logical value based on the read total charge amount. FIG. 4 is a circuit diagram (part 1) illustrating the structure of the logic circuit and the driving method according to the first embodiment. FIG. 5 is a circuit diagram (part 2) illustrating the structure of the logic circuit and the driving method according to the first embodiment. FIG. 6 is a circuit diagram (part 3) illustrating the structure of the logic circuit and the driving method according to the first embodiment. FIG. 7 is a circuit diagram (part 4) illustrating the structure of the logic circuit and the driving method according to the first embodiment. FIG. 8 is a circuit diagram (part 5) illustrating the structure of the logic circuit and the driving method according to the first embodiment. FIG. 9 is a circuit diagram (part 6) illustrating the structure and driving method of the logic circuit according to the first embodiment. FIG. 10 is a circuit diagram (part 7) illustrating the structure of the logic circuit and the driving method according to the first embodiment. FIG. 11 is a circuit diagram (part 1) illustrating the structure and driving method of the logic circuit according to the second embodiment. FIG. 12 is a circuit diagram (part 2) illustrating the structure and driving method of the logic circuit according to the second embodiment. FIG. 13 is a circuit diagram (part 3) illustrating the structure and driving method of the logic circuit according to the second embodiment. FIG. 14 is a circuit diagram (part 4) illustrating the structure and driving method of the logic circuit according to the second embodiment. FIG. 15 is a circuit diagram (part 5) illustrating the structure and driving method of the logic circuit according to the second embodiment. FIG. 16 is a circuit diagram (part 6) illustrating the structure of the logic circuit and the driving method according to the second embodiment. FIG. 17 is a circuit diagram (part 7) illustrating the structure and driving method of the logic circuit according to the second embodiment. FIG. 18 is a circuit diagram (part 1) illustrating the structure and driving method of the logic circuit according to the third embodiment. FIG. 19 is a circuit diagram (part 2) illustrating the structure and driving method of the logic circuit according to the third embodiment. FIG. 20 is a circuit diagram (part 3) illustrating the structure and driving method of the logic circuit according to the third embodiment. FIG. 21 is a circuit diagram (part 4) illustrating the structure and driving method of the logic circuit according to the third embodiment. FIG. 22 is a circuit diagram (part 5) illustrating the structure and driving method of the logic circuit according to the third embodiment. FIG. 23 is a circuit diagram (part 6) illustrating the structure and driving method of the logic circuit according to the third embodiment. FIG. 24 is a circuit diagram showing a structure of a logic circuit and a driving method according to the fourth embodiment. FIG. 25 is a circuit diagram showing a structure of a logic circuit and a driving method according to the fifth embodiment. FIG. 26 is a circuit diagram showing a structure of a logic circuit and a driving method according to the sixth embodiment. FIG. 27 is a circuit diagram showing a basic configuration of a scramble circuit. FIG. 28 is a circuit diagram showing a basic configuration of the selector. FIG. 29 is a circuit diagram (part 1) illustrating the structure and driving method of the logical circuit according to the seventh embodiment. FIG. 30 is a circuit diagram (part 2) illustrating the structure of the logic circuit and the driving method according to the seventh embodiment. FIG. 31 is a circuit diagram showing a structure of a logic circuit according to the eighth embodiment. FIG. 32 is a circuit diagram (part 1) illustrating the driving method of the logic circuit according to the eighth embodiment. FIG. 33 is a circuit diagram (part 2) illustrating the driving method of the logic circuit according to the eighth embodiment. FIG. 34 is a circuit diagram showing a structure of a logic circuit according to the ninth embodiment. FIG. 35 is a circuit diagram (part 1) illustrating the driving method of the logic circuit according to the ninth embodiment. FIG. 36 is a circuit diagram (part 2) illustrating the driving method of the logic circuit according to the ninth embodiment. FIG. 37 is a circuit diagram showing a structure of a logic circuit and a driving method according to the tenth embodiment. FIG. 38 is a circuit diagram showing the structure and driving method of a logical circuit according to the eleventh embodiment. FIG. 39 is a circuit diagram showing an example of a general 4-capacitor type nonvolatile latch circuit. FIG. 40 is a circuit diagram (part 1) illustrating the structure of the nonvolatile latch circuit according to the twelfth embodiment. FIG. 41 is a circuit diagram (part 2) illustrating the structure of the nonvolatile latch circuit according to the twelfth embodiment.

[First Embodiment]
A logic circuit and a driving method thereof according to the first embodiment will be described with reference to FIGS.

  FIG. 1 is a diagram showing the principle of a logic circuit using a ferroelectric capacitor. FIG. 2 is a circuit diagram showing an example of a method for detecting a composite charge in a logic circuit using a ferroelectric capacitor. FIG. 3 is a diagram illustrating a method of evaluating a logical value based on the read total charge amount. 4 to 10 are circuit diagrams illustrating the structure of the logic circuit and the driving method according to the present embodiment.

  First, before describing the logic circuit according to the present embodiment, the principle of a logic circuit using a ferroelectric capacitor will be described with reference to FIG.

The circuit shown in FIG. 1 has a plurality of ferroelectric capacitors C _fa , C _fb , C _fc and a comparator 10 connected to the plurality of ferroelectric capacitors C _fa , C _fb , C _fc . One electrode (also referred to as a lower electrode, a common electrode, or a plate electrode) of the capacitors C _fa , C _fb , and C _fc is connected to each other and connected to the input terminal of the comparator 10. Input signals A, B, and C are input to the other electrodes (also referred to as upper electrodes) of the capacitors C _fa , C _fb , and C _fc , respectively, and an output signal X that is a determination value is output from the comparator 10. Here, although the case where it has three ferroelectric capacitors _Cfa , _Cfb , _Cfc is shown, the number of the ferroelectric capacitors 10 is not limited to this.

The ferroelectric capacitors C _fa , C _fb , and C _fc have a spontaneous polarization direction, and exhibit voltage-charge hysteresis characteristics depending on the voltage applied to the electrodes. When the voltage difference applied between the electrodes exceeds + V _c and −V _c which are positive or negative values, many charges are released or absorbed when the internal spontaneous polarization direction is reversed. V _c is called coercive voltage.

Here, it is assumed that a predetermined spontaneous polarization direction is programmed in advance in the ferroelectric capacitors C _fa , C _fb , and C _fc . Here, upward polarization is defined as U-polarization in the figure, and downward polarization is defined as P-polarization in the figure.

Ferroelectric capacitor _{C fa,} C _{fb, C fc} upper electrode signals A, B, and enter the C raising the potential of the upper electrode, the electric field direction and the ferroelectric capacitor _{C fa,} C _{fb, C fc} The amount of charge absorbed by the capacitor from the lower electrode changes according to the relationship with the spontaneous polarization direction. That is, in the ferroelectric capacitor with U polarization, the amount of charge absorbed from the lower electrode side is small, and in the ferroelectric capacitor with P polarization, the amount of charge absorbed from the lower electrode side is large. As a result, the synthesis of the signals A, B, and C weighted in an analog manner can be realized.

  The synthesized analog charge amount is charged to the stray capacitance in the case of voltage sensing, and depending on the voltage, and in the case of current sensing, the voltage is kept constant, and the comparator 10 determines whether it is high level (H) or low level (L). A value determination is made. That is, the signals A, B, and C can be combined with programmable weights. The comparator 10 can be realized by a latch amplifier and a reference voltage, or by comparing the reference voltage with an operational amplifier (OpeAmp).

  Next, an example of a method for detecting a composite charge in a logic circuit using a ferroelectric capacitor will be described in detail with reference to FIG.

The drain terminal of the P-type transistor P _cont is connected to the node n ₂ that is a common connection terminal of the lower electrodes of the ferroelectric capacitors C _fa , C _fb , and C _fc . The output terminal of the inverter 12 to which a control signal is input and the source terminal of the P-type transistor P _curr are connected to the node n ₁ that is the connection terminal of the source terminal of the P-type transistor P _cont . A capacitor C _tank is connected to the drain terminal of the P-type transistor P _curr . The gate terminal of the P-type transistor P _{cont and} the gate terminal of the P-type transistor P _curr are connected to each other. Between the P-type transistor node _{n 3} and the node _{n 2} is a connection terminal of the gate terminals of the P-type transistor _{P curr} of _{P cont,} capacitance _{C bias} is connected. Thus, a current mirror circuit is configured by the P-type transistor P _cont , the P-type transistor P _curr , and the capacitor C _bias as a voltage source for controlling the threshold voltage. A connection node n _out between the drain terminal of the P-type transistor P _curr and the capacitor C _tank is connected to the input terminal of the comparator 10.

It is assumed that a predetermined spontaneous polarization direction is written in the ferroelectric capacitors C _fa , C _fb , and C _fc . Here, the polarization is upward and the polarization is inverted when the potential of the node n ₂ is inverted, and a large amount of charge is absorbed, while the polarization is downward and the potential of the node n ₂ is increased and the polarization direction is not changed to absorb a small amount of charge. This shall be expressed as U-polarization.

When the signals A, B, and C input to the upper electrodes of the ferroelectric capacitors C _fa , C _fb , and C _fc are fixed at a low level (GND (ground) level), a control that is an input signal to the inverter 12 When the signal falls from the high level to the low level, the node n ₁ of the VDD side of the current mirror circuit rises from the low level to the high level. As a result, the node n _2, which is a common connection terminal of the lower electrodes of the ferroelectric capacitors C _fa , C _fb , and C _fc , is changed from the initial state that is at the low level to the VDD level due to the current flowing through the P-type transistor P _cont. It is charged towards. At this time, the threshold voltage _{V th} of the real P-type transistor _{P cont} With 0 by volume _{C bias,} is it possible to charge the node _{n 2} to VDD.

When the node n ₂ becomes high level, a low level voltage is applied to the upper electrodes of the ferroelectric capacitors C _fa , C _fb , and C _fc , and a high level voltage is applied to the lower electrodes. A voltage exceeding the coercive voltage is applied to the capacitors C _fa , C _fb , and C _fc . As a result, polarization inversion occurs in the P-polarized ferroelectric capacitor, and a large amount of charge is absorbed in the ferroelectric capacitor. On the other hand, a U-polarized ferroelectric capacitor absorbs a small amount of charge without changing the direction of polarization.

Here, since the charging current of the node n _{2 and} the charging current to the mirrored capacitor C _tank are equal to each other, the total charge amount absorbed by the ferroelectric capacitors C _fa , C _fb , and C _fc and the capacitor C _tank are The total amount of charge to be charged is equal. As a result, the voltage at the node n _out becomes a level corresponding to the total amount of charge absorbed by the ferroelectric capacitors C _fa , C _fb , and C _fc .

The voltage level of the node n _out changes according to the spontaneous polarization direction of the ferroelectric capacitors C _fa , C _fb , and C _fc . That is, when three of the ferroelectric capacitors C _fa , C _fb , and C _fc are U-polarized (U × 3), one is P-polarized and two are U-polarized (P × 1 + U × 2), two are The voltage level of the node _nout increases in the order of P polarization when one is U polarization (P × 2 + U × 1) and three are P polarization (P × 3).

Here, if the 1/0 determination level V _t in the comparator 10 is set to a level between the voltage level of (P × 3) and the voltage level of (P × 2 + U × 1), all are P-polarized. The logic of a certain AND can be determined. Further, when the determination level V _t is set to a level between the voltage level of (P × 1 + U × 2) and (U × 3), the logic of NOR that is all U-polarized can be determined ( (See FIG. 3). In this manner, logic synthesis of information written in the three ferroelectric capacitors C _fa , C _fb , and C _fc can be performed with an analog amount.

Signal A rises in synchronization with the signal to be input to the inverter 12, B, C the ferroelectric capacitor _{C fa, C fb,} when entering the _{C fc,} the ferroelectric capacitors _{C fa, C fb,} absorbed _{C fc} Including the case where the charge amount is 0, the charge amount becomes three values of P, U, 0 (P>U> 0).

In this case, the signal A is low level and the ferroelectric capacitor C _fa is P-polarized, the signal B is low level and the ferroelectric capacitor C _fb is P-polarized, and the signal C is low level and the ferroelectric capacitor C _fc is Only in the case of P polarization, it becomes 3P level. That is, with respect to the signals A, B, and C that are driven by the synchronous pulse after taking the logic of the level of each signal A, B, and C and the spontaneous polarization direction of the ferroelectric capacitors C _fa , C _fb , and C _fc NOR synthesis can be performed. For example, the signal A is high level and the ferroelectric capacitor C _fa is P-polarized, the signal B is low level and the ferroelectric capacitor C _fb is P-polarized, and the signal C is low level and the ferroelectric capacitor C _fc is P-polarized. In polarization, the condition is not satisfied. Alternatively, the signal A is low level and the ferroelectric capacitor C _fa is U-polarized, the signal B is low level and the ferroelectric capacitor C _fb is P-polarized, and the signal C is low level and the ferroelectric capacitor C _fc is P Even with polarization, the condition is not satisfied.

The operation principle at the time of reading, that is, the evaluation of the logical value is as described above, but the spontaneous polarization directions of the ferroelectric capacitors C _fa , C _fb , and C _fc are all U-polarized after one operation. For this reason, in order to operate again, it is necessary to set the initial spontaneous polarization direction again. Therefore, in the logic circuit according to the present embodiment, after the ferroelectric capacitors C _fa , C _fb , and C _fc are read, writing back to the initial state is performed.

  Next, a method for performing writing back after reading out the ferroelectric capacitors Cfa, Cfb, Cfc will be described with reference to FIGS.

  In addition to evaluating ferroelectric capacitors (hereinafter referred to as “evaluation capacitors”), backup ferroelectric capacitors (hereinafter referred to as “slave capacitors”) Call).

  Here, a description will be given from reading to writing back of one ferroelectric capacitor. When a plurality of evaluation capacitors are used, a plurality of slave capacitors are used correspondingly. In the present specification, when a plurality of evaluation capacitors and slave capacitors are used, they may be expressed as a “ferroelectric capacitor group”.

  From reading to writing back of the evaluation capacitor can be performed by, for example, four steps shown in FIGS.

4 to 7, the upper three ferroelectric capacitors represent the evaluation capacitor C _f , and the lower three ferroelectric capacitors represent the slave capacitor C _fx . The three ferroelectric capacitors show different states for one ferroelectric capacitor. That is, the connection relationship between the evaluation capacitor C _f and slave capacitor C _fx on the left, the direction of spontaneous polarization of the change when the initial state of the evaluation capacitor C _f is a P-polarization at the center, of the evaluation capacitor C _f The change of the spontaneous polarization direction when the initial state is U polarization is shown on the right side.

In the initial state, the slave capacitor C _fx is set to U polarization. That is, when the evaluation capacitor C _f is P-polarized, the slave capacitor C _fx is U-polarized (center of FIG. 4), and when the evaluation capacitor C _f is U-polarized, the slave capacitor C _fx is U-polarized ( The right side of FIG. Further, in the following series of steps, the upper electrode of the evaluation capacitor C _f and slave capacitor C _fx, considered to keep constantly applying a GND level voltage.

First, the evaluation capacitor _Cf is read. Reading of the evaluation capacitor C _f is performed by applying a pulse signal of a positive potential to the plate electrode (lower electrode) PL _Eva evaluation capacitor C _f.

When positive potential is applied to the plate electrode PL _Eva evaluation capacitor C _f, so that the voltage exceeding the magnitude of the coercive voltage is applied to the evaluation capacitor C _f. Thus, evaluation capacitor C _f is the polarization inversion occurs when the P polarization, the evaluation capacitor C _f is changed to U polarization from P polarization (center of FIG. 4). Further, when the evaluation capacitor _Cf is U-polarized, polarization inversion does not occur, and the evaluation capacitor _Cf is maintained as U-polarized (right side in FIG. 4).

At this time, a negative potential is applied to the plate electrode PL _Slv of the slave capacitor C _{fx in} synchronization with the positive potential applied to the plate electrode PL _Eva of the evaluation capacitor C _f . Further, the upper electrode and the upper electrode of the slave capacitor C _fx evaluation capacitor C _f, connected via a charge transfer amplifier comprising P-type transistor Q _P1. The charge transfer amplifier is a source follower with a fixed gate potential.

When the gate voltage of the P-type transistor Q _P1 is set to a potential of −V _th , the potential of the source (upper side in the drawing) of the P-type transistor Q _P1 is increased by the charge generated when the evaluation capacitor C _f is read. The amount of the charge potential of the source is increased to move the slave capacitor C _fx through the P-type transistor Q _P1, slave capacitor C _fx is charged.

When the polarization reversal of the evaluation capacitor C _f occurs, sufficient charge polarization inversion slave capacitor C _fx is sent, slave capacitor C _fx changes to P polarization from U polarization (center of FIG. 4). When the polarization reversal of the evaluation capacitor C _f is not generated, sufficient charge polarization reversal of the slave capacitor C _fx is not sent, the polarization reversal of the slave capacitor C _fx does not occur, the slave capacitor C _fx remains the U polarization Maintained (right side of FIG. 4). That is, the direction of spontaneous polarization of the evaluation capacitor C _f in the initial state, it is possible to copy (backup) in slave capacitor C _fx.

Then, the connection between the evaluation capacitor _{C f} and slave capacitor _{C fx,} returned to the charge transfer amplifier (FIG. 6) including the P-type transistor _{Q P1.} Thereafter, the potential of the plate electrode PL _Eva of the evaluation capacitor C _f and the potential of the plate electrode PL _Slv of the slave capacitor C _fx are returned to the GND level. At this time, the spontaneous polarization directions of the evaluation capacitor C _f and the slave capacitor C _fx do not change. In other words, the spontaneous polarization direction of the evaluation capacitor C _f and slave capacitor C _fx maintains intact U polarization if U polarization maintaining intact P polarization if P polarization (FIG. 5).

Next, the evaluation capacitor _Cf is written back. Writeback evaluation capacitor C _f is performed by applying a pulse signal of a positive potential to the plate electrode PL _Slv slave capacitor C _fx.

When positive potential is applied to the plate electrode PL _Slv slave capacitor C _fx, the slave capacitor C _fx voltage exceeding the magnitude of the coercive voltage is applied. Thereby, when the slave capacitor C _fx is P-polarized, polarization inversion occurs, and the slave capacitor C _fx changes from P-polarized to U-polarized (center of FIG. 6). When the slave capacitor C _fx is U-polarized, no polarization inversion occurs and the slave capacitor C _fx U-polarized is maintained (right side in FIG. 6).

At this time, a negative potential is applied to the plate electrode PL _Eva of the evaluation capacitor C _{f in} synchronization with the positive potential applied to the plate electrode PL _Slv of the slave capacitor C _fx . Further, the upper electrode and the upper electrode of the slave capacitor C _fx evaluation capacitor C _f, connected via a charge transfer amplifier comprising P-type transistor Q _P1.

When the gate voltage of the P-type transistor Q _P1 to the potential of V _th, the potential of the source of the P-type transistor Q _P1 by the charge generated due to the reading of the slave capacitor C _fx (lower side in the drawing) is raised. The amount of the charge potential of the source is increased to move the P-type transistor Q _P1 passage to evaluate capacitor C _f, the evaluation capacitor C _f is charged.

When the polarization reversal of the slave capacitor C _fx occurs, sufficient charge is sent to the polarization inversion evaluation capacitor C _f, the evaluation capacitor C _f is changed to P polarization from U polarization (center of FIG. 6). When the polarization reversal of the slave capacitor C _fx has not occurred is not sent sufficient charge polarization inversion of the evaluation capacitor C _f, the polarization reversal of the evaluation capacitor C _f does not occur, the evaluation capacitor C _f is U polarization (Right side of FIG. 6). That is, the direction of spontaneous polarization of the evaluation capacitor C _f after reading can be written back to the initial state.

Then, the connection between the evaluation capacitor _{C f} and slave capacitor _{C fx,} switch the charge transfer amplifier (Fig. 4) containing a P-type transistor _{Q P1.} Thereafter, the potential of the plate electrode PL _Eva of the evaluation capacitor C _f and the potential of the plate electrode PL _Slv of the slave capacitor C _fx are returned to the GND level in the standby state. At this time, the spontaneous polarization directions of the evaluation capacitor C _f and the slave capacitor C _fx do not change. That is, if the evaluation capacitor C _f and the slave capacitor C _fx are U-polarized, the U-polarization is maintained as it is, and if it is P-polarized, the P-polarization is maintained as it is (FIG. 7). Thereby, the spontaneous polarization directions of the evaluation capacitor C _f and the slave capacitor C _fx return to the initial state of FIG. 4.

In the steps shown in FIGS. 5 and 7, charge transfer occurs due to the paraelectric component capacitance without polarization inversion, but the evaluation capacitor C _f and the slave capacitor C _fx have the same capacitance and cancel each other. That is, no unnecessary potential difference occurs between the capacitor electrodes.

Further, when the evaluation capacitor _Cf is U-polarized in the step shown in FIG. 4, the spontaneous polarization direction in the initial state of the slave capacitor _Cfx is also U-polarized. As a result, even though the steps shown in FIGS. 4 to 7 are performed once, since the plate electrode PL _Eva and the plate electrode PL _Slv are driven in opposite phases, the paraelectric charge transfer occurs, but the two capacitors cancel each other. Both can maintain the U-polarized state.

Further, in the step shown in FIG. 4, the voltage applied to the plate electrode PL _Eva is raised by a drive circuit as shown in FIG. 2, and the majority charge logic can be obtained by outputting the integrated value of the total charge. .

The above is the principle of the write-back method of the evaluation capacitor C _f with charge transfer amplifier. However, in reality, when the gain of the charge transferred in the forward direction / reverse direction is 1 or less, the charge amount is gradually attenuated, and data cannot be held.

  Accordingly, two methods for amplifying the transfer charge are shown below.

  The first method is a method of adding a circuit for supplying an enhanced charge in the steps of FIGS. 4 and 6 (FIG. 8).

Specifically, in the step shown in FIG. 4, as shown in FIG. 8 (a), in addition to the charge transfer P-type transistor _QP1 , the charge amplifier inverter amplifier and the source are set to the GND level for the enhanced charge. And a P-type transistor Q _P2 is added. As a result, a charge of about 3 to 4 times the transfer charge can be supplied to the slave capacitor _Cfx .

Similarly, in the step shown in FIG. 6, as shown in FIG. 8 (b), in addition to the charge transfer P-type transistor _QP1 , the charge amplifier inverter amplifier, and the source is set to the GND level to perform the enhanced charge. A P-type transistor _QP2 to be supplied is added. Since the current direction is reversed in FIG. 8A and FIG. 8B, the connection between the inverter amplifier and the gate of the P-type transistor is different. Thus, it is possible to supply 3-fold to 4 times the charge of the transfer charges in the evaluation capacitor C _f.

Similar to the first method, the second method performs charge enhancement by an inverter amplifier and a P-type transistor _QP2. However, the charge enhancement at that time is about nine times, and the capacitance of the slave capacitor _Cfx is increased. This is a method of about 3 times (FIG. 9).

Specifically, in the step shown in FIG. 4, as shown in FIG. 9 (a), in addition to the P-type transistor Q _P1 for the charge transfer, and an inverter amplifier for charge enhancing, enhancing the charge source as GND level And a P-type transistor Q _P2 is added. Further, the capacitance of the slave capacitor C _fx is set to about three times (in the figure, the capacitor is represented by three capacitors for easy understanding of the difference in capacitance). Thereby, about nine times the transfer charge can be supplied to the slave capacitor _Cfx .

In the step shown in FIG. 7, as shown in FIG. 9B, the charge is not increased and the charge is transferred from the slave capacitor C _fx to the evaluation capacitor C _f . However, since the capacity of the slave capacitor C _fx is three times that of the first method, the transfer charge amount is three times. For this reason, the gain in a series of loops is obtained about nine times as in the first method. Charge enhancement may be further performed in the same manner as in the first method.

If the gain in a series of loops is 1 or more, data can be held continuously. It is desirable to appropriately set the charge enhancement magnification of the charge enhancement circuit and the capacity of the slave capacitor _{Cfx so} that the gain in a series of loops is 1 or more.

Next, a method of writing an arbitrary direction of spontaneous polarization of the initial state to the evaluation capacitor C _f, will be described with reference to FIG. 10.

As shown in FIG. 10, between the upper electrode and the GND level of the evaluation capacitor C _f, connects the N-type transistor Q _N3 for forced write.

In reading step of FIG. 4, when the plate electrode PL _Eva evaluation capacitor C _f rises to a positive potential, regardless of the direction of spontaneous polarization of the evaluation capacitor C _f, and U polarized the N-type transistor Q _N3 is turned on To do. Also, charge is injected into the slave capacitor _Cfx . As a result, the spontaneous polarization direction of the slave capacitor C _fx is forcibly set to P polarization (FIG. 10 shows a state in which the N-type transistor Q _N3 is turned on after driving the plate electrode PL _Eva and the plate electrode PL _Slv. And the evaluation capacitor C _f = U ↑ and the slave capacitor C _fx = P ↓). It turns off the N-type transistor _{Q N3} back from here and a plate electrode _{PL Eva} and the plate electrode _{PL Slv} to GND. Thereafter, if the evaluation cycle starts from FIG. 9A, the cycle starts from the evaluation capacitor C _f = U setting. On the other hand, if the evaluation cycle is skipped and writing back to the evaluation capacitor C _{f in} FIG. 9B is performed, the evaluation capacitor C _f can be set to P polarization. After the setting of the evaluation capacitor C _f is finished, it Susumere as usual evaluation cycle + write-back cycle.

  As described above, according to the present embodiment, a backup ferroelectric capacitor is provided in addition to the evaluation ferroelectric capacitor, and writing is performed after reading the evaluation ferroelectric capacitor. The charge retention state of the ferroelectric capacitor can be maintained. In addition, since logic synthesis is performed according to the charge retention state written in the ferroelectric capacitor, it is possible to prevent logic from being analyzed from the layout pattern. Thereby, a logic circuit with high tamper resistance can be realized.

[Second Embodiment]
A logic circuit and a driving method thereof according to the second embodiment will be described with reference to FIGS. Constituent elements similar to those of the logic circuit according to the first embodiment shown in FIGS. 1 to 10 are denoted by the same reference numerals, and description thereof is omitted or simplified.

  11 to 17 are circuit diagrams showing the structure of the logic circuit and the driving method according to the present embodiment.

In the present embodiment, a description will be given of another method of performing write back of the evaluation capacitor C _f with slave capacitor C _fx.

To write back the read-out of the evaluation capacitor C _f can be performed, for example, by four steps shown in FIGS. 11 to 14.

11 to 14, the upper three ferroelectric capacitors represent the evaluation capacitor C _f , and the lower three ferroelectric capacitors represent the slave capacitor C _fx . The three ferroelectric capacitors show different states for one ferroelectric capacitor. That is, the connection relationship between the evaluation capacitor C _f and slave capacitor C _fx on the left, the direction of spontaneous polarization of the change when the initial state of the evaluation capacitor C _f is a P-polarization at the center, of the evaluation capacitor C _f The change of the spontaneous polarization direction when the initial state is U polarization is shown on the right side.

In the initial state, the slave capacitor _Cfx is set to P polarization. That is, when the evaluation capacitor C _f is P-polarized, the slave capacitor C _fx is P-polarized (center of FIG. 11), and when the evaluation capacitor C _f is U-polarized, the slave capacitor C _fx is P-polarized ( FIG. 11 right side).

First, the evaluation capacitor _Cf is read. Upon reading the evaluation capacitor C _f, between the evaluation capacitor C _f and slave capacitor C _fx, transfer circuit including a current mirror circuit composed of N-type transistors are connected (see FIG. 11). The upper electrode TEL of the evaluation capacitor Cf is connected to the N-type transistor N _cont on the input side of the current mirror circuit, and is fixed to the GND level. The upper electrode TEL slave capacitor _{C fx} is connected to the N-type transistor _{N curr} output side of the current mirror circuit.

The application of a pulse signal that rises to the VDD level from the GND level to the plate electrode PL _Eva evaluation capacitor C _f in this state, a voltage exceeding the magnitude of the coercive voltage is applied to the evaluation capacitor C _f.

Thus, evaluation capacitor C _f is the polarization inversion occurs when the P polarization, the evaluation capacitor C _f is changed to U polarization from P polarization (center of FIG. 11). Charge released from the evaluation capacitor C _f With this is transferred to the N-type transistor N _cont input side, the slave capacitor C _fx through N-type transistor N _curr minute charge amplified by the current mirror circuit the output side Pulled out from.

In the initial state, the slave capacitor C _fx precharges the upper electrode TEL to the VDD level, and the plate electrode PL _Slv is fixed to the VDD level. When charge is extracted from the slave capacitor _Cfx , the upper electrode TEL falls from the VDD level to the GND level. Thus, the slave capacitor C _fx voltage exceeding the magnitude of the coercive voltage is applied, the slave capacitor C _fx is changed to U polarization from P polarization (center of FIG. 11).

On the other hand, when the evaluation capacitor _Cf is U-polarized, polarization inversion does not occur, and the evaluation capacitor _Cf is maintained as U-polarized (right side in FIG. 11). At this time, a small amount of charge is transferred from the evaluation capacitor C _f to the N-type transistor N _cont on the input side of the current mirror circuit, and is extracted from the slave capacitor C _fx by the N-type transistor N _curr on the output side of the current mirror circuit. A small amount of charge is generated. For this reason, the upper electrode of the slave capacitor C _fx hardly changes from the VDD level, and the slave capacitor C _fx is maintained in the P polarization (right side in FIG. 11).

Next, the potential of the plate electrode PL _Eva of the evaluation capacitor C _f is returned to the GND level, and the potential of the upper electrode TEL of the slave capacitor C _fx is returned to the VDD level. At this time, the spontaneous polarization directions of the evaluation capacitor C _f and the slave capacitor C _fx do not change. That is, the evaluation capacitor C _f and slave capacitor C _fx maintains intact U polarization if U polarization maintaining intact P polarization if P polarization (FIG. 12).

Next, the evaluation capacitor _Cf is written back. When the evaluation capacitor C _f is written back, a transfer circuit including a current mirror circuit formed of a P-type transistor is connected between the evaluation capacitor C _f and the slave capacitor C _fx (see FIG. 13). The upper electrode TEL of the slave capacitor C _fx is connected to the P-type transistor P _cont on the input side of the current mirror circuit and is fixed to the VDD level. The upper electrode TEL of the evaluation capacitor _{C f} is connected to the P-type transistor _{P curr} output side of the current mirror circuit.

The application of a falling pulse signal in this state from the plate electrode PL _Slv the VDD level slave capacitor C _fx to the GND level, the voltage exceeding the magnitude of the coercive voltage is to be applied to the slave capacitor C _fx.

Accordingly, when the slave capacitor C _fx is U-polarized, polarization inversion occurs, and the slave capacitor C _fx changes from U-polarization to P-polarization (center of FIG. 13). Along with this, charge is extracted from the P-type transistor P _cont on the input side of the current mirror circuit to the slave capacitor C _fx, and the charge amplified by the current mirror circuit is transferred to the P-type transistor P _curr on the output side of the current mirror circuit. Through the capacitor Cf for evaluation.

Evaluation capacitor _{C f} in the initial state, precharging upper electrode TEL to the GND level, the plate electrode _{PL Eva} is kept fixed at GND level. When the evaluation capacitor _Cf is charged, the upper electrode rises from the GND level to the VDD level. Thus, the evaluation capacitor C _f voltage exceeding the magnitude of the coercive voltage is applied, the evaluation capacitor Cf changes into P polarization from U polarization (middle of FIG. 13).

On the other hand, when the slave capacitor C _fx is P-polarized, polarization inversion does not occur, and the slave capacitor C _fx is maintained as P-polarized (right side in FIG. 13). At this time, a small amount of charge is drawn from the P-type transistor P _cont on the input side of the current mirror circuit to the slave capacitor C _fx , and the evaluation capacitor C _f is charged by the P-type transistor P _curr on the output side of the current mirror circuit. The charge is small. Therefore, the upper electrode of the evaluation capacitor C _f hardly changes from the GND level, the evaluation capacitor C _f is maintained at U polarization (right side in FIG. 13).

Next, the potential of the plate electrode PL _Slv of the slave capacitor C _fx is returned to the VDD level, and the potential of the upper electrode TEL of the evaluation capacitor C _f is returned to the GND level. At this time, the spontaneous polarization directions of the evaluation capacitor C _f and the slave capacitor C _fx do not change. That is, the evaluation capacitor C _f and slave capacitor C _fx maintains intact U polarization if U polarization maintaining intact P polarization if P polarization (FIG. 14).

As described above, when the evaluation capacitor C _f is P-polarized in the initial state, the evaluation capacitor C _f and the slave capacitor C _fx change from P-polarization to U-polarization in the read step, and U in the write-back step. It changes from polarization to P polarization and returns to the initial state. On the other hand, when the evaluation capacitor C _f is U-polarized in the initial state, if the slave capacitor C _fx is P-polarized in the initial state, the evaluation capacitor C _f and the slave capacitor C _fx are affected in the read and write back steps. The polarization direction is maintained.

In reading and writing back according to the present embodiment, the voltage applied to the plate electrodes PL _Eva and PL _Slv is the GND level or the VDD level, and the −VDD level is not required as in the first embodiment. This has the merit that the apparatus configuration can be simplified.

  In the system of this embodiment, the amplification factor of the current mirror circuit can be set arbitrarily. By making the gate width of the output-side transistor of the current mirror circuit wider (for example, twice) than that of the input-side transistor, amplification for compensating for the charge loss can be performed.

The threshold voltage _Vth of the transistor forming the current mirror circuit can be set to an arbitrary voltage by inserting a capacitor that gives a voltage offset to the input-side transistor. For example, if the voltage is set to 0 V, the potential of the upper electrode TEL of the evaluation capacitor C _f can be set to the GND level by completely fixing the GND level in the reading step, and the potential of the upper electrode TEL of the slave capacitor C _{fx in} the writing back step. Can be set to the VDD level.

In the present embodiment, using the nMOS current mirror from the evaluation capacitor C _f to the transfer of charge to the slave capacitor C _fx, it was used pMOS current mirror for transfer of charge to the evaluation capacitor C _f from slave capacitor C _fx Any one of them may be used. That is, both charges can be transferred by using two nMOS current mirrors or two pMOS current mirrors.

  Note that an example in which two offset capacitors and two current mirrors of the current mirror are used will be described in later embodiments.

Next, a method of writing an arbitrary direction of spontaneous polarization of the initial state to the evaluation capacitor C _f, will be described with reference to FIG. 15.

As shown in FIG. 15, the upper electrode TEL of the evaluation capacitor _{C f,} connects the forced write gate (inverter) 14.

In reading step of FIG. 11, while applying a voltage of VDD level or GND level to the upper electrode TEL of the evaluation capacitor _{C f,} the period GND level half the plate electrode _{PL Eva} evaluation capacitor _{C f,} the other half During this period, VDD level is applied. Thus, the evaluation capacitor C _f, P polarization is written when applying the VDD level voltage to the upper electrode TEL, U polarization is written upon application of a GND level voltage to the upper electrode TEL.

When reset all slave capacitor _{C fx} to the P polarization, in a state in which launched the upper electrode TEL slave capacitor _{C fx} to the VDD level, then by raising up the plate electrode _{PL Slv} slave capacitor _{C fx} to the VDD level Good.

After resetting all the slave capacitors C _fx to P polarization in this way, the upper electrode TEL and the plate electrode PL _{Eva of} the evaluation capacitor C _f , and the upper electrode TEL and the plate electrode PL _Slv of the slave capacitor C _fx are _changed as shown in FIG. Set to the initial level in the read step.

  Next, operations at power-on and power-off will be described with reference to FIGS.

In the power-off state, the upper electrode TEL and the plate electrode PL _Eva of the evaluation capacitor C _f and the upper electrode TEL and the plate electrode PL _Slv of the slave capacitor C _fx are at the GND level. Power During ON, while maintaining the polarization direction of the evaluation capacitor C _f, performs reset by writing P polarization to all the slave capacitor C _fx, it Sonaere the read step of FIG.

Therefore, first, the upper electrode TEL and plate electrodes PLSlv slave capacitor _{C fx,} as shown in FIG. 15, rise to the VDD level upper electrode TEL, in the order of the plate electrode PLSlv, P polarization to all slave capacitor _{C fx} Is written (FIG. 16A).

The state in which the upper electrode TEL and the plate electrode PL _Slv of the slave capacitor C _fx are raised to the VDD level is the voltage application level in the initial state of the reading step shown in FIG. 11 (FIG. 16B). Therefore, after this, as described above, it may perform reading and writing back the evaluation capacitor C _f.

At power-off, in the state of holding the spontaneous polarization direction of the evaluation capacitor C _f, or if you drop all node potential to the GND level.

Writes back at step 13, after returning to the voltage level of the read previous initial state in step 14, the upper electrode TEL and a plate electrode PL _Eva evaluation capacitor C _f, taken GND level (FIG. 17A). Accordingly, the voltage level of the upper electrode TEL and a plate electrode PL _Eva evaluation capacitor C _f may be maintained a state after the write back.

After that, the upper electrode TEL and the plate electrode PL _Slv of the slave capacitor C _fx at the VDD level (in the initial state before reading) fall to the GND level in the order of the plate electrode PL _Slv and the upper electrode TEL (FIG. 17). (B)). As a result, the P polarization direction is written in all the slave capacitors _Cfx .

Thus, _if the upper electrode TEL and the plate electrode PL _{Eva of} the evaluation capacitor C _f and the upper electrode TEL and the plate electrode PL _{Slv of} the slave capacitor C _fx are at the GND level, the power is turned off. Good.

In the case where the process of writing the P polarization to all the slave capacitors C _fx is performed when the power is turned on, there is no problem even if the spontaneous polarization direction of the slave capacitor C _fx changes with the power off operation. Therefore, when the power is turned off, the sequence of FIG. 17B may be omitted, and the upper electrode TEL and the plate electrode PL _Slv of the slave capacitor C _fx may be simultaneously lowered to the GND level without doing anything. There is no problem even if the power is suddenly turned off from the state.

  As described above, according to the present embodiment, a backup ferroelectric capacitor is provided in addition to the evaluation ferroelectric capacitor, and writing is performed after reading the evaluation ferroelectric capacitor. The charge retention state of the ferroelectric capacitor can be maintained. In addition, since logic synthesis is performed according to the charge retention state written in the ferroelectric capacitor, it is possible to prevent logic from being analyzed from the layout pattern. Thereby, a logic circuit with high tamper resistance can be realized.

[Third Embodiment]
A logic circuit and a driving method thereof according to the third embodiment will be described with reference to FIGS. The same components as those of the logic circuits according to the first and second embodiments shown in FIGS. 1 to 17 are denoted by the same reference numerals, and the description thereof is omitted or simplified.

  18 to 23 are circuit diagrams showing the structure of the logic circuit and the driving method according to the present embodiment.

In the present embodiment, a logic circuit provided with a capacitor pair (C _eva , C _evax ) dedicated to logic evaluation in addition to a capacitor pair (C _data , C _datax ) through which _data for holding is transferred will be described.

A logic circuit according to the present embodiment, as shown in FIG. 18, the holding capacitor _{C data} and its slave capacitor _{C DATAX,} evaluation capacitor _{C eva,} and a _{C EVAX.}

From reading to writing back of the holding capacitor C _data can be performed by, for example, six steps shown in FIGS.

In the initial state, the slave capacitor C _datax and the evaluation capacitor C _evax are set to P polarization.

First, the holding capacitor C _data is read. During reading of the holding capacitor _{C data,} the holding capacitor _{C data,} slave capacitor _{C DATAX,} between the evaluation capacitor _{C EVAX,} transfer circuit including a current mirror circuit composed of N-type transistors are connected (FIG. 18 reference). The upper electrode TEL of the holding capacitor C _data is connected to the N-type transistor N _cont on the input side of the current mirror circuit, and is fixed to the GND level. The upper electrode TEL slave capacitor _{C DATAX} and evaluation capacitor _{C EVAX} are respectively connected to the two N-type transistors _{N curr1, N CURR2} provided on the output side of the current mirror circuit.

The size of the plate when the electrode _{PL 11} and evaluation capacitor _{C eva} plate electrode _{PL 12} to GND level applies a pulse signal which rises to the VDD level, the holding capacitor _{C data} coercive voltage of the holding capacitor _{C data} in this state A voltage exceeding 1 is applied.

As a result, when the holding capacitor C _data is P-polarized, polarization inversion occurs, and the holding capacitor C _data changes from P-polarized to U-polarized. Accordingly, the charge discharged from the holding capacitor C _data is transferred to the N-type transistor N _cont on the input side of the current mirror circuit, and the amplified charge is _slaved by the N-type transistors N _curr1 and N _curr2 on the output side. It is pulled out from the capacitor C _datax and the evaluation capacitor C _evax .

In the initial state, the slave capacitor C _datax and the evaluation capacitor C _evax precharge the upper electrode TEL to the VDD level. Also, the plate electrode _{PL 22} of the plate electrode _{PL 21} and the evaluation capacitor _{C EVAX} slave capacitor _{C DATAX} is previously fixed to the VDD level.

When charges are extracted from the slave capacitor C _datax and the evaluation capacitor C _evax , the upper electrode TEL falls from the VDD level to the GND level. Thus, the slave capacitor _{C DATAX} and evaluation capacitor _{C EVAX} voltage exceeding the magnitude of the coercive voltage is applied, the slave capacitor _{C DATAX} and evaluation capacitor _{C EVAX} is changed to U polarization from P polarization (FIG. 18) .

On the other hand, when the holding capacitor C _data is U-polarized, no polarization inversion occurs, and the holding capacitor C _data is maintained as U-polarized. At this time, a small amount of charge is transferred from the holding capacitor C _data to the N-type transistor N _cont on the input side of the current mirror circuit, and the N-type transistors N _curr1 and N _curr2 on the output side _serve as the slave capacitor C _datax and the evaluation capacitor. A small amount of charge is extracted from the capacitor C _evax . Therefore, the upper electrode TEL slave capacitor _{C DATAX} and evaluation capacitor _{C EVAX} hardly changes from the VDD level, the slave capacitor _{C DATAX} and evaluation capacitor _{C EVAX} is maintained at P polarization.

Next, the potentials of the plate electrode PL ₁₁ of the holding capacitor C _data and the plate electrode PL ₁₂ of the evaluation capacitor C _eva are returned to the GND level, and the potentials of the slave capacitor C _data and the upper electrode TEL of the evaluation capacitor C _evax are set to the VDD level. Return to. At this time, the spontaneous polarization directions of the holding capacitor C _data , the slave capacitor C _datax , and the evaluation capacitor C _evax do not change (FIG. 19).

In this state, the evaluation capacitor C _evax can be used for summation evaluation (in FIG. 18 to FIG. 23, evaluation capacitors that can be used for summation evaluation are _marked with a circle and cannot be used. Is marked with an x). By separating the plate electrode _{PL 22} Rated capacitor _{C DATAX} from the holding capacitor _{C DATAX} the plate electrode _{PL 21,} while maintaining the spontaneous polarization direction of the holding capacitor _{C data,} and the slave capacitor _{C DATAX,} evaluation capacitor _{C EVAX} Can be used.

When the initial state of the holding capacitor C _data is P-polarized, the evaluation capacitor C _evax is U-polarized. In this state, the upper electrode TEL of the evaluation capacitor _{C EVAX} from VDD level when fall to GND level, the polarization reversal of the evaluation capacitor _{C EVAX} does not occur, the plate electrode _{PL 22} Rated capacitor _{C EVAX's} VDD level Maintained.

On the other hand, when the initial state of the holding capacitor C _data is U polarization, the evaluation capacitor C _evax is P polarization. In this state, when the upper electrode TEL of the evaluation capacitor _{C EVAX} lowers from the VDD level to the GND level, the polarization reversal occurs in the evaluation capacitor _{C EVAX,} the plate electrode _{PL 22} Rated capacitor _{C EVAX} stood GND level Lower (FIG. 20).

In this step, if the evaluation capacitor C _evax takes logic, the stored data is destroyed, but there is no problem because the evaluation capacitor C _evax is written back in the next phase.

Next, the holding capacitor C _data is written back. When the storage capacitor C _data is written back, a transfer circuit including a current mirror circuit composed of a P-type transistor is connected between the _storage capacitor C _data and the evaluation capacitors C _eva and C _evax (see FIG. 21). ). The upper electrode TEL of the slave capacitor C _datax is connected to the P-type transistor P _cont on the input side of the current mirror circuit, and is fixed to the VDD level. The upper electrodes TEL of the holding capacitor C _data and the evaluation capacitor C _eva are connected to two P-type transistors P _curr1 and P _curr2 provided on the output side of the current mirror circuit, respectively.

The application of a falling pulse signal to GND level from VDD level to the plate electrode _{PL 21} and the evaluation capacitor _{C EVAX} the plate electrode _{PL 22} slave capacitor _{C DATAX} In this state, the slave capacitor _{C DATAX} the magnitude of the coercive voltage Exceeding voltage will be applied.

Accordingly, when the slave capacitor C _datax is U-polarized, polarization inversion occurs, and the slave capacitor C _datax changes from U-polarization to P-polarization. As a result, charge is extracted from the P-type transistor P _cont on the input side of the current mirror circuit to the slave capacitor C _fx , and the amplified charge is _passed through the P-type transistors P _curr1 and P _curr2 on the output side for holding capacitors. C _data and the evaluation capacitor C _eva are charged.

In the initial state, the holding capacitor C _data and the evaluation capacitor C _eva precharge the upper electrode TEL to the GND level. Also, the plate electrode _{PL 12} of the plate electrode _{PL 11} and evaluation capacitor _{C eva} of the holding capacitor _{C data} is previously fixed to the GND level. When the holding capacitor C _data and the evaluation capacitor C _eva are charged, the upper electrode TEL rises from the GND level to the VDD level. Accordingly, the holding capacitor _{C data} and evaluation capacitor _{C eva} voltage exceeding the magnitude of the coercive voltage is applied, spontaneous polarization direction of the holding capacitor _{C data} and evaluation capacitor _{C eva} is changed to P polarization ( FIG. 21).

On the other hand, the spontaneous polarization direction of the slave capacitor _{C DATAX} is not generated is polarization inversion at the time of P, slave capacitor _{C DATAX} is maintained at P polarization. At this time, a small amount of charge is drawn from the input-side P-type transistor P _cont to the slave capacitor C _datax of the current mirror circuit, and the holding-side capacitor C _data and the evaluation capacitor are output by the output-side P-type transistors P _curr1 and P _curr2 . A small amount of charge is charged to C _eva . Therefore, the upper electrode TEL of the holding capacitor _{C data} and evaluation capacitor _{C eva} hardly changes from the GND level, the holding capacitor _{C data} and evaluation capacitor _{C eva} is maintained at U polarization.

Subsequently, the _potentials of the plate electrode PL ₂₁ of the slave capacitor C _data and the plate electrode PL ₂₂ of the evaluation capacitor C _evax are returned to the VDD level, and the potentials of the holding capacitor C _data and the upper electrode TEL of the evaluation capacitor C _eva are set to the GND level. Return to. At this time, the spontaneous polarization directions of the holding capacitor C _data , the slave capacitor C _datax , and the evaluation capacitor C _eva do not change (FIG. 22).

In this state, the evaluation capacitor C _eva can be used for the total evaluation. By separating the plate electrode _{PL 12} Rated capacitor _{C data} from the holding capacitor _{C data} of the plate electrode _{PL 11,} while maintaining the spontaneous polarization direction of the holding capacitor _{C data,} and the slave capacitor _{C DATAX,} evaluation capacitor _{C eva} Can be used.

When the initial state of the holding capacitor C _data is P-polarization, the evaluation capacitor C _eva is P-polarization. In this state, the upper electrode TEL of the evaluation capacitor _{C eva} from GND level when starting up to the VDD level, the polarization reversal of the evaluation capacitor _{C eva} does not occur, the plate electrode _{PL 12} Rated capacitor _{C eva's} GND level Maintained.

On the other hand, when the initial state of the holding capacitor C _data is U-polarized, the evaluation capacitor C _eva is U-polarized. In this state, when the upper electrode TEL of the evaluation capacitor _{C eva} launch from the GND level to the VDD level, the polarization reversal occurs in the evaluation capacitor _{C eva,} the plate electrode _{PL 12} Rated capacitor _{C eva} rises to VDD level (FIG. 23).

In this step, if the evaluation capacitor C _eva is logically taken, the stored data is destroyed, but there is no problem because the evaluation capacitor C _eva is written back in the next phase.

The logic circuit according to the second embodiment can evaluate the summation only in one of the four steps shown in FIGS. On the other hand, in the logic circuit according to the present embodiment, the total evaluation can be performed in two steps out of the six steps shown in FIGS. A plurality of evaluation capacitors may be further provided in parallel with the holding capacitor C _data and the slave capacitor C _datax so that more total evaluations can be performed.

  As described above, according to the present embodiment, a backup ferroelectric capacitor is provided in addition to the evaluation ferroelectric capacitor, and writing is performed after reading the evaluation ferroelectric capacitor. The charge retention state of the ferroelectric capacitor can be maintained. In addition, since logic synthesis is performed according to the charge retention state written in the ferroelectric capacitor, it is possible to prevent logic from being analyzed from the layout pattern. Thereby, a logic circuit with high tamper resistance can be realized. Further, by providing a ferroelectric capacitor for evaluation in addition to the ferroelectric capacitor for holding data, more total evaluations can be performed.

[Fourth Embodiment]
A logic circuit and a driving method thereof according to the fourth embodiment will be described with reference to FIG. Constituent elements similar to those of the logic circuits according to the first to third embodiments shown in FIGS. 1 to 23 are denoted by the same reference numerals, and description thereof is omitted or simplified.

  FIG. 24 is a circuit diagram illustrating the structure of the logic circuit and the driving method according to the present embodiment.

  In the present embodiment, a two-input selector using a ferroelectric capacitor will be described as an example of a circuit that operates based on the evaluation result of the ferroelectric capacitor.

The circuit shown in FIG. 24 inputs signals A and B through the bilateral gate circuit 16 controlled by the signal φ in the readout circuit shown in FIG. The signals A and B are input to the bilateral gate circuit 16 via the inverters 22 _A and 22 _B. Further, the control signal φ is input to the bilateral gate circuit 16 directly and via the inverter 24. This circuit is an example in which the pMOS current driver evaluates the common plate line PL in the direction of rising from the GND level to the VDD level. The ferroelectric capacitors C _fa and C _fb correspond to the evaluation capacitors C _f , C _eva and C _evax in the logic circuits according to the first to third embodiments, and these ferroelectric capacitors C _fa and C _{fb are used.} The program and write back are performed in the manner described above.

First, the capacitor C _tank is reset, and the input signal to the inverter 12 is lowered from the high level to the low level before the control signal φ rises. As a result, the plate line PL rises from the low level to the high level. Note that the resetting of the capacitor _{C tank,} after discharging the capacitor _{C tank} to the GND level, is to keep the high impedance state.

Next, the signals A and B which are two inputs are gated by the bilateral gate 16 operated by the control signal φ, and the upper electrodes of the ferroelectric capacitors C _fa and C _fb are driven. That is, when the signals A and B are at the high level, the upper electrode falls from the high level to the low level in synchronization with the control signal φ. If the signals A and B are at a low level, the upper electrode maintains a high level.

Here, it is assumed that the spontaneous polarization direction of the ferroelectric capacitor C _fa is downward (P polarization), and the spontaneous polarization direction of the ferroelectric capacitor C _fb is upward (U polarization). It is assumed that the read charge amount of P polarization is about three times the read charge amount of U polarization.

  At this time, when the signal A is at a high level, if the readout charge amount for U polarization is U and the readout charge amount for P polarization is P = 3 U, the readout charge amount when the signal B is at a high level is P + U = 4 U. The read charge amount when the signal B is at the low level is P + 0 = 3U. When the signal A is at the low level, the read charge amount when the signal B is at the high level is 0 + U = U, and the read charge amount when the signal B is at the low level is 0 + 0 = 0.

Therefore, if the comparator level is set between U to 3U, for example, 2U, an output signal that is high when the signal A is high and low when the signal A is low is Output is possible regardless of the B level. That is, it is possible to realize a state where the signal A is selected as a selector. The charge flowing into the plate line PL is mirrored by the current mirror circuit, the capacitor C _tank is charged, and the voltage obtained there is compared by the comparator in the same manner as described in FIG.

When selecting the signal B, as in the case of selecting the signal A, the spontaneous polarization direction of the ferroelectric capacitor C _fa is upward (U-polarization), and the spontaneous polarization direction of the ferroelectric capacitor C _fb is downward (P-polarization). ).

Table 1 summarizes the relationship between the input of the signals A and B and the spontaneous polarization direction of the ferroelectric capacitors C _fa and C _fb and the read charge amount.

As can be seen from Table 1, by setting one of the ferroelectric capacitors C _fa and C _fb to P polarization and the other to U polarization, and setting the comparator level so as to output a high level in the case of 3 U or more, P polarization is obtained. This is a selector for detecting the high level of the signal line on the side programmed. If the ferroelectric capacitors C _fa and C _fb are P-polarized and the comparator level is set to 6 U or more, AND (A, B) can be detected. If the comparator level is set to 0.5 U or less, OR (A, B) can be detected. As described above, a plurality of logical functions can be realized while using the same hardware.

  As described above, according to the present embodiment, a backup ferroelectric capacitor is provided in addition to the evaluation ferroelectric capacitor, and writing is performed after reading the evaluation ferroelectric capacitor. The charge retention state of the ferroelectric capacitor can be maintained. In addition, since logic synthesis is performed according to the charge retention state written in the ferroelectric capacitor, it is possible to prevent logic from being analyzed from the layout pattern. Thereby, a logic circuit with high tamper resistance can be realized.

[Fifth Embodiment]
A logic circuit and a driving method thereof according to the fifth embodiment will be described with reference to FIG. Constituent elements similar to those of the logic circuits according to the first to fourth embodiments shown in FIGS. 1 to 24 are denoted by the same reference numerals, and description thereof is omitted or simplified.

  FIG. 25 is a circuit diagram showing the structure of the logic circuit and the driving method according to the present embodiment.

  Also in this embodiment, a two-input selector using a ferroelectric capacitor will be described as an example of a circuit that operates based on the evaluation result of the ferroelectric capacitor.

  In the fourth embodiment, the example in which the pMOS current driver evaluates the common plate line PL in the direction of rising from the GND level to the VDD level is shown. In the present embodiment, an example in which the nMOS current driver evaluates the common plate line in the direction of falling from the VDD level to the GND level is shown.

The circuit shown in FIG. 25 inputs signals A and B through a bilateral gate circuit 16 controlled by a control signal φ, similarly to the circuit shown in FIG. The signals A and B are directly input to the bilateral gate circuit 16. Further, the control signal φ is input to the bilateral gate circuit 16 directly and via the inverter 24. The ferroelectric capacitors C _fa and C _fb correspond to the evaluation capacitors C _f , C _eva and C _evax in the logic circuits according to the first to third embodiments, and these ferroelectric capacitors C _fa and C _{fb are used.} The program and write back are performed in the manner described above.

The drain terminal of the N-type transistor N _cont is connected to the plate line PL connected to the lower electrodes (plate electrodes) of the ferroelectric capacitors C _fa and C _fb . An output terminal of the inverter 12 to which an evaluation start signal is input and a source terminal of the N-type transistor N _curr are connected to a node n ₁ that is a connection terminal of the source terminal of the N-type transistor N _cont . A capacitor C _tank is connected to the drain terminal of the N-type transistor N _curr . The gate terminal of the N-type transistor N _{cont and} the gate terminal of the N-type transistor N _curr are connected to each other. A capacitor C _bias is connected between the node n ₂ which is a connection terminal between the gate terminal of the N-type transistor N _{cont and} the gate terminal of the N-type transistor N _curr and the plate line PL. Thus, a current mirror circuit is configured by the N-type transistor N _cont , the N-type transistor N _curr , and the capacitor C _bias as a voltage source for threshold voltage control. A connection node n _out between the drain terminal of the N-type transistor N _curr and the capacitor C _tank is connected to the comparator 10.

First, the capacitor C _tank is reset, and the evaluation start signal input to the inverter 12 is raised from the low level to the high level. As a result, the plate line PL falls from the high level to the low level. Note that the resetting of the capacitor _{C tank,} after the node _{n out} VDD level to discharge capacity _{C tank,} is to keep the high impedance state.

Next, the signals A and B which are two inputs are gated by the bilateral gate 16 operated by the control signal φ, and the upper electrodes of the ferroelectric capacitors C _fa and C _fb are driven. That is, when the signals A and B are at the high level, the upper electrode rises from the low level to the high level in synchronization with the signal φ. If the signals A and B are at the low level, the upper electrode maintains the low level.

Here, the spontaneous polarization direction of the ferroelectric capacitor C _fa is upward (P polarization: a large amount of charge is generated with polarization inversion upon reading), and the spontaneous polarization direction of the ferroelectric capacitor C _fb is downward (U polarization: It is assumed that a small amount of electric charge is output without polarization reversal). In FIG. 25, since the common plate line PL is read with the reverse polarity at the GND level, the arrow in the polarization direction is inverted only in this case. It is assumed that the read charge amount of P polarization is about three times the read charge amount of U polarization.

  At this time, when the signal A is at a high level, if the readout charge amount for U polarization is U and the readout charge amount for P polarization is P = 3 U, the readout charge amount when the signal B is at a high level is P + U = 4 U. The read charge amount when the signal B is at the low level is P + 0 = 3U. When the signal A is at the low level, the read charge amount when the signal B is at the high level is 0 + U = U, and the read charge amount when the signal B is at the low level is 0 + 0 = 0.

Therefore, if the comparator level is set between U to 3U, for example, 2U, an output signal that is high when the signal A is high and low when the signal A is low is Output is possible regardless of the B level. That is, it is possible to realize a state where the signal A is selected as a selector. The charge flowing into the plate line PL is mirrored by the current mirror circuit, the capacitor C _tank is charged, and the voltage obtained there is compared by the comparator in the same manner as described in FIG.

When selecting the signal B, as in the case of selecting the signal A, the spontaneous polarization direction of the ferroelectric capacitor C _fa is downward (U-polarization), and the spontaneous polarization direction of the ferroelectric capacitor C _fb is upward (P-polarization). ).

The relationship between the input of the signals A and B and the spontaneous polarization direction of the ferroelectric capacitors C _fa and C _fb and the read charge amount are the same as in the case of the fourth embodiment (Table 1).

As can be seen from Table 1, by setting one of the ferroelectric capacitors C _fa and C _fb to P polarization and the other to U polarization, and setting the comparator level so as to output a high level in the case of 3 U or more, P polarization is obtained. This is a selector for detecting the high level of the signal line on the side programmed. If the ferroelectric capacitors C _fa and C _fb are P-polarized and the comparator level is set to 6 U or more, AND (A, B) can be detected. If the comparator level is set to 0.5 U or less, OR (A, B) can be detected. As described above, a plurality of logical functions can be realized while using the same hardware.

  As described above, according to the present embodiment, a backup ferroelectric capacitor is provided in addition to the evaluation ferroelectric capacitor, and writing is performed after reading the evaluation ferroelectric capacitor. The charge retention state of the ferroelectric capacitor can be maintained. In addition, since logic synthesis is performed according to the charge retention state written in the ferroelectric capacitor, it is possible to prevent logic from being analyzed from the layout pattern. Thereby, a logic circuit with high tamper resistance can be realized.

[Sixth Embodiment]
A logic circuit and a driving method thereof according to the sixth embodiment will be described with reference to FIG. Constituent elements similar to those of the logic circuits according to the first to fifth embodiments shown in FIGS. 1 to 25 are denoted by the same reference numerals, and description thereof is omitted or simplified.

  FIG. 26 is a circuit diagram illustrating the structure of the logical circuit and the driving method according to the present embodiment.

  In the present embodiment, a three-input selector using a ferroelectric capacitor will be described as an example of a circuit that operates based on the evaluation result of the ferroelectric capacitor. Here, an example using the pMOS current driver similar to that of the logic circuit according to the fourth embodiment is shown, but an nMOS current driver similar to that of the fifth embodiment may be used.

The circuit shown in FIG. 26 inputs signals A, B, and C through the bilateral gate circuit 16 controlled by the control signal φ in the readout circuit shown in FIG. This circuit is an example in which a common plate line is evaluated by a pMOS current driver in the direction of rising from the GND level to the VDD level. The ferroelectric capacitors C _fa , C _fb , C _fc correspond to the evaluation capacitors C _eva , C _evax in the logic circuit according to the second and third embodiments, and these ferroelectric capacitors C _fa , C _fb , C _fc program and write back are performed in the manner described above.

First, the capacitor C _tank is reset, and the control signal φ input to the inverter 12 is lowered from the high level to the low level. As a result, the plate line PL rises from the low level to the high level. Note that the resetting of the capacitor _{C tank,} after discharging the node _{n out} of the capacitor _{C tank} to the GND level, is to keep the high impedance state.

Next, the signals A, B, and C, which are three inputs, are gated by the bilateral gate 16 operated by the control signal φ, and the upper electrodes of the ferroelectric capacitors C _fa , C _fb , and C _fc are driven. That is, when the signals A, B, and C are at the high level, the upper electrode falls from the high level to the low level in synchronization with the signal φ. If the signals A, B, and C are at a low level, the upper electrode maintains a high level.

Here, it is assumed that the spontaneous polarization direction of the ferroelectric capacitor C _fa is downward (P polarization), and the spontaneous polarization direction of the ferroelectric capacitors C _fb and C _fc is upward (U polarization). It is assumed that the read charge amount of P polarization is about three times the read charge amount of U polarization.

  At this time, when the signal A is at a high level, if the readout charge amount for U polarization is U and the readout charge amount for P polarization is P = 3U, the readout charge amount when the signals B and C are at a high level is P + U + U = 5U. It becomes. When one of the signals B and C is at a high level and the other is at a low level, the read charge amount is P + U + 0 = 4U. The read charge amount when the signals B and C are at the low level is P + 0 + 0 = 3U.

  On the other hand, when the signal A is at a low level, the read charge amount when the signals B and C are at a high level is 0 + U + U = 2U. When one of the signals B and C is at a high level and the other is at a low level, the read charge amount is 0 + U + 0 = U. The read charge amount when the signals B and C are at the low level is 0 + 0 + 0 = 0.

Therefore, if the comparator level is set between U and 3U, for example, 2.5 U, an output signal that is high when A is high and low when A is low is Output is possible regardless of the levels of B and C. That is, it is possible to realize a state where the signal A is selected as a selector. The charge flowing into the plate line PL is mirrored by the current mirror circuit, the capacitor C _tank is charged, and the voltage obtained there is compared by the comparator in the same manner as described in FIG.

When selecting the signal B, as in the case of selecting the signal A, the spontaneous polarization direction of the ferroelectric capacitor C _fb is directed downward (P polarization), and the spontaneous polarization direction of the ferroelectric capacitors C _fa , C _fc is directed upward (U-polarization) may be set. When the signal C is selected, the spontaneous polarization direction of the ferroelectric capacitor C _fc is set downward (P polarization), and the spontaneous polarization direction of the ferroelectric capacitors C _fa and C _fb is set upward (U polarization). Just keep it.

Table 2 summarizes the relationship between the input of the signals A, B, and C and the spontaneous polarization directions of the ferroelectric capacitors C _fa , C _fb , and C _fc and the read charge amount.

As can be seen from Table 2, one of the ferroelectric capacitors C _fa , C _fb , and C _fc is P-polarized, the other is U-polarized, and the comparator level is set to output a high level when 2.5 U or more. Is set as a selector for detecting the high level of the signal line on the side where the P polarization is programmed.

If the comparator level is set to 0.5 U or less, OR (A, B, C) can be detected regardless of the spontaneous polarization direction of the ferroelectric capacitors C _fa , C _fb , and C _fc .

If the ferroelectric capacitors C _fa , C _fb , and C _fc are P-polarized and the comparator level is set to 8 U or more, AND (A, B, C) can be detected.

Further, for example, the ferroelectric capacitors C _fa and C _fb are P-polarized, the ferroelectric capacitor C _fc is U-polarized, and the comparator level is set so as to output a high level in the case of 6 U or more. A, B) can be detected. The same applies to other combinations in which two of the three are P-polarized.

  As described above, a plurality of logical functions can be realized while using the same hardware.

  As described above, according to the present embodiment, a backup ferroelectric capacitor is provided in addition to the evaluation ferroelectric capacitor, and writing is performed after reading the evaluation ferroelectric capacitor. The charge retention state of the ferroelectric capacitor can be maintained. In addition, since logic synthesis is performed according to the charge retention state written in the ferroelectric capacitor, it is possible to prevent logic from being analyzed from the layout pattern. Thereby, a logic circuit with high tamper resistance can be realized.

[Seventh Embodiment]
A logic circuit and a driving method thereof according to the seventh embodiment will be described with reference to FIGS. Constituent elements similar to those of the logic circuits according to the first to sixth embodiments shown in FIGS. 1 to 26 are denoted by the same reference numerals, and description thereof is omitted or simplified.

  FIG. 27 is a circuit diagram showing a basic configuration of a scramble circuit. FIG. 28 is a circuit diagram showing a basic configuration of the selector. 29 and 30 are circuit diagrams showing the structure of the logic circuit and the driving method according to the present embodiment.

  The scramble circuit is used for an encryption circuit or the like, and is designed to make it difficult to analyze by hashing addresses and data. Usually, since it is formed by hard logic, its operation may be analyzed when the circuit is read. For example, if a selector circuit as shown in the fourth to sixth embodiments is used, the polarization direction of the ferroelectric capacitor Since it is difficult to detect, high confidentiality can be obtained.

The circuit shown in FIG. 27 is a scramble circuit that converts six input signals of signals A to F into six output signals of signals A ^{* to} F ^* using a selector. The signal A ^* is a signal obtained by processing the signals A to F with the selectors SW _1A to SW _1F . The signal B ^* is a signal obtained by processing the signals A to F with the selectors SW _2A to SW _2F . The signal C ^* is a signal obtained by processing the signals A to F with the selectors SW _3A to SW _3F . The signal D ^* is a signal obtained by processing the signals A to F with the selectors SW _4A to SW _4F . The signal E ^* is a signal obtained by processing the signals A to F with the selectors SW _5A to SW _5F . The signal F ^* is a signal obtained by processing the signals A to F by the selectors SW _6A to SW _6F .

FIG. 28 is an example of a 6-input 1-output selector applicable to the selectors SW _{1A to} SW _6F in FIG. 27A is a logic notation, FIG. 27B is a block notation, and FIG. 27C is a MOS notation. The input signal can be selected by setting any one of SW _{A to} SW _F to a high level.

  In the present embodiment, a method of extending the number of inputs of a selector using a ferroelectric capacitor in order to realize the selector as described above with a selector using a ferroelectric capacitor will be described. Unlike the capacitive coupling logic described so far, the selector only needs to select one signal, so it is only necessary to compare the maximum charge without comparing the total charge amount of P = 3U, and the number of inputs can be expanded. It becomes.

The circuit shown in FIG. 29 has a capacitance C (C _{a to} C _f ) and a capacitance C _l (C _{la to} C _lf ) connected in series to each of the inputs A to F, and gates connected to these connection nodes. An N-type transistor Q (Q _{a to} Q _f ) to which electrodes are connected is included. The drain terminals of the N-type transistors Q _{a to} Q _f are bundled and connected to the comparator 10.

When the input signal is switched from the low level to the high level, a plurality of one capacitor C of the input (assuming the capacitance C _a in this case) only upward polarization: keep the (P polarization readout charge amount is large). Other capacitance C (capacitance here _C b -C _f, assume the capacitance _C la _{-C lf)} the downward polarization: keep the (U polarization readout charge amount is small). Then, the potential of the connection node between the capacitor C and the capacitor C _l, by capacitive division between the capacitance C and the capacitance C _l, high in capacitance C (capacitance C _a) is connected to the node of the P polarization, the capacity of the U polarization C (capacitance _C b -C _f) is lower than the connected nodes. These connection nodes of inputs A to F are wired-ORed by the source follower of the N-type transistor Q, and the maximum voltage is output to the node _Nmax .

29, if left input A is low, node _{G a} remains at the GND level, even if the input B~F has risen from the low level to the high level, the readout of the capacitance _C b -C _f Since the amount of charge is small, the levels of the nodes G _{b to} G _f are low. Therefore, the node _Nmax has a low U correspondence level. In contrast, when the input A has transitioned from a low level to a high level, the level of the node G _a is high, the node N _max becomes higher P corresponding level.

Therefore, by determining whether the potential of the node N _max is a level corresponding to U or a level corresponding to P, whether the input A is at a low level or a high level can be output. . That is, a selector can be realized.

  The same applies when selecting the inputs B to F.

Figure 30, in the circuit of FIG. 29, a capacitor C _l and the N-type transistor Q, it is obtained by sharing two inputs. That is, the capacitance _{C l1} and N-type transistor _{Q 1} is arranged in connection to the capacitance _{C a} and the capacitance _{C b,} the capacitance _{C l2} and N-type transistor _{Q 2} arranged in connection to the capacitor _{C c} and the capacitor _{C d,} capacity _{C l3} and N-type transistor _{Q 3} is provided connected to the capacitance _{C e} and capacitance _{C f.} In this way, it is possible to halve the total capacitance C _l and the N-type transistor Q.

Again, when the input signal is switched from the low level to the high level, a plurality of one volume of the input C (assuming capacitance C _a in this case) only upward polarization (P polarization: reading the charge amount large ). Other capacitors C (capacitances C _{b to} C _f and capacitors C _{11 to} C ₁₃ are assumed here) are set to downward polarization (U polarization: small read charge amount).

Level of the node G ₁ is input A, P + U = 4U when B is high, P + 0 = 3U at the input B a low level input A is high level, the input A is input B is high at the low level 0 + U = U, and when inputs A and B are at low level, 0 + 0 = 0. On the other hand, the unselected pair has U + U = 2U at the maximum at the high level and high level input.

  Therefore, if the comparison level of the comparator is set to a level between 2U and 3U (for example, 2.5 U), it can be determined whether the input A is at a high level or a low level. That is, a selector can be realized.

  The same applies when selecting the inputs B to F.

[Eighth Embodiment]
A logic circuit and a driving method thereof according to the eighth embodiment will be described with reference to FIGS. The same components as those of the logic circuits according to the first to seventh embodiments shown in FIGS. 1 to 30 are denoted by the same reference numerals, and description thereof will be omitted or simplified.

  FIG. 31 is a circuit diagram showing the structure of the logic circuit according to the present embodiment. 32 and 33 are circuit diagrams illustrating the driving method of the logic circuit according to the present embodiment.

  The logic circuit according to the present embodiment is a selector that determines any one of the input signals inA to inD. Here, a 4-input circuit configuration is shown for the sake of space, but it can be expanded to a selector with an arbitrary number of inputs by increasing the number of similar units.

Capacitances C _a , C _b , C _c , C _d are ferroelectric capacitors used for evaluation. These capacitors C _a , C _b , C _c , and C _d form two pairs as in the case of the selector shown in FIG. 30, and one read circuit is provided for each pair. Here, the return circuit 18 rating / write connected to the capacitor C _a, and a read circuit 20 connected capacitor Ca, the Cb, or described as a representative. The evaluation / write-back circuit 18 and the read circuit 20 connected to the other capacitors C _b , C _c , and C _d are the same as the evaluation / write-back circuit 18 and the read circuit 20 connected to the capacitor C _a .

The evaluation / write-back circuit 18 has an evaluation capacitor C _a and a backup capacitor C _ax . One electrode (left side of the drawing) of the capacitor C _a is connected to the N-type transistor on the input side of the current mirror circuit CMEa via the N-type transistor Q _1a that operates with the signal φEVAL3. One electrode of the capacitor C _a is also connected to the VDD line via a P-type transistor Q _2a operating with the signal φRSM1x. One electrode (the left side of the drawing) of the capacitor C _ax is connected to the N-type transistor on the output side of the current mirror circuit CMEa via the N-type transistor Q _3a operating with the signal φEVAL4. One electrode of the capacitor C _ax is also connected to the VDD line via a P-type transistor Q _4a operating with a signal φRSM2x. The common node of the current mirror circuit CMEa is connected to the output of a NAND gate that receives the input signal inA and the signal φEVAL5.

The other electrode (right side of the drawing) of the capacitor C _ax is connected to the N-type transistor on the input side of the current mirror circuit CMRa through the N-type transistor Q _5a that operates with the signal φRSM2. The other electrode of the capacitor C _ax is also connected to the VDD line via a P-type transistor Q _6a operating with a signal φEVAL 3x. The other electrode (the right side in the drawing) of the capacitance _{C a,} via the N-type transistor _{Q 7a} operating at signals FaiRSM1, is connected to the N-type transistor of the output side of the current mirror circuit CMRA. The other electrode of the capacitor C _a is also connected to the VDD line via a P-type transistor Q _8a operating with a signal φpreEVAL2x. The output side node of the current mirror circuit CMRa is connected to the output of a NOT gate that receives the signal φRSM3.

The other electrode of the capacitor Ca is further connected via a P-type transistor _{Q 9a} which operates in the signal FaiEVAL2x, is connected to the P-type transistor on the input side of the current mirror circuit CMS1 forming the readout circuit 20. The P-type transistor of the output side of the current mirror circuit CMS1 includes a capacitance _{C s1,} and N-type transistor _{Q 10a} which operates by the signal FaipreEVAL1, an N-type transistor _{Q 11a} are connected. The N-type transistor _Q10a is used when resetting the capacitor _Cs1 . The drain terminal of the N-type transistor Q _11a is connected to the VDD line, the source terminal is connected to the node SFO together with other N-type transistors Q _11c, etc., and takes the maximum voltage and is connected to the comparator 10. In addition, the N-type transistor _{Q 12} which operates by the signal FaipreEVAL1, this node SFO is reset to the GND level.

Next, the operation of the selector according to the present embodiment will be described with reference to FIGS. 32 and 33. FIG. Here, the operation of the 2-input selector section that selectively passes either the input signal inA or inB is shown. In the following example, (in the figure, represented by right-pointing arrows) P polarization in the capacitor C _a, and (in the figure, represented by left-pointing arrow) U polarization in the capacitor C _b advance by writing, to select the input signal inA An example will be described. In the capacities C _ax and C _bx , as in the case of the second embodiment, P polarization is written in the initial state.

  First, the evaluation steps will be described with reference to FIG.

In the evaluation step, as shown in FIG. 32, the signals φEVAL1 to 5 are set to the high level, and the signals φRSM1 to 3 are set to the low level. Thereby, the N-type transistors Q _1a , Q _1b , Q _3a , Q _3b and the P-type transistors Q _6a , Q _6b , Q _9a , Q _9b are turned on. Signal φpreEVAL1, after pulse driving for precharging the capacitance _{C s1} to GND level, the low level at step evaluation. Further, the signal φpreEVAL2x is driven to the high level in the evaluation step after the electrodes on the right side of the capacitors C _a and C _b that are at the low level at the end of the write back step are pulse-driven to the VDD level.

When the input signal inA is at a high level, the common node of the current mirror circuit CMEa is at a low level, and the path passes through the current mirror circuit CMS1, the P-type transistor Q _9a , the capacitor C _a , the N-type transistor Q _1a , and the current mirror circuit CMEa. current _{I 1} flows. With this current I ₁ , the capacitance C _a is inverted in polarization, and readout is performed to pass a large amount of charges. The capacitance _{C s1} by a current (charge) of the current _{I s,} which is mirrored by the current mirror circuit CMS1 is charged to a higher potential. The current - giving the gate potential of the source follower of the N-type transistor Q _11a by voltage conversion takes Waiyadooa with other pairs, the final high level is output from the comparator 10. At the same time, the current I ₂ mirrored by the current mirror circuit CMEa has a large current (charge), so that the capacitance C _ax is inverted in polarity. That is, the information on the polarization direction of the capacitor C _{a in} the initial state is backed up by the capacitor C _ax .

On the other hand, when the input signal inA is low, period signal φEVAL1~5 is high level the common node of the current mirror circuit CMEa goes high, current _{I 1} does not flow. Therefore, the capacitance C _a maintains the P polarization as it is. A current (charge) is zero mirrored current I _s in the current mirror circuit CMS1, capacitance C _s1 remains low potential, taken further Waiyadooa in the source follower of the N-type transistor Q _11a, eventually The comparator 10 outputs a low level. At the same time, since the current I ₂ does not flow, the capacitor C _ax maintains the P polarization. Therefore, write-back is not necessary because destructive reading does not occur in the evaluation step. However, in the write-back step that is performed simultaneously, the polarization of the capacitor C _ax does not occur, and the capacitor C _a does not undergo polarization inversion. _a retains P polarization.

When the input signal inB is high level, the common node of the current mirror circuit CMEb is low level, and the path passes through the current mirror circuit CMS1, the P-type transistor Q _9b , the capacitor Cb, the N-type transistor Q _1b , and the current mirror circuit CMEb. in the current _{I 3} flows. In this case, the capacitance C _b is not poled by a current I ₃ (maintaining the U polarization), and read to pass a small amount of charge. Therefore, current contribution is small to the current mirror circuit CMS1 by current I _3, are mostly current by the current path of the current I _1. At the same time, since the current (charge) of the current I ₄ mirrored by the current mirror circuit CMEb is small, the capacitor C _bx does not invert the polarization and maintains the P polarization as it is.

On the other hand, when the input signal inB is low, the common node of the signal φEVAL1~5 also the current mirror circuit in the high level period of CMEb goes high, current _{I 3} does not flow. Therefore, the capacitance _{C b} keeps the U polarization as it is. Nor current _{I 3} contributes to the current _{I s,} which is mirrored by the current mirror circuit CMS1. At the same time, since the current I ₄ does not flow, the capacitor C _bx maintains the P polarization. Accordingly, no destructive read occurs in the evaluation step, so that write back is not required. However, in the write back step that is performed simultaneously, the capacitance C _bx does not undergo polarization inversion, and thus the capacitance C _b does not undergo polarization inversion. _b retains U polarization.

Thus, the input signal inA and shunts most only current I _s When high be to output a high level at the comparator 10, the selector operation is realized.

  Next, the write back step will be described with reference to FIG.

In the write back step, as shown in FIG. 33, the signals φRSM1 to 3 are set to the high level and the signals φEVAL1 to 5 are set to the low level. Thereby, the N-type transistors Q _5a , Q _5b , Q _7a , Q _7b and the P-type transistors Q _2a , Q _2b , Q _4a , Q _4b are turned on.

When the signal φRSM3 becomes high level, the common node of the current mirror circuit CMRa becomes low level, and the current I ₅ flows through a path passing through the P-type transistor Q _4a , the capacitor C _ax , and the current mirror circuit CMRa. This current I ₅ is accompanied by inversion of the capacitance C _{ax to} the P polarization, and becomes a large amount of current. By this current I ₅ , the capacitance C _ax is reversed to P polarization and returned to the initial state. At the same time, a large amount of current I ₆ mirrored by the current mirror circuit CMRa flows through a path passing through the P-type transistor Q _2a , the capacitor Ca, the N-type transistor Q _7a , and the current mirror circuit CMRa. By this current I ₆ , the capacitance C _a is inverted to P polarization and returns to the initial state.

Similarly, the common node of the current mirror circuit CMRb is at a low level, and the current I ₇ flows through a path passing through the P-type transistor Q _4b , the capacitor C _bx , and the current mirror circuit CMRb. This current I ₇ does not accompany the polarization inversion of the capacitance C _bx , and becomes a small amount of current. At the same time, the current I ₈ mirrored by the current mirror circuit CMRb flows through a path passing through the P-type transistor Q _2b , the capacitor C _b , the N-type transistor Q _7b , and the current mirror circuit CMRb. The current I ₈ is a small amount of current that mirrors the current I ₇ , and the polarization inversion of the capacitance C _b does not occur. Thus, the capacitance _{C b} maintains the U polarization capacity _{C bx} maintains the P polarization.

In this way, the spontaneous polarization directions of the capacitors C _a , C _ax , C _b , and C _bx can be returned to the initial state.

In the above example, the capacitance Ca, Cb only, but are evaluated by an evaluation circuit using a current mirror circuit CMS1, capacitance _{C ax,} using a current mirror circuit CMSx1 similarly for _{C bx} Rating A circuit may be provided. As a result, charge integration and logic evaluation can be performed by this evaluation circuit even in the write back step.

  As described above, according to the present embodiment, a backup ferroelectric capacitor is provided in addition to the evaluation ferroelectric capacitor, and writing is performed after reading the evaluation ferroelectric capacitor. The charge retention state of the ferroelectric capacitor can be maintained. In addition, since logic synthesis is performed according to the charge retention state written in the ferroelectric capacitor, it is possible to prevent logic from being analyzed from the layout pattern. Thereby, a logic circuit with high tamper resistance can be realized.

[Ninth Embodiment]
A logic circuit and a driving method thereof according to the ninth embodiment will be described with reference to FIGS. The same components as those of the logic circuits according to the first to eighth embodiments shown in FIGS. 1 to 33 are denoted by the same reference numerals, and description thereof will be omitted or simplified.

  FIG. 34 is a circuit diagram showing the structure of the logic circuit according to the present embodiment. 35 and 36 are circuit diagrams illustrating the driving method of the logic circuit according to the present embodiment.

Similarly to the eighth embodiment, the logic circuit according to the present embodiment is also a selector that determines one of the input signals inA to inD. Here, a 4-input circuit configuration is shown for the sake of space, but it can be expanded to a selector with an arbitrary number of inputs by increasing the number of similar units. The selector according to the present embodiment is different from the selector according to the eighth embodiment in that a pMOS current mirror circuit is used for writing back to the capacitors C _{ax to} C _dx .

Capacitances C _a , C _b , C _c , C _d are ferroelectric capacitors used for evaluation. These capacitors C _a , C _b , C _c , and C _d form two pairs as in the case of the selector shown in FIG. 30, and one read circuit is provided for each pair. Here, the return circuit 18 rating / write connected to the capacitor C _a, and a read circuit 20 connected capacitor Ca, the Cb, or described as a representative. The evaluation / write-back circuit 18 and the read circuit 20 connected to the other capacitors C _b , C _c , and C _d are the same as the evaluation / write-back circuit 18 and the read circuit 20 connected to the capacitor C _a .

The evaluation / write-back circuit 18 has an evaluation capacitor C _a and a backup capacitor C _ax . One electrode (left side of the drawing) of the capacitor C _a is connected to the N-type transistor on the input side of the current mirror circuit CMEa via the N-type transistor Q _1a that operates with the signal φEVAL3. One electrode (left side of the drawing) of the capacitor C _ax is connected to a P-type transistor on the input side of the current mirror circuit CMRa through a P-type transistor Q _2a operating with a signal φRSM2. One electrode of the capacitor _{C a} is also connected via a P-type transistor _{Q 3a} which operates by the signal FaiRSM1x, is connected to the P-type transistor of the output side of the current mirror circuit CMRA. One electrode of the capacitor C _ax is also connected to the N-type transistor on the output side of the current mirror circuit CMEa via the N-type transistor Q _4a operating with the signal φEVAL4. The common node of the current mirror circuit CMEa is connected to the output of a NAND gate that receives the input signal inA and the signal φEVAL5. The common node of the current mirror circuit CMRa is connected to the signal line of the signal φRSM3 via a positive logic buffer.

The other electrode (right side of the drawing) of the capacitor C _a is connected to a connection node between the N-type transistor Q _5a operating with the signal φRSM1 and the P-type transistor Q _6a operating with the signal φpreEVAL2x. The other node of the N-type transistor _{Q 5a} is connected to a GND line, the other node of the P-type transistor _{Q 6a} is connected to the VDD line.

The other electrode of the capacitor C _a is further connected to a P-type transistor on the input side of the current mirror circuit CMS1 that forms a read circuit, via a P-type transistor Q _9a that operates with a signal φEVAL2x. The P-type transistor of the output side of the current mirror circuit CMS1 includes N-type transistor _{Q 10a} which operates by the signal FaipreEVAL1, an N-type transistor _{Q 11a} are connected. The drain terminal of the N-type transistor Q ₁₁ a is connected to the VDD line, and the source terminal is connected to the comparator 10.

Next, the operation of the selector according to the present embodiment will be described with reference to FIGS. Here, the operation of the 2-input selector section that selectively passes either the input signal inA or inB is shown. In the following example, (in the figure, represented by right-pointing arrows) P polarization in the capacitor C _a, and (in the figure, represented by left-pointing arrow) U polarization in the capacitor C _b advance by writing, to select the input signal inA An example will be described. In the capacities C _ax and C _bx , as in the case of the second embodiment, P polarization is written in the initial state.

  First, the evaluation steps will be described with reference to FIG.

In the evaluation step, as shown in FIG. 35, the signals φEVAL1 to 5 are set to the high level, and the signals φRSM1 to 3 are set to the low level. Thereby, the N-type transistors Q _1a , Q _1b , Q _4a , Q _4b and the P-type transistors Q _9a , Q _9b are turned on. Signal φpreEVAL1, after pulse driving for precharging the capacitance _{C s1} to GND level, the low level at step evaluation. Further, the signal φpreEVAL2x is driven to the high level in the evaluation step after the electrodes on the right side of the capacitors C _a and C _b that are at the low level at the end of the write back step are pulse-driven to the VDD level. The plate line is at the VDD level.

When the input signal inA is at a high level, the common node of the current mirror circuit CMEa is at a low level, and the path passes through the current mirror circuit CMS1, the P-type transistor Q _9a , the capacitor C _a , the N-type transistor Q _1a , and the current mirror circuit CMEa. current _{I 1} flows. With this current I ₁ , the capacitance C _a is inverted in polarization, and readout is performed to pass a large amount of charges. The capacitance _{C s1} by a current (charge) of the current _{I s,} which is mirrored by the current mirror circuit CMS1 is charged to a higher potential. The current - giving the gate potential of the source follower of the N-type transistor Q _11a by voltage conversion takes Waiyadooa with other pairs, the final high level is output from the comparator 10. At the same time, the current I ₂ mirrored by the current mirror circuit CMEa has a large current (charge), so that the capacitance C _ax is inverted in polarity. That is, the information on the polarization direction of the capacitor C _{a in} the initial state is backed up by the capacitor C _ax .

On the other hand, when the input signal inA is low, period signal φEVAL1~5 is high level the common node of the current mirror circuit CMEa goes high, current _{I 1} does not flow. Therefore, the capacitance C _a maintains the P polarization as it is. A current (charge) is zero mirrored current I _s in the current mirror circuit CMS1, capacitance C _s1 remains low potential, taken further Waiyadooa in the source follower of the N-type transistor Q _11a, eventually The comparator 10 outputs a low level. At the same time, since the current I ₂ does not flow, the capacitor C _ax maintains the P polarization. Therefore, write-back is not required because destructive reading does not occur in the evaluation step, but the capacitance C _ax is not reversed in polarity in the simultaneous write-back step, so that the capacitance C _a is not reversed without reversing the polarization of the capacitance C a. _a maintains P polarization.

When the input signal inB is at a high level, the common node of the current mirror circuit CMEb is at a low level and passes through the current mirror circuit CMS1, the P-type transistor Q _9b , the capacitor C _b , the N-type transistor Q _1b , and the current mirror circuit CMEb. current _{I 3} flows through the path. In this case, the capacitance C _b is not poled by a current I ₃ (maintaining the U polarization), and read to pass a small amount of charge. Therefore, current contribution is small to the current mirror circuit CMS1 by current I _3, are mostly current by the current path of the current I _1. At the same time, since the current (charge) of the current I ₄ mirrored by the current mirror circuit CMEb is small, the capacitor C _bx does not invert the polarization and maintains the P polarization as it is.

On the other hand, when the input signal inB is low, the common node of the signal φEVAL1~5 also the current mirror circuit in the high level period of CMEb goes high, current _{I 3} does not flow. Therefore, the capacitance _{C b} keeps the U polarization as it is. Nor current _{I 3} contributes to the current _{I s,} which is mirrored by the current mirror circuit CMS1. At the same time, since the current I ₄ does not flow, the capacitor C _bx maintains the P polarization. Therefore, write back is not required because destructive reading does not occur in the evaluation step, but the capacitance C _bx is not inverted in polarity in the simultaneous write-back step, so that the capacitance C _b is not inverted, and the capacitance C _b is not inverted. Maintain the U polarization of _b .

Thus, the input signal inA and shunts most only current I _s When high be to output a high level at the comparator 10, the selector operation is realized.

  Next, the write back step will be described with reference to FIG.

In the write back step, as shown in FIG. 36, the signals φRSM1 to 3 are set to the high level and the signals φEVAL1 to 5 are set to the low level. Thereby, the N-type transistors Q _5a and Q _5b and the P-type transistors Q _2a , Q _2b , Q _3a , and Q _3b are turned on. The plate line is at the GND level.

When the signal φRSM3 goes high, the common node of the current mirror circuit CMRA goes high, current mirror circuit CMRA, P-type transistors _{Q 2a,} the current _{I 5} a path passing through the capacitor _{C ax} flows. This current I ₅ is accompanied by inversion of the capacitance C _{ax to} the P polarization, and becomes a large amount of current. By this current I ₅ , the capacitance C _ax is reversed to P polarization and returned to the initial state. At the same time, a large amount of current I ₆ mirrored by the current mirror circuit CMRa flows along a path passing through the current mirror circuit CMRa, the P-type transistor Q _3a , the capacitor C _a , and the N-type transistor Q _5a . By this current I ₆ , the capacitance C _a is inverted to P polarization and returns to the initial state.

Similarly, the common node of the current mirror circuit CMRb is at a high level, and the current I ₇ flows through a path that passes through the current mirror circuit CMRb, the P-type transistor Q _2b , and the capacitor C _bx . This current I ₇ does not accompany the polarization inversion of the capacitor Cbx, and is a small amount of current. At the same time, the current I ₈ mirrored by the current mirror circuit CMRb flows along a path passing through the current mirror circuit CMRb, the P-type transistor Q _3b , the capacitor C _b , and the N-type transistor Q _5b . The current I ₈ is a small amount of current that mirrors the current I ₇ , and the polarization inversion of the capacitance C _b does not occur. Thus, the capacitance _{C b} maintains the U polarization capacity _{C bx} maintains the P polarization.

In this way, the spontaneous polarization directions of the capacitors C _a , C _ax , C _b , and C _bx can be returned to the initial state.

In the above example, only the capacitors C _a and C _b are evaluated by the evaluation circuit using the current mirror circuit CMS1, but the current mirror circuit CMSx1 is similarly used for the capacitors C _ax and C _bx . An evaluation circuit may be provided. As a result, charge integration and logic evaluation can be performed by this evaluation circuit even in the write back step.

  As described above, according to the present embodiment, a backup ferroelectric capacitor is provided in addition to the evaluation ferroelectric capacitor, and writing is performed after reading the evaluation ferroelectric capacitor. The charge retention state of the ferroelectric capacitor can be maintained. In addition, since logic synthesis is performed according to the charge retention state written in the ferroelectric capacitor, it is possible to prevent logic from being analyzed from the layout pattern. Thereby, a logic circuit with high tamper resistance can be realized.

[Tenth embodiment]
A logic circuit and a driving method thereof according to the tenth embodiment will be described with reference to FIG. The same components as those of the logic circuits according to the first to ninth embodiments shown in FIGS. 1 to 36 are denoted by the same reference numerals, and description thereof will be omitted or simplified.

  FIG. 37 is a circuit diagram showing the structure of the logic circuit and the driving method according to the present embodiment.

  In this embodiment, an example in which the ferroelectric capacitor portion of the selector according to the ninth embodiment is replaced with a NAND capacitor unit is shown.

The selector according to the present embodiment, as shown in FIG. 37, in which the capacity of the selector according to a ninth embodiment C, and C _x, is replaced with a NAND-type capacitor unit. That is, instead of the ferroelectric capacitors C _a and C _ax , a NAND capacitor unit is provided in which a plurality of parallel connection bodies of ferroelectric capacitors and bilateral gates are connected in series.

The bilateral gate disconnects the connection between terminals with a low-level input and connects the terminals with a high-level input. For example, when the capacitors C _a2 and C _ax2 are selected, the signals S ₁ , S ₃ , and S ₄ are set to the high level, and the signal S _{2 is set} to the low level. Thus, the signal _{S 1,} S 3, capacitor is connected in parallel with the bilateral gate driven by _{S 4 C a1, C a3,} C a4, C ax1, C ax3, C ax4 is bypassed, the capacitance _{C a2,} Only C _ax2 contributes to substantial circuit operation.

Therefore, a predetermined spontaneous polarization direction is programmed in advance in a set of capacitors C _a1 and C _ax1, a set of capacitors C _a2 and C _ax2, a set of capacitors C _a3 and C _{ax3, and} a set of capacitors C _a4 and C _ax4. Thus, an arbitrary set can be selected by the signals S _{1 to} S ₄ .

  The operation of the selector according to the present embodiment is the same as that of the selector according to the ninth embodiment except that a set of capacitors to be used is selected.

  In the above example, one example is shown in which one set is selected from four sets of capacities, but the number of sets of capacities is not limited to four, and can be any number.

  As described above, according to the present embodiment, since the capacitor unit for selecting and connecting a desired ferroelectric capacitor from a plurality of ferroelectric capacitors is provided, the charge holding state of the ferroelectric capacitor group for evaluation is desired. You can easily switch to

[Eleventh embodiment]
A logic circuit and a driving method thereof according to the eleventh embodiment will be described with reference to FIG. The same components as those of the logic circuits according to the first to ninth embodiments shown in FIGS. 1 to 37 are denoted by the same reference numerals, and description thereof will be omitted or simplified.

  FIG. 38 is a circuit diagram illustrating the structure of the logic circuit and the driving method according to the present embodiment.

  This embodiment shows an example in which the ferroelectric capacitor portion of the selector according to the ninth embodiment is replaced with a NOR type capacitor unit.

The selector according to the present embodiment, as shown in FIG. 38, the capacity of the selector according to a ninth embodiment C, and C _x, is replaced with a NOR-type capacitor unit. That is, instead of the ferroelectric capacitors C _a and C _ax , a NOR type capacitor unit in which a plurality of serially connected bodies of ferroelectric capacitors and bilateral gates are connected in parallel is provided. The bilateral gate functions as a switch for controlling connection / release between terminals.

The bilateral gate disconnects the connection between terminals with a low-level input and connects the terminals with a high-level input. For example, when the capacitors C _a2 and C _ax2 are selected, the signals S ₁ , S ₃ and S ₄ are set to a low level, and the signal S _{2 is set} to a high level. Thus, the signal _{S 1,} S 3, capacitor connected to the bilateral gate driven by _{S 4 C a1, C a3,} C a4, C ax1, C ax3, C ax4 is disconnected, the capacitance _{C a2, C ax2} Only contributes to substantial circuit operation.

Therefore, a predetermined spontaneous polarization direction is programmed in advance in a set of capacitors C _a1 and C _ax1, a set of capacitors C _a2 and C _ax2, a set of capacitors C _a3 and C _{ax3, and} a set of capacitors C _a4 and C _ax4. Thus, an arbitrary set can be selected by the signals S _{1 to} S ₄ .

  The operation of the selector according to the present embodiment is the same as that of the selector according to the ninth embodiment except that a set of capacitors to be used is selected.

  In the above example, one example is shown in which one set is selected from four sets of capacities, but the number of sets of capacities is not limited to four, and can be any number.

  Thus, according to the present embodiment, as the ferroelectric capacitor of the latch circuit, the capacitor unit for selecting and connecting a desired ferroelectric capacitor from a plurality of ferroelectric capacitors is provided. The charge retention state of the body capacitor can be easily switched to a desired set.

[Twelfth embodiment]
A logic circuit and a driving method thereof according to the twelfth embodiment will be described with reference to FIGS. The same components as those of the logic circuits according to the first to eleventh embodiments shown in FIGS. 1 to 38 are denoted by the same reference numerals, and the description thereof is omitted or simplified.

  FIG. 39 is a circuit diagram showing an example of a general 4-capacitor type nonvolatile latch circuit. 40 and 41 are circuit diagrams showing the structure of the nonvolatile latch circuit according to the present embodiment.

For example, as shown in FIG. 39, a general 4-capacitor type nonvolatile latch circuit includes ferroelectric capacitors C _a and C _ax connected to the input side terminal of the flip-flop circuit, and an output terminal of the flip-flop circuit. The ferroelectric capacitors C _b and C _bx are connected. By storing polarization information corresponding to the initial value of the flip-flop circuit in these ferroelectric capacitors C _a , C _ax , C _b , and C _bx , the flip-flop circuit after power-on is returned to the initial value state. be able to.

In FIG. 40, the ferroelectric capacitors C _a , C _ax , C _b , and C _bx of such a nonvolatile latch circuit are replaced with NAND type capacitor units as shown in the tenth embodiment. In FIG. 41, the ferroelectric capacitors C _a , C _ax , C _b , and C _bx are replaced with NOR type capacitor units as shown in the eleventh embodiment.

By doing in this way, it is possible to switch to four sets of data selected by the signals S _{1 to} S ₄ as the data of the ferroelectric capacitors C _a , C _ax , C _b , and C _bx . The NAND type capacitor unit of FIG. 40 can be read and written back in the same manner as a general latch by using the circuit shown in FIG. 39, for example. 41 can be read and written back by the circuit shown in FIG. 39, for example.

  In the above example, one of four capacitors is selected. However, the number of capacitors provided in parallel or in series is not limited to four, and can be any number. .

In the example of the nonvolatile latch circuit of FIG. 40, the capacitors C _ax and C _bx may be formed of paraelectric capacitors, and only the capacitors C _a and C _b may be a NAND capacitor unit of a ferroelectric capacitor.

In the example of the nonvolatile latch of FIG. 41, the capacitors C _ax and C _bx may be formed of paraelectric capacitors, and only the capacitors C _a and C _b may be NOR capacitor units of ferroelectric capacitors.

Further, the capacitor unit that replaces the ferroelectric capacitors C _a , C _ax , C _b , and C _bx of the nonvolatile latch shown in FIG. 39 is not necessarily required to be unified with either the NAND type capacitor unit or the NOR type capacitor unit. Absent. For example, the ferroelectric capacitors C _a and C _b may be replaced with NOR type capacitor units, and the ferroelectric capacitors C _ax and C _bx may be replaced with NAND type capacitor units.

  In this embodiment, the nonvolatile latch circuit having the ferroelectric capacitor connected to the input node and the output node of the flip-flop circuit is shown. However, the basic configuration of the nonvolatile latch circuit is not limited to this. Absent. Any nonvolatile latch circuit using a ferroelectric capacitor can be widely applied.

  Thus, according to the present embodiment, as the ferroelectric capacitor of the latch circuit, the capacitor unit for selecting and connecting a desired ferroelectric capacitor from a plurality of ferroelectric capacitors is provided. The charge retention state of the body capacitor can be easily switched to a desired set.

[Modified Embodiment]
The logic circuit and the driving method thereof described in the above embodiment are merely examples, and can be appropriately modified or changed according to the common general knowledge of those skilled in the art.

  Regarding the above embodiment, the following additional notes are disclosed.

(Supplementary Note 1) First and second ferroelectric capacitor groups;
It is connected to the first ferroelectric capacitor group, detects the amount of charge read from the first ferroelectric capacitor group, and enters the charge holding state stored in the first ferroelectric capacitor group. An evaluation circuit for evaluating the result of a predetermined logic synthesis according to
The second ferroelectric capacitor group is connected between the first ferroelectric capacitor group and the second ferroelectric capacitor group, and a charge corresponding to a read charge from the first ferroelectric capacitor group is transferred to the second ferroelectric capacitor group. A first transfer circuit for transferring to the body capacitor group and writing to the second ferroelectric capacitor group;
The first ferroelectric capacitor group and the second ferroelectric capacitor group are connected between the first ferroelectric capacitor group, and a charge corresponding to a read charge from the second ferroelectric capacitor group is transferred to the first ferroelectric capacitor group. And a second transfer circuit for transferring to the body capacitor group and writing to the first ferroelectric capacitor group.

(Appendix 2) In the logic circuit described in Appendix 1,
The first transfer circuit has a first current mirror circuit that inputs a read current from the first ferroelectric capacitor group and outputs a write current to the second ferroelectric capacitor group. And
The second transfer circuit includes a second current mirror circuit that inputs a read current from the second ferroelectric capacitor group and outputs a write current to the first ferroelectric capacitor group. A logic circuit characterized by that.

(Appendix 3) In the logic circuit described in Appendix 1,
The first transfer circuit includes a first charge transfer amplifier that transfers charges read from the first ferroelectric capacitor group to the second ferroelectric capacitor group;
The logic circuit, wherein the second transfer circuit includes a second charge transfer amplifier that transfers charges read from the second ferroelectric capacitor group to the first ferroelectric capacitor group.

(Appendix 4) In the logic circuit described in Appendix 3,
The logic circuit according to claim 1, wherein the first transfer circuit amplifies the electric charge read from the first ferroelectric capacitor group and writes the amplified charge to the second ferroelectric capacitor group.

(Appendix 5) In the logic circuit described in Appendix 4,
The logic circuit according to claim 2, wherein the second transfer circuit amplifies the electric charge read from the second ferroelectric capacitor group and writes the amplified charge to the first ferroelectric capacitor group.

(Appendix 6) In the logic circuit described in Appendix 4 or 5,
A logic circuit, wherein a capacitance of a ferroelectric capacitor included in the second ferroelectric capacitor group is larger than a capacitance of a ferroelectric capacitor included in the first ferroelectric capacitor group.

(Supplementary note 7) In the logic circuit according to supplementary note 1 or 2,
The first ferroelectric capacitor group includes a first ferroelectric capacitor and a second ferroelectric capacitor;
The second ferroelectric capacitor group includes a third ferroelectric capacitor and a fourth ferroelectric capacitor,
The first transfer circuit transfers charges corresponding to the read charges from the first ferroelectric capacitor to the third ferroelectric capacitor and the fourth ferroelectric capacitor, respectively. 3 ferroelectric capacitors and the fourth ferroelectric capacitor,
The second transfer circuit transfers charges corresponding to the read charges from the third ferroelectric capacitor to the first ferroelectric capacitor and the second ferroelectric capacitor, respectively. A logic circuit, wherein one ferroelectric capacitor and the second ferroelectric capacitor are written.

(Supplementary note 8) In the logic circuit according to any one of supplementary notes 1 to 7,
The first ferroelectric capacitor group and the second ferroelectric capacitor group include a NAND type capacitor unit in which a plurality of parallel connection bodies of ferroelectric capacitors and switches are connected in series. Logic circuit.

(Supplementary note 9) In the logic circuit according to any one of supplementary notes 1 to 7,
The first ferroelectric capacitor group and the second ferroelectric capacitor group include a NOR type capacitor unit in which a plurality of serially connected bodies of ferroelectric capacitors and switches are connected in parallel. Logic circuit.

(Supplementary note 10) In the logic circuit according to any one of supplementary notes 1 to 9,
One electrode of the plurality of ferroelectric capacitors included in the first ferroelectric capacitor group is commonly connected to a plate line, and the evaluation circuit calculates the total amount of charge read to the plate line. A logic circuit characterized by evaluating the result of logic synthesis.

(Supplementary note 11) In the logic circuit according to any one of supplementary notes 1 to 9,
The evaluation circuit evaluates a result of logic synthesis based on a maximum value among charge amounts read from each of a plurality of ferroelectric capacitors included in the first ferroelectric capacitor group; Characteristic logic circuit.

(Additional remark 12) The electric charge read from the 1st ferroelectric capacitor group is detected, and the result of the predetermined logic composition according to the electric charge holding state memorize | stored in the said 1st ferroelectric capacitor group is evaluated. A logic circuit driving method,
When reading out the first ferroelectric capacitor group, by transferring a charge corresponding to the read charge from the first ferroelectric capacitor group to the second ferroelectric capacitor group, the charge The holding state is backed up by the second ferroelectric capacitor group,
The second ferroelectric capacitor group is read out, and the backup is performed by transferring the charge according to the readout charge from the second ferroelectric capacitor group to the first ferroelectric capacitor group. A method of driving a logic circuit, wherein the charge holding state is written back to the first ferroelectric capacitor group.

(Supplementary note 13) In the logic circuit driving method according to supplementary note 12,
A logic circuit driving method, comprising: amplifying the electric charge read from the first ferroelectric capacitor group and writing the amplified charge to the second ferroelectric capacitor group.

(Supplementary note 14) In the logic circuit driving method according to supplementary note 12 or 13,
A method for driving a logic circuit, comprising: amplifying a charge read from the second ferroelectric capacitor group and writing the amplified charge to the first ferroelectric capacitor group.

(Supplementary Note 15) In the logic circuit driving method according to any one of Supplementary Notes 12 to 14,
The first ferroelectric capacitor group includes a first ferroelectric capacitor and a second ferroelectric capacitor;
The second ferroelectric capacitor group includes a third ferroelectric capacitor and a fourth ferroelectric capacitor,
When backing up the charge retention state, the charge corresponding to the read charge from the first ferroelectric capacitor is transferred to each of the third ferroelectric capacitor and the fourth ferroelectric capacitor. Writing the third ferroelectric capacitor and the fourth ferroelectric capacitor;
When the first ferroelectric capacitor group is written back to the backed-up charge retention state, the charge corresponding to the read charge from the third ferroelectric capacitor is changed to the first ferroelectric capacitor and the first ferroelectric capacitor. A method for driving a logic circuit, wherein the first ferroelectric capacitor and the second ferroelectric capacitor are written by transferring to each of the two ferroelectric capacitors.

(Supplementary note 16) In the logic circuit driving method according to any one of supplementary notes 12 to 15,
A logic circuit driving method, comprising: evaluating a result of logic synthesis based on a total charge amount read from a plurality of ferroelectric capacitors included in the first ferroelectric capacitor group.

(Supplementary note 17) In the logic circuit driving method according to any one of supplementary notes 12 to 15,
A logic circuit characterized in that a logic synthesis result is evaluated based on a maximum value among electric charges read from each of a plurality of ferroelectric capacitors included in the first ferroelectric capacitor group. Driving method.

(Supplementary Note 18) Flip-flop circuit,
First and second capacitors connected to an input node of the flip-flop circuit;
A third and a fourth capacitor connected to an output node of the flip-flop circuit;
A nonvolatile latch circuit, wherein at least one of the first to fourth capacitors includes a first capacitor unit in which a plurality of parallel connection bodies of a ferroelectric capacitor and a switch are connected in series.

(Supplementary note 19) Flip-flop circuit;
First and second capacitors connected to an input node of the flip-flop circuit;
A third and a fourth capacitor connected to an output node of the flip-flop circuit;
A nonvolatile latch circuit, wherein at least one of the first to fourth capacitors includes a first capacitor unit in which a plurality of serially connected bodies of ferroelectric capacitors and switches are connected in parallel.

(Supplementary note 20) In the nonvolatile latch circuit according to supplementary note 18 or 19,
A second capacitor unit of the same type as the first capacitor unit;
Connected between the first capacitor unit and the second capacitor unit, and transfers a charge corresponding to a read charge from the ferroelectric capacitor of the first capacitor unit to the second capacitor unit. A first transfer circuit for writing into a ferroelectric capacitor of the second capacitor unit;
A second transfer circuit for transferring a charge corresponding to a read charge from the ferroelectric capacitor of the second capacitor unit to the first capacitor unit and writing the charge to the ferroelectric capacitor of the first capacitor unit; And a non-volatile latch circuit.

DESCRIPTION OF SYMBOLS 10 ... Comparator 12 ... Inverter 14 ... Forced write gate 16 ... Bilateral gate 18 ... Evaluation / write-back circuit 20 ... Read-out circuit

Claims (10)

First and second ferroelectric capacitor groups;
It is connected to the first ferroelectric capacitor group, detects the amount of charge read from the first ferroelectric capacitor group, and enters the charge holding state stored in the first ferroelectric capacitor group. An evaluation circuit for evaluating the result of a predetermined logic synthesis according to
The second ferroelectric capacitor group is connected between the first ferroelectric capacitor group and the second ferroelectric capacitor group, and a charge corresponding to a read charge from the first ferroelectric capacitor group is transferred to the second ferroelectric capacitor group. A first transfer circuit for transferring to the body capacitor group and writing to the second ferroelectric capacitor group;
The first ferroelectric capacitor group and the second ferroelectric capacitor group are connected between the first ferroelectric capacitor group, and a charge corresponding to a read charge from the second ferroelectric capacitor group is transferred to the first ferroelectric capacitor group. And a second transfer circuit for transferring to the body capacitor group and writing to the first ferroelectric capacitor group. The logic circuit according to claim 1, wherein
The first transfer circuit has a first current mirror circuit that inputs a read current from the first ferroelectric capacitor group and outputs a write current to the second ferroelectric capacitor group. And
The second transfer circuit includes a second current mirror circuit that inputs a read current from the second ferroelectric capacitor group and outputs a write current to the first ferroelectric capacitor group. A logic circuit characterized by that. The logic circuit according to claim 1, wherein
The first transfer circuit includes a first charge transfer amplifier that transfers charges read from the first ferroelectric capacitor group to the second ferroelectric capacitor group;
The logic circuit, wherein the second transfer circuit includes a second charge transfer amplifier that transfers charges read from the second ferroelectric capacitor group to the first ferroelectric capacitor group. The logic circuit according to claim 1 or 2,
The first ferroelectric capacitor group includes a first ferroelectric capacitor and a second ferroelectric capacitor;
The second ferroelectric capacitor group includes a third ferroelectric capacitor and a fourth ferroelectric capacitor,
The first transfer circuit transfers charges corresponding to the read charges from the first ferroelectric capacitor to the third ferroelectric capacitor and the fourth ferroelectric capacitor, respectively. 3 ferroelectric capacitors and the fourth ferroelectric capacitor,
The second transfer circuit transfers charges corresponding to the read charges from the third ferroelectric capacitor to the first ferroelectric capacitor and the second ferroelectric capacitor, respectively. A logic circuit, wherein one ferroelectric capacitor and the second ferroelectric capacitor are written. A logic circuit that detects a charge amount read from the first ferroelectric capacitor group and evaluates a result of a predetermined logic synthesis according to a charge holding state stored in the first ferroelectric capacitor group. A driving method comprising:
When reading out the first ferroelectric capacitor group, by transferring a charge corresponding to the read charge from the first ferroelectric capacitor group to the second ferroelectric capacitor group, the charge The holding state is backed up by the second ferroelectric capacitor group,
The second ferroelectric capacitor group is read out, and the backup is performed by transferring the charge according to the readout charge from the second ferroelectric capacitor group to the first ferroelectric capacitor group. A method of driving a logic circuit, wherein the charge holding state is written back to the first ferroelectric capacitor group. The logic circuit driving method according to claim 5, wherein:
A logic circuit driving method, comprising: amplifying the electric charge read from the first ferroelectric capacitor group and writing the amplified charge to the second ferroelectric capacitor group. The logic circuit driving method according to claim 5 or 6, wherein:
A method for driving a logic circuit, comprising: amplifying a charge read from the second ferroelectric capacitor group and writing the amplified charge to the first ferroelectric capacitor group. The method for driving a logic circuit according to any one of claims 5 to 7,
The first ferroelectric capacitor group includes a first ferroelectric capacitor and a second ferroelectric capacitor;
The second ferroelectric capacitor group includes a third ferroelectric capacitor and a fourth ferroelectric capacitor,
When backing up the charge retention state, the charge corresponding to the read charge from the first ferroelectric capacitor is transferred to each of the third ferroelectric capacitor and the fourth ferroelectric capacitor. Writing the third ferroelectric capacitor and the fourth ferroelectric capacitor;
When the first ferroelectric capacitor group is written back to the backed-up charge retention state, the charge corresponding to the read charge from the third ferroelectric capacitor is changed to the first ferroelectric capacitor and the first ferroelectric capacitor. A method for driving a logic circuit, wherein the first ferroelectric capacitor and the second ferroelectric capacitor are written by transferring to each of the two ferroelectric capacitors. In the driving method of the logic circuit according to any one of claims 5 to 8,
A logic circuit driving method, comprising: evaluating a result of logic synthesis based on a total charge amount read from a plurality of ferroelectric capacitors included in the first ferroelectric capacitor group. In the driving method of the logic circuit according to any one of claims 5 to 8,
A logic circuit characterized in that a logic synthesis result is evaluated based on a maximum value among electric charges read from each of a plurality of ferroelectric capacitors included in the first ferroelectric capacitor group. Driving method.

Images