JP2013034040A - Nonvolatile flip-flop and nonvolatile latch - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nonvolatile flip-flop that implements simple and stable store and recall actions.SOLUTION: A nonvolatile storage section 2_1 has: an N channel transistor 209 and a variable resistance element 224 between an output node of an inverter 208 of a slave latch section 1S_1 and a common node CN; an N channel transistor 210 and a variable resistance element 223 between an output node of an inverter 207 of the slave latch section 1S_1 and the common node CN; and an N channel transistor 211 between the common node CN and a ground. In a store action, the N channel transistors 209, 210 are turned on and the N channel transistor 211 is turned off to generate a magnitude relationship depending on stored data in the slave latch section 1S_1 between respective resistance values of the variable resistance elements 224 and 223. In a recall action, the N channel transistors 209-211 are turned on and a supply voltage to a volatile flip-flop section 1_1 is built up.

Description

  The present invention relates to a nonvolatile flip-flop and a nonvolatile latch using a resistance variable element.

  In the LSI, as the transistor becomes finer, not only the subthreshold leakage current but also the gate leakage tends to increase. Further, these leakage currents increase as the LSI density increases. Therefore, the current consumption of the entire LSI increases. In order to reduce current consumption, various current consumption reduction measures such as low voltage and gated clock have been taken. In order to achieve further reduction in power consumption, a method is considered in which the power of a block that does not operate is cut off and the power is turned on when necessary. However, storage elements such as latches and flip-flops used in LSIs are volatile storage elements, and there is a problem that stored information is lost when the power is turned off.

  Therefore, an integrated circuit in which a nonvolatile memory element made of a ferroelectric capacitor is added to a latch, a flip-flop, or the like has been proposed (see, for example, Patent Document 1). However, when a ferroelectric capacitor is used as a nonvolatile memory element, there is a problem that a read margin is reduced due to miniaturization.

  Nonvolatile memory elements include resistance change elements in addition to ferroelectric capacitors. FIGS. 26A and 26B are diagrams showing the configuration and operation of a memory cell using a typical MTJ (Magnetic Tunnel Junction) element as a resistance variable element. As shown in FIGS. 26A and 26B, the MTJ element includes a pinned layer having a constant magnetic direction, a tunnel barrier film, and a free layer whose magnetic direction changes. As shown in FIG. 26A, when a current in the direction from the free layer to the pinned layer is passed, the magnetization direction of the free layer becomes the same as that of the pinned layer, the MTJ element becomes low resistance, and data “0” is stored. It becomes a state. On the other hand, as shown in FIG. 26B, when a current in the direction from the pinned layer toward the free layer is passed, the magnetization direction of the free layer is opposite to that of the pinned layer, the MTJ element becomes high resistance, and data “1” "Is stored. When a memory cell is configured with such an MTJ element, a transistor Ts is connected in series to the MTJ element as a switch for selecting the MTJ element, as illustrated in FIGS. .

  FIG. 27 is a diagram illustrating a cross-sectional structure of a memory array including memory cells as shown in FIGS. 26 (a) and 26 (b). In the example shown in FIG. 27, the selection transistor Ts shown in FIGS. 26A and 26B is formed on a semiconductor substrate. A selection voltage WL is applied to the gate of each transistor Ts. The source of the transistor Ts is connected to the second layer metal wiring 2M for supplying the write voltage BL via the through hole and the first layer metal wiring 1M. The drain of the transistor Ts is connected to the pin layer of the MTJ element through a through hole, and the free layer of the MTJ element is connected to the second layer metal wiring 2M for supplying the source voltage SL through the through hole. Has been.

  Japanese Patent Application Laid-Open No. 2004-228867 proposes a rewritable nonvolatile latch and flip-flop using such an MTJ element. FIG. 28 is a circuit diagram showing the nonvolatile latch shown in FIG. In FIG. 28, the transfer gates TMG1 and TMG2 and the NOR gates 10 and 20 constitute a known latch. One end of the MTJ element R1 is connected to the source of the P-channel transistor 11 of the NOR gate 10, and one end of the MTJ element R2 is connected to the source of the P-channel transistor 21 of the NOR gate 20, and other MTJ elements R1 and R2 are connected. A P-channel transistor Tr1 is interposed between the connection point between the ends and the power supply Vdd. Data D is applied to the connection point between the P channel transistor 11 and the MTJ element R1 via the transfer gate TMG3, and the transfer gate TMG4 is connected to the connection point between the P channel transistor 21 and the MTJ element R2. The data DB is provided via the. Further, a P-channel transistor Tr2 is interposed between the connection point of the P-channel transistor 11 and the MTJ element R1 and the power supply Vdd, and a P-channel is connected between the connection point of the P-channel transistor 21 and the MTJ element R2 and the power supply Vdd. A transistor Tr3 is inserted.

  In the above configuration, when the input data D and DB are written to the MTJ elements R1 and R2, the P-channel transistors Tr1, Tr2, Tr3, 12, and 22 are turned off and the N-channel transistors 13 and 23 are turned on. Thereby, currents in opposite directions flow through the MTJ elements R1 and R2 according to the values of the input data D and DB, respectively, and the MTJ elements R1 and R2 change to different resistance values. Since this resistance value is held by the non-volatile nature of the MTJ element, data is not lost even when the power supply of this latch is shut off.

  The operation of reading the stored data is performed in two stages: 1) precharge operation and 2) read operation after the power is turned on.

  First, in the case of 1) precharging, the P-channel transistors Tr1, Tr2, Tr3, 12, 22 are turned off and the N-channel transistors 13, 23 are turned on. As a result, the output signals of the NOR gates 10 and 20 become “0”, and both nodes A and B of the NOR gates 10 and 20 that are cross-coupled are equal and precharged to “0”.

  Subsequently, 2) as a read operation, the state of the control signal NV_RW is changed from “1” to “0”. Then, the cross-coupled NOR gates 10 and 20 operate as a cross-coupled inverter, and the nodes A and B of the NOR gates 10 and 20 cross-coupled due to the difference in delay according to the resistance values of the MTJ elements R1 and R2. Is determined to be “1” or “0”. The values of the nodes A and B correspond to the stored states Q and QB.

JP 2004-88469 A JP 2008-85770 A

  By the way, in the nonvolatile latch disclosed in the above-mentioned Patent Document 2, the data Q and QB stored in the latch section including the NOR gates 10 and 20 and the transfer gates TMG1 and TMG2 are directly written into the MTJ elements R1 and R2. I can't. In order to write the data Q and QB of the latch portion into the MTJ elements R1 and R2, it is necessary to read the data Q and QB and then apply them to the transfer gates TMG3 and TMG4. Therefore, there is a problem that the control for causing the store operation to write the data stored in the volatile latch unit to the MTJ elements R1 and R2 becomes complicated. In the nonvolatile latch disclosed in Patent Document 2, when performing a recall operation for reading data stored in the MTJ elements R1 and R2 and holding the data in the volatile latch unit, first, the signal NV_RW is set to the H level. The output node B of the NOR gate 10 and the output node A of the NOR gate 20 are precharged to 0V. Thereafter, the signal NV_RW is set to L level to turn on the P-channel transistors 12 and 22, and the data stored in the MTJ elements R1 and R2 are read. At this time, the behavior of the nodes A and B becomes unstable due to the influence of the threshold variation of the cross-coupled P-channel transistors 11 and 21, and an appropriate value reflecting the magnitude relationship of the resistance values of the MTJ elements R1 and R2 is reflected. Data may not be held in the volatile latch. Further, in the nonvolatile latch of Patent Document 2, although reference is not made to the load capacitances of the output node Q and the output node QB, in reality, a large capacitance is interposed in the output nodes Q and QB. In addition, depending on how it is used, it is assumed that the load capacity is unbalanced between the output node Q and the output node QB. In such a case, there is a concern that the recall operation becomes unstable. As described above, the nonvolatile latch of Patent Document 2 has a problem that the control for performing the store operation is complicated and the recall operation becomes unstable. In addition, since the nonvolatile latch of Patent Document 2 does not have means for optimizing the current flowing through the MTJ elements R1 and R2 during store and recall, it can effectively prevent erroneous writing and erroneous reading. There was a problem that could not.

  The present invention has been made in view of the circumstances described above. The first object of the present invention is to store the storage data from the volatile storage unit to the nonvolatile storage unit, and to read the storage data of the nonvolatile storage unit. An object of the present invention is to provide a nonvolatile flip-flop and a nonvolatile latch capable of easily and stably performing a recall operation stored in a volatile storage unit. A second object of the present invention is to prevent erroneous writing and erroneous reading from occurring due to the influence of variations in element characteristics in the nonvolatile flip-flop and the nonvolatile latch. A third object of the present invention is to provide a high-speed and high-performance nonvolatile flip-flop and nonvolatile latch that can be realized with a small number of elements (or a small required area).

  The present invention includes a volatile flip-flop unit composed of a master latch unit and a slave latch unit, and a non-volatile storage unit. The slave latch unit uses each other's output signal as an input signal for each other. And a second inverter, which performs an operation of capturing input data from the master latch unit in synchronization with a clock and an operation of retaining the captured input data by the first and second inverters. The storage unit includes a first switch and a first variable resistance element inserted in series between an output node of the first inverter and a common node, and an output node of the second inverter and the common node. A second switch and a second resistance variable element inserted in series with the node, and a second switch inserted between the common node and the reference node. The first and second variable resistance elements have the first inverter in a state where the first and second switches are ON and the third switch is OFF. When a current flows from the output node to the output node of the second inverter, the resistance value of the first variable resistance element is in the first direction, and the resistance value of the second variable resistance element is The first resistance variable element is changed when a current flows from the output node of the second inverter to the output node of the first inverter, each changing in a second direction opposite to the first direction. A nonvolatile variable flip-flop, wherein the resistance value of the second variable resistance element changes in the second direction and the resistance value of the second variable resistance element changes in the first direction. .

  In the present invention, by turning off the first and second switches, the volatile storage unit can be disconnected from the slave latch unit, and the volatile flip-flop unit can be operated as a normal flip-flop. Therefore, it is possible to operate at high speed like a normal flip-flop.

  In the present invention, when the first and second switches are turned on and the third switch is turned off, the first and second switches are turned on according to the level relationship between the output voltage of the first inverter and the output voltage of the second inverter. Current flowing in the direction from the output node of the inverter toward the output node of the second inverter or in the opposite direction flows through the first and second resistance variable elements. As a result, the magnitude relationship between the resistance values of the first and second variable resistance elements is a magnitude relationship corresponding to the magnitude relationship between the output voltage of the first inverter and the output voltage of the second inverter. As described above, in the nonvolatile flip-flop according to the present invention, a store operation can be performed in which the magnitude relationship between the resistance values of the first and second variable resistance elements is changed according to the data stored in the slave latch unit. it can.

  In the present invention, when the first and second switches are turned on, the third switch is turned on, and the power supply voltage of the volatile flip-flop section is raised, the first and second switches in the process of raising the power supply voltage. Current flows from the output nodes of the inverters to the first and second variable resistance elements. At this time, if the resistance value of the first variable resistance element is smaller than the resistance value of the second variable resistance element, the current flowing from the output node of the first inverter to the first variable resistance element is greater. More than the current flowing from the output node of the second inverter to the second variable resistance element. As a result, compared to the output voltage of the second inverter, more brakes are applied due to the increase in the output voltage of the first inverter, the output voltage of the first inverter is L level, and the output voltage of the second inverter is H level. Become a level. Conversely, if the resistance value of the first variable resistance element is larger than the resistance value of the second variable resistance element, the output voltage of the second inverter increases more than the output voltage of the first inverter. As a result, the output voltage of the first inverter becomes H level and the output voltage of the second inverter becomes L level. As described above, the nonvolatile flip-flop according to the present invention can perform a recall operation in which data corresponding to the magnitude relationship between the resistance values of the first and second variable resistance elements is stored in the slave latch unit.

  In a preferred embodiment, the first and second switches are field effect transistors. By adjusting the gate voltage applied to the field effect transistor at the time of storage and setting the ON resistance of the field effect transistor to an appropriate value, the data stored in the slave latch unit can be reliably written into the nonvolatile storage unit .

  Further, at the time of recall, by setting the ON resistance of the field effect transistors as the first and second switches to an appropriate value, the current flowing through the first and second variable resistance elements is suppressed within an appropriate range, It is possible to effectively prevent erroneous reading.

  The present invention also includes a volatile latch unit and a non-volatile storage unit, the volatile latch unit including first and second inverters each having an output signal of each other as an input signal, When the clock becomes the first logic value, the input data is taken in, and when the clock becomes the second logic value, the first and second inverters are cut off from the supply source of the input data, The nonvolatile memory section includes a first switch and a first variable resistance element inserted in series between an output node and a common node of the first inverter, an output node of the second inverter, A second switch and a second variable resistance element inserted in series between the common node and a third switch interposed between the common node and a reference node; The first And the second variable resistance element is configured such that the first and second switches are turned on and the third switch is turned off, and is directed from the output node of the first inverter to the output node of the second inverter. When a current flows, the resistance value of the first resistance variable element is in a first direction, and the resistance value of the second resistance variable element is in a second direction opposite to the first direction. When a current flowing from the output node of the second inverter to the output node of the first inverter flows, the resistance value of the first variable resistance element changes in the second direction. There is provided a nonvolatile latch, wherein the resistance value of each of the two variable resistance elements is a variable resistance element that changes in the first direction.

  In this nonvolatile latch, a store operation and a recall operation similar to those of the nonvolatile flip-flop according to the present invention are possible.

  According to the present invention, since the number of elements in the nonvolatile memory section is small and less current flows through the resistance variable element during storage and recall, the nonvolatile flip-flop and nonvolatile latch that are small in area and inexpensive can be used. Can be realized.

  In another aspect of the present invention, the nonvolatile flip-flop and the nonvolatile latch have bias setting means for applying a bias voltage to the common node. In this aspect, the first and second variable resistance elements have the first and second switches turned on, and the second output node from the output node of the first inverter through the common node. When a current flowing in the direction flows, a resistance value of the first resistance variable element is in a first direction, and a resistance value of the second resistance variable element is a second direction opposite to the first direction. And when a current flows from the output node of the second inverter to the first output node via the common node, the resistance value of the first resistance variable element is changed to the second value. The resistance value of the second resistance variable element changes in the first direction in the direction of. Here, at the time of storing, the bias setting means applies, for example, a bias voltage that is ½ of the power supply voltage to the common node.

  According to this aspect, the voltage applied to the first resistance change element and the second resistance change element at the time of storing can be always kept constant regardless of the data stored in the non-volatile storage unit, thereby realizing a stable store operation. can do.

1 is a circuit diagram showing a configuration of a nonvolatile flip-flop according to a first embodiment of the present invention. FIG. It is a circuit diagram which shows the structural example of a general flip-flop. It is a figure which shows the operating condition of the non-volatile flip-flop. It is a figure which shows the store operation | movement of the non-volatile flip flop. It is a time chart which shows the waveform of each part at the time of store operation of the non-volatile flip-flop. It is a time chart which shows the waveform of each part at the time of the recall operation | movement of the non-volatile flip-flop. It is a circuit diagram which shows the structure of the non-volatile flip-flop which is 2nd Embodiment of this invention. It is a circuit diagram which shows the structure of the non-volatile flip-flop which is 3rd Embodiment of this invention. It is a figure which shows the operating condition of the non-volatile flip-flop. It is a circuit diagram which shows the structure of the non-volatile flip-flop which is 4th Embodiment of this invention. It is a circuit diagram which shows the structure of the non-volatile flip-flop which is 5th Embodiment of this invention. It is a circuit diagram which shows the structure of the non-volatile flip-flop which is 6th Embodiment of this invention. It is a circuit diagram which shows the structure of the non-volatile flip-flop which is 7th Embodiment of this invention. It is a circuit diagram which shows the structure of the non-volatile flip-flop which is 8th Embodiment of this invention. It is a circuit diagram which shows the structure of the non-volatile latch which is 9th Embodiment of this invention. It is a circuit diagram which shows the structure of the non-volatile latch which is 10th Embodiment of this invention. It is a circuit diagram which shows the structure of the non-volatile latch which is 11th Embodiment of this invention. It is a circuit diagram which shows the structure of the non-volatile latch which is 12th Embodiment of this invention. It is a circuit diagram which shows the structure of the non-volatile latch which is 13th Embodiment of this invention. It is a circuit diagram which shows the structure of the non-volatile latch which is 14th Embodiment of this invention. It is a circuit diagram which shows the structure of the non-volatile latch which is 15th Embodiment of this invention. It is a circuit diagram which shows the structure of the non-volatile latch which is 16th Embodiment of this invention. It is a block diagram which shows the structure of the non-volatile shift register which is 18th Embodiment of this invention. It is a block diagram which shows the structure of the non-volatile register which is 19th Embodiment of this invention. It is a block diagram which shows the structure of the non-volatile counter which is 20th Embodiment of this invention. It is a figure which shows the structure and operation | movement of an MTJ element. It is a figure which illustrates the cross-sectional structure of the memory cell using an MTJ element. It is a circuit diagram which shows the structural example of the conventional non-volatile latch.

  Embodiments of the present invention will be described below with reference to the drawings. In the following embodiments, the transistor refers to a MOSFET (Metal Oxide Semiconductor Field Effect Transistor; field-effect transistor having a metal-oxide film-semiconductor structure).

<First Embodiment>
FIG. 1 is a circuit diagram showing a configuration of a nonvolatile flip-flop 200 according to the first embodiment of the present invention. FIG. 2 is a circuit diagram showing a configuration example of a normal flip-flop. In order to facilitate understanding of the characteristics of the nonvolatile flip-flop according to the present embodiment, first, a normal flip-flop will be described with reference to FIG.

  The flip-flop illustrated in FIG. 2 includes a master latch unit 100M, a slave latch unit 100S, and a clock driver 100C. Here, the clock driver 100C includes two stages of inverters 107 and 108, and outputs an internal clock CK having the same logical value as the input clock CLK and an internal clock / CK obtained by inverting the clock CLK. The master latch unit 100M includes clocked inverters 101 and 103 and an inverter 102. The slave latch unit 100S includes clocked inverters 104 and 106 and inverters 105, 109, and 110.

  In such a configuration, when the clock CLK changes from H level to L level, the internal clock CK becomes L level and the internal clock / CK becomes H level. Therefore, clocked inverters 101 and 106 are in an output enable state in which the input signal is inverted and output, and clocked inverters 103 and 104 are in an output disable state in which the output impedance is high impedance (the output terminal is floating). As a result, the input data D is taken into the master latch unit 100M, and the slave latch unit 100S holds the data taken in before the clock CLK becomes L level. Next, when the clock CLK changes from L level to H level, the internal clock CK becomes H level and the internal clock / CK becomes L level. Therefore, the clocked inverters 103 and 104 are in an output enable state, and the clocked inverters 101 and 106 are in an output disable state. As a result, the master latch unit 100M holds the data acquired before the clock CLK becomes H level, and the slave latch unit 100S receives the output data of the inverter 102 of the master latch unit 100M, which is the same as the acquired data. Logical value data Q and the opposite logical value data / Q are output from inverters 110 and 109, respectively.

  As shown in FIG. 1, the non-volatile flip-flop 200 according to the present embodiment includes a volatile flip-flop unit 1_1, a non-volatile storage unit 2_1, and a control logic unit 3_1. Here, the volatile flip-flop unit 1_1 includes a master latch unit 1M_1 and a slave latch unit 1S_1.

  The master latch unit 1M_1 has a configuration similar to that of the master latch unit 100M of the flip-flop in FIG. 2, and inverts the clocked inverter 201 to which the input data D is input and the output signal of the clocked inverter 201. And the clocked inverter 203 that inverts the output signal of the inverter 202 and outputs the inverted signal to the connection point between the output node of the clocked inverter 201 and the input node of the inverter 202 in the output enable state. .

  The configuration of the slave latch unit 1S_1 is different from the configuration of the slave latch unit 100S of the flip-flop of FIG. The slave latch unit 1S_1 includes inverters 204, 207, and 208, transfer gates 205 and 206, a NAND gate 219, an inverter 220, a NOR gate 221, and an inverter 222.

  Here, inverter 204 outputs data / DM obtained by inverting data DM output from inverter 202 of master latch unit 1M_1. Inverters 207 and 208 use the output signals of the other party as input signals, and constitute a latch. Transfer gate 205 is interposed between the output node of inverter 202 and the connection point between the input node of inverter 207 and the output node of inverter 208. Transfer gate 206 is interposed between the output node of inverter 204 and the connection point of the input node of inverter 208 and the output node of inverter 207.

  Two-phase internal clocks CKS and / CKS are applied to transfer gates 205 and 206. Here, when the internal clock CKS is at the H level and the internal clock / CKS is at the L level, both the transfer gates 205 and 206 are turned on. In this state, the output node of inverter 202 is connected to the input node of inverter 207 and the output node of inverter 208, and the output node of inverter 204 is connected to the input node of inverter 208 and the output node of inverter 207. Therefore, the output data DM of the master latch unit 1M_1 is written into the latch composed of the inverters 207 and 208, the output data DS of the inverter 208 is the same logic data as the data DM, and the output data / DS of the inverter 207 is the same as the data / DM. It becomes logical data.

  When internal clock CKS is at L level and internal clock / CKS is at H level, both transfer gates 205 and 206 are turned off. Therefore, both inverters 207 and 208 are disconnected from master latch unit 1M_1. The latch composed of the inverters 207 and 208 holds the data written before being disconnected from the master latch unit 1M_1.

NAND gate 219 and inverter 220 output output data DS of inverter 208 as output signal Q of nonvolatile flip-flop 200 when reference node connection signal / WE is at H level, and reference node connection signal / WE is L In the case of the level, the output signal Q of the nonvolatile flip-flop 200 is fixed to the L level regardless of the output data DS of the inverter 208. When the reference node cutoff signal WE is at the L level, the NOR gate 221 and the inverter 222 output the output data / DS of the inverter 207 as the inverted output signal / Q of the nonvolatile flip-flop 200, and the reference node cutoff signal WE When it is at the H level, the inverted output signal / Q of the nonvolatile flip-flop 200 is fixed at the H level regardless of the output data / DS of the inverter 207. Note that the reference node connection signal / WE and the reference node cutoff signal WE are signals generated by the control logic unit 3_1.
The above is the details of the configuration of the slave latch unit 1S_1 in the present embodiment.

  In the slave latch unit 100S in FIG. 2, the latch for holding the data fetched from the master latch unit 100M is composed of the inverter 105 and the clocked inverter 106. On the other hand, in the slave latch unit 1S_1 in this embodiment, the latches for holding the data DM fetched from the master latch unit 1M_1 are configured by the inverters 207 and 208. These inverters 207 and 208 have the same output impedance and output current characteristics. This is the difference between the slave latch unit 100S in FIG. 2 and the slave latch unit 1S_1 in the present embodiment.

  Next, the nonvolatile memory unit 2_1 will be described. The nonvolatile memory unit 2_1 includes N-channel transistors 209 and 210 that are first and second switches, variable resistance elements 224 and 223 that are first and second variable resistance elements, and a third switch. An N-channel transistor 211 is included.

  Here, the N-channel transistor 209 and the resistance variable element 224 are inserted in series between the output node of the inverter 208, which is the first inverter constituting the latch, and the common node CN. The N-channel transistor 210 and the resistance variable element 223 are inserted in series between the output node of the inverter 207 that is the second inverter constituting the latch and the common node CN.

  More specifically, N channel transistors 209 and 210 have their drains connected to the output nodes of inverters 208 and 207, respectively. Activation signal VWR is applied to the gates of N channel transistors 209 and 210. In this example, variable resistance elements 224 and 223 are MTJ elements, and the pin layers of variable resistance elements 224 and 223 are connected to the sources of N-channel transistors 209 and 210, respectively. In addition, each free layer of variable resistance elements 224 and 223 is connected to common node CN.

  As the variable resistance elements 224 and 223, in addition to such MTJ elements, CER (Collective Electro-Resistance) resistance elements used for ReRAM memory cells may be used.

  N-channel transistor 211 is interposed between common node CN and the reference node. A reference node connection signal / WE is applied to the gate of N channel transistor 211. In this embodiment, the reference node is grounded. Similarly, the low potential side power supply lines of the volatile flip-flop 1_1 and the control logic unit 3_1 are also grounded.

  Next, the control logic unit 3_1 will be described. Nonvolatile flip-flop 200 is supplied with input data D, clock CLK, read enable signal REEN and write enable signal WEEN, and activation signal VWR described above. Inverter 217 inverts write enable signal WEEN and outputs it as reference node connection signal / WE described above. Inverter 218 inverts reference node connection signal / WE and outputs it as reference node cutoff signal WE.

  NOR gate 212 and inverters 213 and 214 constitute a circuit that generates internal clocks CK and / CK based on clock CLK and reference node cutoff signal WE. This circuit generates an internal clock CK having the same logical value as that of the clock CLK and an internal clock / CK obtained by inverting the clock CLK when the reference node cutoff signal WE is at the L level, and the reference node cutoff signal WE is at the H level. In some cases, internal clock CK is fixed at H level and internal clock / CK is fixed at L level. When the internal clock CK is at the H level and the internal clock / CK is at the L level, the clocked inverter 201 of the master latch unit 1M_1 is in the output disabled state and the clocked inverter 203 is in the output enabled state. Further, when the internal clock CK is at the L level and the internal clock / CK is at the H level, the clocked inverter 201 of the master latch unit 1M_1 is in the output enabled state and the clocked inverter 203 is in the output disabled state.

  NOR gates 212 and 215 and inverter 216 constitute a circuit for generating internal clocks CKS and / CKS based on clock CLK, reference node cutoff signal WE, and read permission signal REEN. This circuit generates an internal clock CKS having the same logical value as that of the clock CLK and an internal clock / CKS obtained by inverting the clock CLK when both the reference node cutoff signal WE and the read enable signal REEN are at the L level. When at least one of the cutoff signal WE and the read enable signal REEN is at the H level, the internal clock CKS is fixed at the L level and the internal clock / CKS is fixed at the H level. When internal clock CKS is at L level and internal clock / CKS is at H level, transfer gates 205 and 206 of slave latch unit 1S_1 are turned off. When internal clock CKS is at H level and internal clock / CKS is at L level, transfer gates 205 and 206 of slave latch unit 1S_1 are turned on.

  FIG. 3 is a diagram showing operating conditions of the nonvolatile flip-flop 200 according to the present embodiment. 4A and 4B are diagrams showing a store operation for writing the storage data of the slave latch unit 1S_1 into the nonvolatile storage unit 2_1 in the present embodiment. FIG. 5 is a time chart showing waveforms of respective parts in the normal operation and the store operation. FIG. 6 is a time chart showing waveforms of respective units when a recall operation is performed in which data stored in the nonvolatile storage unit 2_1 is read and written to the slave latch unit 1S_1 in the present embodiment. Hereinafter, the operation of this embodiment will be described with reference to these drawings, taking as an example the case where the power supply voltage VDD for the nonvolatile flip-flop 200 is 1.2V.

  When the nonvolatile flip-flop 200 is operated as a normal flip-flop, as shown in FIG. 3, the activation signal VWR is set to 0 V (= low-potential side power supply voltage VSS), and the read permission signal REEN and the write permission signal WEEN Both are set to L level. As a result, the N-channel transistors 209 and 210 are turned off, and the nonvolatile memory portion 2_1 is disconnected from the slave latch portion 1S_1. Further, internal clocks CK and CKS having the same logic as clock CLK and internal clocks / CK and / CKS obtained by inverting clock CLK are generated. As a result, the nonvolatile flip-flop 200 operates as a normal flip-flop.

  More specifically, during the period when the clock CLK is at L level, the clocked inverter 201 is in the output enabled state, the clocked inverter 203 is in the output disabled state, and the transfer gates 205 and 206 are OFF. Therefore, the input data D is written to the master latch unit 1M_1, and the output data DM of the master latch unit 1M_1 is switched to the input data D. In addition, the slave latch unit 1S_1 holds previous data captured before the clock CLK becomes L level. During the period when the clock CLK is at the H level, the clocked inverter 201 is in the output disabled state, the clocked inverter 203 is in the output enabled state, and the transfer gates 205 and 206 are ON. For this reason, in the master latch unit 1M_1, data captured before the clock CLK becomes H level is held. In the slave latch unit 1S_1, the output data DS and / DS are rewritten by the output data DM of the master latch unit 1M_1.

  When performing storage to write the storage data DS of the slave latch unit 1S_1 to the nonvolatile storage unit 2_1, the read enable signal REEN is at L level (“0”) and the write enable signal WEEN is at H level (“1”). Is done. As a result, the reference node connection signal / WE becomes L level and the N-channel transistor 211 is turned off. Since reference node cutoff signal WE is at H level, internal clocks CK and / CKS are at H level and internal clocks / CK and CKS are at L level. As a result, the clocked inverter 201 is in the output disabled state, the clocked inverter 203 is in the output enabled state, and the master latch unit 1M_1 is in the previous data holding state. Further, the transfer gates 205 and 206 are turned OFF, and the slave latch unit 1S_1 is also in the previous data holding state.

  When the store operation is performed, the activation signal VWR is set to 1.5V. In this case, since the power supply voltage VDD is 1.2V, the activation signal VWR is generated by boosting the power supply voltage VDD of 1.2V by the booster circuit. When activation signal VWR becomes 1.5 V, N-channel transistors 209 and 210 are turned ON, and the output node (data DS) of inverter 208 is connected to resistance variable element 224 via N-channel transistor 209, and An output node (data / DS) is connected to variable resistance element 223 via N-channel transistor 210.

  Here, when the slave latch unit 1S_1 stores data “0” and DS = “0” and / DS = “1”, as shown in FIG. 4A, the output node of the inverter 207 → A current flows through a path of N channel transistor 210 → resistance change element 223 → resistance change element 224 → N channel transistor 209 → output node of inverter 208. In this case, the resistance change element 223 increases in resistance because a current flowing from the pin layer to the free layer flows, and the resistance change element 224 decreases in resistance because a current flows from the free layer to the pin layer. .

  On the other hand, when the slave latch unit 1S_1 stores data “1” and DS = “1” and / DS = “0”, as shown in FIG. 4B, the output node of the inverter 208 → N A current flows through a path of channel transistor 209 → resistance change element 224 → resistance change element 223 → N channel transistor 210 → output node of inverter 207. In this case, the resistance value of the resistance variable element 223 decreases because a current flowing from the free layer to the pinned layer flows, and the resistance value of the resistance variable element 224 increases because of the current flowing from the pinned layer to the free layer. .

  In this way, the storage data of the slave latch unit 1S_1 is written to the nonvolatile storage unit 2_1. In this case, the magnitude relationship between the resistance values of the resistance variable elements 224 and 223 represents the data stored in the nonvolatile storage unit 2_1. That is, if the resistance value of the resistance variable element 223 is larger than the resistance value of the resistance variable element 224, the storage data of the nonvolatile memory unit 2_1 is “0”, and the resistance value of the resistance variable element 224 is the resistance variable type. If it is larger than the resistance value of the element 223, the data stored in the nonvolatile memory portion 2_1 is “1”.

  3, the voltage SL of the common node CN when storing data “0” is 0.45 V, whereas the voltage SL of the common node CN when storing data “1” is 0. .55V. Such a difference occurs in the voltage SL because the resistance value between the variable resistance elements 223 and 224 at the time of storage is the same regardless of whether the data stored in the nonvolatile memory portion 2_1 is “0” or “1”. This is because there is a difference. First, when the nonvolatile storage unit 2_1 stores data “0”, the resistance variable element 224 has a low resistance and the resistance variable element 223 has a high resistance. When the output data DS of the slave latch unit 1S_1 is “0”, when the N-channel transistors 209 and 210 are turned on, the output voltage VDD (data / DS) of the inverter 207 is a resistance variable element having a high resistance. A voltage SL divided by the variable resistance element 224 having low resistance and 223 appears at the common node CN, and this voltage SL is 0.45 V, which is smaller than VDD / 2. On the other hand, when the output data DS of the slave latch unit 1S_1 is “1” and the N-channel transistors 209 and 210 are turned on, the output voltage VDD (data DS) of the inverter 208 is changed to a resistance variable element 224 having a low resistance. A voltage SL divided by the variable resistance element 223 having a high resistance appears at the common node CN, and this voltage SL becomes 0.55 V, which is larger than VDD / 2. As described above, in the present embodiment, there is a slight difference in the voltage SL appearing at the common node CN between the case where the data “0” is stored and the case where the data “1” is stored.

  The reason why the activation signal VWR is set to 1.5V higher than the power supply voltage 1.2V during the store operation is as follows. First, if activation signal WRE is set to 1.2 V, which is the same as the power supply voltage, the maximum value of the voltage that can be applied to resistance change elements 224 and 223 from inverters 208 and 207 is from this activation signal VWR = 1.2 V. The voltage is reduced by the threshold value of the N-channel transistors 209 and 210. Such a decrease in the voltage applied to the resistance variable elements 224 and 223 is not preferable because it hinders data writing. In addition, the resistances of N-channel transistors 209 and 210 need to be reduced in order to set the current flowing through resistance variable elements 224 and 223 to a current value sufficient to cause a change in resistance value. Therefore, a voltage of 1.5 V obtained by adding a voltage Vth corresponding to the threshold value of N channel transistors 224 and 223 to power supply voltage VDD = 1.2 V is applied to N channel transistors 209 and 210 as activation signal WRE. It is.

  In the operation example shown in FIG. 5, after the operation as a normal flip-flop is performed, “0” store for writing data “0” from the slave latch unit 1S_1 to the nonvolatile storage unit 2_1 is performed, and then the normal flip-flop is again operated. After the operation as the flip-flop, the data “1” is written from the slave latch unit 1S_1 to the nonvolatile memory unit 2_1.

  In the store operation, since current is passed through resistance change elements 223 and 224 by inverters 207 and 208, IR drops occur in the output voltages of inverters 207 and 208, respectively. Here, the output voltage (data DS) of the inverter 207 is input to the NAND gate 219 and the output voltage (data / DS) of the inverter 207 is input to the NOR gate 221. Therefore, if no measures are taken, these output voltages are set. Leakage current flows through the NAND gate 219 and the NOR gate 221 due to the influence of the appearing IR drop. However, in the present embodiment, during the store operation, the reference node connection signal / WE is set to L level, thereby turning off one N-channel transistor in the NAND gate 219 and setting the reference node cutoff signal WE to H level. Thus, one P-channel transistor in the NOR gate 221 is turned off. Therefore, generation of such a leakage current is prevented.

  After the store operation is completed, the power supply voltage VDD for the nonvolatile flip-flop 200 may be cut off. Even in the state where the power supply voltage VDD is cut off, the resistance change elements 223 and 224 maintain the resistance values set by the store operation in the nonvolatile memory portion 2_1.

  Next, the recall operation will be described. When the nonvolatile flip-flop 200 performs a recall operation, the write enable signal WEEN is set to L level (“0”), the read enable signal REEN is set to H level (“1”), and a predetermined activation signal VWR is set. Clamp voltage VCLAMP is applied to N-channel transistors 209 and 210. In this state, the power supply voltage VDD of the nonvolatile flip-flop 200 is raised.

  In this case, since the write enable signal WEEN is at the L level (“0”), the N-channel transistor 211 is turned on. Since read permission signal REEN is at H level (“1”), internal clock CKS is at L level, internal clock / CKS is at H level, and transfer gates 205 and 206 are turned off. Further, when the clamp voltage VCLAMP is applied as the activation signal VWR, the N-channel transistors 209 and 210 are turned on.

  Here, when the nonvolatile storage unit 2_1 stores data “0”, the resistance variable element 223 has a high resistance and the resistance variable element 224 has a low resistance. In this state, when the power supply voltage VDD rises from 0V to 1.2V, the current flowing from the output node of the inverter 208 toward the common node CN is greater than the current flowing from the output node of the inverter 207 toward the common node CN. Therefore, the voltage at the output node of the inverter 207 (data / DS) is higher than the voltage at the output node of the inverter 208 (data DS). As a result, in the slave latch unit 1S_1, the voltage (data / DS) at the output node of the inverter 207 becomes H level, and the voltage (data DS) V2 at the output node of the inverter 208 becomes L level, and this state is maintained. In this way, the data “0” is read from the nonvolatile storage unit 2_1 and stored in the slave latch unit 1S_1, and the recall of the data “0” is completed.

  On the other hand, when the nonvolatile storage unit 2_1 stores data “1”, the resistance variable element 223 has a low resistance and the resistance variable element 224 has a high resistance. In this state, when the power supply voltage VDD rises from 0 V to 1.2 V, the current flowing from the output node of the inverter 207 toward the common node CN is greater than the current flowing from the output node of the inverter 208 toward the common node CN. Therefore, the voltage at the output node of the inverter 208 (data DS) is higher than the voltage at the output node of the inverter 207 (data / DS). As a result, in the slave latch unit 1S_1, the voltage (data DS) at the output node of the inverter 208 becomes H level, and the voltage (data / DS) V2 at the output node of the inverter 207 becomes L level, and this state is maintained. In this way, the data “1” is read from the nonvolatile storage unit 2_1 and stored in the slave latch unit 1S_1, and the recall of the data “1” is completed.

  In the recall operation, the predetermined clamp voltage VCLAMP is applied to the N-channel transistors 209 and 208 as the activation signal VWR for the following reason. First, if a certain amount of bias is applied to the resistance variable elements 224 and 223, erroneous writing occurs, leading to read failure. For example, there is no problem when a current of 15 μA is applied by applying 0.2 V to the resistance variable elements 224 and 223, but a current of approximately 50 μA flows when a bias of 0.66 V or more is applied, and the resistance variable An erroneous writing of data to the elements 224 and 223 occurs. In order to prevent such erroneous writing, by applying a predetermined clamp voltage VCLAMP to the N-channel transistors 209 and 208, the ON resistance of the N-channel transistors 209 and 208 is appropriately increased, and the resistance variable elements 224 and 223 are appropriately adjusted. It is trying to apply a bias.

  After the recall is completed, the activation signal VWR is set to 0 V, and the resistance variable elements 223 and 224 are disconnected from the slave latch unit 1S_1. Thereafter, the read permission signal REEN is set to the L level (“0”). As a result, an operation as a normal flip-flop is started.

The nonvolatile flip-flop 200 according to the present embodiment can be realized by the following 55 transistors and two variable resistance elements.
<Number of transistors of nonvolatile flip-flop 200>
Inverter 11 Transistor number 22 Transfer gate 2 Transistor number 4 Clocked inverter 2 Transistor number 8 2 input NAND gate 1 Transistor number 4 2 input NOR gate 2 Transistor number 8 3 input NOR gate 1 Number of transistors 6 N-channel transistors 3
55 total

  On the other hand, the conventional flip-flop (FIG. 2) is realized by 28 transistors. Therefore, the required area of the nonvolatile flip-flop 200 is about twice that of the conventional flip-flop. Thus, according to the present embodiment, the nonvolatile flip-flop 200 can be realized without excessively increasing the required area.

Second Embodiment
FIG. 7 is a circuit diagram showing a configuration of a nonvolatile flip-flop 250 according to the second embodiment of the present invention. The nonvolatile flip-flop 250 includes a volatile flip-flop unit 1_2, a nonvolatile memory unit 2_2, and a control logic unit 3_2. The volatile flip-flop unit 1_2 includes a master latch unit 1M_2 and a slave latch unit 1S_2.

  The master latch unit 1M_2 includes clocked inverters 251 and 253 and an inverter 252. The configuration of the master latch unit 1M_2 is the same as that of the master latch unit 1M_1 of the first embodiment.

  The slave latch unit 1S_2 includes clocked inverters 254 to 256, a NAND gate 257, and an inverter 258. The output data DM of the master latch unit 1M_2 is input to the clocked inverter 255 via the clocked inverter 254. The clocked inverter 255 and the clocked inverter 256 constitute a latch that uses the output signals of the other party as input signals. Here, the clocked inverter 255 includes two P-channel transistors inserted in series between the power supply VDD and the output node, and two N-channel transistors inserted in series between the output node and the ground line GND. It is a thing of the known structure which consists of. In the clocked inverter 255, input data (data DSn in the illustrated example) is applied to the gates of one P-channel transistor and one N-channel transistor, and the ground level is applied to the gates of the remaining P-channel transistors. The power supply voltage VDD is always applied to the gates of GND and the remaining N-channel transistors. Therefore, the clocked inverter 255 is always in an output enable state. In order to realize a normal latch, a simple inverter may be used instead of the clocked inverter 255, but in this embodiment, the latch is constituted by two clocked inverters 255 and 256. The reason is that these two clocked inverters 255 and 256 are composed of transistors of the same size, so that the output current characteristics of the two are aligned with each other.

  The NAND gate 257 receives the output data DS of the clocked inverter 255 and the output suppression signal WERen. Inverter 258 inverts and outputs the output signal of NAND gate 257. The output signal of the inverter 258 becomes the output signal Q of the nonvolatile flip-flop 250. Further, the output signal of the NAND gate 257 becomes the inverted output signal / Q of the nonvolatile flip-flop 250.

  The nonvolatile memory unit 2_2 includes N-channel transistors 259 and 260, resistance change elements 267 and 266, and an N-channel transistor 261. The configuration of the nonvolatile storage unit 2_2 is the same as that of the nonvolatile storage unit 2_1 in the first embodiment.

  Next, the control logic unit 3_2 will be described. Inverter 265 inverts write enable signal WEEN and supplies it as a reference node connection signal / WE to the gate of N-channel transistor 261. The NOR gate 264 sets the output suppression signal WIREn applied to the NAND gate 257 to L level when at least one of the write enable signal WEEN or the read enable signal REEN is at H level. This is because the output voltage (data DS) of the clocked inverter 255 when the write enable signal WEEN is H level and the store operation is performed, or when the read enable signal REEN is H level and the recall operation is performed. This is because it is necessary to prevent an IR drop from occurring and a leakage current resulting from the IR drop from flowing into the NAND gate 257.

  NAND gate 262 and inverter 263 form a circuit for generating internal clocks CKS and / CKS. This circuit generates an internal clock CKS having the same logical value as that of the clock CLK and an internal clock / CKS obtained by inverting the clock CLK when the output suppression signal WEEn is at the H level. Also, this circuit fixes the internal clock CKS to the L level and the internal clock / CKS to the H level regardless of the clock CLK when the output suppression signal WEEn is at the L level.

  When the internal clock CKS is L level and the internal clock / CKS is H level, in the master latch unit 1M_2, the clocked inverter 251 is in the output enabled state and the clocked inverter 253 is in the output disabled state. Data DM is rewritten. In the slave latch unit 1S_2, since the clocked inverter 254 is in the output disabled state and the clocked inverter 256 is in the output enabled state, the previous data is held.

  On the other hand, when the internal clock CKS is H level and the internal clock / CKS is L level, the master latch unit 1M_2 holds the previous data because the clocked inverter 251 is in the output disabled state and the clocked inverter 253 is in the output enabled state. Is done. In the slave latch unit 1S_2, since the clocked inverter 254 is in the output enable state and the clocked inverter 256 is in the output disable state, the output data DS is rewritten by the output data DM of the master latch unit 1M_2.

  At the time of store, write enable signal WEEN is set to H level, and read enable signal REEN is set to L level. In this case, since reference node connection signal / WE is at L level, N-channel transistor 261 is turned OFF. Further, since the output suppression signal WERen becomes L level, the clocked inverter 254 is in the output disabled state, the clocked inverter 256 is in the output enabled state, and the latch including the clocked inverters 255 and 256 is disconnected from the master latch unit 1M_2. . In this state, activation signal VWR is applied to N channel transistors 259 and 260, whereby a store operation is performed. The details of this store operation are the same as in the first embodiment.

  At the time of recall, write enable signal WEEN is set to L level, and read enable signal REEN is set to H level. In this case, since reference node connection signal / WE is at H level, N-channel transistor 261 is turned on. Further, since the output suppression signal WERen becomes L level, the clocked inverter 254 is in the output disabled state, the clocked inverter 256 is in the output enabled state, and the latch including the clocked inverters 255 and 256 is disconnected from the master latch unit 1M_2. . In this state, a predetermined clamp voltage VCLAMP is applied to N-channel transistors 259 and 260 as activation signal VWR, and a recall operation is performed by raising power supply voltage VDD. The details of this recall operation are the same as in the second embodiment.

The nonvolatile flip-flop 250 according to the present embodiment can be realized by the following 43 transistors and two variable resistance elements.
<Number of transistors of nonvolatile flip-flop 250>
Inverter 4 transistor number 8 clocked inverter 5 transistor number 20 transistor 2 input NAND gate 2 transistor number 8 2 input NOR gate 1 transistor number 4 N channel transistor 3
A total of 43 The same effects as in the first embodiment can be obtained in this embodiment.

<Third Embodiment>
FIG. 8 is a circuit diagram showing a configuration of a nonvolatile flip-flop 300 according to the third embodiment of the present invention. The nonvolatile flip-flop 300 includes a volatile flip-flop unit 1_3, a nonvolatile storage unit 2_3, and a control logic unit 3_3. In addition, the volatile flip-flop unit 1_3 includes a master latch unit 1M_3 and a slave latch unit 1S_3.

  The configurations of the nonvolatile storage unit 2_3 and the control logic unit 3_3 are the same as the configurations of the nonvolatile storage unit 2_1 and the control logic unit 3_1 in the first embodiment (FIG. 1). However, in the volatile flip-flop unit 1_3, the elements 201 to 208 and 219 to 222 constituting the volatile flip-flop unit 1_1 of the first embodiment are replaced with elements 201v to 208v and 219v to 222v. Each of the elements 201v to 208v and 219v to 222v of the volatile flip-flop unit 1_3 is provided with a power supply system independently of other circuits, and the power supply voltage VDD supplied to the control logic unit 3_3 and the like Is supplied with an independently controllable power supply voltage VDDC.

FIG. 9 is a diagram showing the operation of this embodiment. As shown in FIG. 9, in a situation where the power supply voltage VDD of the entire system is supplied to the volatile flip-flop unit 1_3 as the power supply voltage VDDC, the operation and store as a normal flip-flop similar to the first embodiment is performed. Operation is possible. Further, by raising the power supply voltage VDDC for the volatile flip-flop unit 1_3 to the power supply voltage VDD of the entire system, the non-volatile flip-flop 300 can perform a recall operation similar to that of the first embodiment. In addition, in this embodiment, the power supply voltage VDDC for the volatile flip-flop unit 1_3 can be cut off independently.
The above is the details of the present embodiment.

  Also in this embodiment, the same effect as the first embodiment can be obtained. In addition, in this embodiment, the power supply voltage VDDC for the volatile flip-flop unit 1_3 can be cut off or started up independently of the power supply voltage of the entire system. Therefore, various operations can be realized in a system in which the nonvolatile flip-flop 300 is mounted. In the present embodiment, during the recall operation, first, the power supply voltage VDD for the circuits other than the volatile flip-flop unit 1_3 such as the control logic unit 3_3 is raised, and then the power supply voltage VDDC for the volatile flip-flop unit 1_3 is raised. By raising it, it is possible to improve the stability of the recall operation.

  In addition, the following modifications can be considered in this embodiment. That is, a power supply system is provided independently for a plurality of nonvolatile flip-flops, a desired nonvolatile flip-flop is selected, only the power supply voltage VDDC for the selected nonvolatile flip-flop is cut off, and a leakage current is reduced. It is reduced. Alternatively, the plurality of nonvolatile flip-flops are divided into groups of one or more nonvolatile flip-flops, and the supply of the power supply voltage VDC is cut off in units of groups. According to this aspect, fine power saving control is possible.

<Fourth embodiment>
FIG. 10 is a circuit diagram showing a configuration of a nonvolatile flip-flop 350 according to the fourth embodiment of the present invention. The nonvolatile flip-flop 350 includes a volatile flip-flop unit 1_4, a nonvolatile memory unit 2_4, and a control logic unit 3_4. In addition, the volatile flip-flop unit 1_4 includes a master latch unit 1M_4 and a slave latch unit 1S_4.

The configurations of the nonvolatile storage unit 2_4 and the control logic unit 3_4 are the same as the configurations of the nonvolatile storage unit 2_2 and the control logic unit 3_2 of the second embodiment (FIG. 7). However, in the volatile flip-flop unit 1_4 in the present embodiment, the elements 251 to 258 constituting the volatile flip-flop unit 1_2 in the second embodiment are replaced with elements 251v to 258v. Each element 251v to 258v of the volatile flip-flop unit 1_4 is provided with a power supply system independent of other circuits, and is controlled independently of the power supply voltage VDD supplied to the control logic unit 3_4 and the like. A possible power supply voltage VDDC is supplied.
Also in this embodiment, the same effect as the third embodiment can be obtained.

<Fifth Embodiment>
FIG. 11 is a circuit diagram showing a configuration of a nonvolatile flip-flop 400 according to the fifth embodiment of the present invention. The nonvolatile flip-flop 400 includes a volatile flip-flop unit 1_5, a nonvolatile storage unit 2_5, and a control logic unit 3_5. In addition, the volatile flip-flop unit 1_5 includes a master latch unit 1M_5 and a slave latch unit 1S_5.

  The configurations of the volatile flip-flop unit 1_5 and the control logic unit 3_5 are the same as the configurations of the volatile flip-flop unit 1_1 and the control logic unit 3_1 in the first embodiment (FIG. 1). In the nonvolatile memory unit 2_1 in the first embodiment, the source of the N-channel transistor 211 is connected to the ground line GND. In contrast, in the nonvolatile memory unit 2_5 in the present embodiment, the source of the N-channel transistor 211 is connected to a voltage source that generates the bias voltage SLL.

  The operation of the nonvolatile flip-flop 400 according to the present embodiment as a normal flip-flop and the store operation are the same as those in the first embodiment. However, the operation at the time of recall of the nonvolatile flip-flop 400 according to the present embodiment is different from that of the first embodiment.

In the first embodiment, during the recall operation, a clamp voltage VCLAMP lower than the power supply voltage VDD is applied as the activation signal VWR to the gates of the N-channel transistors 209 and 210 to suppress the current flowing through the resistance variable elements 224 and 223. did. On the other hand, in the present embodiment, a voltage having the same level as the power supply voltage VDD is applied as the activation signal VWR during the recall operation. Instead, in this embodiment, the level SL of the common node CN of the resistance variable elements 224 and 223 is increased by setting the bias voltage SLL applied to the source of the N-channel transistor 211 to 0.2 V to 0.4 V, The ON resistances of the N-channel transistors 209 and 210 are increased, and the current flowing through the resistance variable elements 224 and 223 is suppressed.
Also in this embodiment, the same effect as the first embodiment can be obtained.

<Sixth Embodiment>
FIG. 12 is a circuit diagram showing a configuration of a nonvolatile flip-flop 450 according to the sixth embodiment of the present invention. The nonvolatile flip-flop 450 includes a volatile flip-flop unit 1_6, a nonvolatile storage unit 2_6, and a control logic unit 3_6. In addition, the volatile flip-flop unit 1_6 includes a master latch unit 1M_6 and a slave latch unit 1S_6.

  In the present embodiment, the same change operation as the change operation from the first embodiment to the fifth embodiment is performed on the second embodiment. Also in this embodiment, the same effect as the first embodiment can be obtained.

<Seventh embodiment>
FIG. 13 is a circuit diagram showing a configuration of a nonvolatile flip-flop 500 according to the seventh embodiment of the present invention. The nonvolatile flip-flop 500 includes a volatile flip-flop unit 1_7, a nonvolatile storage unit 2_7, and a control logic unit 3_7. In addition, the volatile flip-flop unit 1_7 includes a master latch unit 1M_7 and a slave latch unit 1S_7.

  In the present embodiment, the same change operation as the change operation from the first embodiment to the fifth embodiment is performed on the third embodiment. Also in this embodiment, the same effect as the third embodiment can be obtained.

<Eighth Embodiment>
FIG. 14 is a circuit diagram showing a configuration of a nonvolatile flip-flop 550 according to the eighth embodiment of the present invention. The nonvolatile flip-flop 550 includes a volatile flip-flop unit 1_8, a nonvolatile storage unit 2_8, and a control logic unit 3_8. In addition, the volatile flip-flop unit 1_8 includes a master latch unit 1M_8 and a slave latch unit 1S_8.

  In the present embodiment, the same change operation as the change operation from the first embodiment to the fifth embodiment is applied to the fourth embodiment. Also in this embodiment, the same effect as the fourth embodiment can be obtained.

<Ninth Embodiment>
FIG. 15 is a circuit diagram showing a configuration of a nonvolatile latch 600 according to the ninth embodiment of the present invention. The nonvolatile latch 600 includes a volatile latch unit 1L_9, a nonvolatile storage unit 2_9, and a control logic unit 3_9.

  The volatile latch unit 1L_9 includes inverters 601, 602, 604 and 606, transfer gates 603 and 605, a NAND gate 617 and an inverter 618, a NOR gate 619 and an inverter 620. The configuration of the volatile latch unit 1L_9 is the same as that of the slave latch unit 1S_1 in the first embodiment.

  The nonvolatile memory unit 2_9 includes N channel transistors 607 and 608, resistance change elements 610 and 611, and an N channel transistor 609. The configuration of the nonvolatile storage unit 2_9 is the same as that of the nonvolatile storage unit 2_1 of the first embodiment (FIG. 1).

  Next, the control logic unit 3_9 will be described. Nonvolatile latch 600 is supplied with input data D, clock CLK, read enable signal REEN and write enable signal WEEN, and activation signal VWR. Inverter 615 inverts write enable signal WEEN and outputs the inverted signal as reference node connection signal / WE. Inverter 616 inverts this reference node connection signal / WE and outputs it as reference node cutoff signal WE.

  NOR gate 613 and inverters 612 and 614 constitute a circuit for generating internal clocks CKS and / CKS based on clock CLK, read permission signal REEN and reference node cutoff signal WE. This circuit generates an internal clock CKS having the same logical value as that of the clock CLK and an internal clock / CKS obtained by inverting the clock CLK when both the reference node cutoff signal WE and the read enable signal REEN are at the L level. When at least one of the cutoff signal WE and the read enable signal REEN is at the H level, the internal clock CKS is fixed at the L level and the internal clock / CKS is fixed at the H level. When internal clock CKS is at L level and internal clock / CKS is at H level, transfer gates 603 and 605 are turned off. When internal clock CKS is at H level and internal clock / CKS is at L level, transfer gates 603 and 605 are turned on.

  The nonvolatile latch 600 according to the present embodiment functions as a normal latch when both the write enable signal WE and the read enable signal REEN are at the L level and the activation signal VWR is at the L level (0 V).

  When causing the nonvolatile latch 600 to perform a store operation, the write enable signal WE is set to the H level, the read enable signal REEN is set to the L level, and the transfer gates 603 and 605 are forcibly turned off. Further, the activation signal VWR is set to 1.5 V, for example, higher than the power supply voltage VDD. As a result, the storage data DS of the volatile latch unit 1L_9 is stored in the nonvolatile storage unit 2_9. The operation of this store is the same as in the first embodiment.

  When the nonvolatile latch 600 performs a recall operation, the write enable signal WE is set to L level, the read enable signal REEN is set to H level, and the transfer gates 603 and 605 are forcibly turned off. A clamp voltage VCLAMP similar to that in the first embodiment is applied as the activation signal VWR to the gates of the N-channel transistors 607 and 608. In this state, the power supply voltage VDD for the nonvolatile latch 600 is raised. As a result, the data stored in the nonvolatile storage unit 2_9 is read and held in the volatile latch unit 1L_9. This recall operation is also the same as in the first embodiment.

  According to the present embodiment, an operation as a normal latch is possible, and a store operation and a recall operation can be stably performed as in the first to eighth embodiments related to the nonvolatile flip-flop.

<Tenth Embodiment>
FIG. 16 is a circuit diagram showing a configuration of a nonvolatile latch 650 according to the tenth embodiment of the present invention. The nonvolatile flip-flop 650 includes a volatile latch unit 1L_10, a nonvolatile storage unit 2_10, and a control logic unit 3_10.

  The volatile latch unit 1L_10 includes clocked inverters 651 to 653, a NAND gate 654, and an inverter 655. The configuration of the volatile latch unit 1L_10 is the same as that of the slave latch unit 1S_2 in the second embodiment.

  The nonvolatile memory portion 2_10 includes N channel transistors 656 and 657, resistance change elements 664 and 663, and an N channel transistor 658. The configuration of the nonvolatile storage unit 2_10 is the same as that of the nonvolatile storage unit 2_1 of the first embodiment (FIG. 1). The configuration of the control logic unit 3_10 is the same as that of the control logic unit 3_2 of the second embodiment (FIG. 7).

  In the present embodiment, as in the ninth embodiment, the normal latch operation, store operation, and recall operation can be performed stably.

<Eleventh embodiment>
FIG. 17 is a circuit diagram showing a configuration of a nonvolatile latch 700 according to the eleventh embodiment of the present invention. The nonvolatile latch 700 includes a volatile latch unit 1L_11, a nonvolatile storage unit 2_11, and a control logic unit 3_11.

  The configurations of the nonvolatile storage unit 2_11 and the control logic unit 3_11 are the same as those of the nonvolatile storage unit 2_9 and the control logic unit 3_9 of the ninth embodiment (FIG. 15). However, in the volatile latch unit 1L_11, the elements 601 to 606 and 617 to 620 constituting the volatile latch unit 1L_9 of the ninth embodiment are replaced with elements 601v to 606v and 617v to 620v. Each of the elements 601v to 606v and 617v to 620v of the volatile latch unit 1L_11 is provided with a power supply system independently of other circuits. What is the power supply voltage VDD supplied to the control logic unit 3_11 and the like? An independently controllable power supply voltage VDDC is supplied.

  According to this embodiment, the same effect as the ninth embodiment can be obtained. In addition, in this embodiment, the power supply voltage VDDC for the volatile latch unit 1L_11 can be cut off or started up independently of the power supply voltage of the entire system. Accordingly, various operations can be realized in a system in which the nonvolatile latch 700 is mounted. In this embodiment, at the time of the recall operation, first, the power supply voltage VDD for the circuits other than the volatile latch unit 1L_11 such as the control logic unit 3_11 is raised, and then the power supply voltage VDDC for the volatile latch unit 1L_11 is raised. Thus, the stability of the recall operation can be improved.

<Twelfth embodiment>
FIG. 18 is a circuit diagram showing a configuration of a nonvolatile latch 750 according to the twelfth embodiment of the present invention. The nonvolatile latch 750 includes a volatile latch unit 1L_12, a nonvolatile storage unit 2_12, and a control logic unit 3_12.

The configurations of the nonvolatile memory unit 2_12 and the control logic unit 3_12 are the same as those of the nonvolatile memory unit 2_10 and the control logic unit 3_10 of the tenth embodiment (FIG. 16). However, in the volatile latch unit 1L_12, the elements 651 to 655 constituting the volatile latch unit 1L_10 of the tenth embodiment are replaced with elements 651v to 655v. Each of the elements 651v to 655v of the volatile latch unit 1L_12 is provided with a power supply system independently of other circuits, and can be controlled independently of the power supply voltage VDD supplied to the control logic unit 3_12 and the like. Power supply voltage VDDC is supplied.
Also in this embodiment, the same effect as the eleventh embodiment can be obtained.

<13th Embodiment>
FIG. 19 is a circuit diagram showing a configuration of a nonvolatile latch 800 according to the thirteenth embodiment of the present invention. The nonvolatile latch 800 includes a volatile latch unit 1L_13, a nonvolatile storage unit 2_13, and a control logic unit 3_13.

The configurations of the volatile latch unit 1L_13 and the control logic unit 3_13 are the same as the configurations of the volatile latch unit 1L_9 and the control logic unit 3_9 of the ninth embodiment (FIG. 15). In the nonvolatile memory unit 2_9 in the ninth embodiment, the source of the N-channel transistor 609 is connected to the ground line GND. On the other hand, in the nonvolatile memory unit 2_13 in the present embodiment, the source of the N-channel transistor 609 is connected to a voltage source that generates the bias voltage SLL. That is, in this embodiment, the change operation from the first embodiment to the fifth embodiment is applied to the ninth embodiment.
According to this embodiment, the same effect as that of the fifth embodiment can be obtained in the nonvolatile latch of the ninth embodiment.

<Fourteenth embodiment>
FIG. 20 is a circuit diagram showing a configuration of a nonvolatile latch 850 according to the fourteenth embodiment of the present invention. The nonvolatile latch 850 includes a volatile latch unit 1L_14, a nonvolatile storage unit 2_14, and a control logic unit 3_14.

  In the present embodiment, the same change operation as the change operation from the ninth embodiment to the thirteenth embodiment is performed on the tenth embodiment. Also in this embodiment, the same effect as the thirteenth embodiment can be obtained.

<Fifteenth embodiment>
FIG. 21 is a circuit diagram showing a configuration of a nonvolatile latch 900 according to the fifteenth embodiment of the present invention. The non-volatile latch 900 includes a volatile latch unit 1L_15, a non-volatile storage unit 2_15, and a control logic unit 3_15.

  In the present embodiment, the same change operation as the change operation from the ninth embodiment to the thirteenth embodiment is performed on the eleventh embodiment. Also in this embodiment, the same effect as the thirteenth embodiment can be obtained.

<Sixteenth Embodiment>
FIG. 22 is a circuit diagram showing a configuration of a nonvolatile latch 950 according to the sixteenth embodiment of the present invention. The nonvolatile latch 950 includes a volatile latch unit 1L_16, a nonvolatile storage unit 2_16, and a control logic unit 3_16.

  In the present embodiment, the same change operation as the change operation from the ninth embodiment to the thirteenth embodiment is performed on the twelfth embodiment. Also in this embodiment, the same effect as the thirteenth embodiment can be obtained.

<Seventeenth Embodiment>
This embodiment includes the fifth embodiment (FIG. 11), the sixth embodiment (FIG. 12), the seventh embodiment (FIG. 13), the eighth embodiment (FIG. 14), and the thirteenth embodiment (FIG. 19). The fourteenth embodiment (FIG. 20), the fifteenth embodiment (FIG. 21), and the sixteenth embodiment (FIG. 22) are modified.

  In each of these embodiments, the N-channel transistor 211 or 261 is turned OFF during the store operation. For this reason, even when the same data is stored, the voltage applied to the two resistance variable elements at the time of storage changes depending on the data stored in the nonvolatile storage unit. For example, in the fifth embodiment (FIG. 11), the case where the output data DS = “0” of the slave latch unit 1S_5 is stored in the nonvolatile storage unit 2_5 will be considered. First, it is assumed that the nonvolatile storage unit 2_5 stores data “0”, the resistance variable element 224 has a low resistance, and the resistance variable element 223 has a high resistance. In this case, when the N-channel transistors 209 and 210 are turned ON, the voltage VDD of the output node (output data / DS = “1”) of the inverter 207 is changed to the resistance variable element 223 having a high resistance and the resistance change having a low resistance. Since the voltage is divided by the type element 224, a voltage larger than VDD / 2 is applied to the resistance variable element 223, and a voltage smaller than VDD / 2 is applied to the resistance variable element 224. In contrast, when the nonvolatile storage unit 2_5 stores data “1”, the resistance variable element 224 has a high resistance, and the resistance variable element 223 has a low resistance, the N-channel transistors 209 and 210 are turned on. Then, a voltage lower than VDD / 2 is applied to the resistance variable element 223 having a low resistance, and a voltage higher than VDD / 2 is applied to the resistance variable element 224 having a high resistance. As described above, in each of the above embodiments, even when the same data is stored, the voltage applied to each of the two resistance variable elements at the time of storage changes depending on the data stored in the nonvolatile storage unit. .

  However, in order to perform a stable store operation, it is preferable to always apply a constant voltage to each of the two resistance variable elements regardless of the data stored in the nonvolatile storage unit.

  Therefore, in the seventeenth embodiment of the present invention, the reference node connection signal / WE is set to the active level even during the store operation, the N-channel transistor 211 is turned on, and the bias voltage SLL of, for example, VDD / 2 (0.6 V in this example). Is supplied to the common node CN via the N-channel transistor 211, and the bias voltage SL of the common node CN is set to approximately VDD / 2 (0.6 V). The N-channel transistor 211 in this embodiment functions as a bias setting unit that applies the bias voltage SL to the common node CN during the store operation.

  In this case, for example, in FIG. 11, when the nonvolatile storage unit 2_5 stores data “0”, the resistance variable element 224 has a low resistance, and the resistance variable element 223 has a high resistance, the N-channel transistors 209 and 210 Is turned on, the voltage VDD of the output node (output data / DS = “1”) of the inverter 207 and the bias voltage SL = VDD / 2 of the common node CN are between the pin layer and the free layer of the resistance variable element 223. The voltage VDD / 2, which is the difference between the two, is applied. Further, between the free layer and the pin layer of the resistance variable element 224, there is a difference between the bias voltage SL = VDD / 2 of the common node CN and the voltage 0 V of the output node of the inverter 208 (output data DS = “0”). A voltage VDD / 2 is applied. In the case where the N-channel transistors 209 and 210 are turned on when the nonvolatile storage unit 2_5 stores data “1”, the resistance variable element 224 has a high resistance, and the resistance variable element 223 has a low resistance. The same voltage is applied to each resistance variable element.

  As described above, according to the present embodiment, whether the stored data of the resistance change types 223 and 224 is “1” or “0” (that is, which is high resistance and which is low resistance). Regardless, the voltage applied between the output node (output data DS) of the inverter 208 and the common node CN and the voltage applied between the common node CN and the output node (output data / DS) of the inverter 207. Can be kept constant (VDD / 2 in this example). Therefore, according to this embodiment, a nonvolatile flip-flop and a nonvolatile latch capable of stable store operation can be realized.

  In this embodiment, the N-channel transistor 211 used at the time of recall is also used as a bias setting means for applying the bias voltage SL to the common node CN at the time of storing. However, a transistor other than the N-channel transistor 211 is used as the bias setting means. May be added. In this case, the N-channel transistor 211 for the recall operation is turned off by turning on the transistor as the bias setting means at the store time, and the N-channel transistor 211 for the recall operation is turned off by turning off the transistor as the bias setting means at the recall time. Should be turned on.

<Eighteenth embodiment>
FIG. 23 is a block diagram showing a configuration of a nonvolatile shift register according to the eighteenth embodiment of the present invention. In this example, four nonvolatile flip-flops 200 according to the first embodiment are used, and a 4-bit shift register that sequentially shifts input data D in synchronization with a clock CLK is configured.

The write enable signal WEEN, the read enable signal REEN, and the activation signal VWR are supplied to the four nonvolatile flip-flops 200 in parallel. Accordingly, it is possible to cause the four nonvolatile flip-flops 200 to simultaneously perform a store operation and a recall operation.
In addition, as the nonvolatile flip-flop constituting the shift register, those in the second to eighth and seventeenth embodiments may be adopted in addition to those in the first embodiment.

<Nineteenth embodiment>
FIG. 24 is a block diagram showing a configuration of a nonvolatile register according to the nineteenth embodiment of the present invention. In this example, four nonvolatile flip-flops 200 according to the first embodiment are used to constitute a 4-bit register.

  The write enable signal WEEN, the read enable signal REEN, and the activation signal VWR are supplied to the four nonvolatile flip-flops 200 in parallel. Accordingly, it is possible to cause the four nonvolatile flip-flops 200 to simultaneously perform a store operation and a recall operation.

  This register has a wide range of uses, like a general register, and is used, for example, for storing data generated in the course of some arithmetic processing. If it is necessary to shut off the power supply in the course of the arithmetic processing, the store operation is performed in each nonvolatile flip-flop 200 prior to that, and then the power supply is shut off. Thereafter, when the power is turned on, each nonvolatile flip-flop 200 is caused to perform a recall operation. As a result, the data before power-off can be restored in the register, and the arithmetic processing can be resumed.

  Note that the nonvolatile flip-flops constituting the register may employ the second to eighth and seventeenth embodiments in addition to the first embodiment. Further, the register may be constituted by the nonvolatile latches of the ninth to seventeenth embodiments instead of the nonvolatile flip-flop.

<20th Embodiment>
FIG. 25 is a block diagram showing the configuration of a nonvolatile counter according to the twentieth embodiment of the present invention. In the present embodiment, a 4-bit up counter is configured by the four flip-flops 200 and the illustrated XOR gate and AND gate. Since the counter itself has a well-known configuration, description thereof is omitted.

  Each flip-flop 200 is the nonvolatile flip-flop 200 according to the first embodiment. These flip-flops 200 are supplied with a clock CLK, an activation signal VWR, a write enable signal WEEN, and a read enable signal REEN.

  In this embodiment, in addition to operating the counter shown in FIG. 25 as a normal counter, the following operation can be performed.

  First, in the process in which the counter shown in FIG. 25 performs the counting operation, when it is necessary to shut off the power, the flip-flops 200 constituting the counter are caused to perform a store operation, and then the power is shut off.

  Thereafter, when the power is turned on, each flip-flop 200 constituting the counter is caused to perform a recall operation. Thereby, the count value before power-off is restored, and the count operation can be restarted from the count value before power-off.

  In the example shown in FIG. 25, the synchronous counter is configured by the plurality of nonvolatile flip-flops 200, but an asynchronous counter may be configured. Further, the flip-flops constituting the counter may be the nonvolatile flip-flops of the second to eighth and seventeenth embodiments.

1_1 to 1_8... Volatile flip-flop unit, 1M_1 to 1M_8... Master latch unit, 1S_1 to 1S_8... Slave latch unit, 2_1 to 2_16. -3_16 ... control logic section, 207, 208 ... inverter, 255, 256 ... clocked inverter, 209, 210, 211, 259, 260, 261 ... N-channel transistor, 224, 223 ... resistance change element , CN... Common node, 200, 250, 300, 350, 400, 450, 500, 550... Nonvolatile flip-flop, 600, 650, 700, 750, 800, 850, 900, 950.

Japanese Patent Application Laid-Open No. 2004-228867 proposes a rewritable nonvolatile latch and flip-flop using such an MTJ element. Figure 28 is a circuit diagram of the nonvolatile latch shown in FIG. 1 of Patent Document 2. In FIG. 28, the transfer gates TMG1 and TMG2 and the NOR gates 10 and 20 constitute a known latch. One end of the MTJ element R1 is connected to the source of the P-channel transistor 11 of the NOR gate 10, and one end of the MTJ element R2 is connected to the source of the P-channel transistor 21 of the NOR gate 20, and other MTJ elements R1 and R2 are connected. A P-channel transistor Tr1 is interposed between the connection point between the ends and the power supply Vdd. Data D is applied to the connection point between the P channel transistor 11 and the MTJ element R1 via the transfer gate TMG3, and the transfer gate TMG4 is connected to the connection point between the P channel transistor 21 and the MTJ element R2. The data DB is provided via the. Further, a P-channel transistor Tr2 is interposed between the connection point of the P-channel transistor 11 and the MTJ element R1 and the power supply Vdd, and a P-channel is connected between the connection point of the P-channel transistor 21 and the MTJ element R2 and the power supply Vdd. A transistor Tr3 is inserted.

By the way, in the nonvolatile latch disclosed in the above-mentioned Patent Document 2, the data Q and QB stored in the latch section including the NOR gates 10 and 20 and the transfer gates TMG1 and TMG2 are directly written into the MTJ elements R1 and R2. I can't. In order to write the data Q and QB of the latch portion into the MTJ elements R1 and R2, it is necessary to read the data Q and QB and then apply them to the transfer gates TMG3 and TMG4. Therefore, there is a problem that the control for causing the store operation to write the data stored in the volatile latch unit to the MTJ elements R1 and R2 becomes complicated. In the nonvolatile latch disclosed in Patent Document 2, when performing a recall operation for reading data stored in the MTJ elements R1 and R2 and holding the data in the volatile latch unit, first, the signal NV_RW is set to the H level. to precharge the nodes B and node a to 0V. Thereafter, the signal NV_RW is set to L level to turn on the P-channel transistors 12 and 22, and the data stored in the MTJ elements R1 and R2 are read. At this time, the behavior of the nodes A and B becomes unstable due to the influence of the threshold variation of the cross-coupled P-channel transistors 11 and 21, and an appropriate value reflecting the magnitude relationship of the resistance values of the MTJ elements R1 and R2 is reflected. Data may not be held in the volatile latch. Further, in the nonvolatile latch of Patent Document 2, although reference is not made to the load capacitances of the output node Q and the output node QB, in reality, a large capacitance is interposed in the output nodes Q and QB. In addition, depending on how it is used, it is assumed that the load capacity is unbalanced between the output node Q and the output node QB. In such a case, there is a concern that the recall operation becomes unstable. As described above, the nonvolatile latch of Patent Document 2 has a problem that the control for performing the store operation is complicated and the recall operation becomes unstable. In addition, since the nonvolatile latch of Patent Document 2 does not have means for optimizing the current flowing through the MTJ elements R1 and R2 during store and recall, it can effectively prevent erroneous writing and erroneous reading. There was a problem that could not.

Claims (34)

A volatile flip-flop unit composed of a master latch unit and a slave latch unit;
A non-volatile storage unit,
The slave latch unit includes first and second inverters each having an output signal of each other as an input signal for each other. The slave latch unit receives the input data from the master latch unit in synchronization with a clock and the input data acquired The operation held by the first and second inverters is performed,
The nonvolatile memory section includes a first switch and a first variable resistance element inserted in series between an output node of the first inverter and a common node, and an output node of the second inverter A second switch and a second variable resistance element inserted in series between the common node and the common node, and a third switch interposed between the common node and a reference node ,
In the first and second variable resistance elements, the first and second switches are turned on and the third switch is turned off, and the output of the second inverter is output from the output node of the first inverter. When a current toward the node flows, a resistance value of the first resistance variable element is in a first direction, and a resistance value of the second resistance variable element is a second direction opposite to the first direction. When the current flows from the output node of the second inverter to the output node of the first inverter, the resistance value of the first variable resistance element changes in the second direction. A nonvolatile flip-flop, wherein the resistance value of the second variable resistance element is a variable resistance element that changes in the first direction.   2. The nonvolatile flip-flop according to claim 1, wherein the first and second variable resistance elements are a magnetic tunnel junction element or a resistive element in which an electric field induced giant resistance change occurs. The slave latch unit captures input data from the master latch unit when the clock has a first logic value, and the first and second inverters cause the master latch to operate when the clock has a second logic value. The input data that is cut off from the master latch unit and taken in from the master latch unit is held,
When performing a store for writing data from the slave latch unit to the non-volatile storage unit, the slave latch unit is disconnected from the master latch unit by setting the clock to the second logical value, and the first latch When the second switch is turned on and the third switch is turned off, the magnitude relationship between the resistance values of the first and second variable resistance elements is determined by the outputs of the first and second inverters. The nonvolatile flip-flop according to claim 1 or 2, wherein the magnitude relationship is in accordance with a signal. The first and second switches are field effect transistors;
The said 1st and 2nd switch is turned ON by the gate voltage higher than the high potential side power supply voltage of the said volatile flip-flop part, when performing the said store. Non-volatile flip-flop. The slave latch unit captures input data from the master latch unit when the clock has a first logic value, and the first and second inverters cause the master latch to operate when the clock has a second logic value. The input data that is cut off from the master latch unit and taken in from the master latch unit is held,
When performing a recall to read data from the nonvolatile storage unit and write to the slave latch unit, the slave latch unit is cut off from the master latch unit by the clock being the second logical value, The first and second switches are turned on, the third switch is turned on, and the power supply voltage for the volatile flip-flop unit is raised, so that the output signals of the first and second inverters are high and low. 5. The nonvolatile flip-flop according to claim 1, wherein the relationship is a height relationship corresponding to a magnitude relationship of resistance values of the first and second resistance change elements. . The first and second switches are field effect transistors;
When performing the recall, the first and second switches are turned on by a gate voltage lower than the high-potential-side power supply voltage of the volatile flip-flop section after the power-supply voltage of the volatile flip-flop section rises. The nonvolatile flip-flop according to claim 5, wherein The first and second switches are field effect transistors;
6. The non-volatile device according to claim 5, wherein when the recall is performed, a bias voltage having an offset with respect to a low-potential side power supply voltage of the volatile flip-flop unit is supplied to the reference node. flip flop.   A power supply voltage supply system for the volatile flip-flop unit is provided independently of a power supply voltage supply system for other circuits, and the volatile flip-flop is independent of supply / cutoff of the power supply voltage to other circuits. The nonvolatile flip-flop according to claim 1, wherein the nonvolatile flip-flop is configured to supply / shut off the power supply voltage to the power supply unit. A volatile latch unit and a nonvolatile storage unit;
The volatile latch unit includes first and second inverters each having an output signal of a counterpart as an input signal for each other, and takes in input data when the clock becomes a first logic value, and the clock receives a second Shutting off the first and second inverters from the input data source by becoming a logical value;
The nonvolatile memory section includes a first switch and a first variable resistance element inserted in series between an output node of the first inverter and a common node, and an output node of the second inverter A second switch and a second variable resistance element inserted in series between the common node and the common node, and a third switch interposed between the common node and a reference node ,
In the first and second variable resistance elements, the first and second switches are turned on and the third switch is turned off, and the output of the second inverter is output from the output node of the first inverter. When a current toward the node flows, a resistance value of the first resistance variable element is in a first direction, and a resistance value of the second resistance variable element is a second direction opposite to the first direction. When the current flows from the output node of the second inverter to the output node of the first inverter, the resistance value of the first variable resistance element changes in the second direction. The nonvolatile latch is a resistance variable element in which a resistance value of the second resistance variable element changes in each of the first directions.   When performing a store for writing the data stored in the volatile latch unit to the non-volatile storage unit, the first and second inverters are connected to the input data by setting the clock to the second logical value. The first and second switches are turned on and the third switch is turned off, so that the magnitude relationship between the resistance values of the first and second variable resistance elements is 10. The nonvolatile latch according to claim 9, wherein the non-volatile latch has a magnitude relationship corresponding to each output signal of the first and second inverters.   The first and second switches are field effect transistors, and are higher than a power supply voltage for the volatile latch unit when storing data stored in the volatile latch unit in the nonvolatile storage unit The nonvolatile latch according to claim 10, wherein the first switch and the second switch are turned on by a gate voltage.   When performing a recall to read data from the nonvolatile storage unit and write to the volatile latch unit, the slave latch unit is cut off from the master latch unit by the clock being the second logical value, The first and second switches are turned on, the third switch is turned on, and the power supply voltage for the volatile flip-flop is raised, so that the output signals of the first and second inverters are high and low. 12. The nonvolatile latch according to claim 9, wherein the relationship is a height relationship corresponding to a magnitude relationship between the resistance values of the first and second variable resistance elements. The first and second switches are field effect transistors;
The nonvolatile memory according to claim 12, wherein when the recall is performed, the first and second switches are turned on by a gate voltage lower than a high-potential side power supply voltage of the volatile latch unit. latch.   14. The nonvolatile latch according to claim 13, wherein when the recall is performed, a bias voltage having an offset with respect to a low-potential side power supply voltage of the volatile latch unit is supplied to the reference node. .   The power supply voltage supply system for the volatile latch unit is independent of the power supply voltage supply system for other circuits, and the power supply voltage supply to the volatile latch unit is independent of the supply / cutoff of the power supply voltage to other circuits. The nonvolatile latch according to claim 13, wherein the nonvolatile latch is configured to perform supply / cutoff. A volatile flip-flop unit composed of a master latch unit and a slave latch unit;
A non-volatile storage unit,
The slave latch unit includes first and second inverters each having an output signal of each other as an input signal for each other. The slave latch unit receives the input data from the master latch unit in synchronization with a clock and the input data acquired The operation held by the first and second inverters is performed,
The nonvolatile memory section includes a first switch and a first variable resistance element inserted in series between an output node of the first inverter and a common node, and an output node of the second inverter A second switch and a second variable resistance element inserted in series between the common node and the common node, and bias setting means for applying a bias voltage to the common node,
In the first and second variable resistance elements, the first and second switches are turned on, and the output node of the first inverter passes through the common node to the output node of the second inverter. When a flowing current flows, a resistance value of the first resistance variable element is in a first direction, and a resistance value of the second resistance variable element is a second direction opposite to the first direction. And when a current flows from the output node of the second inverter to the output node of the first inverter through the common node, the resistance value of the first resistance variable element becomes the first value. 2. A nonvolatile flip-flop, wherein the resistance change element is a resistance change element in which a resistance value of the second resistance change element changes in the first direction.   The bias setting unit applies a bias voltage that is ½ of a power supply voltage to the common node when performing a store for writing data from the slave latch unit to the nonvolatile storage unit. The non-volatile flip-flop as described. The slave latch unit captures input data from the master latch unit when the clock has a first logic value, and the first and second inverters cause the master latch to operate when the clock has a second logic value. The input data that is cut off from the master latch unit and taken in from the master latch unit is held,
When performing a store for writing data from the slave latch unit to the non-volatile storage unit, the slave latch unit is disconnected from the master latch unit by setting the clock to the second logical value, and the first latch When the second switch is turned ON, the magnitude relationship between the resistance values of the first and second variable resistance elements becomes a magnitude relationship corresponding to the output signals of the first and second inverters. The nonvolatile flip-flop according to claim 16 or 17, The first and second switches are field effect transistors;
The said 1st and 2nd switch is turned ON by the gate voltage higher than the high potential side power supply voltage of the said volatile flip-flop part when performing the said store, The Claim 17 or 18 characterized by the above-mentioned. The non-volatile flip-flop as described. The slave latch unit captures input data from the master latch unit when the clock has a first logic value, and the first and second inverters cause the master latch to operate when the clock has a second logic value. The input data that is cut off from the master latch unit and taken in from the master latch unit is held,
When performing a recall to read data from the nonvolatile storage unit and write to the slave latch unit, the slave latch unit is cut off from the master latch unit by the clock being the second logical value, When the first and second switches are turned on and the power supply voltage for the volatile flip-flop unit is raised, the level relationship between the output signals of the first and second inverters is changed between the first and second outputs. 20. The nonvolatile flip-flop according to claim 16, wherein the nonvolatile flip-flop has a height relationship corresponding to a magnitude relationship of resistance values of the variable resistance element. The first and second switches are field effect transistors;
When performing the recall, the first and second switches are turned on by a gate voltage lower than the high-potential-side power supply voltage of the volatile flip-flop section after the power-supply voltage of the volatile flip-flop section rises. 21. The nonvolatile flip-flop according to claim 20, wherein: The first and second switches are field effect transistors;
21. When performing the recall, the bias setting means supplies a bias voltage having an offset with respect to a low-potential side power supply voltage of the volatile flip-flop unit to the node. Non-volatile flip-flop as described in.   A power supply voltage supply system for the volatile flip-flop unit is provided independently of a power supply voltage supply system for other circuits, and the volatile flip-flop is independent of supply / cutoff of the power supply voltage to other circuits. The nonvolatile flip-flop according to any one of claims 16 to 22, wherein the nonvolatile flip-flop is configured to supply / shut off a power supply voltage to the buffer unit. A volatile latch unit and a nonvolatile storage unit;
The volatile latch unit includes first and second inverters each having an output signal of a counterpart as an input signal for each other, and takes in input data when the clock becomes a first logic value, and the clock receives a second Shutting off the first and second inverters from the input data source by becoming a logical value;
The nonvolatile memory section includes a first switch and a first variable resistance element inserted in series between an output node of the first inverter and a common node, and an output node of the second inverter A second switch and a second variable resistance element inserted in series between the common node and the common node, and bias setting means for applying a bias voltage to the common node,
In the first and second variable resistance elements, the first and second switches are turned on, and the output node of the first inverter passes through the common node to the output node of the second inverter. When a flowing current flows, a resistance value of the first resistance variable element is in a first direction, and a resistance value of the second resistance variable element is a second direction opposite to the first direction. And when a current flows from the output node of the second inverter to the output node of the first inverter through the common node, the resistance value of the first resistance variable element becomes the first value. The nonvolatile latch is a resistance variable element in which a resistance value of the second resistance variable element changes in each direction in the first direction.   25. The nonvolatile latch according to claim 24, wherein the bias setting unit applies a bias voltage that is ½ of a power supply voltage to the common node.   When performing a store for writing the data stored in the volatile latch unit to the non-volatile storage unit, the first and second inverters are connected to the input data by setting the clock to the second logical value. And the first and second switches are turned on, so that the magnitude relationship between the resistance values of the first and second variable resistance elements is the same as that of the first and second inverters. 26. The nonvolatile latch according to claim 24 or 25, which has a magnitude relationship corresponding to each output signal.   The first and second switches are field effect transistors, and are higher than a power supply voltage for the volatile latch unit when storing data stored in the volatile latch unit in the nonvolatile storage unit 27. The nonvolatile latch according to claim 25 or 26, wherein the first and second switches are turned on by a gate voltage.   When performing a recall to read data from the nonvolatile storage unit and write to the volatile latch unit, the slave latch unit is cut off from the master latch unit by the clock being the second logical value, When the first and second switches are turned on and the power supply voltage for the volatile flip-flop is raised, the level relationship between the output signals of the first and second inverters is changed to the first and second. The nonvolatile latch according to any one of claims 24 to 27, wherein the non-volatile latch has a height relationship corresponding to a magnitude relationship of resistance values of the variable resistance element. The first and second switches are field effect transistors;
The nonvolatile memory according to claim 28, wherein when the recall is performed, the first and second switches are turned on by a gate voltage lower than a high-potential side power supply voltage of the volatile latch unit. latch.   29. When performing the recall, the bias setting means supplies a bias voltage having an offset to the low-potential side power supply voltage of the volatile latch unit to the common node. A non-volatile latch according to 1.   The power supply voltage supply system for the volatile latch unit is independent of the power supply voltage supply system for other circuits, and the power supply voltage supply to the volatile latch unit is independent of the supply / cutoff of the power supply voltage to other circuits. The nonvolatile latch according to claim 28, wherein the nonvolatile latch is configured to supply / shut down.   A plurality of nonvolatile flip-flops according to any one of claims 1 to 8 and 16 to 23 are provided, a common clock is given to each nonvolatile flip-flop, and the preceding nonvolatile flip-flop Each non-volatile flip-flop is connected so that output data is given as input data to a subsequent non-volatile flip-flop, and the first and second switches of each volatile flip-flop are switched uniformly. A shift register characterized by.   A plurality of the nonvolatile flip-flops according to any one of claims 1 to 8 and 16 to 23 or a nonvolatile latch according to any one of claims 9 to 15 and 24 to 31 are provided, A common clock is applied to the plurality of nonvolatile flip-flops or the plurality of nonvolatile latches, and the first and second switches of the plurality of nonvolatile flip-flops or the plurality of nonvolatile latches are switched uniformly. A register characterized by that.   A counter using the nonvolatile flip-flop according to any one of claims 1 to 8 and 16 to 23 as means for storing a count value.

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