JP2010232959A - Electronic circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To nonvolatilely set the current drive capability of a field-effect transistor. <P>SOLUTION: The electronic circuit includes the field-effect transistor 40, and a resistance change element Re connected at one end to the source S of the field-effect transistor 40 and for nonvolatilely setting a resistance value. In the electronic circuit wherein the resistance change element Re nonvolatilely stores data stored in a bistable circuit corresponding to the resistance value and restores the stored data in the bistable circuit for instance, the bistable circuit and the resistance change element are prevented from affecting each other. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an electronic circuit, and more particularly to an electronic circuit capable of setting a current driving capability.

  As a volatile memory circuit used for electronic devices and the like, an SRAM (Static Random Access Memory), a latch circuit, a flop-flop, and the like are known. In addition, as a nonvolatile memory circuit in which data is not lost even when the power is turned off, flash memory, MRAM (Magnetic Random Access Memory), FeRAM (Ferroelectric Random Access Memory), PRAM (Phase-change Random Access Memory) and PRAM (Phase-Random Access Memory) Resistance Random Access Memory) and the like are known. In these memory circuits, data is not lost even when the power is turned off, so that data can be read out after the power is restored.

  Patent Documents 1 and 2 disclose a ReRAM that stores data in a resistance change element. Further, Patent Document 3 discloses a memory circuit in which a variable resistance element is connected to a memory node of a bistable circuit.

Applied Physics Letters 93, 033506 (2008) IEEE Transaction on Electron Devices, 55, 1185 (2008) IEEE IEDM Tech. Dig., Dec. 2006, pp. 1-4

  The volatile SRAM, the latch circuit, and the flip-flop can write and read data at high speed. On the other hand, flash memory, MRAM, FeRAM, PRAM, ReRAM, and the like are slow in writing and reading data. As described above, although the SRAM is high-speed, data is lost when the power is turned off. On the other hand, the conventional nonvolatile memory does not lose data even when the power is cut off, but high speed operation is difficult.

  The SRAM, the latch circuit, and the flip-flop consume power due to the leakage current even in a memory holding state (standby state) where data access is not performed. If a nonvolatile SRAM, a latch circuit, and a flip-flop can be realized, it is possible to reduce both standby power consumption and high-speed data writing and reading operations.

  However, in the invention according to Non-Patent Document 3, the bistable circuit and the low resistance element affect each other.

  The present invention has been made in view of the above problems, and an object thereof is to provide an electronic circuit capable of suppressing the influence of a bistable circuit and a low resistance element on each other. Alternatively, for example, in order to realize such an electronic circuit, an object is to provide an electronic circuit in which current drive capability can be set in a nonvolatile manner.

  The present invention is an electronic circuit comprising a field effect transistor and a variable resistance element having one end connected to the source of the field effect transistor and capable of setting a resistance value in a nonvolatile manner. According to the present invention, the current drive capability can be set in a nonvolatile manner.

  In the above configuration, a bistable circuit for storing data is provided, the drain of the field effect transistor is connected to at least one of mutually complementary nodes in the bistable circuit, and the other end of the variable resistance element is controlled. The variable resistance element may be connected to a line and store the data in a nonvolatile manner according to the resistance value and restore the stored data to the bistable circuit. According to this configuration, the resistance change element stores the data stored in the bistable circuit in a nonvolatile manner. Therefore, an electronic circuit that can operate at high speed and can store data in a nonvolatile manner can be provided. Furthermore, the field effect transistor can suppress the bistable circuit and the resistance change element from affecting each other.

  In the above configuration, the field effect transistor is configured such that a current flowing through the variable resistance element is smaller than when erasing data stored in the variable resistance element when storing data in the bistable circuit. The current flowing through the variable resistance element can be controlled. According to this configuration, the current flowing through the resistance change element at the time of store and reset can be controlled by the field effect transistor.

  In the above configuration, the field effect transistor is turned on when data is stored from the bistable circuit to the variable resistance element and when data is restored from the variable resistance element to the bistable circuit. When data is input / output from the input / output line, it can be configured to be non-conductive. According to this configuration, it is possible to suppress the variable resistance element from affecting the input / output of data to the bistable circuit.

  In the above configuration, when storing data from the bistable circuit to the variable resistance element, a voltage higher than the high level voltage of the node is applied to the control line, and data is transferred from the variable resistance element to the bistable circuit. When restoring, a voltage lower than a power supply voltage applied to the bistable circuit can be applied to the control line.

  In the above configuration, when erasing data stored in the variable resistance element, a voltage higher than a low level voltage of the node may be applied to the control line.

  In the above configuration, the resistance value of the variable resistance element is set according to the voltage applied to the gate of the field effect transistor when storing data from the bistable circuit to the variable resistance element. Can do.

  In the above configuration, the node includes a first node and a second node that are complementary to each other, and the variable resistance element includes a first variable resistance element connected between the first node and the control line; A second variable resistance element connected between the second node and the control line may be included.

  In the above configuration, the first variable resistance element is set to have a higher resistance value than the second variable resistance element when the first node stores high level data, and the first node stores low level data. When storing, the resistance value may be set lower than that of the second variable resistance element.

  In the above configuration, a fixed resistor connected between another node complementary to the node in the bistable circuit and the control line may be provided.

  In the above configuration, when the node stores high level data, the variable resistance element is set to be higher than the resistance value of the fixed resistance, and when the node stores low level data, the resistance change element It can be set as the structure set lower than a value.

  In the above configuration, a first switch for writing the data to the bistable circuit and a second switch that operates complementarily to the first switch and holds the data of the bistable circuit are provided. be able to.

  In the above configuration, the bistable circuit is connected to a first circuit group having one or more inputs and one or more outputs and a second circuit group having one or more inputs and one or more outputs, The node is a node in which one of the outputs of the first circuit group and one of the inputs of the second circuit group are connected, or one of the outputs of the second circuit group and the first circuit group. It is possible to adopt a configuration in which one of the inputs is connected to a node.

  In the above configuration, in the bistable circuit, a first circuit group that is an inverter and a second circuit group that is an inverter are connected in a ring shape, and the node includes the first circuit group and the second circuit group. Can be configured as a node to which and are connected.

  In the above configuration, the current driving capability of the field effect transistor can be set in a nonvolatile manner by the resistance value.

  In the above configuration, the current driving capability of the field effect transistor can be changed by a negative feedback effect and a substrate bias effect by the variable resistance element.

  In the above configuration, the field effect transistor is configured to adjust the resistance value in a variable manner by controlling the current flowing through the variable resistance element, and to set the current driving capability of the field effect transistor in a nonvolatile manner based on the resistance value. It can be.

  In the above configuration, the bias applied between the source and the drain of the field effect transistor is opposite when the resistance value of the variable resistance element is set and when the field effect transistor operates. It can be.

  According to the present invention, input / output of data to / from the bistable circuit can be performed at high speed. In addition, data can be stored in a nonvolatile manner. Alternatively, the current drive capability of the field effect transistor can be set in a nonvolatile manner.

FIG. 1 is a circuit diagram of a functional MOSFET in which a variable resistance element is connected to the source side of an FET. FIG. 2A to FIG. 2D are diagrams for explaining the characteristics of the variable resistance element. FIGS. 3A and 3B are diagrams showing the current ID with respect to the voltage VD in the circuit configuration of FIG. FIG. 4 is a block diagram of the memory circuit according to the first embodiment. FIG. 5 is a circuit diagram of the SRAM memory cell according to the second embodiment. FIG. 6 is a timing chart (No. 1) of the SRAM memory cell according to the second embodiment. FIG. 7 is a second timing chart of the SRAM memory cell according to the second embodiment. FIG. 8 is a circuit diagram of the SRAM memory cell according to the third embodiment. FIG. 9 is a circuit diagram of a latch circuit according to the fourth embodiment. FIG. 10 is a circuit diagram of a master-slave flip-flop according to the fifth embodiment. FIG. 11 is a circuit diagram of a flip-flop according to the sixth embodiment. FIG. 12 is a circuit diagram (part 1) of the SR latch circuit according to the seventh embodiment. FIG. 13 is a circuit diagram (part 2) of the SR latch circuit according to the seventh embodiment. FIG. 14 is a circuit diagram of a circuit according to the eighth embodiment. FIG. 15 is a circuit diagram (No. 1) of the JK flip-flop according to the ninth embodiment. FIG. 16 is a circuit diagram of the JK flip-flop according to Embodiment 9 (No. 2). FIG. 17 is a block diagram of an electronic device according to a tenth embodiment. FIG. 18 is a block diagram of the power domain.

  First, the characteristics of the variable resistance element used in the present invention will be described. FIG. 1 is a circuit diagram of a functional MOSFET in which a resistance change element is connected to the source side of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). Referring to FIG. 1, the functional MOSFET 45 includes a FET 40 such as a MOSFET and a resistance change element Re. One end of the variable resistance element Re is connected to the source S of the FET 40. The drain D of the FET 40 is connected to the third terminal T3, and the gate G is connected to the second terminal T2. The other end of the variable resistance element Re is connected to the first terminal T1.

  The FET 40 has a silicon substrate (not shown), a gate oxide film, a gate electrode, a source and a drain. In the case of an n-type MOSFET, a gate electrode is provided on a p-type well in a silicon substrate via a gate oxide film. A source and drain which are n-type diffusion regions are provided in the silicon substrate on both sides of the gate electrode. Thus, although an n-type MOSFET will be described below as an example, the MOSFET 20 may be a p-type MOSFET. The characteristics of the variable resistance element Re will be described later. As the variable resistance element Re, for example, a nonpolar variable resistance element using a nickel oxide (NiO) thin film can be used.

The voltage applied to the third terminal T3 with respect to the first terminal T1 is the pseudo drain-source voltage VD, the current flowing from the third terminal T3 to the first terminal T1 is the drain current ID, and the second terminal T2 with respect to the first terminal T1. The applied voltage is a pseudo gate-source voltage VG. A voltage applied to the second terminal T2 with respect to the source S of the FET 40 is _referred to as a gate-source voltage _VGS0 . A voltage applied to the substrate with respect to the source S of the FET is _defined as a substrate voltage _VBS0 .

In the function MOSFET 45, the voltage drop is negatively fed back to the gate G by the variable resistance element Re. Therefore, depending on the state of resistance of the variable resistance element Re (high resistance or low resistance), the gate of FET 40 - can be varied source voltage _{V GS0} and substrate voltage _{V BS0.} When the resistance value of the variable resistance element Re is low, the voltage drop due to the variable resistance element Re is small, so that the gate-source voltage _VGS0 is large and the substrate voltage _VBS0 is small. Therefore, the current driving capability of the functional MOSFET 45 is increased. On the other hand, when the resistance value of the variable resistance element Re is high, the voltage drop due to the variable resistance element Re is large, so that the gate-source voltage _VGS0 is small and the substrate voltage _VBS0 is large. Therefore, the current driving capability of the functional MOSFET 45 is lowered. As described above, when the function MOSFET 45 is used, the current driving capability of the FET 40 can be changed by the negative feedback effect and the substrate bias effect by the resistance change element Re according to the state of the resistance change element Re.

  Next, the characteristics of the variable resistance element Re will be described. FIG. 2A is a circuit diagram for explaining the characteristics of the variable resistance element Re. As shown in FIG. 2A, the source S of the FET 40 is grounded, and the gate voltage VG 1 is applied to the gate G. A drain voltage VD1 is applied to the drain D via the resistance change element Re. A current ID1 flows through the resistance change element Re. The FET 40 has a function of limiting the current ID1 flowing through the variable resistance element Re.

  FIG. 2B is a diagram illustrating the voltage VD1-current ID1 characteristics when the resistance of the variable resistance element Re is changed. Here, lowering the resistance value of the variable resistance element Re is referred to as setting, and increasing the resistance value is referred to as resetting. The variable resistance element Re is set by applying a voltage of a certain level or higher to both ends of the variable resistance element Re. At this time, the gate voltage VG1 of the FET 40 is applied so that a current ID1 exceeding a certain value does not flow through the variable resistance element Re. In FIG. 2B, by setting the gate voltage VG1 = 0.7V and applying the voltage VD1, the resistance value of the resistance change element Re becomes low.

  On the other hand, the variable resistance element Re is reset by holding the variable resistance element Re above a certain temperature. Therefore, the resistance change element Re is reset by passing a current ID1 of a certain value or more to the resistance change element Re. At this time, the gate voltage VG1 of the FET 40 is applied so that the current ID1 flowing through the variable resistance element Re is not limited. In FIG. 2B, the resistance value of the variable resistance element Re is increased by setting the gate voltage VG1 = 2V and applying the voltage VD1. As described above, the resistance change element Re can be set or reset by controlling the gate voltage VG1 of the FET 40 and applying the voltage VD1.

FIG. 2C is a diagram illustrating a resistance value R _LRS after setting with respect to the limited current I _comp that is limited when the variable resistance element Re is set. The limiting current I _comp is set by the gate voltage VG1 of the FET 40. In FIG. 2C, the resistance value R _HRS is the resistance value after reset, and the resistance value R _LRS0 is the lowest resistance value. As shown in FIG. 2C, the resistance change element Re can set the resistance value R _LRS of the resistance change element Re after setting to an arbitrary value by the current ID1 limited when the resistance change element is set.

FIG. 2D is a diagram illustrating a reset current I _reset that resets the variable resistance element Re with respect to the limit current I _comp . As shown in FIG. 2D, the limit current I _comp and the reset current I _reset are substantially the same value.

  FIGS. 3A and 3B are diagrams showing the current ID with respect to the voltage VD in the circuit configuration of FIG. In FIG. 3A, the first quadrant corresponds to the case where the resistance change element Re is connected to the drain D side of the FET 40 as shown in FIG. 1 (that is, when it functions as a functional MOSFET), and the gate voltage VG changes. The voltage VD-current ID characteristic at the time of making it show is shown. The gate voltage VG is applied in a 0.3V step from 0V to 1.5V. The third quadrant corresponds to the case where the variable resistance element Re is connected to the source S side of the FET as shown in FIG. 2A, and the voltage VD-current ID characteristic when the variable resistance element Re is set and reset. Is shown. In FIG. 3A, the solid line shows the case where the gate voltage VG = 1.5V is set, and the broken line shows the case where the gate voltage = 0.7V. As shown in FIG. 3A, when the gate voltage VG = 1.5V is set, the resistance value of the variable resistance element Re is low, so that the mutual conductance in the first quadrant increases (that is, the current drive capability increases). When the gate voltage VG is set at 0.7V, the mutual conductance in the first quadrant is reduced (that is, the current driving capability is reduced). As described above, the current driving capability can be modulated by the limiting current when the variable resistance element Re is set.

  FIG. 3B shows the voltage VD-current ID characteristics when the variable resistance element Re is connected to the drain D side of the FET 40 as shown in FIG. A solid line indicates a case where the resistance change element Re is set, and a broken line indicates a case where the resistance change element Re is a reset state. The current ID in the reset state is enlarged 50 times. The gate voltage VG is applied in a 0.3V step from 0V to 1.5V. When the variable resistance element Re is in the reset state, the resistance value becomes very high, so that the current driving capability of the functional MOSFET 45 in the reset state becomes very small.

  In the functional MOSFET 45, one end of the variable resistance element Re whose resistance value can be set in a nonvolatile manner is connected to the source of the FET 40 (field effect transistor). Thus, the functional MOSFET 45 current drive capability is set in a non-volatile manner as shown in FIGS. 3A and 3B by the resistance value of the variable resistance element Re. In other words, the FET 40 can adjust the resistance value in a variable manner by controlling the current flowing through the variable resistance element Re, and can set the current driving capability of the FET 40 in a nonvolatile manner by the resistance value.

  In addition, when the FET 40 operates as in the first quadrant of FIG. 3A, the other end of the variable resistance element Re (first terminal T1 in FIG. 1) and the FET 40 are reversed so that the source and drain are inverted. By applying a voltage to the drain (the third terminal in FIG. 1), the resistance value is set in a nonvolatile manner. In other words, the bias applied between the source S and the drain D of the FET 40 is opposite when the resistance value of the variable resistance element Re is set and when the FET 40 operates. Thus, the source and the drain can be used interchangeably when setting the resistance value of the variable resistance element Re in a nonvolatile manner and when operating as the functional MOSFET 45.

  As described above, in the functional MOSFET 45, as shown in FIG. 3B, data can be stored in the resistance change element Re in a nonvolatile manner depending on whether the resistance change element Re is in the set state or the reset state. Further, as shown in FIG. 3A, data can be stored in the resistance change element Re in a nonvolatile manner by the resistance value in the set state of the resistance change element Re.

  FIG. 4 is a block diagram of the memory circuit according to the first embodiment. The memory circuit according to the first embodiment includes a first circuit group 10, a second circuit group 20, an FET 40, a resistance change element Re, and an input / output switch 38. The first circuit group 10 and the second circuit group 20 are connected in a ring shape to form a bistable circuit 30. The first circuit group 10 and the second circuit group 20 are, for example, inverters. Nodes to which the first circuit group 10 and the second circuit group 20 are connected are storage nodes Q and QB, respectively. The node Q and the node QB are complementary nodes, and the bistable circuit 30 has the node Q and the node QB at the high level and the low level, respectively, or the node Q and the node QB at the low level and the high level, respectively. It will be in a stable state. The bistable circuit 30 can store data when it is in a stable state.

  The resistance change element Re is connected between at least one of the complementary node Q and the node QB and the control line CTRL, and as described above, the resistance value is high or low, that is, the data is nonvolatile depending on the resistance value. To store. The data stored in the resistance change element Re in a nonvolatile manner can be restored to the bistable circuit 30. The FET 40 is connected between the variable resistance element Re and at least one of the node Q and the node QB. The FET 40 and the resistance change element Re form the same functional MOSFET as in FIG. By operating the FET 40 as shown in FIG. 2B, the variable resistance element Re can be set or reset. Further, the FET 40 operates as in the third quadrant of FIG. 3A, so that the resistance value of the variable resistance element Re can be set in a nonvolatile manner.

  The input / output switch 60 cuts off or conducts the input / output line DIN and the node Q. When the input / output switch 60 is turned on, the data of the input / output line DIN can be written to the bistable circuit 30. Further, the data of the bistable circuit 30 can be read out to the input / output line DIN.

  According to the first embodiment, data can be written to and read from the bistable circuit 30 at a high speed as in a circuit without the resistance change element Re. The resistance change element Re stores the data stored in the bistable circuit 30 in a nonvolatile manner. As a result, the data of the resistance change element Re is not lost even when the power is cut off. Thereafter, the data stored in a nonvolatile manner can be restored to the bistable circuit 30. Therefore, even if the power is turned off after the power is turned off, the data stored before the power is turned off can be read. Further, the FET 40 can prevent the bistable circuit 30 and the resistance change element Re from affecting each other. Note that at least one FET 40, variable resistance element Re, and input / output switch 38 may be provided.

  Example 2 is an example in which a resistance change element is provided in an SRAM memory cell. FIG. 5 is a circuit diagram of an SRAM memory cell according to the second embodiment. As shown in FIG. 5, the memory cell includes a bistable circuit 30a, variable resistance elements Re1 and Re2, FETs 41 and 42, and input / output FETs 43 and 44. In the bistable circuit 30a, the first circuit group 10a and the second circuit group 20a are connected in a ring shape. The first circuit group 10 a is a CMOS inverter having a p-type MOSFET 12 and an n-type MOSFET 14. In FET12 and FET14, the source is connected to the power supply VDD and the ground, the gate is commonly connected to the node Q, and the drain is commonly connected to the node QB. The second circuit group 20 a is a COS inverter having a p-type MOSFET 22 and an n-type MOSFET 24. In the FETs 22 and 24, the sources are connected to the power supply VDD and the ground, the gates are commonly connected to the node QB, and the drains are commonly connected to the node Q.

  Node Q is connected to data input / output line DIN via n-type FET 43, and node QB is connected to data input / output line DINB via n-type FET 44. The gates of the FETs 43 and 44 are connected to the word line WL. The FET 41 and the variable resistance element Re1 are connected between the node Q and the control line CTRL, and the FET 42 and the variable resistance element Re2 are connected between the node QB and the control line CTRL. The gates of the FETs 41 and 42 are connected to the switch line SR. The FET 41 and the variable resistance element Re1 constitute a functional MOSFET 46, and the FET 42 and the variable resistance element Re2 constitute a functional MOSFET 47.

  The operation of the SRAM memory cell according to the second embodiment will be described. Data is written to and read from the bistable circuit 30a in the same manner as a conventional SRAM. That is, the data of the input / output lines DIN and DINB are written to the bistable circuit 30a by setting the word line WL to the high level and turning on the FETs 43 and 44. Further, the data of the bistable circuit 30a can be read out to the input / output lines DIN and DINB by setting the input / output lines DIN and DINB to the equipotential floating state, the word line WL to the high level, and the FETs 43 and 44 to be in the conductive state. it can. By turning off the FETs 43 and 44, the data of the bistable circuit 30a is held. Note that when writing, reading, and holding data in the bistable circuit 30a, the switch line SR is preferably at a low level, and the FETs 41 and 42 are preferably cut off. Thereby, the current between the nodes Q and QB and the control line CTRL can be suppressed, and the power consumption can be reduced.

  Next, a method for storing data stored in the bistable circuit 30a in the resistance change elements Re1 and Re2 in a nonvolatile manner will be described. The characteristics of the variable resistance elements Re1 and Re2 as shown in FIG. 2B to FIG. 2D were used as SPICE simulator parameters, and the operation of the circuit of FIG. 5 was calculated. FIG. 6 shows the calculated power supply voltage VDD, voltage WL of word line WL, voltages DIN and DINB of input / output lines DIN and DINB, voltage SR of switch line SR, voltage CTRL of control line CTRL, voltage Q of node Q, node The time change of the voltage QB of QB, the resistance value Re1 of the resistance change element Re1, and the resistance value Re2 of the resistance change element Re2 is shown.

  Referring to FIG. 6, in an initial state, word line WL, input / output lines DIN and DINB, switch line SR, and control line CTRL are at a low level (0 V). The power supply VDD is at a high level (1.2 V). Node Q is at a high level (1.2V), and node QB is at a low level (0V). The resistance values Re1 and Re2 are both high resistance (150 kΩ). In the SRAM mode, a high level (1.2 V) is applied to the word line WL at time t1 while a high level (1.2 V) is applied to the input / output line DIN. As a result, the node Q becomes high level and the node QB becomes low level. Thus, in the SRAM mode in which the FETs 41 and 42 are non-conductive, normal SRAM operation is performed.

  In the set operation, 0.45 V is applied to the switch line SR at time t2. The voltage SR at this time is a voltage at which a current flows to such an extent that the resistance change elements Re1 and Re2 are not reset in FIG. Further, the voltage SR is set so as to have a desired resistance value in FIG. Thereafter, 1.8 V is applied to the control line CTRL. The voltage at this time is set to be a voltage at which the variable resistance element Re1 or Re2 between the low level voltage of the nodes Q and QB and the control line CTRL is set. Thereafter, the variable resistance element Re1 or Re2 (Re2 in FIG. 6) connected to the lower level node (node QB in FIG. 6) of the nodes Q and QB is set. As a result, the resistance value of the variable resistance element Re1 or Re2 (Re2 in FIG. 6) becomes a low resistance (32.2 kΩ). Thereafter, the switch line SR and the control line CTRL are set to the low level.

  At time t3, the power supply VDD is set to 0V and the power is turned off. Node Q or node QB is discharged, and the data stored in the SRAM memory cell is lost. The resistance values of the resistance change elements Re1 and Re2 are maintained even when the power is turned off. In this way, the store operation is performed.

  Next, a method for restoring the data stored in the resistance change elements Re1 and Re2 in a nonvolatile manner to the bistable circuit 30a will be described. FIG. 7 shows the calculated power supply voltage VDD, voltage WL of word line WL, voltages DIN and DINB of input / output lines DIN and DINB, voltage SR of switch line SR, voltage CTRL of control line CTRL, voltage Q of node Q, node The time change of the voltage QB of QB, the resistance value Re1 of the resistance change element Re1, and the resistance value Re2 of the resistance change element Re2 is shown.

  Referring to FIG. 7, the restore operation is performed in the power-off state of FIG. In the initial state, the nodes Q and QB are both at a low level, the resistance change element Re1 has a high resistance (150 kΩ), and the resistance change element Re2 has a low resistance (32.2 kΩ). Between time t4 and t5, the power supply VDD is set to the high level (1.2V). From time t4 to time t5, the switch line SR is set to the high level in a spike shape. The voltages at the nodes Q and QB tend to increase as the power supply voltage VDD increases. However, since the resistance value of the resistance change element Re2 is small, the charge of the node QB is discharged to the control line CTRL more than the node Q. Therefore, the voltage of the node QB is lower than the node Q. Thus, when an imbalance occurs in the voltage between the node Q and the node QB, the bistable circuit 30a is stabilized so that the node Q is at a high level and the node QB is at a low level. As described above, the data stored in the resistance change elements Re1 and Re2 in a nonvolatile manner can be restored to the bistable circuit 30a. Note that the voltage SR of the switch line SR may be applied with a pulse voltage so as to be a desired voltage between time t4 and time t5.

  Next, a reset operation for erasing data of the resistance change elements Re1 and Re2 will be described. At time t6, 1.2V is applied to the switch line SR and 1.2V to the control line CTRL. The voltage SR of the switch line SR is set such that a sufficient current for resetting flows through the resistance change elements Re1 and Re2, as with the gate voltage VG in FIG. Further, the voltage of the control line CTRL is set such that a sufficient voltage for resetting is applied to the resistance change elements Re1 and Re2, as the drain voltage VD in FIG. Thereby, the resistance change elements Re1 and Re2 are reset to have a high resistance (150 kΩ). At time t7, a low level (0 V) is applied to the switch line SR and the control line CTRL. Thus, the data restore operation is completed. The reset operation may be performed before the store operation.

  In the SRAM mode, with the high level (1.2 V) applied to the input / output line DINB, the high level (1.2 V) is applied to the word line WL at time t8. As a result, the node Q becomes low level and the node QB becomes high level. As described above, new data can be written to the bistable circuit 30a.

  According to the second embodiment, the resistance change element Re1 (first resistance change element) is connected between the node Q (first node) and the control line CTRL, and the node QB (second node) and the control line CTRL are connected to each other. A resistance change element Re2 (second resistance change element) is connected therebetween. Thus, the data of the bistable circuit 30a can be stored in a nonvolatile manner using the two variable resistance elements Re1 and Re2.

  As shown in FIG. 6, the resistance change element Re1 is set to have a higher resistance value than the resistance change element Re2 when the node Q stores high level data. When the node Q stores low level data, the resistance value is set lower than that of the resistance change element Re2. Thus, at the time of restoration, when the resistance value of the resistance change element Re1 is higher than the resistance change element Re2, the node Q is set to a high level, and when the resistance value of the resistance change element Re1 is lower than the resistance change element Re2, Q can be set to a low level.

  Further, as shown in FIG. 6, when storing, the resistance value of the variable resistance element Re1 or Re2 varies (for example, 150 kΩ or 32) depending on the level of the node Q or QB (for example, high level or low level). .2 kΩ) to be set (for example, 1.8 V) is applied to the control line CTRL. For example, a voltage higher than the high level voltage of the node Q or QB is applied to the control line CTRL. As a result, the control line CTRL has a higher voltage than the nodes Q and QB, and the resistance change element Re1 or Re2 can be set according to the levels of the nodes Q and QB as in the third quadrant of FIG. . Therefore, the data of the bistable circuit 30a can be stored in the resistance change elements Re1 and Re2.

  Further, as shown in FIG. 7, when restoring, the level of the node Q or QB (for example, high level or low level) depends on the resistance value of the variable resistance element Re1 or Re2 (for example, 150 kΩ or 32.2 kΩ). A voltage to be set (for example, 1.2 V) is applied to the control line CTRL. For example, a voltage lower than the power supply voltage VDD applied to the bistable circuit 30a is applied to the control line CTRL. As a result, as in the first quadrant of FIG. 3, the current drivability of the functional MOSFETs 46 and 47 differs depending on the resistance values of the variable resistance elements Re1 and Re2. In this state, different amounts of charge can be discharged from the nodes Q and QB to the control line CTRL. Therefore, data can be restored to the bistable circuit 30a according to the resistance values of the resistance change elements Re1 and Re2.

  Further, as shown in FIG. 7, when resetting, a voltage (for example, 1.2 V) that is not set but the resistance change elements Re1 and Re2 are reset is applied to the control line CTRL. For example, a voltage higher than the low level voltage of the node Q or QB but lower than the voltage applied during the store operation is applied to the control line CTRL. Thereby, the voltage of the control line CTRL is higher than the low level of the nodes Q and QB, and the variable resistance element Re1 or Re2 can be reset as in the third quadrant of FIG. Therefore, the resistance change elements Re1 and Re2 can be reset.

  Further, as shown in FIGS. 6 and 7, the FETs 41 and 42 are connected between the nodes Q and QB and the resistance change elements Re1 and Re2, respectively, and conduct when storing, restoring and resetting, and the bistable circuit 30a. It functions as a switch that becomes non-conductive when data is input / output. Thereby, nodes Q and QB and resistance change elements Re1 and Re2 are connected during the store, restore and reset operations. On the other hand, when inputting / outputting data to / from the bistable circuit 30a, it is possible to suppress the resistance change elements Re1 and Re2 from affecting the SRAM operation (data input / output operation to the bistable circuit 30a).

  Further, the FETs 41 and 42 function as a current limiting circuit that limits the current flowing through the resistance change elements Re1 and Re2. The FETs 41 and 42 limit the current more during the store operation than during the reset operation. For example, the voltage SR in the store operation of FIG. 6 is 0.45V, and the voltage SR in the reset operation of FIG. 7 is 1.2V. As described above, the currents flowing through the resistance change elements Re1 and Re2 at the time of storing and resetting can be controlled by the FETs 41 and 42. Thereby, as shown in FIG. 2B, the variable resistance elements Re1 and Re2 can be set and reset.

  Further, as shown in FIG. 3A, the resistance values of the resistance change elements Re1 and Re2 are set according to the voltage SR applied to the gates of the FETs 41 and 42 when data is stored in the resistance change elements Re1 and Re2. . Thus, the resistance value when the resistance change elements Re1 and Re2 are set can be changed by the voltage SR.

  In the second embodiment, the data of the bistable circuit 30a is stored in the variable resistance elements Re1 and Re2 depending on whether the variable resistance elements Re1 and Re2 are set or reset, but FIG. ), The data of the bistable circuit 30a may be stored according to the difference in resistance value between the resistance change elements Re1 and Re2.

  Example 3 is an example in which one resistance change element is used. FIG. 8 is a circuit diagram of a memory cell according to the third embodiment. Referring to FIG. 8, a resistor R2 is connected between node QB and control line CTRL instead of resistance change element Re2 in FIG. The resistor R2 is a fixed resistor, and has a resistance value between a high resistance value and a low resistance value of the variable resistance element Re1. Other configurations are the same as those of the second embodiment shown in FIG. When the node Q is at a high level and the node QB is at a low level, the resistance of the resistance change element Re1 is high in the store operation. Since the resistance value of the resistor R2 is lower than the resistance value of the variable resistance element Re1, the node Q is at a high level and the node QB is at a low level during restoration. When the node Q is at a low level and the node QB is at a high level, the resistance of the variable resistance element Re1 is low during the store operation. Since the resistance value of the resistor R2 is higher than the resistance value of the variable resistance element Re1, the node Q is at a low level and the node QB is at a high level during restoration. As described above, the variable resistance element is connected between one of node Q and node QB and control line CTRL, and the fixed resistor is connected between either node Q or node QB and control line CTRL. Even in this case, the same operation as that of the second embodiment shown in FIGS. 6 and 7 can be performed.

  As in the third embodiment, a fixed resistor R2 may be connected instead of the variable resistance element between another node QB complementary to the node Q in the bistable circuit 30a and the control line CTRL. Even in such a configuration, when the node Q stores high level data, the resistance value of the variable resistance element Re1 is set higher than the resistance value of the fixed resistor R2, and when the node Q stores low level data, It is set lower than the resistance value of the fixed resistor R2. As a result, similarly to the second embodiment, the data stored in the variable resistance element Re1 can be restored to the bistable circuit 30a. Further, the FET 41 can prevent the bistable circuit 30a and the resistance change element Re1 from affecting each other.

  The fourth embodiment is an example of a D latch circuit. FIG. 9 is a circuit diagram of a D latch circuit according to the fourth embodiment. The word line WL and the input / output FETs 43 and 44 in FIG. 5 of the second embodiment are not provided. A pass gate 50 is connected between the node Q and the input / output line DIN. A pass gate 52 is connected between the node Q and the second circuit group 20a. Pass gates 50 and 52 each have a p-type MOSFET 53 and an n-type MOSFET 54. The sources and drains of the FETs 53 and 54 are connected to each other. The complementary clock signal CLKB is input to the gates of the FET 53 of the pass gate 50 and the FET 54 of the pass gate 52. The clock signal CLK is input to the gates of the FET 54 of the pass gate 50 and the FET 53 of the pass gate 52. When a high level is input as the clock signal CLK, both the FETs 53 and 54 of the pass gate 50 are turned on, and the pass gate 50 is turned on. On the other hand, when a low level is input as the clock signal CLK, the FETs 53 and 54 of the pass gate 52 are both turned off and the pass gate 50 is turned off.

  With such a configuration, when the clock signal CLK is at a high level, the pass gate 50 is turned on and the pass gate 52 is cut off. Thereby, the data of the input / output line DIN is written in the bistable circuit 30a. When the clock signal CLK is at a low level, the pass gate 50 is cut off and the pass gate 52 becomes conductive. Thereby, the bistable circuit 30a holds data. Data stored in the bistable circuit 30a can be output from the node Q or QB. Thus, the pass gate 50 functions as a first switch for writing data to the bistable circuit 30a. The pass gate 52 operates in a complementary manner to the pass gate 50 and functions as a second switch that holds data of the bistable circuit 30a. Other configurations are the same as those of the second embodiment shown in FIG. Also in the fourth embodiment, by performing the same operation as in FIGS. 6 and 7 of the second embodiment, the data of the bistable circuit 30a can be stored in the resistance change elements Re1 and Re2 in a nonvolatile manner. Further, the data stored in the resistance change elements Re1 and Re2 can be restored to the bistable circuit 30a. Further, the FETs 41 and 42 can suppress the influence of the bistable circuit 30a and the resistance change elements Re1 and Re2 on each other.

  The fifth embodiment is an example of a master-slave flip-flop circuit in which a plurality of D latch circuits are connected. FIG. 10 is a circuit diagram of a latch circuit according to the fifth embodiment. A D latch circuit 102 is further connected to the D latch circuit 100 of FIG. The node QB of the D latch circuit 102 is input to the pass gate 50 of the latch circuit 100. In the D latch circuits 100 and 102, the clock signal CLK and the clock complementary signal CLKB input to the pass gate are reversed. As described above, the resistance change elements Re1 and Re2 are provided in the D latch circuit 102 in the subsequent stage of the master-slave flip-flop, and data can be stored in a nonvolatile manner. In addition, data can be restored. At the time of storing and restoring data to the resistance change elements Re1 and Re2, the pass gate 50 of the D latch circuit 100 is in a cut-off state. Therefore, the operation of the D latch circuit 102 does not affect data storage and restoration in the D latch circuit 100.

  The sixth embodiment is an example in which a bistable circuit is configured using a logic circuit. FIG. 11 is a circuit diagram of a flip-flop according to the sixth embodiment. Referring to FIG. 11, the bistable circuit 30b is configured by connecting a first circuit group 10b and a second circuit group 20b, which are logic circuits. The first circuit group 10b has one or more inputs A1 to An and one or more outputs (one output is shown in FIG. 11). The second circuit group 20b has one or more inputs B1 to Bm and one or more outputs (one output is shown in FIG. 11). The output of the first circuit group 10b and the input B1 of the second circuit group 20b are connected to the node Q. The output of the second circuit group 20b and the input A1 of the first circuit group 10b are connected to the node QB. The node Q is connected to the control line CTRL via the FET 41 and the resistance change element Re1, and the node QB is connected to the control line CTRL via the FET 42 and the resistance change element Re2.

  When storing the data of the bistable circuit 30b in the resistance change elements Re1 and Re2, complementary data to be stored are output from the first circuit group 10b and the second circuit group 20b to the node Q and the node QB, respectively. When data is restored from the variable resistance elements Re1 and Re2 to the bistable circuit 30b, the first circuit group 10b is connected to the inputs A2 to An of the first circuit group 10b (that is, inputs other than the input A1 connected to the node QB). A signal that outputs the logical inversion of the node QB is input to the node Q. A signal that causes the second circuit group 20b to output the logical inversion of the node Q1 to the node QB is input to the inputs B2 to Bm of the second circuit group 20b (that is, inputs other than the input B1 connected to the node Q). Yes.

  In the sixth embodiment, the bistable circuit 30b includes a first circuit group 10b having one or more inputs and one or more outputs, a second circuit group 20b having one or more inputs and one or more outputs, Are connected and configured. Also in this case, the node Q to which one of the outputs of the first circuit group 10b and one of the inputs of the second circuit group 20b are connected, and one of the outputs of the second circuit group 20b and the first circuit group. The variable resistance elements Re1 and Re2 are connected between at least one of the node QB to which one of the inputs of 10b is connected and the control line CTRL. Then, the same operation as in FIG. 6 and FIG. 7 of the second embodiment is performed. Thereby, the data of the bistable circuit 30b can be stored in the resistance change elements Re1 and Re2 in a nonvolatile manner. Further, the data stored in the resistance change elements Re1 and Re2 can be restored to the bistable circuit 30b. Further, the FETs 41 and 42 can prevent the bistable circuit 30b and the resistance change elements Re1 and Re2 from affecting each other.

  The seventh embodiment is an example of an SR latch circuit as a specific example of the sixth embodiment. FIG. 12 is a circuit diagram of an SR latch circuit according to the seventh embodiment. The first circuit group 10b in FIG. 11 of the sixth embodiment is referred to as a NAND circuit 90, and the second circuit group 20b is referred to as a NAND circuit 90. The first circuit group 10b and the second circuit group 20b constitute a bistable circuit 30b. S (set) and the output of the second circuit group 20b are input to the NAND circuit 90 of the first circuit group 10b. R (reset) and the output of the first circuit group 10b are input to the NAND circuit 90 of the second circuit group 20b. The output of the NAND circuit 90 of the first circuit group 10b is connected to the node Q, and the output of the NAND circuit 90 of the second circuit group 20b is connected to the node QB. The node Q is connected to the control line CTRL via the FET 41 and the resistance change element Re1, and the node QB is connected to the control line CTRL via the FET 42 and the resistance change element Re2.

  FIG. 13 is a circuit diagram in which the SR latch circuit according to the seventh embodiment is configured by FETs. The first circuit group 10 b and the second circuit group 20 b can be configured by the pMOSFET 70 and the nMOSFET 72. Also in the seventh embodiment, the data of the bistable circuit 30b can be stored in the resistance change elements Re1 and Re2 in a nonvolatile manner, and the data of the resistance change elements Re1 and Re2 can be restored to the bistable circuit 30b. Further, the FETs 41 and 42 can prevent the bistable circuit 30b and the resistance change elements Re1 and Re2 from affecting each other.

  Example 8 is another example in which a bistable circuit is configured using a logic circuit. Referring to FIG. 14, the bistable circuit 30 c has a logic circuit 31. The logic circuit 31 has a first circuit group and a second circuit group inside. The logic circuit 31 has two or more inputs C1 to Cn and two or more outputs (two outputs are shown in FIG. 14). The two outputs of the logic circuit 31 are complementary to each other and are connected to the nodes Q and QB, respectively. The two outputs are connected to one of the inputs of the logic circuit 31 (C1 and C2 in FIG. 14). The node Q is connected to the control line CTRL via the FET 41 and the resistance change element Re1, and the node QB is connected to the control line CTRL via the FET 42 and the resistance change element Re2.

  Even if a more general circuit is used as in the eighth embodiment, the data of the bistable circuit 30c is stored in the variable resistance elements Re1 and Re2 by performing the same operation as in FIGS. 6 and 7 of the second embodiment. The data of the resistance change elements Re1 and Re2 can be restored to the bistable circuit 30c. Further, the FETs 41 and 42 can prevent the bistable circuit 30c and the resistance change elements Re1 and Re2 from affecting each other.

  The ninth embodiment is an example of a JK flip-flop path as a specific example of the eighth embodiment. FIG. 15 is a circuit diagram of a JK flip-flop according to the ninth embodiment. The logic circuit 31 shown in FIG. 14 according to the eighth embodiment is realized by eight NAND circuits 90. The NAND circuit 90 that outputs to the node Q corresponds to the first circuit group 10c, and the NAND circuit 90 that outputs to the node QB corresponds to the second circuit group 20c. The node Q is connected to the control line CTRL via the FET 41 and the resistance change element Re1, and the node QB is connected to the control line CTRL via the FET 42 and the resistance change element Re2.

  FIG. 16 is a circuit diagram in which the JK flip-flop according to the ninth embodiment is configured by an FET. The logic circuit 31 can be composed of a pMOSFET 70 and an nMOSFET 72. The node Q is connected to the control line CTRL via the FET 41 and the resistance change element Re1, and the node QB is connected to the control line CTRL via the FET 42 and the resistance change element Re2. Also in the ninth embodiment, the data of the bistable circuit 30c can be stored in the resistance change elements Re1 and Re2 in a nonvolatile manner, and the data of the resistance change elements Re1 and Re2 can be restored to the bistable circuit 30c. Further, the FETs 41 and 42 can prevent the bistable circuit 30c and the resistance change elements Re1 and Re2 from affecting each other.

  According to Non-Patent Document 3, the resistance change element is directly connected to the storage node. For this reason, the current consumed by the SRAM or the like increases due to the current that flows from the storage node to the variable resistance element when the SRAM or the latch circuit operates. On the other hand, according to the first to ninth embodiments, during normal SRAM operation or the like, the leakage current path flowing through the resistance change elements Re1 and Re2 is blocked by turning off the FETs 41 and 42, thereby suppressing standby power consumption. be able to.

  According to Non-Patent Document 3, the noise margin deteriorates when data is read from the bistable circuit due to the current flowing from the bistable circuit to the variable resistance element. On the other hand, according to the first to ninth embodiments, since the bistable circuit 30a and the resistance change elements Re1 and Re2 can be separated by the FETs 41 and 42, it is possible to suppress noise margin deterioration.

  Furthermore, the restore operation is affected by variations in characteristics of the first circuit group 10a and the second circuit group 20a of the bistable circuit 30a. In order to suppress this influence, it is preferable to increase the potential difference between the node Q and the node QB during the restore operation. For this reason, it is preferable to reduce the resistance at least when the variable resistance elements Re1 and Re2 are set. However, in Non-Patent Document 3, there is a trade-off between lowering the resistance when the variable resistance element is set and suppressing the standby power consumption and the noise margin. On the other hand, according to the first to ninth embodiments, the bistable circuit 30a and the resistance change elements Re1 and Re2 can be separated by turning off the FETs 41 and 42 during normal SRAM or latch circuit operation. Therefore, it is possible to use a variable resistance element having a low resistance when set.

  In the second to ninth embodiments, the CMOSFET is used as the first circuit group and the second circuit group. However, the first circuit group and the second circuit group are configured using a resistance load or a D-mode load. Also good. Although an example of an n-type FET has been shown as the FETs 41 and 42, a p-type FET may be used.

  Example 10 is an example of an electronic device using Examples 1-9. FIG. 17 is a block diagram of an electronic device according to a tenth embodiment. The electronic device has a microprocessor 110, a nonvolatile main memory 132, and an external memory 134. The nonvolatile main memory 132 is configured by, for example, an MRAM. The external memory 134 is, for example, a hard desk drive (HDD). The microprocessor 110, the nonvolatile main memory 132, and the external memory 134 are connected by a bus.

  The microprocessor 110 has a power management unit 112, a nonvolatile SARM 114, and a power domain 116. The nonvolatile SRAM 114 is, for example, a nonvolatile memory according to the second or third embodiment. The powered domain-in includes, for example, the nonvolatile flip-flop 118 according to the fourth to eighth embodiments. The nonvolatile SRAM 114 and the power domain 116 have a sleep transistor 120. The power management unit 112 can cut off the power supplied to the volatile SRAM 114 and the power domain 116 by cutting off the volatile SRAM 114 and the sleep transistor 120 of the power domain 116.

  FIG. 18 is a block diagram of the power domain 116. As illustrated in FIG. 18, the power domain 116 includes a logic circuit 122 and a nonvolatile register 124. The nonvolatile register 124 includes, for example, the nonvolatile D flip-flop 126 and the AND circuit 128 according to the fourth embodiment. The AND circuit 128 outputs the AND of the latch drive signal (latch EN) of the register controller 131, the clock CLK, and the signal of the power management unit 112 to the nonvolatile D flip-flop 126 as the clock CLK. The register controller 131 receives an address bus and an input signal. An external signal input is input to the logic circuit 122. The OR circuit 130 ORs the output of the logic circuit 122 and the output of the power management unit 112 and outputs the result as an external output signal. The sleep transistor 120 turns on / off the power supply to the power domain 116.

  In FIG. 18, when the power management unit 112 shuts off the power supply of the power domain 116, the power management unit 112 outputs a low to the AND circuit 128, thereby ensuring the complementarity to the nonvolatile D flip-flop 126. The clock input signal (corresponding to the output of the AND circuit 128) is stopped to enter the clock gating state. The power management unit 112 controls the switch line SR and the control line CTRL of the nonvolatile D flip-flop 126, and stores data of the bistable circuit in the nonvolatile D flip-flop 126 in the resistance change element as shown in FIG. . Further, by outputting high to the OR circuit 130, the output of the external output signal from the logic circuit 122 is fixed to high. Further, the power supply to the power domain 116 is stopped by outputting high to the gate of the sleep transistor 120.

  When the power management unit 112 restores the power supply of the power domain 116, the power management unit 112 controls the switch line SR and the control line CTRL of the nonvolatile D flip-flop 126 and outputs low to the gate of the steep transistor 120. As shown in FIG. 7, the data of the resistance change element in the nonvolatile D flip-flop 126 is restored to the bistable circuit. Further, low is output to the OR circuit 130. The power management unit 112 cancels the clock gating by outputting high to the AND circuit 128. As described above, the power management unit 112 can shut off and restore the power of the power domain 116.

  According to the tenth embodiment, the power management unit 112 can completely reduce the power consumption during standby by completely disconnecting the volatile SRAM 114 and the power domain 116 from the power source. Further, by configuring the SRAM, latch circuit, and flip-flop in the microprocessor 110 with the circuits of the first to ninth embodiments, data immediately before power-off can be stored in a nonvolatile manner even when the power is turned off. it can. Therefore, even if the power is turned off when the microprocessor 110 is in operation, the microprocessor can be operated from the state immediately before the power is turned off when the power is turned on again.

  The preferred embodiments of the present invention have been described in detail above. However, the present invention is not limited to the specific embodiments, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims. It can be changed.

10 first circuit group 20 second circuit group 30 bistable circuit 41, 42 FET
50, 52 Pass gate Q, QB Node Re1, Re2 Resistance change element CTRL Control line DIN, DINB I / O line

Claims (18)

A field effect transistor;
One end is connected to the source of the field effect transistor, and a resistance change element capable of setting a resistance value in a nonvolatile manner,
An electronic circuit comprising: A bistable circuit for storing data;
The drain of the field effect transistor is connected to at least one of mutually complementary nodes in the bistable circuit;
The other end of the variable resistance element is connected to a control line,
The electronic circuit according to claim 1, wherein the variable resistance element stores the data in a nonvolatile manner according to the resistance value, and restores the stored data to the bistable circuit.   The field effect transistor is configured such that a current flowing through the variable resistance element is smaller than when erasing data stored in the variable resistance element when storing data in the bistable circuit. The electronic circuit according to claim 2, wherein a current flowing through the circuit is controlled.   The field effect transistor is conductive when storing data from the bistable circuit to the variable resistance element and when restoring data from the variable resistance element to the bistable circuit, and is connected to the bistable circuit from an input / output line. 3. The electronic circuit according to claim 2, wherein the electronic circuit becomes non-conductive when data is input / output.   When storing data from the bistable circuit to the variable resistance element, a voltage higher than the high level voltage of the node is applied to the control line, and when restoring data from the variable resistance element to the bistable circuit 5. The electronic circuit according to claim 2, wherein a voltage lower than a power supply voltage applied to the bistable circuit is applied to the control line. 6.   6. The electronic circuit according to claim 5, wherein a voltage higher than a low level voltage of the node is applied to the control line when erasing data stored in the variable resistance element.   3. The resistance value of the variable resistance element is set according to a voltage applied to a gate of the field effect transistor when data is stored from the bistable circuit to the variable resistance element. The electronic circuit according to any one of 1 to 6. The node includes a first node and a second node complementary to each other;
The variable resistance element includes a first variable resistance element connected between the first node and the control line, and a second variable resistance element connected between the second node and the control line. The electronic circuit according to claim 2, wherein the electronic circuit is included.   The first resistance change element is set to have a higher resistance value than the second resistance change element when the first node stores high level data, and the first node stores low level data. 9. The electronic circuit according to claim 8, wherein a resistance value is set lower than that of the second variable resistance element.   The fixed resistor connected between another node complementary to the node in the bistable circuit and the control line is provided. The electronic circuit described.   The variable resistance element is set higher than the resistance value of the fixed resistance when the node stores high level data, and is set lower than the resistance value of the fixed resistance when the node stores data of low level. The electronic circuit according to claim 10, wherein: A first switch for writing the data to the bistable circuit;
The electronic circuit according to claim 2, further comprising a second switch that operates in a complementary manner with the first switch and holds data of the bistable circuit. The bistable circuit is connected to a first circuit group having one or more inputs and one or more outputs and a second circuit group having one or more inputs and one or more outputs,
The node is a node in which one of the outputs of the first circuit group and one of the inputs of the second circuit group are connected, or one of the outputs of the second circuit group and the first circuit group. The electronic circuit according to claim 2, wherein the electronic circuit is a node connected to one of the inputs. In the bistable circuit, a first circuit group that is an inverter and a second circuit group that is an inverter are connected in a ring shape,
The electronic circuit according to claim 2, wherein the node is a node connecting the first circuit group and the second circuit group.   2. The electronic circuit according to claim 1, wherein the current drive capability of the field effect transistor is set in a non-volatile manner by the resistance value.   2. The electronic circuit according to claim 1, wherein the current driving capability of the field effect transistor can be changed by a negative feedback effect and a substrate bias effect by the variable resistance element.   The field effect transistor adjusts the resistance value in a variable manner by controlling a current flowing through the variable resistance element, and sets a current driving capability of the field effect transistor in a nonvolatile manner by the resistance value. The electronic circuit according to claim 1.   The bias applied between the source and drain of the field effect transistor is opposite between setting the resistance value of the variable resistance element and operating the field effect transistor. The electronic circuit according to claim 1.

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