JP2014192809A - Reference clock switching circuit and clock distribution circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a reference clock switching circuit that prevents a PLL circuit from unlocking when a reference clock is switched.SOLUTION: A reference clock switching circuit 10 includes: a switching clock generation section 11 for generating a phase division number of switching clocks different in phase by a switching phase difference from Reference clock 1; a switching clock selection section 12 for comparing a phase of each of the phase division number of switching clocks with a phase of Reference clock 2 and selecting the switching clock that is closest in phase to Reference clock 2; a clock switching section 13 for, after outputting the switching clock that is closest in phase to Reference clock 2 to the PLL circuit for a phase retention time, repeatedly outputting one other switching clock earlier in phase by the switching phase difference to the PLL circuit for the phase retention time, until the switching clock matches Reference clock 1 in phase; and a phase division number setting section 14 for determining the switching phase difference and the phase division number.

Description

  The present invention relates to a reference clock switching circuit and a clock distribution circuit.

  Conventionally, a circuit for switching from one reference clock to another reference clock is used. Such a circuit may be provided in a clock distribution circuit, for example.

  FIG. 1 is a diagram for explaining an example of clock distribution in the slave synchronization method.

  The main station 100 and a plurality of subordinate stations 101 and 102 subordinate to the main station 100 form a communication network, and transmit and receive data between the stations. Then, in order to synchronize communication, a slave synchronization type clock distribution is used.

  The main station 100 has a clock source having high accuracy and reliability, and distributes a reference clock generated by the clock source to the subordinate stations 101.

  The dependent station 101 operates by generating a synchronized clock having a predetermined frequency based on the input reference clock.

  FIG. 2 is a diagram for explaining a clock distribution circuit of a dependent station.

  The dependent station 101 includes a clock distribution circuit 110 that distributes the input reference clock.

  The clock distribution circuit 110 includes a clock control circuit 120 and a plurality of subscriber circuits 140a and 140b.

  The clock control circuit 120 receives an external clock as a reference clock, generates a synchronized clock having a predetermined frequency, and outputs the clock to a plurality of subscriber circuits 140a and 140b.

  The clock control circuit 120 includes an internal clock source 121, a selector 122, and a pre-stage PLL (Phased Locked Loop) circuit 123.

  The clock control circuit 120 inputs a plurality of external clocks 1 and 2 from the outside in preparation for a failure in one external clock. The plurality of external clocks 1 and 2 are input from the main station 100, for example. The internal clock source 121 generates an internal clock.

  The selector 122 is controlled by a control unit (not shown) to select one of the external clocks 1 and 2 and the internal clock, and outputs the selected clock to the pre-stage PLL circuit 123. The clock switching is performed, for example, when a failure occurs in the clock used as the reference clock.

  The pre-stage PLL circuit 123 generates a synchronized clock having a predetermined frequency based on the input clock.

  The subscriber circuits 140 a and 140 b operate by generating a clock having a predetermined frequency synchronized with the clock input from the clock control circuit 120.

  The subscriber circuits 140a and 140b have a post-stage PLL circuit 141. The post-stage PLL circuit 141 generates a synchronized clock having a predetermined frequency based on the input clock.

  FIG. 3 is a diagram illustrating the PLL circuit.

  The PLL circuit 200 illustrated in FIG. 3 illustrates an example of the front-stage PLL circuit 123 or the rear-stage PLL circuit 141.

  The PLL circuit 200 includes a phase comparator 201 that inputs an input clock, a loop filter 202, a DC amplifier 203, a voltage-controlled oscillator 204 that outputs an output clock, and a frequency divider 205.

  The phase comparator 201 compares the input clock with the output clock fed back via the frequency divider 205, generates an error signal corresponding to the phase difference, and outputs the error signal to the loop filter 202.

  The loop filter 202 converts the error signal into a DC voltage and outputs the DC voltage from which the high frequency component has been removed to the DC amplifier 203. The DC amplifier 203 amplifies the DC voltage and outputs it to the voltage controlled oscillator 204. The voltage controlled oscillator 204 generates an output clock having a frequency corresponding to the DC voltage.

Japanese Patent Laid-Open No. 8-154051 Japanese National Patent Publication No. 8-510366 JP 2001-44979 A Japanese Patent Laid-Open No. 02-075223

  Here, it is assumed that a failure has occurred in the external clock selected by the selector 122 of the clock control circuit 120, so that the selector 122 switches the clock output to the preceding PLL circuit 123.

  The pre-stage PLL circuit 123 varies the frequency or phase of the output clock in order to follow the switched input clock. The follow-up speed of the output clock with respect to the input clock of the pre-stage PLL circuit 123 is determined by the filter characteristics of the loop filter, the characteristics of the voltage controlled oscillator, and the like.

  The post-stage PLL circuit 141 also changes the frequency or phase of the output clock in order to follow the fluctuation of the clock input from the pre-stage PLL circuit 123. The follow-up speed with respect to the input clock of the post-stage PLL circuit 141 is similarly determined by the filter characteristics of the loop filter, the characteristics of the voltage controlled oscillator, and the like.

  If the front-stage PLL circuit 123 or the rear-stage PLL circuit 141 cannot follow the fluctuation of the input clock, the synchronization is lost. The output clock of the PLL circuit is synchronized with the input clock. As shown in FIG. 3, one pulse of the output clock is generated at a predetermined timing with respect to one pulse of the corresponding input clock. Means that. The loss of synchronization of the PLL circuit means that one pulse of the output clock is not generated at a predetermined timing with respect to one pulse of the corresponding input clock.

  The filter characteristics of the loop filter and the characteristics of the voltage-controlled oscillator can be adjusted. However, these characteristics may vary with time, and thus the synchronization may be lost when the characteristics vary.

  Further, the post-stage PLL circuit used for the subscriber circuit may be modularized. In such a case, it is difficult to adjust the characteristics of the post-stage PLL circuit.

  In one aspect, an object of the present invention is to provide a reference clock switching circuit that prevents a PLL circuit from being out of synchronization when switched from one reference clock to another reference clock.

  In another aspect, an object of the present invention is to provide a clock distribution circuit that prevents a PLL circuit from being out of synchronization when switched from one reference clock to another reference clock.

  According to the reference clock switching circuit according to one aspect, the switching clock generation unit that generates the switching clock having the phase division number different from the first reference clock by the switching phase difference, the phase of the second reference clock, and the phase division number The switching clock selection unit that compares the phases of the switching clocks of the second reference clock and selects the switching clock that is closest to the phase of the second reference clock, and the switching clock that is closest to the phase of the second reference clock After being output to the PLL circuit during the holding time, until the phase of the switching clock matches the first reference clock, another switching clock whose phase is smaller by the switching phase difference than before is transferred during the phase holding time. A clock switching unit that repeatedly outputs to the PLL circuit, the switching phase difference and the phase A phase division number setting unit for obtaining a division number, wherein after outputting the first reference clock to the PLL circuit, a first test clock having a phase different from the first reference clock by a phase difference P is output to the PLL circuit; If the input clock of the PLL circuit to which the first test clock is input and the output clock are not synchronized, the phase difference P is set as the switching phase difference, while the input clock of the PLL circuit to which the first test clock is input When the synchronization with the output clock is lost, after outputting the first reference clock to the PLL circuit, a new first test clock having a phase difference P with a smaller phase difference with respect to the first reference clock than before is output to the PLL. The output to the circuit is repeated until the synchronization between the input clock and the output clock of the PLL circuit to which the first test clock is input is not lost. Since the phase difference P and the switching phase difference comprises a phase division number setting section for obtaining a quotient obtained by dividing the 2π radians by the switching phase difference as the phase division number, the.

  The clock distribution circuit according to one aspect includes the above-described reference clock switching circuit, inputs or generates the first reference clock and the second reference clock, and distributes the second reference clock to one or a plurality of PLL circuits. When a failure occurs in the second reference clock, the clock output to one or a plurality of PLL circuits is switched from the second reference clock to the first reference clock using the reference clock switching circuit.

  According to the reference clock switching circuit described above, the PLL circuit can be prevented from being out of synchronization when switching from one reference clock to another reference clock.

  Further, according to the above-described clock distribution circuit, it is possible to prevent the PLL circuit from being out of synchronization when switching from one reference clock to another reference clock.

  The objects and advantages of the invention will be realized and obtained by means of the elements and combinations particularly pointed out in the appended claims.

  Both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention as claimed.

It is a figure explaining the example of the clock distribution of a slave synchronization system. It is a figure explaining the clock distribution circuit of a dependent station. It is a figure explaining a PLL circuit. It is a figure which shows the clock distribution circuit disclosed in this specification. It is a figure explaining the operation | movement of a PLL circuit when a reference clock switches. It is a functional block diagram showing a reference clock switching circuit disclosed in the present specification. It is a circuit block diagram showing a reference clock switching circuit disclosed in this specification. It is a flowchart explaining operation | movement of a phase division number setting part. It is a timing chart of a clock explaining operation of a phase division number setting part. It is a flowchart explaining operation | movement of a phase holding time setting part. It is a timing chart of a clock explaining operation of a phase maintenance time setting part. It is a flowchart explaining operation | movement of a clock switching part. It is a timing chart of a clock explaining operation of a clock change part. It is a circuit block diagram which shows the modification of the clock distribution circuit disclosed by this specification.

  Hereinafter, a preferred embodiment of the clock distribution circuit disclosed in the present specification will be described with reference to the drawings. However, the technical scope of the present invention is not limited to these embodiments, but extends to the invention described in the claims and equivalents thereof.

  FIG. 4 is a diagram illustrating a clock distribution circuit disclosed in this specification.

  The clock distribution circuit 1 according to this embodiment includes a clock control circuit 20, a plurality of subscriber circuits 40a and 40b, a reference clock switching circuit 10, and a failure detection unit 30.

  The clock control circuit 20 generates a clock having a synchronized predetermined frequency based on an external clock or an internal clock that is a reference clock, and outputs the generated clock to the plurality of subscriber circuits 40a and 40b.

  The clock control circuit 20 includes an internal clock source 21, a first selector 22, and a pre-stage PLL circuit 23.

  The clock control circuit 20 inputs a plurality of external clocks 1 and 2 from the outside in case a failure occurs in one external clock. The internal clock source 21 generates an internal clock.

  The external clocks 1 and 2 and the internal clock are input to the first selector 22.

  The first selector 22 is controlled by the reference clock switching circuit 10 to select any one of the external clocks 1 and 2 and the internal clock, and outputs the selected clock to the preceding PLL circuit 23. Clock switching is performed, for example, when a failure occurs in the reference clock.

  The pre-stage PLL circuit 23 generates a clock having a synchronized predetermined frequency based on the input clock, and outputs the generated clock to the plurality of subscriber circuits 40a and 40b.

  Each of the subscriber circuits 40 a and 40 b includes a post-stage PLL circuit 41 and a loss of synchronization detection unit 42. The post-stage PLL circuit 41 generates a synchronized clock having a predetermined frequency based on the input clock. The subscriber circuits 40a and 40b operate based on the clock generated by the post-stage PLL circuit 41.

  The out-of-synchronization detection unit 42 monitors the synchronization between the clock input to the post-stage PLL circuit 41 and the clock output from the post-stage PLL circuit 41. When detecting that the rear-stage PLL circuit 41 is out of synchronization, the out-of-synchronization detection unit 42 outputs a signal indicating that the rear-stage PLL circuit 41 is out of synchronization to the reference clock switching circuit 10. The out-of-synchronization detection unit 42 is formed using a known technique, for example.

  The failure detection unit 30 monitors the external clocks 1 and 2 and the internal clock, and outputs a signal indicating the occurrence of a failure to the reference clock switching circuit 10 when the occurrence of a failure in each clock is detected.

  FIG. 5 is a diagram for explaining the operation of the PLL circuit when the reference clock is switched.

  The external clock 1, the internal clock, and the external clock 2 generate clocks having the same frequency, but are different in phase by π radians.

  First, it is assumed that the first selector 22 selects the external clock 1 as the reference clock, and the external clock 1 is input to the preceding PLL circuit 23.

  Here, at time t0, the failure detection unit 30 detects that a failure has occurred in the external clock 1, so that the reference clock switching circuit 10 outputs the internal clock to the preceding PLL circuit 23 as the reference clock. Assume that one selector 22 is switched.

  In the pre-stage PLL circuit 23, the input voltage of the voltage controlled oscillator greatly fluctuates in order to follow the switched input clock. When this input voltage is within the synchronizable range, the pre-stage PLL circuit 23 can generate an output clock synchronized with the input clock.

  On the other hand, when the input voltage of the voltage controlled oscillator is outside the synchronizable range, the pre-stage PLL circuit 23 cannot generate an output clock synchronized with the switched input clock.

  Further, the frequency or phase of the clock output from the pre-stage PLL circuit 23 varies greatly in order to follow the switched input clock by switching the reference clock.

  Since the post-stage PLL circuit 41 receives the clock output from the pre-stage PLL circuit 23, the frequency or phase varies greatly by switching the reference clock.

  Also in the post-stage PLL circuit 41, in order to follow the switched input clock, the input voltage of the voltage controlled oscillator greatly fluctuates. When the input voltage is within the synchronizable range, the post-stage PLL circuit 41 can generate an output clock synchronized with the input clock.

  On the other hand, when the input voltage of the voltage controlled oscillator is outside the synchronizable range, the post-stage PLL circuit 41 cannot generate an output clock synchronized with the input clock.

  Therefore, the pulse distribution circuit 1 of the present embodiment includes the reference clock switching circuit 10 in order to prevent the rear-stage PLL circuit 41 from being out of synchronization when the reference clock is switched.

  When a failure occurs in one reference clock that is used, the pulse distribution circuit 1 uses the reference clock switching circuit 10 to change from the one reference clock so that the synchronization of the subsequent PLL circuit 41 is not lost. Switch to the reference clock.

  Next, the reference clock switching circuit 10 will be described in detail below with reference to the drawings.

  FIG. 6 is a functional block diagram illustrating the reference clock switching circuit disclosed in this specification. FIG. 7 is a circuit block diagram showing a reference clock switching circuit disclosed in this specification.

  The reference clock switching circuit 10 includes a switching clock generation unit 11, a switching clock selection unit 12, a clock switching unit 13, a phase division number setting unit 14, and a phase holding time setting unit 15.

  The above-described functional blocks of the reference clock switching circuit 10 are realized by the cooperation of the circuit blocks shown in FIG. The reference clock switching circuit 10 can be formed using, for example, a DSP or an FPGA.

  The reference clock switching circuit 10 includes a control unit 50, units 55a to 55c, and a third selector 54.

  The control unit 50 controls the operations of the units 55a to 55c and the third selector 54.

  The unit 55a receives an internal clock, generates a clock having a phase different from that of the internal clock, and outputs the generated clock to the third selector 54. The unit 55a includes a test clock generation unit 51a, a second selector 52a, and a comparison calculation unit 53a. The test clock generation unit 51a and the comparison calculation unit 53a receive an internal clock. The comparison calculation unit 53a receives the clock output from the first selector 22.

  The unit 55 b receives the external clock 1, generates a clock having a phase different from that of the external clock 1, and outputs the generated clock to the third selector 54. The unit 55b includes a test clock generation unit 51b, a second selector 52b, and a comparison calculation unit 53b. The test clock generation unit 51b and the comparison calculation unit 53b receive the external clock 1. The comparison calculation unit 53b receives the clock output from the first selector 22.

  The unit 55 c receives the external clock 2, generates a clock having a phase different from that of the external clock 2, and outputs the generated clock to the third selector 54. The unit 55c includes a test clock generation unit 51c, a second selector 52c, and a comparison calculation unit 53c. The test clock generation unit 51c and the comparison calculation unit 53c receive the external clock 2. The comparison calculation unit 53c receives the clock output from the first selector 22.

  The third selector 54 is controlled by the control unit 50 to select any one of the units 55 a to 55 c and outputs the selected clock to the pre-stage PLL circuit 23.

  When switching from one reference clock being used to another reference clock, the reference clock switching circuit 10 switches the clock step by step with a phase difference within a range where synchronization is not lost (hereinafter also referred to as a switching phase difference). Hereinafter, the number of stages of clock switching is also referred to as a phase division number. The phase division number setting unit 14 obtains the switching phase difference and the phase division number.

  The reference clock switching circuit 10 switches the clock while maintaining the phase of the clock for a predetermined time (hereinafter also referred to as phase holding time) at each stage when switching the clock step by step with the switching phase difference. The phase holding time setting unit 15 obtains this phase holding time.

  First, the phase division number setting unit 14 will be described below with reference to the drawings.

  FIG. 8 is a flowchart for explaining the operation of the phase division number setting unit. FIG. 9 is a clock timing chart for explaining the operation of the phase division number setting unit.

  The switching phase difference and the number of phase divisions are set for an external clock or an internal clock that is not currently used as a reference clock. In the present embodiment, it is assumed that the external clock 1 is used as the reference clock. The description of the phase division number setting unit described below is an example of setting the switching phase difference and the number of phase divisions for the internal clock.

  During the operation in which the phase division number setting unit 14 sets the switching phase difference and the phase division number, the clock distribution circuit 1 stops the operation of distributing a normal clock. The first selector 22 is controlled by the reference clock switching circuit 10 and stops outputting the clock to the preceding PLL circuit 23.

  The operation in which the phase division number setting unit 14 sets the switching phase difference and the phase division number can be performed, for example, when a new subscriber circuit is connected to the clock control circuit 20 or periodically.

  First, in step S10, the control unit 50 sets a phase difference P1 = π for the test clock generation unit 51a. The test clock generation unit 51a is controlled by the control unit 50 to generate a test clock A1 whose phase is different from the internal clock by a phase difference P1 (π) and outputs the test clock A1 to the second selector 52a. In addition, the test clock generation unit 51a is controlled by the control unit 50 to output the input internal clock to the second selector 52a. Note that the test clock generator 51a may generate a different test clock by proceeding by the phase difference P1.

  Next, in step S <b> 12, the second selector 52 a is controlled by the control unit 50 and outputs an internal clock to the third selector 54. The third selector 54 is controlled by the control unit 50, selects the clock output from the unit 55a, and outputs the internal clock to the preceding PLL.

  Next, in step S <b> 14, the second selector 52 a is controlled by the control unit 50 and outputs the test clock A <b> 1 to the third selector 54. The third selector 54 is controlled by the control unit 50, selects the clock output from the unit 55a, and outputs the test clock A1 to the preceding PLL.

  Next, in step S16, the control unit 50 waits for a signal to be input from the failure detection unit 30 for a predetermined time. If the signal from the failure detection unit 30 is input during a predetermined time, the control unit 50 determines that the subsequent PLL circuit 41 is out of synchronization, and proceeds to step S18. On the other hand, if a signal from the failure detection unit 30 is not input during a predetermined time, it is determined that the subsequent PLL circuit 41 is not synchronized, and the process proceeds to step S20.

  When the process proceeds to step S18, the control unit 50 sets the phase difference P1 = P1 / 2 for the test clock generation unit 51a, and returns to step S12. Thereafter, the processing of step S12 to step S16 is repeated.

  In the example shown in FIG. 9, the test clock generation unit 51a halves the phase difference every time the process is repeated with respect to the internal clock such that the phase difference is π, π / 2, π / 4, π / 8. Generate a test clock that changes slightly. The test clocks A1 to A7 have a phase difference of π to π / 64 with respect to the internal clock. The phase of the test clock only needs to be smaller than the phase of the previous test clock, and the rate of change need not be half.

  On the other hand, when the processing proceeds to step S20, the control unit 50 sets the phase difference P1 in which the synchronization of the post-stage PLL circuit 41 is not out of phase as the switching phase difference Q and sets the quotient of 2π / P1 as the phase division number N.

  In the present embodiment, it is assumed that π / 4 radians is set as the switching phase difference Q and 8 (= 2π / (π / 4)) is set as the phase division number N.

  In the above description, the switching phase difference and the number of phase divisions are set for the internal clock. However, the switching phase difference and the number of phase divisions are similarly set for the external clock 1 or the external clock 2. Can be set. When setting the switching phase difference and the number of phase divisions for the external clock 1, the control unit 50 uses the unit 55b. When setting the switching phase difference and the number of phase divisions for the external clock 2, the control unit 50 uses the unit 55c. The operation of the unit 55a described above is also applied as appropriate to the unit 55b and the unit 55c.

  In this embodiment, since the external clock 1 is used as the reference clock, when a failure occurs in the external clock 1, the reference clock is switched to the internal clock or the external clock 2. Therefore, the phase division number setting unit 14 sets the switching phase difference and the phase division number for each of the internal clock and the external clock 2.

  Next, the phase holding time setting unit 15 will be described below with reference to the drawings.

  FIG. 10 is a flowchart for explaining the operation of the phase holding time setting unit. FIG. 11 is a clock timing chart for explaining the operation of the phase holding time setting unit.

  The phase holding time is set for a clock that is not currently used as a reference clock. The description of the phase holding time setting unit 15 described below is an example of setting the phase holding time for the internal clock.

  During the operation in which the phase holding time setting unit 15 sets the phase holding time, the clock distribution circuit 1 stops the operation of distributing a normal clock. The first selector 22 is controlled by the reference clock switching circuit 10 and stops outputting the clock to the preceding PLL circuit 23.

  The operation of setting the phase holding time by the phase holding time setting unit 15 may be performed, for example, when a new subscriber circuit is connected to the clock control circuit 20 or periodically.

  First, in step S30, the control unit 50 sets time T = T0 and phase difference P2 = switching phase difference Q to the test clock generation unit 51a. For example, the period of the internal clock can be used as T0. In the example shown in FIG. 11, T0 = 125 μS. The test clock generation unit 51a is controlled by the control unit 50 to generate a test clock B1 whose phase is different from the internal clock by a phase difference P2 (Q), and outputs the test clock B1 to the second selector 52a. In addition, the test clock generation unit 51a is controlled by the control unit 50 to output the input internal clock to the second selector 52a.

  Next, in step S <b> 32, the second selector 52 a is controlled by the control unit 50 and outputs an internal clock to the third selector 54 for a time T. The third selector 54 is controlled by the control unit 50, selects the clock output from the unit 55a, and outputs the internal clock to the preceding PLL.

  Next, in step S <b> 34, the second selector 52 a is controlled by the control unit 50 and outputs the test clock B <b> 1 to the third selector 54 during the time T. The third selector 54 is controlled by the control unit 50, selects the clock output from the unit 55a, and outputs the test clock B1 to the preceding PLL.

  Next, in step 36, the control unit 50 waits for a signal to be input from the failure detection unit 30 for a predetermined time. If the signal from the failure detection unit 30 is input during a predetermined time, the control unit 50 determines that the subsequent PLL circuit 41 is out of synchronization, and proceeds to step S38. On the other hand, if the signal from the failure detection unit 30 is not input during a predetermined time, the control unit 50 determines that the subsequent PLL circuit 41 is not synchronized and proceeds to step S40.

  When the process proceeds to step S38, the control unit 50 sets time T = 2 × T and phase difference P2 = switching phase difference Q for the test clock generation unit 51a, and returns to step 32. Thereafter, the processing from step S32 to step S38 is repeated.

  In the example shown in FIG. 11, when the processing of step S32 to step S38 is repeated, the time T changes to 125 μS, 250 μS, 500 μS,...

  In this way, by increasing the time T stepwise, even if the phase of the input clock is switched to a clock that is different by the switching phase difference Q, a phase holding time that does not cause the rear-stage PLL circuit 41 to be out of synchronization is generated. Can be found.

  On the other hand, when the process proceeds to step S40, the control unit 50 sets the phase difference P2 = P2 + Q for the test clock generation unit 51a, and then proceeds to step S42.

  Next, in step S42, the control unit 50 determines whether or not the phase difference P2 is 2π radians or more. If the phase difference P2 is 2π radians or more, the process proceeds to step S44. Otherwise, the process returns to step S34.

  When the process proceeds to step S44, the control unit 50 sets the time T as the phase holding time.

  In the present embodiment, it is assumed that 128 mS is set as the phase holding time.

  On the other hand, when the process returns to step S34, the second selector 52a is controlled by the control unit 50 and outputs the test clock B2 to the third selector 54 for the time T. The third selector 54 is controlled by the control unit 50, selects the clock output from the unit 55a, and outputs the test clock B2 to the preceding PLL.

  In the example shown in FIG. 11, the phase of the test clock B2 is delayed by π / 2 with respect to the phase of the test clock B2, and π / 2 (= π / 4 + π / 4) with respect to the phase of the internal clock. Running late.

  Next, in step S36, if the synchronization is not lost, the phase of the test clock is switched by increments of the phase difference Q until the phase difference P2 ≧ 2π, and the processing in steps S40 to S36 is repeated.

  In the example illustrated in FIG. 11, the test clock generation unit 51 a generates a test clock whose phase difference increases by π / 4 from π / 4 to 2π with respect to the internal clock. Then, the internal clock B0 and the test clocks B1 to B7 are continuously output to the pre-stage PLL circuit 23 during the time T.

  The fact that the internal clock B0 and the test clocks B1 to B7 are continuously output to the pre-stage PLL circuit 23 during time T is shown below the input voltage graph of the voltage controlled oscillator of FIG. The pre-stage PLL circuit 23 continuously inputs test clocks having different phases by the switching phase difference Q at time T intervals. When the input clock is switched, the input voltage of the voltage controlled oscillator fluctuates because the pre-stage PLL circuit 23 follows the switched input clock. When the internal clock B0 and the test clocks B1 to B7 are continuously output to the previous-stage PLL circuit 23 at intervals of time T, the previous-stage PLL circuit 23 performs the following before the input voltage of the voltage controlled oscillator is stabilized. The input clock is switched.

  Similarly, when the internal clock B0 and the test clocks B1 to B7 are continuously output to the front-stage PLL circuit 23 at the interval of time T, the rear-stage PLL circuit 41 also has a time before the input voltage of the voltage controlled oscillator is stabilized. Then, the next input clock is switched.

  Therefore, even if the internal clock B0 and the test clocks B1 to B7 are continuously output to the front PLL circuit 23 at the interval of time T, the phase holding time setting unit 15 causes the rear PLL circuit 41 to lose synchronization. Find no time and set as phase hold time.

  In the above description, an example in which the phase holding time is set for the internal clock has been described. However, the phase holding time can be similarly set for the external clock 1 or the external clock 2. When setting the phase holding time for the external clock 1, the control unit 50 uses the unit 55b. Further, when setting the phase holding time for the external clock 2, the control unit 50 uses the unit 55c. The operation of the unit 55a described above is also applied as appropriate to the unit 55b and the unit 55c.

  In this embodiment, since the external clock 1 is used as the reference clock, when a failure occurs in the external clock 1, the reference clock is switched to the internal clock or the external clock 2. Therefore, the phase holding time setting unit 15 sets the phase holding time for each of the internal clock and the external clock 2.

  Next, the switching clock generation unit 11 will be described below.

  The switching clock generation unit 11 generates switching clocks having different phase division numbers N by increasing the phase by a switching phase difference Q from a clock that is not used as a reference clock.

  In the present embodiment, the test clock generation unit 51a of the unit 55a is controlled by the control unit 50 so that the phase is changed from the internal clock by the switching phase difference Q (π / 4) by different phase division numbers N (8). Switching clocks C0 to C7 (see FIG. 13) are generated. Here, the switching clock C0 is an internal clock. The test clock generation unit 51a outputs the generated switching clocks C0 to C7 to the second selector 52a.

  Similarly, the unit 55c is controlled by the control unit 50 to generate a switching clock having a different phase division number by increasing the phase by the switching phase difference from the external clock 2.

  Next, the switching clock selection unit 12 will be described below.

  The switching clock selection unit 12 compares the phase of the currently used reference clock with the phase of each of the switching clocks having the number N of phase divisions, and the switching clock having the closest phase to the phase of the currently used reference clock. Select.

  In the present embodiment, the comparison calculation unit 53a of the unit 55a receives the external clock 1 that is the reference clock output from the first selector 22, receives the phase of the external clock 1, and the switching clocks C0 to C7 (see FIG. 13). ) And the switching clock having the closest phase to the phase of the external clock 1 is selected. The comparison calculation unit 53a outputs to the control unit 50 a flag indicating a switching clock that is closest in phase to the phase of the external clock 1. Here, it is assumed that the comparison calculation unit 53a has selected the switching clock C5 whose phase is closest to the phase of the external clock 1.

  Similarly, the unit 55c is controlled by the control unit 50 to compare the phase of the external clock 1 with the phase of each of the switching clocks of the number of phase divisions, and the switching clock having the closest phase to the phase of the external clock 1 Select.

  Next, the clock switching unit 13 will be described below with reference to the drawings.

  FIG. 12 is a flowchart for explaining the operation of the clock switching unit. FIG. 13 is a clock timing chart for explaining the operation of the clock switching unit.

  In this embodiment, since the external clock 1 is used as the reference clock, when a failure occurs in the external clock 1, the reference clock is switched to the internal clock or the external clock 2. The order in which the reference clock is switched to the internal clock or the external clock 2 is determined in advance. Here, it is assumed that the rank of the internal clock is higher than that of the external clock 2.

  During the operation of the clock switching unit 13, the clock distribution circuit 1 stops the operation of distributing a normal clock. The first selector 22 is controlled by the reference clock switching circuit 10 and stops outputting the clock to the preceding PLL circuit 23.

  The description of the clock switching unit 13 described below is an example in which the external clock 1 that is the reference clock is switched to the internal clock.

  First, in step S50, the control unit 50 determines whether or not the phase of the switching clock C5 that is closest in phase to the external clock 1 matches the phase of the internal clock. If the phase of the switching clock C5 matches the phase of the internal clock, the process proceeds to step S52. Otherwise, the process proceeds to step S54.

  When the process proceeds to step S <b> 52, the first selector 22 is controlled by the control unit 50 to select an internal clock and output it to the preceding PLL circuit 23. As a result, the reference clock switching circuit 10 ends the switching of the reference clock from the external clock 1 where the failure has occurred to the internal clock.

  On the other hand, when the process proceeds to step S54, the second selector 52a is controlled by the comparison calculation unit 53 to switch the switching clock C5 having the closest phase to the phase of the external clock 1 during the phase holding time (128 μS). Output to the third selector 54. The third selector 54 is controlled by the control unit 50 to select the clock output from the unit 55a, and outputs the switching clock C5 to the pre-stage PLL circuit 23. The comparison calculation unit 53 is controlled by the control unit 50.

  Next, in step S56, the control unit 50 determines whether or not the phase of the switching clock C4 whose phase is smaller than the previous phase by the switching phase difference Q (π / 4) matches the phase of the internal clock. If the phase of the switching clock C4 matches the phase of the internal clock, the process proceeds to step S58. Otherwise, the process proceeds to step S60.

  When the process proceeds to step S58, the first selector 22 is controlled by the control unit 50 to select the internal clock and output it to the preceding PLL circuit 23. As a result, the reference clock is switched from the external clock 1 where the failure has occurred to the internal clock.

  On the other hand, when the process proceeds to step S60, the second selector 52a is controlled by the comparison calculation unit 53, and the switching clock C4 whose phase is smaller by the switching phase difference Q (π / 4) than the previous one is set to the phase holding time. During (128 μS), it outputs to the third selector 54. The third selector 54 is controlled by the control unit 50 to select the clock output from the unit 55a and output it to the switching clock C4 upstream PLL circuit 23. Then, the process returns to step S56.

  In the example shown in FIG. 13, the clock switching unit 13 outputs the switching clock C5 to the switching clock C1 to the previous PLL circuit 23 for the phase holding time (128 μS), and then outputs the internal clock to the previous PLL circuit 23. To do. In this way, the reference clock is switched from the external clock 1 where the failure has occurred to the internal clock.

  Note that the reference clock switching circuit 10 may output the switching clock C0 as the internal clock to the preceding PLL circuit 23 via the second selector 52a and the third selector 54.

  According to the clock distribution circuit 1 of the present embodiment described above, it is possible to prevent loss of synchronization of the post-stage PLL circuit 41 when switching from one reference clock to another reference clock.

  Specifically, when switching from one reference clock to another reference clock, the clocks are switched step by step while outputting different switching clocks with different switching phase differences at intervals of the phase holding time. Loss of synchronization can be prevented.

  Here, the switching phase difference uses the largest phase in the range examined by the phase division number setting unit 14, and the phase holding time uses the shortest time in the range examined by the phase holding time setting unit 15. . Therefore, the time required for switching the reference clock can be made as short as possible. For example, when the number of phase divisions is 8 and the phase holding time is 128 mS, the reference clock can be switched at about 1.024 S.

  Further, according to the present embodiment, even if the PLL circuit at the rear stage of the subscriber circuit is modularized, it is possible to prevent the PLL circuit from being out of synchronization without adjusting the filter characteristics of the PLL circuit or the characteristics of the voltage controlled oscillator. Can do.

  Next, a modified example of the clock distribution circuit of the present embodiment described above will be described below with reference to the drawings.

  FIG. 14 is a circuit block diagram illustrating a modified example of the reference clock switching circuit disclosed in this specification.

  In the clock distribution circuit 1 of this modification, another subsequent circuit 60 is connected to the subsequent stage of the subscriber circuit 40a.

  The post-stage circuit 60 includes a post-stage PLL circuit 61 and an out-of-synchronization detector 62.

  The post-stage PLL circuit 61 receives a clock output from the post-stage PLL circuit 41 of the subscriber circuit 40a, and generates a synchronized clock having a predetermined frequency based on the input clock. The post-stage circuit 60 operates based on the clock generated by the post-stage PLL circuit 61.

  The out-of-synchronization detection unit 62 monitors the synchronization between the clock input to the post-stage PLL circuit 61 and the clock output from the post-stage PLL circuit 61. When the out-of-synchronization detection unit 62 detects that the subsequent-stage PLL circuit 61 is out of synchronization, the out-of-synchronization detection unit 62 outputs a signal indicating that the subsequent-stage PLL circuit 61 is out of synchronization to the OR circuit 70.

  The out-of-synchronization detection unit 42 of the subscriber circuits 40 a and 40 b also outputs a signal indicating that the subsequent-stage PLL circuit 41 is out of synchronization to the OR circuit 70.

  The OR circuit 70 outputs, to the reference clock switching circuit 10, an OR signal obtained by ORing signals input from the out-of-synchronization detection unit 42 of the subscriber circuits 40 a and 40 b and the out-of-synchronization detection unit 62 of the post-stage PLL circuit 61. To do.

  According to the clock distribution circuit 1 of this modified example, it is possible to detect the loss of synchronization of the post-stage PLL circuit 61 together with the post-stage PLL circuit 41 of the subscriber circuits 40a and 40b.

  In the present invention, the reference clock switching circuit and the clock distribution circuit of the above-described embodiment can be appropriately changed without departing from the gist of the present invention.

  For example, in the above-described embodiment, the out-of-synchronization detection unit detects the out-of-synchronization of the subsequent PLL circuit. However, the out-of-synchronization detection unit may detect the out-of-synchronization of the preceding PLL circuit.

  In the above-described embodiment, two external clocks are input to the pulse distribution circuit. However, one or three or more external clocks may be input to the pulse distribution circuit. In this case, the pulse distribution circuit has a number of units corresponding to the number of external clocks. Similarly, the pulse distribution circuit may have a plurality of internal clock sources and a corresponding number of units.

  All examples and conditional words mentioned herein are intended for educational purposes to help the reader deepen and understand the inventions and concepts contributed by the inventor. All examples and conditional words mentioned herein are to be construed without limitation to such specifically stated examples and conditions. Also, such exemplary mechanisms in the specification are not related to showing the superiority and inferiority of the present invention. While embodiments of the present invention have been described in detail, it should be understood that various changes, substitutions or modifications can be made without departing from the spirit and scope of the invention.

DESCRIPTION OF SYMBOLS 1 Clock distribution circuit 10 Reference clock switching circuit 11 Switching clock generation part 12 Switching clock selection part 13 Clock switching part 14 Phase division | segmentation number setting part 15 Phase holding time setting part 20 Clock control circuit 21 Internal clock source 22 First selector 23 Previous stage PLL Circuit 30 Fault detection unit 40a, 40b Subscriber circuit 41 Post-stage PLL circuit 42 Out-of-synchronization detection unit 50 Control unit 51a-51c Test clock generation unit 52a-52c Second selector 53a-53c Comparison calculation unit 54 Third selector 55a-55c Unit 60 Post-stage circuit 61 Post-stage PLL circuit 62 Out-of-synchronization detection unit 70 OR circuit 100 Master station 101 Subordinate station 110 Clock distribution circuit 120 Clock control circuit 121 Internal clock source 122 Selector 123 Pre-stage PLL circuit 140 a, 140b Subscriber circuit 141 Subsequent PLL circuit 200 PLL circuit 201 Phase comparator 202 Loop filter 203 DC amplifier 204 Voltage controlled oscillator 205 Frequency divider

Claims (5)

A switching clock generation unit that generates a switching clock having a phase division number that is different from the first reference clock by a phase difference of the switching phase;
A switching clock selector that compares the phase of the second reference clock with the phase of each of the switching clocks of the number of phase divisions, and selects a switching clock that is closest in phase to the phase of the second reference clock;
After the switching clock having the closest phase to the phase of the second reference clock is output to the PLL circuit during the phase holding time, the phase is switched from the previous level until the phase of the switching clock matches the first reference clock. A clock switching unit that repeatedly outputs another switching clock having a small phase difference to the PLL circuit during the phase holding time;
A phase division number setting unit for obtaining the switching phase difference and the number of phase divisions;
After outputting the first reference clock to the PLL circuit, a first test clock whose phase is different from the first reference clock by a phase difference P is output to the PLL circuit,
If the input clock and the output clock of the PLL circuit to which the first test clock is input are not synchronized, the phase difference P is set as the switching phase difference,
On the other hand, if the input clock and output clock of the PLL circuit to which the first test clock is input are out of synchronization,
After the first reference clock is output to the PLL circuit, the first test clock outputs a new first test clock having a phase difference P that is smaller than the first reference clock to the PLL circuit. Repeat until the input clock and the output clock of the input PLL circuit are not synchronized, and the phase difference P that is not synchronized is set as the switching phase difference.
A phase division number setting unit for obtaining a quotient obtained by dividing 2π radians by the switching phase difference as the number of phase divisions;
A reference clock switching circuit. A phase holding time setting unit for obtaining the phase holding time,
An iterative process,
After outputting the first reference clock to the PLL circuit, during a time T, a second test clock having a phase increased by the switching phase difference with respect to the first reference clock is output to the PLL circuit,
If the input clock and output clock of the PLL circuit to which the second test clock is input are not synchronized,
Subsequently, during the time T, the phase of the second test clock is that the phase of the second test clock is output to the PLL circuit by outputting a new second test clock having a phase increased by the switching phase difference with respect to the second test clock. Iterate until the phase of the reference clock reaches 2π radians or more, and execute a repetition process to obtain the time T as the phase holding time,
On the other hand, when the input clock of the PLL circuit to which the second test clock is input and the output clock are out of synchronization,
2. The reference clock switching circuit according to claim 1, further comprising a phase holding time setting unit that executes the repetitive processing after changing the time T to a new time T that has been changed to be longer than before.   The reference clock switching circuit according to claim 1, wherein the PLL circuit includes a first PLL circuit and a second PLL circuit that inputs an output clock of the first PLL circuit.   The reference clock switching circuit according to claim 1, further comprising an out-of-synchronization detection unit that detects that a clock input to the PLL circuit and a clock output from the PLL circuit are out of synchronization. A reference clock switching circuit according to claim 1,
Inputting or generating a first reference clock and a second reference clock;
Distributing the second reference clock to one or more PLL circuits;
A clock distribution circuit that switches the output of the clock to one or a plurality of PLL circuits from the second reference clock to the first reference clock using the reference clock switching circuit when a failure occurs in the second reference clock.

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