JP2014192429A - Wiring board - Google Patents

Wiring board Download PDF

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Publication number
JP2014192429A
JP2014192429A JP2013068182A JP2013068182A JP2014192429A JP 2014192429 A JP2014192429 A JP 2014192429A JP 2013068182 A JP2013068182 A JP 2013068182A JP 2013068182 A JP2013068182 A JP 2013068182A JP 2014192429 A JP2014192429 A JP 2014192429A
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Prior art keywords
semiconductor element
element connection
connection pad
connection pads
insulating substrate
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JP2013068182A
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Japanese (ja)
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Hiroaki Nagashima
浩明 永島
Naohiro Katori
直広 鹿取
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Kyocera SLC Technologies Corp
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Kyocera SLC Technologies Corp
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Priority to JP2013068182A priority Critical patent/JP2014192429A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

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  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a wiring board having good electrical insulation between semiconductor element connection pads.SOLUTION: A wiring board A comprises: an insulating substrate 1 having a mounting part 1a for mounting a semiconductor element S at a top face central part; a number of semiconductor element connection pads 2 arranged on a periphery of the mounting part 1a in two lines of an inner line and an outer line, which are parallel with each other along a periphery of the semiconductor element S and at a distance from each other; wiring conductors 3 which are deposited on a top face of the insulating substrate 1 and extend from the semiconductor element connection pads 2 in the inner line to a central part side of the mounting part 1a and extend from the semiconductor element connection pads 2 in the outer line to the outside of the mounting part 1a; and a solder resist layer 5 which is deposited on the top face of the insulating substrate 1 so as to expose the semiconductor element connection pads 2 and covers the wiring conductors 3 and has a solder dam 5a between the inner line and the outer line, in which side end of the solder dam 5a are formed at a distance from the semiconductor element connection pads 2.

Description

本発明は、半導体素子等を搭載するための配線基板に関するものである。   The present invention relates to a wiring board for mounting a semiconductor element or the like.

図３（ａ）および（ｂ）に、半導体集積回路素子等の半導体素子Ｓを搭載するための従来の配線基板Ｃを示す。なお、図３（ａ）は、（ｂ）に示すＺ−Ｚ部における断面図である。
配線基板Ｃは、絶縁基板２１と、半導体素子接続パッド２２と、配線導体２３と、外部接続パッド２４と、ソルダーレジスト層２５とを備えている。
絶縁基板２１は、上面中央部に半導体素子Ｓを搭載するための搭載部２１ａを有するとともに、上下に貫通する複数のスルーホール２６を有している。
半導体素子接続パッド２２は、搭載部２１ａにおける外周部に、半導体素子Ｓの外周辺に沿って内側列と外側列との２列の並びで配置されている。また、半導体素子接続パッド２２において後述するソルダーダム２５ａ側の一端には、それぞれソルダーダム２５ａ下に延びる延長部２７が付加されている。
配線導体２３は、各半導体素子接続パッド２２から絶縁基板２１の上面をスルーホール２６に向けて延びるとともにスルーホール２６を介して外部接続パッド２４に導出されている。なお、内側列の半導体素子接続パッド２２に接続された配線導体２３は、搭載部２１ａの中央部側に延びており、外側列の半導体素子接続パッド２２に接続された配線導体２３は、搭載部２１ａの外側に延びている。
ソルダーレジスト層２５は、絶縁基板２１の上下面に被着されている。上面側のソルダーレジスト層２５は、半導体素子接続パッド２２を露出する第１開口部２８を有するとともに、配線導体２３を被覆している。また、内側列および外側列の半導体素子接続パッド２２の間には帯状のソルダーダム２５ａを有している。また、下面側のソルダーレジスト層２５は、外部接続パッド２４を露出する第２開口部２９を有している。 3 (a) and 3 (b) show a conventional wiring substrate C for mounting a semiconductor element S such as a semiconductor integrated circuit element. FIG. 3A is a cross-sectional view taken along the line ZZ shown in FIG.
The wiring board C includes an insulating substrate 21, a semiconductor element connection pad 22, a wiring conductor 23, an external connection pad 24, and a solder resist layer 25.
The insulating substrate 21 has a mounting portion 21a for mounting the semiconductor element S at the center of the upper surface, and has a plurality of through holes 26 penetrating vertically.
The semiconductor element connection pads 22 are arranged along the outer periphery of the semiconductor element S in two rows of an inner row and an outer row along the outer periphery of the mounting portion 21a. In addition, an extension 27 that extends below the solder dam 25a is added to one end of the semiconductor element connection pad 22 on the solder dam 25a side, which will be described later.
The wiring conductor 23 extends from each semiconductor element connection pad 22 toward the through hole 26 on the upper surface of the insulating substrate 21 and is led to the external connection pad 24 through the through hole 26. The wiring conductors 23 connected to the semiconductor element connection pads 22 in the inner row extend toward the center of the mounting portion 21a, and the wiring conductors 23 connected to the semiconductor element connection pads 22 in the outer row are connected to the mounting portion. It extends to the outside of 21a.
The solder resist layer 25 is deposited on the upper and lower surfaces of the insulating substrate 21. The solder resist layer 25 on the upper surface side has a first opening 28 that exposes the semiconductor element connection pad 22 and covers the wiring conductor 23. A band-shaped solder dam 25a is provided between the semiconductor element connection pads 22 in the inner and outer rows. The solder resist layer 25 on the lower surface side has a second opening 29 that exposes the external connection pad 24.

そして、半導体素子Ｓの電極Ｔを半導体素子接続パッド２２に半田を介して接続するとともに、外部接続パッド２４を外部の電気回路基板の配線導体に半田を介して接続することにより、半導体素子Ｓが外部の電気回路基板に電気的に接続され、半導体素子Ｓと外部の電気回路基板との間で配線導体２３を介して信号を伝送することにより半導体素子Ｓが稼働する。   Then, the electrode T of the semiconductor element S is connected to the semiconductor element connection pad 22 via solder, and the external connection pad 24 is connected to the wiring conductor of the external electric circuit board via solder. The semiconductor element S operates by being electrically connected to an external electric circuit board and transmitting a signal between the semiconductor element S and the external electric circuit board via the wiring conductor 23.

ところで、半導体素子Ｓの電極Ｔを半導体素子接続パッド２２に接続するときには、周知のフリップチップ技術が好適に用いられる。具体的には、例えば各半導体素子接続パッド２２上にあらかじめ半田を溶着させておき、２３０〜２６０℃程度の高温に加熱した半導体素子Ｓの電極Ｔをそれぞれ対応する半田上に載置して半田を溶融させる。その後、冷却して半田を電極Ｔに固着させることで電極Ｔと半導体素子接続パッド２２とを接続する。   By the way, when the electrode T of the semiconductor element S is connected to the semiconductor element connection pad 22, a known flip chip technique is preferably used. Specifically, for example, solder is deposited on each semiconductor element connection pad 22 in advance, and the electrodes T of the semiconductor element S heated to a high temperature of about 230 to 260 ° C. are placed on the corresponding solder, respectively. To melt. Then, the electrode T and the semiconductor element connection pad 22 are connected by cooling and fixing the solder to the electrode T.

ところが、各半導体素子接続パッド２２上の半田を高温で溶融させる際に、半導体素子接続パッド２２に加わった熱が、延長部２７を介して延長部２７を被覆するソルダーダム２５ａに伝わり、ソルダーダム２５ａが高温になることがある。このとき、ソルダーダム２５ａ内に、例えばソルダーレジスト層２５を被着形成する際に噛み込んだ微小な気泡が熱により大きく膨張してしまう場合がある。このため、ソルダーダム２５ａ中において、互いに近接して配置された延長部２７同士の間に、膨張した気泡による大きな空隙が発生してしまうことがあり、そのような大きな空隙が発生すると、延長部２７と接続する半導体素子接続パッド２２間の電気的な絶縁性が不十分となる恐れがある。   However, when the solder on each semiconductor element connection pad 22 is melted at a high temperature, the heat applied to the semiconductor element connection pad 22 is transmitted to the solder dam 25a covering the extension 27 via the extension 27, and the solder dam 25a is May become hot. At this time, in some cases, for example, minute bubbles caught when the solder resist layer 25 is deposited and formed in the solder dam 25a may expand greatly due to heat. For this reason, in the solder dam 25a, a large space may be generated due to the expanded bubbles between the extended portions 27 arranged close to each other. When such a large space is generated, the extended portion 27 is generated. There is a risk that the electrical insulation between the semiconductor element connection pads 22 to be connected to will be insufficient.

特開２０１２−９９６８２号公報JP 2012-99682 A

本発明は、半導体素子搭載時の高温処理の際に、半導体素子接続パッドが、例えばソルダーダムに生じる気泡から受ける影響を回避することで、互いに近接する半導体素子接続パッド間の電気的な絶縁性が良好な配線基板を提供することを課題とする。   The present invention avoids the influence of the semiconductor element connection pads from, for example, bubbles generated in the solder dam during the high-temperature treatment when the semiconductor elements are mounted, so that the electrical insulation between the semiconductor element connection pads adjacent to each other can be achieved. It is an object to provide a good wiring board.

本発明の配線基板は、上面中央部に半導体素子が搭載される搭載部を有する絶縁基板と、搭載部における外周部に、半導体素子の外周辺に沿って互いに離間して並列する内側列と外側列との２列の並びで配置された多数の半導体素子接続パッドと、絶縁基板の上面に被着されており、内側列の半導体素子接続パッドから搭載部の中央部側に延びるとともに外側列の半導体素子接続パッドから搭載部の外側に延びる配線導体と、絶縁基板の上面に、半導体素子接続パッドを露出させるように被着されており、配線導体を覆うとともに内側列と外側列との間にソルダーダムを有するソルダーレジスト層とを具備する配線基板であって、ソルダーダムの側端が、半導体素子接続パッドから離隔して形設されていることを特徴とするものである。   The wiring board according to the present invention includes an insulating substrate having a mounting portion on which a semiconductor element is mounted at the center of the upper surface, an inner row and an outer side that are spaced apart from each other along the outer periphery of the semiconductor element, and are arranged in parallel on the outer periphery A plurality of semiconductor element connection pads arranged in two rows, and are attached to the upper surface of the insulating substrate, extend from the semiconductor element connection pads in the inner row to the center side of the mounting portion, and A wiring conductor extending from the semiconductor element connection pad to the outside of the mounting portion, and an upper surface of the insulating substrate is attached so as to expose the semiconductor element connection pad, and covers the wiring conductor and between the inner row and the outer row. A wiring board having a solder resist layer having a solder dam, wherein a side end of the solder dam is formed apart from a semiconductor element connection pad.

本発明の配線基板によれば、ソルダーダムの側端が、半導体素子接続パッドから離隔した状態で形設されている。このため、例えば半導体素子接続パッドが、従来のようにソルダーダムに生じる大きな空隙の影響を受けることを回避することができる。その結果、近接して配置された半導体素子接続パッド間の電気的な絶縁性が良好な配線基板を提供することができる。   According to the wiring board of the present invention, the side end of the solder dam is formed in a state of being separated from the semiconductor element connection pad. For this reason, for example, it can be avoided that the semiconductor element connection pad is affected by a large gap generated in the solder dam as in the prior art. As a result, it is possible to provide a wiring board with good electrical insulation between the semiconductor element connection pads arranged close to each other.

図１（ａ）および（ｂ）は、本発明の配線基板の実施の形態の一例を示す概略断面図および平面図である。1A and 1B are a schematic cross-sectional view and a plan view showing an example of an embodiment of a wiring board according to the present invention. 図２（ａ）および（ｂ）は、本発明の配線基板の別の実施の形態の一例を示す概略断面図および平面図である。2A and 2B are a schematic cross-sectional view and a plan view showing an example of another embodiment of the wiring board of the present invention. 図３（ａ）および（ｂ）は、従来の配線基板の実施の形態の一例を示す概略断面図および平面図である。3A and 3B are a schematic cross-sectional view and a plan view showing an example of an embodiment of a conventional wiring board.

次に、本発明の実施形態の一例を図１（ａ）および（ｂ）を基に説明する。図１（ａ）は、（ｂ）に示すＸ−Ｘ部における断面図である。
図１（ａ）に示すように本例の配線基板Ａは、絶縁基板１と、半導体素子接続パッド２と、配線導体３と、外部接続パッド４と、ソルダーレジスト層５とを具備する。 Next, an example of an embodiment of the present invention will be described based on FIGS. 1 (a) and 1 (b). Fig.1 (a) is sectional drawing in the XX part shown to (b).
As shown in FIG. 1A, the wiring board A of this example includes an insulating substrate 1, a semiconductor element connection pad 2, a wiring conductor 3, an external connection pad 4, and a solder resist layer 5.

絶縁基板１は、その上面中央部に、半導体素子Ｓが搭載される搭載部１ａを有するとともに、上下に貫通する複数のスルーホール６を有している。搭載部１ａは半導体素子Ｓに対応する大きさおよび形状をしている。また、絶縁基板１の下面は、外部の電気回路基板と接続するための接続面となっている。   The insulating substrate 1 has a mounting portion 1a on which the semiconductor element S is mounted, and a plurality of through holes 6 penetrating vertically in the central portion of the upper surface. The mounting portion 1a has a size and shape corresponding to the semiconductor element S. The lower surface of the insulating substrate 1 is a connection surface for connecting to an external electric circuit substrate.

絶縁基板１は、例えばガラスクロスにエポキシ樹脂やビスマレイミドトリアジン樹脂等の熱硬化性樹脂を含浸させた電気絶縁材料から成る。絶縁基板１は、この例では単層構造であるが、同一または異なる電気絶縁材料から成る複数の絶縁層を多層に積層した多層構造であってもよい。   The insulating substrate 1 is made of an electrically insulating material in which a glass cloth is impregnated with a thermosetting resin such as an epoxy resin or a bismaleimide triazine resin. The insulating substrate 1 has a single-layer structure in this example, but may have a multilayer structure in which a plurality of insulating layers made of the same or different electrically insulating materials are stacked in multiple layers.

半導体素子接続パッド２は、搭載部１ａにおける外周部に、半導体素子Ｓの外周辺に沿って内側列と外側列との２列の並びで配置されている。そして、この半導体素子接続パッド２に、半導体素子Ｓの電極Ｔを半田バンプを介して接続することにより、配線基板Ａの上面に半導体素子Ｓが電気的に接続される。   The semiconductor element connection pads 2 are arranged in two rows of inner and outer rows along the outer periphery of the semiconductor element S on the outer periphery of the mounting portion 1a. Then, the semiconductor element S is electrically connected to the upper surface of the wiring board A by connecting the electrodes T of the semiconductor element S to the semiconductor element connection pads 2 via solder bumps.

半導体素子接続パッド２は、例えば、銅箔や銅めっき等の良導電性材料から形成されており、後述する配線導体３と一体的に形成されている。   The semiconductor element connection pad 2 is made of, for example, a highly conductive material such as copper foil or copper plating, and is formed integrally with a wiring conductor 3 described later.

配線導体３は、各半導体素子接続パッド２から絶縁基板１の上面をスルーホール６に向けて延びるとともにスルーホール６を介して外部接続パッド４に導出されている。なお、内側列の半導体素子接続パッド２に接続された配線導体３は、搭載部１ａの中央部側に延びるとともに、外側列の半導体素子接続パッド２に接続された配線導体３は、搭載部１ａの外側に延びている。これにより半導体素子Ｓが外部の電気回路基板に電気的に接続され、半導体素子Ｓと外部の電気回路基板との間で配線導体３を介して信号を伝送することにより半導体素子Ｓが稼働する。   The wiring conductor 3 extends from each semiconductor element connection pad 2 toward the through hole 6 on the upper surface of the insulating substrate 1 and is led out to the external connection pad 4 through the through hole 6. The wiring conductor 3 connected to the semiconductor element connection pad 2 in the inner row extends toward the center of the mounting portion 1a, and the wiring conductor 3 connected to the semiconductor element connection pad 2 in the outer row is connected to the mounting portion 1a. Extends outside. As a result, the semiconductor element S is electrically connected to the external electric circuit board, and the semiconductor element S operates by transmitting a signal between the semiconductor element S and the external electric circuit board via the wiring conductor 3.

配線導体３は、周知のサブトラクティブ法やセミアディティブ法により、例えば銅箔や銅めっき等の良導電性材料から形成されている。   The wiring conductor 3 is formed from a highly conductive material such as copper foil or copper plating by a known subtractive method or semi-additive method.

ソルダーレジスト層５は、絶縁基板１の上下面に被着されている。上面側のソルダーレジスト層５は、半導体素子接続パッド２を露出する第１開口部８を有するとともに、配線導体３を被覆している。また、下面側のソルダーレジスト層５は、外部接続パッド４を露出する第２開口部９を有している。さらに、内側列および外側列の半導体素子接続パッド２の間には帯状のソルダーダム５ａを有している。このソルダーダム５ａの側端は、半導体素子接続パッド２から離隔した状態で形設されている。   The solder resist layer 5 is applied to the upper and lower surfaces of the insulating substrate 1. The solder resist layer 5 on the upper surface side has a first opening 8 exposing the semiconductor element connection pad 2 and covers the wiring conductor 3. The solder resist layer 5 on the lower surface side has a second opening 9 that exposes the external connection pad 4. Further, a strip-shaped solder dam 5a is provided between the semiconductor element connection pads 2 in the inner row and the outer row. A side end of the solder dam 5 a is formed in a state of being separated from the semiconductor element connection pad 2.

ソルダーレジスト層５は、例えばエポキシ樹脂やポリイミド樹脂等の熱硬化性樹脂を含有する電気絶縁材料から成る樹脂ペーストまたはフィルムを絶縁基板１の上に塗布または貼着して熱硬化させることにより形成される。   The solder resist layer 5 is formed, for example, by applying or pasting a resin paste or film made of an electrically insulating material containing a thermosetting resin such as an epoxy resin or a polyimide resin on the insulating substrate 1 and thermosetting it. The

ところで、本発明においては、上述したようにソルダーダム５ａの側端が、半導体素子接続パッド２から離隔した状態で形設されている。これにより、半導体素子Ｓ搭載時に半導体素子接続パッド２に加わった高温の熱がソルダーダム５ａに伝わることを抑制することができる。このため、例えば半導体素子接続パッド２が、従来のようにソルダーダムに生じる大きな空隙の影響を受けることを回避することができる。その結果、近接して配置された半導体素子接続パッド間の電気的な絶縁性が良好な配線基板を提供することができる。   By the way, in the present invention, as described above, the side end of the solder dam 5 a is formed in a state of being separated from the semiconductor element connection pad 2. Thereby, it can suppress that the high temperature heat added to the semiconductor element connection pad 2 at the time of mounting the semiconductor element S is transmitted to the solder dam 5a. For this reason, for example, it is possible to avoid the semiconductor element connection pad 2 from being affected by a large gap generated in the solder dam as in the prior art. As a result, it is possible to provide a wiring board with good electrical insulation between the semiconductor element connection pads arranged close to each other.

なお、本発明は上述の実施形態の一例に限定されるものではなく、本発明の要旨を逸脱しない範囲であれば種々の変更は可能である。例えば、上述の実施形態の一例では、図１（ｂ）に示したように、ソルダーダム５ａは帯状に形成しているが、図２（ｂ）に示すように半導体素子接続パッド１２に沿うような凹凸状に形成しても良い。
In addition, this invention is not limited to an example of above-mentioned embodiment, A various change is possible if it is a range which does not deviate from the summary of this invention. For example, in the example of the embodiment described above, the solder dam 5a is formed in a band shape as shown in FIG. 1B, but as shown in FIG. You may form unevenness.

１ 絶縁基板
１ａ 搭載部
２ 半導体素子接続パッド
３ 配線導体
５ ソルダーレジスト層
５ａ ソルダーダム
Ａ 配線基板
Ｓ 半導体素子 DESCRIPTION OF SYMBOLS 1 Insulation board | substrate 1a Mounting part 2 Semiconductor element connection pad 3 Wiring conductor 5 Solder resist layer 5a Solder dam A Wiring board S Semiconductor element

Claims (2)

上面中央部に半導体素子が搭載される搭載部を有する絶縁基板と、前記搭載部における外周部に、前記半導体素子の外周辺に沿って互いに離間して並列する内側列と外側列との２列の並びで配置された多数の半導体素子接続パッドと、前記絶縁基板の上面に被着されており、前記内側列の前記半導体素子接続パッドから前記搭載部の中央部側に延びるとともに前記外側列の前記半導体素子接続パッドから前記搭載部の外側に延びる配線導体と、前記絶縁基板の上面に、前記半導体素子接続パッドを露出させるように被着されており、前記配線導体を覆うとともに前記内側列と前記外側列との間にソルダーダムを有するソルダーレジスト層とを具備する配線基板であって、前記ソルダーダムの側端が、前記半導体素子接続パッドから離隔して形設されていることを特徴とする配線基板。   Two rows of an insulating substrate having a mounting portion on which a semiconductor element is mounted at the center of the upper surface, and an inner row and an outer row that are spaced apart from each other along the outer periphery of the semiconductor element and are arranged in parallel on the outer periphery of the mounting portion A plurality of semiconductor element connection pads arranged in a row and attached to the upper surface of the insulating substrate, extending from the semiconductor element connection pads of the inner row to the center portion side of the mounting portion, and of the outer row A wiring conductor extending from the semiconductor element connection pad to the outside of the mounting portion, and is attached to an upper surface of the insulating substrate so as to expose the semiconductor element connection pad, and covers the wiring conductor and the inner row. A wiring board comprising a solder resist layer having a solder dam between the outer rows, wherein a side end of the solder dam is separated from the semiconductor element connection pad. Wiring board, characterized in that it is. 前記ソルダーダムの側端が、前記半導体素子接続パッドの外周辺に沿って凹凸状に形設されていることを特徴とする請求項１に記載の配線基板。   The wiring board according to claim 1, wherein a side end of the solder dam is formed in a concavo-convex shape along an outer periphery of the semiconductor element connection pad.
JP2013068182A 2013-03-28 2013-03-28 Wiring board Pending JP2014192429A (en)

Priority Applications (1)

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JP2013068182A JP2014192429A (en) 2013-03-28 2013-03-28 Wiring board

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Application Number Priority Date Filing Date Title
JP2013068182A JP2014192429A (en) 2013-03-28 2013-03-28 Wiring board

Publications (1)

Publication Number Publication Date
JP2014192429A true JP2014192429A (en) 2014-10-06

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JP2013068182A Pending JP2014192429A (en) 2013-03-28 2013-03-28 Wiring board

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