JP2014183124A - Semiconductor device manufacturing method and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a normally-off semiconductor device with high yield without performing a heat treatment.SOLUTION: A semiconductor device manufacturing method comprises: a process of forming a first semiconductor layer on a substrate; a process of forming a second semiconductor layer on the first semiconductor layer; a process of forming on the second semiconductor layer, a third semiconductor layer doped with an impurity element to provide p-type conductivity; a process of removing the third semiconductor layer in a region of the third semiconductor layer except a region where a gate electrode is to be formed; a process of forming the gate electrode on the third semiconductor layer; and a process of forming a source electrode and a drain electrode in contact with the second semiconductor layer, in which a substrate temperature at the time of forming the third semiconductor layer is higher than each of substrate temperatures at the time of forming the first semiconductor layer and the second semiconductor layer.

Description

  The present invention relates to a semiconductor device manufacturing method and a semiconductor device.

  Nitride semiconductors such as GaN, AlN, InN, or mixed crystals of these materials have high saturation electron velocities and wide band gaps, and are being studied as high voltage / high power electronic devices. . As such a high withstand voltage / high output electronic device, a technique related to a field effect transistor (FET), particularly, a high electron mobility transistor (HEMT) has been developed.

  As a HEMT using a nitride semiconductor, there is a structure in which an electron transit layer is formed of GaN and an electron supply layer is formed of AlGaN. In the HEMT having this structure, a high density and high output is generated because a high concentration two-dimensional electron gas (2DEG) is generated due to distortion caused by a lattice constant difference between GaN and AlGaN, ie, so-called piezoelectric polarization. A semiconductor device can be obtained.

  By the way, in a HEMT having a structure in which an electron transit layer is formed of GaN and an electron supply layer is formed of AlGaN, a high concentration of 2DEG is generated in the electron transit layer, so that it is difficult to make normally-off. Had a point. For this reason, in order to solve this problem, a p-GaN layer is formed between the gate electrode and the electron supply layer, and the generation of 2DEG directly under the gate electrode is suppressed, thereby making it normally off. Is disclosed (for example, Patent Document 1).

JP 2007-19309 A

  By the way, the p-GaN layer formed between the electron supply layer and the gate electrode generally forms a GaN film doped with Mg on the electron supply layer, and then combines with Mg. P-type by desorbing hydrogen. Thereafter, in a region excluding the region where the gate electrode is formed, the GaN film doped with Mg is removed by dry etching, thereby forming a p-GaN layer in the region where the gate electrode is formed. As a method for desorbing hydrogen from a GaN film doped with Mg, there is generally a heat treatment such as annealing. However, when such heat treatment is performed, main elements such as Ga are also desorbed at the same time, which deteriorates the surface morphology of the GaN film doped with Mg and induces the generation of cracks, etc. As a result, the yield decreases.

  Accordingly, there is a need for a semiconductor device and a method for manufacturing the semiconductor device that are normally off with a high yield without performing a heat treatment or the like after forming a GaN film doped with a p-type impurity element such as Mg. ing.

  According to one aspect of the present embodiment, a step of forming a first semiconductor layer on a substrate, a step of forming a second semiconductor layer on the first semiconductor layer, and the first Forming a third semiconductor layer doped with a p-type impurity element on the second semiconductor layer, and the third semiconductor layer in the region excluding the region where the gate electrode is formed. A step of removing the third semiconductor layer, a step of forming the gate electrode on the third semiconductor layer, and a step of forming a source electrode and a drain electrode in contact with the second semiconductor layer. And the substrate temperature when forming the third semiconductor layer is higher than the substrate temperature when forming the first semiconductor layer and the second semiconductor layer.

  According to another aspect of the present embodiment, a step of forming a first semiconductor layer on a substrate and a step of forming a second semiconductor layer on the first semiconductor layer And forming a third semiconductor layer doped with an impurity element which becomes p-type on the second semiconductor layer, and excluding a region where a gate electrode is formed in the third semiconductor layer Removing the third semiconductor layer in the region, forming the gate electrode on the third semiconductor layer, and forming a source electrode and a drain electrode in contact with the second semiconductor layer And the step of forming the third semiconductor layer includes a first growth step and a second growth step performed after the first growth step, The substrate temperature in one growth step is the substrate temperature in the second growth step, Serial than any of the temperature of the substrate temperature when forming the first semiconductor layer and the second semiconductor layer, wherein the high.

  According to another aspect of the present embodiment, a first semiconductor layer formed on a substrate, a second semiconductor layer formed on the first semiconductor layer, and the first semiconductor layer A third semiconductor layer formed on the second semiconductor layer, a gate electrode formed on the third semiconductor layer, and a source electrode and a drain electrode formed in contact with the second semiconductor layer And the third semiconductor layer is formed in a region immediately below the gate electrode by a semiconductor material doped with an impurity element which becomes p-type, and the second semiconductor layer includes A region where the concentration of the impurity element which becomes the p-type is higher than the concentration of hydrogen exists.

  According to the disclosed semiconductor device manufacturing method and semiconductor device, normally-off can be achieved with a high yield, and the manufacturing process is simplified.

Structure diagram of sample S1 and sample S2 formed of nitride semiconductor multilayer film Characteristic diagram of CV profile in sample S1 Characteristic diagram of CV profile in sample S2 AFM image of the surface of sample S1 AFM image of the surface of sample S2 Concentration distribution chart obtained by SIMS in sample S1 Concentration distribution chart obtained by SIMS in sample S2 Structure diagram of the semiconductor device in the first embodiment Manufacturing Process Diagram of Semiconductor Device in First Embodiment (1) Manufacturing process diagram of semiconductor device in first embodiment (2) Structure diagram of semiconductor device according to second embodiment Explanatory drawing of a discretely packaged semiconductor device according to the third embodiment Circuit diagram of power supply device according to third embodiment Structure diagram of high-power amplifier according to third embodiment

  Modes for carrying out the invention will be described below. In addition, about the same member etc., the same code | symbol is attached | subjected and description is abbreviate | omitted.

[First Embodiment]
(Examination of nitride semiconductor multilayer film)
First, the contents of the study performed on the nitride semiconductor multilayer film up to the semiconductor device in the present embodiment will be described. As described above, when a high-temperature heat treatment such as annealing is performed after film formation, the main elements such as Ga are also desorbed at the same time, the surface morphology at the outermost surface is deteriorated, and the occurrence of cracks and the like is also induced. The reliability as a transistor is lowered, and the yield is lowered.

  In order to describe the semiconductor device in this embodiment, a sample S1 and a sample S2 formed using a nitride semiconductor stacked film were manufactured. As shown in FIG. 1, the sample S1 and the sample S2 have substantially the same structure, but the formation method and the ratio of Mg and hydrogen in the electron supply layer are different.

(Formation method of sample S1)
First, the sample S1 will be described. In the sample S1, a nucleation layer 12, a buffer layer 13, an electron transit layer 21, an electron supply layer 22, and a p-GaN layer 23 are sequentially stacked on a substrate 11 by epitaxial growth by MOVPE (Metal-Organic Vapor Phase Epitaxy). Is formed.

A silicon substrate is used as the substrate 11. The nucleation layer 12 supplies trimethylaluminum (TMA), which is an organometallic material containing Al, and ammonia (NH ₃ ) as source gases, and has a thickness of about 200 nm under conditions of a substrate temperature of 1000 ° C. and a growth pressure of 20 kPa. It is formed by growing.

The buffer layer 13 supplies trimethylgallium (TMG), TMA, and NH ₃ , which are organic metal materials containing Ga, as source gases, and grows AlGaN to a thickness of about 500 nm under conditions of a substrate temperature of 1000 ° C. and a growth pressure of 40 kPa. To form. Although not shown, the buffer layer 13 is formed of three layers having different composition ratios, and an Al _0.8 Ga _0.2 N layer and an Al ₀ are sequentially formed from the side on which the nucleation layer 12 is formed. _.5 Ga _0.5 N layer and Al _0.2 Ga _0.8 N layer. The buffer layer 13 formed of layers having different composition ratios can be formed by changing the ratio of the supply amounts of TMG and TMA.

The electron transit layer 21 is formed by supplying TMG and NH ₃ as source gases and growing GaN to a thickness of about 1000 nm under conditions of a substrate temperature of 1000 ° C. and a growth pressure of 60 kPa.

The electron supply layer 22 is formed by supplying TMG, TMA, and NH ₃ as source gases and growing Al _0.2 Ga _0.8 N to a thickness of about 10 nm under conditions of a substrate temperature of 1000 ° C. and a growth pressure of 40 kPa. To do.

The p-GaN layer 23 is supplied with TMG and NH ₃ as source gases, and as a first growth step, GaN is grown to a thickness of about 25 nm under conditions of a substrate temperature of 1030 ° C. and a growth pressure of 60 kPa. Thereafter, as a second growth step, GaN is grown to a thickness of about 25 nm under conditions of a substrate temperature of 1000 ° C. and a growth pressure of 60 kPa. Thereby, the p-GaN layer 23 having a thickness of 50 nm is formed.

(Formation method of sample S2)
Next, the sample S2 will be described. The sample S2 is formed by sequentially laminating a nucleation layer 12, a buffer layer 13, an electron transit layer 21, an electron supply layer 22, and a p-GaN layer 23 on a substrate 11 by epitaxial growth using MOVPE.

A silicon substrate is used as the substrate 11. The nucleation layer 12 supplies trimethylaluminum (TMA), which is an organometallic material containing Al, and ammonia (NH ₃ ) as source gases, and has a thickness of about 200 nm under conditions of a substrate temperature of 1000 ° C. and a growth pressure of 20 kPa. It is formed by growing.

The buffer layer 13 supplies trimethylgallium (TMG), TMA, and NH ₃ , which are organic metal materials containing Ga, as source gases, and grows AlGaN to a thickness of about 500 nm under conditions of a substrate temperature of 1000 ° C. and a growth pressure of 40 kPa. To form. Although not shown, the buffer layer 13 is formed of three layers having different composition ratios, and an Al _0.8 Ga _0.2 N layer and an Al ₀ are sequentially formed from the side on which the nucleation layer 12 is formed. _.5 Ga _0.5 N layer and Al _0.2 Ga _0.8 N layer. The buffer layer 13 formed of layers having different composition ratios can be formed by changing the ratio of the supply amounts of TMG and TMA.

The electron transit layer 21 is formed by supplying TMG and NH ₃ as source gases and growing GaN to a thickness of about 1000 nm under conditions of a substrate temperature of 1000 ° C. and a growth pressure of 60 kPa.

The electron supply layer 22 is formed by supplying TMG, TMA, and NH ₃ as source gases and growing Al _0.2 Ga _0.8 N to a thickness of about 10 nm under conditions of a substrate temperature of 1000 ° C. and a growth pressure of 40 kPa. To do.

The p-GaN layer 23 is formed by supplying TMG and NH ₃ as source gases and growing GaN to a thickness of about 50 nm under conditions of a substrate temperature of 1000 ° C. and a growth pressure of 60 kPa.

(Evaluation in samples S1 and S2)
Next, the results of evaluating the produced samples S1 and S2 will be described.

  First, the CV profile in the produced samples S1 and S2 will be described. FIG. 2 shows a CV profile measured in the sample S1, and FIG. 3 shows a CV profile measured in the sample S2. In the measurement of the CV profile, two types of electrodes (not shown) such as a ring electrode and an electrode formed inside the ring electrode are formed on the surfaces of the manufactured samples S1 and S2, and the gap between the two types of electrodes is measured. The voltage (V) was applied to the capacitor and the capacity (C) was measured. In the measurement of the CV profile, the first applied voltage was gradually decreased from 0V to -7V, then gradually increased from -7V to + 7V, and then gradually decreased from + 7V to -7V. This was done by measuring the capacity at each voltage. Specifically, in FIG. 3, the voltage is first gradually decreased from 0V to −7V as indicated by an arrow 3a, and then gradually increased from −7V to + 7V as indicated by an arrow 3b. Thereafter, the voltage is gradually decreased from + 7V to -7V as indicated by the arrow 3c.

  In the case of the sample S1, as shown in FIG. 2, there is almost no change in capacitance due to voltage fluctuation, and no hysteresis is generated. Therefore, when a HEMT corresponding to the sample S1 is manufactured, it can be inferred that it can be normally off. On the other hand, in the case of the sample S2, as shown in FIG. 3, the capacitance change accompanying the voltage fluctuation is large, and hysteresis is also generated. Therefore, when a HEMT corresponding to the sample S2 is manufactured, it is assumed that normally-off cannot be performed. When a HEMT having the same structure as that of the sample S2 is manufactured, a heat treatment such as annealing is performed thereafter, so that there is almost no change in capacity due to voltage fluctuation as in the case of the sample S1. It is also possible to make it not occur. However, in this case, as described above, Ga or the like is desorbed from the p-GaN layer 23 to deteriorate the surface morphology, and the occurrence of cracks or the like is also induced, reducing the reliability as a transistor, The yield will be reduced.

  Next, the surface morphology in the produced samples S1 and S2 will be described. FIG. 4 is an AFM image obtained by observation with an AFM (Atomic Force Microscope) on the surface of the p-GaN layer 23 in the sample S1. FIG. 5 is an AFM image obtained by AFM observation on the surface of the p-GaN layer 23 in the sample S2. As shown in FIGS. 4 and 5, the surface morphology of the sample S1 and the sample S2 is good, and it is assumed that Ga or the like is not desorbed from the p-GaN layer 23. Therefore, even when an electrode or the like is formed thereon, peeling of the electrode does not occur, and reliability as a transistor and yield do not decrease. In addition, the reason why such a good surface morphology is obtained is that neither of them is subjected to a heat treatment such as annealing, and as described above, such a good surface morphology is obtained when a heat treatment such as annealing is performed. No surface morphology can be obtained.

Next, the measurement result by SIMS (Secondary Ion Mass Spectrometry) in the produced samples S1 and S2 will be described. FIG. 6 shows a measurement result by SIMS in the sample S1, and FIG. 7 shows a measurement result by SIMS in the sample S2. In both FIGS. 6 and 7, the left axis shows the concentration of H and Mg, and the right axis shows the secondary ion intensity of Al. As shown in FIG. 6, in the sample S <b> 1, a portion where the Mg concentration is higher than the H concentration in the vicinity of the interface with the p-GaN layer 23 in the electron supply layer 22 containing Al. Is present. On the other hand, in the sample S2 shown in FIG. 7, in the electron supply layer 22 containing Al, the Mg concentration is lower than the H concentration. Thus, in the sample S1, the Mg concentration is higher than the H concentration in the vicinity of the interface with the p-GaN layer 23 in the electron supply layer 22 when the p-GaN layer 23 is formed. This is presumably due to Mg being diffused into the electron supply layer 22 because of the high temperature. The peak concentration of Mg in the sample S1 shown in FIG. 6 is about 1.46 × 10 ¹⁹ cm ⁻³ , and the peak concentration of Mg in the sample S2 shown in FIG. , Approximately 5.00 × 10 ¹⁸ cm ⁻³ .

  Thus, by forming the p-GaN layer 23 at a temperature higher than the temperature at which the electron transit layer 21 and the electron supply layer 22 are formed, a HEMT that is normally off without lowering the yield is obtained. It is possible to obtain.

  The present embodiment is based on the above examination results, and by manufacturing a HEMT corresponding to the sample S1, a HEMT that is normally off can be obtained at low cost without reducing the yield.

(Semiconductor device)
Next, the semiconductor device in the first embodiment will be described. The semiconductor device in the present embodiment is a HEMT having the structure shown in FIG.

  Specifically, a nucleation layer 112, a buffer layer 113, an electron transit layer 121, and an electron supply layer 122 are formed on a substrate 111 made of a semiconductor or the like. As a result, 2DEG 121 a is generated in the electron transit layer 121 in the vicinity of the interface between the electron transit layer 121 and the electron supply layer 122. A p-GaN layer 123 is formed on the electron supply layer 122 in a region where the gate electrode 131 is formed. Further, the source electrode 132 and the drain electrode 133 are formed on the electron supply layer 122, and the gate electrode 131 is formed on the p-GaN layer 123. In the present application, the electron transit layer 121 may be referred to as a first semiconductor layer, the electron supply layer 122 may be referred to as a second semiconductor layer, and the p-GaN layer 123 may be referred to as a third semiconductor layer.

  A silicon substrate is used as the substrate 111. The electron transit layer 121 is formed of GaN, the electron supply layer 122 is formed of AlGaN, and the p-GaN layer 123 is formed of GaN doped with p-type impurity elements such as Mg and Be. ing. In the vicinity of the interface between the electron supply layer 122 and the p-GaN layer 123, a p-type impurity element such as Mg contained in the p-GaN layer 123 is diffused, and the concentration of Mg (magnesium) is hydrogen (H ) There is a region higher than the concentration of.

  In the semiconductor device in this embodiment, since there is a region where Mg is more than H in the vicinity of the interface between the electron supply layer 122 and the p-GaN layer 123, the 2DEG 121a immediately below the gate electrode 131 disappears. be able to. Thereby, in the semiconductor device in this embodiment mode, normally-off can be achieved without reducing the yield.

(Method for manufacturing semiconductor device)
Next, a method for manufacturing a semiconductor device in the present embodiment will be described.

  First, as shown in FIG. 9A, a nucleation layer 112, a buffer layer 113, an electron transit layer 121, an electron supply layer 122, and a p-GaN film 123t are sequentially formed on a substrate 111 by epitaxial growth using MOVPE. Laminate.

In the present embodiment, a silicon substrate is used as the substrate 111. The nucleation layer 112 supplies trimethylaluminum (TMA), which is an organometallic material containing Al, and ammonia (NH ₃ ) as source gases, and has a thickness of about 200 nm under conditions of a substrate temperature of 1000 ° C. and a growth pressure of 20 kPa. It is formed by growing.

The buffer layer 113 supplies trimethylgallium (TMG), TMA, and NH ₃ , which are organic metal materials containing Ga, as source gases, and grows AlGaN to a thickness of about 500 nm under conditions of a substrate temperature of 1000 ° C. and a growth pressure of 40 kPa. To form. In the present embodiment, the buffer layer 113 is formed of three layers having different composition ratios, and in order from the side on which the nucleation layer 112 is formed, an Al _0.8 Ga _0.2 N layer, The Al _0.5 Ga _0.5 N layer and the Al _0.2 Ga _0.8 N layer are formed. The buffer layer 113 formed of layers having different composition ratios can be formed by changing the ratio of the supply amounts of TMG and TMA.

The electron transit layer 121 is formed by supplying TMG and NH ₃ as source gases and growing GaN to a thickness of about 1000 nm under conditions of a substrate temperature of 1000 ° C. and a growth pressure of 60 kPa.

The electron supply layer 122 is formed by supplying TMG, TMA, and NH ₃ as source gases and growing Al _0.2 Ga _0.8 N to a thickness of about 10 nm under conditions of a substrate temperature of 1000 ° C. and a growth pressure of 40 kPa. To do.

The p-GaN film 123t is supplied with TMG and NH ₃ as source gases, and as a first growth step, GaN is grown to a thickness of about 25 nm under conditions of a substrate temperature of 1030 ° C. and a growth pressure of 60 kPa. Thereafter, as a second growth step, GaN is grown to a thickness of about 25 nm under conditions of a substrate temperature of 1000 ° C. and a growth pressure of 60 kPa. Thereby, the p-GaN film 123t having a thickness of 50 nm is formed. Note that when forming the p-GaN film 123t, Mg, which is a p-type impurity element, is doped by supplying cyclopentanedienylmagnesium (CP2Mg) together with the source gas. At this time, the concentration of Mg to be doped is about 4 × 10 ¹⁹ cm ⁻³ .

  In the above, when forming the p-GaN film 123t, as a first growth process, a film having a thickness of about 25 nm is first formed at a substrate temperature of 1030 ° C., and then as a second growth process, A case where a film having a thickness of about 25 nm is formed at a substrate temperature of 1000 ° C. has been described. However, in this embodiment, the p-GaN film 123t may all be formed at a substrate temperature of 1030 ° C. That is, the p-GaN film 123t may be formed only by the first growth process. If the substrate temperature at the time of forming the p-GaN layer 123t is higher than the substrate temperature at the time of forming the electron transit layer 121 and the electron supply layer 122, it is inferred that the effect in this embodiment can be obtained. Is done.

  From the viewpoint of the surface morphology of the outermost surface of the p-GaN film 123t, the p-GaN film 123t is first formed at a substrate temperature of 1030 ° C., and then the substrate temperature is lowered and formed at a substrate temperature of 1000 ° C. Is preferred. In the above description, Mg is used as the p-type impurity element. However, Be may be used as the p-type impurity element. In this case, by supplying biscyclopentadienylberyllium (MeCp2Be) together with the source gas, Be, which is a p-type impurity element, is doped to form the p-GaN film 123t.

  Next, as illustrated in FIG. 9B, a p-GaN layer 123 is formed in a region immediately below the gate electrode 131. Specifically, a photoresist is applied on the p-GaN film 123t, and exposure and development are performed by an exposure apparatus, thereby forming a resist pattern (not shown) in a region where the p-GaN layer 123 is formed. . Thereafter, the p-GaN film 123t in the region where the resist pattern is not formed is removed by dry etching such as RIE, and the electron supply layer 122 is exposed, whereby the p-GaN film 123t is formed in the region where the gate electrode 131 is formed. A GaN layer 123 is formed. Thereafter, the resist pattern is removed with an organic solvent or the like.

  Next, as illustrated in FIG. 10, the gate electrode 131 is formed on the p-GaN layer 123, and the source electrode 132 and the drain electrode 133 are formed on the electron supply layer 122. Thus, the semiconductor device in this embodiment can be manufactured. The gate electrode 131 is formed of a metal laminated film made of Ni / Au, and the source electrode 132 and the drain electrode 133 are formed of a metal laminated film made of Ti / Al. In this embodiment, since the heat treatment such as annealing is not performed after the p-GaN film 123t is formed, the surface morphology in the p-GaN layer 123 is good, and the reliability and yield as a transistor are good. It is. In addition, since no heat treatment is performed, the manufacturing process is simplified and the semiconductor device can be manufactured in a short time, and the semiconductor device can be manufactured at low cost.

[Second Embodiment]
Next, a second embodiment will be described. This embodiment is a semiconductor device in which an electron supply layer is formed of InAlN. Specifically, as shown in FIG. 11, the electron supply layer 222 is formed of InAlN on the electron transit layer 121.

In the manufacturing method of the semiconductor device in this embodiment, when the electron supply layer 222 is formed, the substrate temperature is 700 ° C., and the substrate is formed by MOVPE using TMI (trimethylindium), TMA, and NH ₃ as source gases. Thus, the electron supply layer 222 is formed of an In _0.17 Al _0.83 N layer having a thickness of about 10 nm. The contents other than the above are the same as in the first embodiment.

[Third Embodiment]
Next, a third embodiment will be described. The present embodiment is a semiconductor device, a power supply device, and a high-frequency amplifier.

  The semiconductor device according to this embodiment is a discrete package of the semiconductor device according to the first or second embodiment. The semiconductor device thus discretely packaged will be described with reference to FIG. FIG. 12 schematically shows the inside of a discretely packaged semiconductor device. The arrangement of electrodes and the like are different from those shown in the first or second embodiment. Yes.

  First, the semiconductor device manufactured in the first or second embodiment is cut by dicing or the like to form a HEMT semiconductor chip 410 made of a GaN-based semiconductor material. The semiconductor chip 410 is fixed on the lead frame 420 with a die attach agent 430 such as solder.

  Next, the gate electrode 441 is connected to the gate lead 421 by a bonding wire 431, the source electrode 442 is connected to the source lead 422 by a bonding wire 432, and the drain electrode 443 is connected to the drain lead 423 by a bonding wire 433. The bonding wires 431, 432, and 433 are made of a metal material such as Al. In addition, the gate electrode 441 in this embodiment is a gate electrode pad, and is connected to the gate electrode 131 in the first or second embodiment. Similarly, the source electrode 442 is a source electrode pad and is connected to the source electrode 132, and the drain electrode 443 is a drain electrode pad and is connected to the drain electrode 133.

  Next, resin sealing with a mold resin 440 is performed by a transfer molding method. In this way, a HEMT discrete packaged semiconductor device using a GaN-based semiconductor material can be manufactured.

  In addition, the power supply device and the high-frequency amplifier in the present embodiment are a power supply device and a high-frequency amplifier using any of the semiconductor devices in the first or second embodiment.

  Based on FIG. 13, a power supply device according to the present embodiment will be described. The power supply device 460 in this embodiment includes a high-voltage primary circuit 461, a low-voltage secondary circuit 462, and a transformer 463 disposed between the primary circuit 461 and the secondary circuit 462. The primary circuit 461 includes an AC power supply 464, a so-called bridge rectifier circuit 465, a plurality of switching elements (four in the example shown in FIG. 13) 466, a switching element 467, and the like. The secondary side circuit 462 includes a plurality of switching elements (three in the example shown in FIG. 13) 468. In the example shown in FIG. 13, the semiconductor device according to the first or second embodiment is used as the switching elements 466 and 467 of the primary circuit 461. Note that the switching elements 466 and 467 of the primary circuit 461 are preferably normally-off semiconductor devices. The switching element 468 used in the secondary circuit 462 uses a normal MISFET (metal insulator semiconductor field effect transistor) formed of silicon.

  Next, the high frequency amplifier according to the present embodiment will be described with reference to FIG. The high frequency amplifier 470 in the present embodiment may be applied to, for example, a power amplifier for a base station of a mobile phone. The high frequency amplifier 470 includes a digital predistortion circuit 471, a mixer 472, a power amplifier 473, and a directional coupler 474. The digital predistortion circuit 471 compensates for nonlinear distortion of the input signal. The mixer 472 mixes the input signal compensated for nonlinear distortion and the AC signal. The power amplifier 473 amplifies the input signal mixed with the AC signal. In the example illustrated in FIG. 14, the power amplifier 473 includes the semiconductor device according to the first or second embodiment. The directional coupler 474 performs monitoring of input signals and output signals. In the circuit shown in FIG. 14, for example, the output signal can be mixed with an AC signal by the mixer 472 and sent to the digital predistortion circuit 471 by switching the switch.

  Although the embodiment has been described in detail above, it is not limited to the specific embodiment, and various modifications and changes can be made within the scope described in the claims.

In addition to the above description, the following additional notes are disclosed.
(Appendix 1)
Forming a first semiconductor layer on the substrate;
Forming a second semiconductor layer on the first semiconductor layer;
Forming a third semiconductor layer doped with an impurity element to be p-type on the second semiconductor layer;
Removing the third semiconductor layer in a region excluding a region where a gate electrode is formed in the third semiconductor layer;
Forming the gate electrode on the third semiconductor layer;
Forming a source electrode and a drain electrode in contact with the second semiconductor layer;
Have
A method for manufacturing a semiconductor device, wherein a substrate temperature at the time of forming the third semiconductor layer is higher than a substrate temperature at the time of forming the first semiconductor layer and the second semiconductor layer.
(Appendix 2)
Forming a first semiconductor layer on the substrate;
Forming a second semiconductor layer on the first semiconductor layer;
Forming a third semiconductor layer doped with an impurity element to be p-type on the second semiconductor layer;
Removing the third semiconductor layer in a region excluding a region where a gate electrode is formed in the third semiconductor layer;
Forming the gate electrode on the third semiconductor layer;
Forming a source electrode and a drain electrode in contact with the second semiconductor layer;
Have
The step of forming the third semiconductor layer includes a first growth step and a second growth step performed after the first growth step,
The substrate temperature in the first growth step is higher than any of the substrate temperature in the second growth step, and the substrate temperature when forming the first semiconductor layer and the second semiconductor layer. A method of manufacturing a semiconductor device.
(Appendix 3)
The temperature of the substrate in the second growth step is substantially the same as the temperature of the substrate when forming the first semiconductor layer and the second semiconductor layer. A method for manufacturing a semiconductor device.
(Appendix 4)
The method for manufacturing a semiconductor device according to any one of appendices 1 to 3, wherein the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are formed by MOVPE. .
(Appendix 5)
5. The method of manufacturing a semiconductor device according to any one of appendices 1 to 4, wherein the impurity element to be p-type is Mg or Be.
(Appendix 6)
6. The method of manufacturing a semiconductor device according to any one of appendices 1 to 5, wherein the first semiconductor layer is made of a material containing GaN.
(Appendix 7)
7. The method of manufacturing a semiconductor device according to any one of appendices 1 to 6, wherein the third semiconductor layer is doped with a p-type impurity element in a material containing GaN.
(Appendix 8)
8. The method for manufacturing a semiconductor device according to any one of appendices 1 to 7, wherein the second semiconductor layer is formed of a material containing AlGaN.
(Appendix 9)
A first semiconductor layer formed on the substrate;
A second semiconductor layer formed on the first semiconductor layer;
A third semiconductor layer formed on the second semiconductor layer;
A gate electrode formed on the third semiconductor layer;
A source electrode and a drain electrode formed in contact with the second semiconductor layer;
Have
The third semiconductor layer is formed in a region immediately below the gate electrode by a semiconductor material doped with an impurity element which becomes p-type,
The semiconductor device, wherein the second semiconductor layer includes a region in which the concentration of the impurity element to be p-type is higher than the concentration of hydrogen.
(Appendix 10)
The semiconductor device according to appendix 9, wherein the third semiconductor layer is doped with a p-type impurity element in a material containing GaN.
(Appendix 11)
The semiconductor device according to appendix 9 or 10, wherein the p-type impurity element is Mg or Be.
(Appendix 12)
12. The semiconductor device according to any one of appendices 9 to 11, wherein the first semiconductor layer is made of a material containing GaN.
(Appendix 13)
The semiconductor device according to any one of appendices 9 to 12, wherein the second semiconductor layer is formed of a material containing AlGaN.
(Appendix 14)
14. The semiconductor device according to any one of appendices 9 to 13, wherein the substrate is a silicon substrate.
(Appendix 15)
15. The semiconductor device according to any one of appendices 9 to 14, wherein a buffer layer is formed of a material containing AlGaN between the substrate and the first semiconductor layer.
(Appendix 16)
A power supply device comprising the semiconductor device according to any one of appendices 9 to 15.
(Appendix 17)
An amplifier comprising the semiconductor device according to any one of appendices 9 to 15.

11 Substrate 12 Nucleation layer 13 Buffer layer 21 Electron travel layer (first semiconductor layer)
22 Electron supply layer (second semiconductor layer)
23 p-GaN layer (third semiconductor layer)
111 Substrate 112 Nucleation layer 113 Buffer layer 121 Electron travel layer (first semiconductor layer)
121a 2DEG
122 Electron supply layer (second semiconductor layer)
123 p-GaN layer (third semiconductor layer)
131 Gate electrode 132 Source electrode 133 Drain electrode

Claims (8)

Forming a first semiconductor layer on the substrate;
Forming a second semiconductor layer on the first semiconductor layer;
Forming a third semiconductor layer doped with an impurity element to be p-type on the second semiconductor layer;
Removing the third semiconductor layer in a region excluding a region where a gate electrode is formed in the third semiconductor layer;
Forming the gate electrode on the third semiconductor layer;
Forming a source electrode and a drain electrode in contact with the second semiconductor layer;
Have
A method for manufacturing a semiconductor device, wherein a substrate temperature at the time of forming the third semiconductor layer is higher than a substrate temperature at the time of forming the first semiconductor layer and the second semiconductor layer. Forming a first semiconductor layer on the substrate;
Forming a second semiconductor layer on the first semiconductor layer;
Forming a third semiconductor layer doped with an impurity element to be p-type on the second semiconductor layer;
Removing the third semiconductor layer in a region excluding a region where a gate electrode is formed in the third semiconductor layer;
Forming the gate electrode on the third semiconductor layer;
Forming a source electrode and a drain electrode in contact with the second semiconductor layer;
Have
The step of forming the third semiconductor layer includes a first growth step and a second growth step performed after the first growth step,
The substrate temperature in the first growth step is higher than any of the substrate temperature in the second growth step, and the substrate temperature when forming the first semiconductor layer and the second semiconductor layer. A method of manufacturing a semiconductor device.   The temperature of the substrate in the second growth step is substantially the same as the temperature of the substrate when forming the first semiconductor layer and the second semiconductor layer. Semiconductor device manufacturing method.   The semiconductor device according to claim 1, wherein the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are formed by MOVPE. Method.   5. The method of manufacturing a semiconductor device according to claim 1, wherein the impurity element to be p-type is Mg or Be. A first semiconductor layer formed on the substrate;
A second semiconductor layer formed on the first semiconductor layer;
A third semiconductor layer formed on the second semiconductor layer;
A gate electrode formed on the third semiconductor layer;
A source electrode and a drain electrode formed in contact with the second semiconductor layer;
Have
The third semiconductor layer is formed in a region immediately below the gate electrode by a semiconductor material doped with an impurity element which becomes p-type,
The semiconductor device, wherein the second semiconductor layer includes a region in which the concentration of the impurity element to be p-type is higher than the concentration of hydrogen.   The semiconductor device according to claim 6, wherein the third semiconductor layer is doped with a p-type impurity element in a material containing GaN.   The semiconductor device according to claim 6, wherein the impurity element to be p-type is Mg or Be.