JP2017085056A - Compound semiconductor epitaxial substrate and compound semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a compound semiconductor epitaxial substrate and a compound semiconductor device and the like capable of suppressing a leakage current of a GaN-based HEMT.SOLUTION: A compound semiconductor epitaxial substrate 100 includes a GaN substrate 101, and a GaN-based epitaxial layer 109 on the substrate 101. A dislocation density of the epitaxial layer 109 is equal to or less than 7×10cm.SELECTED DRAWING: Figure 8

Description

  The present invention relates to a compound semiconductor epitaxial substrate, a compound semiconductor device, and the like.

  A nitride semiconductor has characteristics such as a high saturation electron velocity and a wide band gap. For this reason, various studies have been conducted on applying nitride semiconductors to high breakdown voltage and high output semiconductor devices using these characteristics. For example, the band gap of GaN, which is a kind of nitride semiconductor, is 3.4 eV, which is larger than the band gap of Si (1.1 eV) and the band gap of GaAs (1.4 eV). For this reason, GaN has a high breakdown electric field strength and is extremely promising as a material for a semiconductor device for a power supply that obtains high voltage operation and high output.

  As semiconductor devices using nitride semiconductors, many reports have been made on field effect transistors, particularly high electron mobility transistors (HEMT). For example, in GaN-based HEMTs, attention is focused on AlGaN / GaN-HEMTs using GaN as a channel layer and AlGaN as a carrier supply layer (barrier layer). In AlGaN / GaN-HEMT, strain is generated in AlGaN due to the difference in lattice constant between GaN and AlGaN. A high-concentration two-dimensional electron gas (2DEG) is obtained by the piezoelectric polarization generated by this strain and the spontaneous polarization of AlGaN.

In recent years, an InAlN / GaN-HEMT using InAlN as a carrier supply layer has also been studied. Since InAlN has a spontaneous polarization stronger than that of AlGaN, a high concentration of 2DEG can be obtained even if the InAlN layer is thin. In _0.17 Al _0.83 N lattice matches with GaN. For this reason, compared with AlGaN / GaN-HEMT, the access resistance between a source and a gate and the access resistance between a gate and a drain can be made low. Further, the thinner the carrier supply layer, the shorter the distance between the gate electrode and 2DEG, so that higher transconductance (g _m ) can be obtained. Against this background, InAlN / GaN-HEMT is expected as a high-performance HEMT than AlGaN / GaN-HEMT.

  However, the conventional GaN-based HEMT has a problem that the gate leakage current is large.

JP 2010-180081 A JP 2006-52102 A

  An object of the present invention is to provide a compound semiconductor epitaxial substrate, a compound semiconductor device, and the like that can suppress the leakage current of a GaN-based HEMT.

One embodiment of the compound semiconductor epitaxial substrate includes a GaN substrate and a GaN-based epitaxial layer on the substrate. The dislocation density of the epitaxial layer is 7 × 10 ⁷ cm ⁻² or less.

  One aspect of the compound semiconductor device includes the above-described compound semiconductor epitaxial substrate and a source electrode, a gate electrode, and a drain electrode above the compound semiconductor epitaxial substrate.

  In one aspect of the method for producing a compound semiconductor epitaxial substrate, the surface of the GaN substrate is heat-treated in a chamber to form a GaN-based epitaxial layer on the substrate. At the time of performing the heat treatment, atomic nitrogen is generated outside the chamber, and the atomic nitrogen is supplied into the chamber.

  In one aspect of the method for manufacturing a compound semiconductor device, a compound semiconductor epitaxial substrate is manufactured by the above-described method, and a source electrode, a gate electrode, and a drain electrode are formed above the compound semiconductor epitaxial substrate.

  According to the above compound semiconductor device and the like, since an appropriate epitaxial layer is included, the leakage current can be suppressed.

It is a figure which shows the image obtained by electric current AFM observation. It is a figure which shows the image obtained by the cross-sectional TEM analysis. It is a figure which shows the relationship between a dislocation density and leakage current. It is a figure which shows the AFM image of the surface of a GaN substrate. It is a schematic diagram which shows the mechanism in which Ga grain is formed. It is a figure which shows the mechanism in which a dislocation | rearrangement generate | occur | produces in an epitaxial layer. It is a figure which shows the relationship between N / Ga ratio and a dislocation density. It is a figure showing a compound semiconductor epitaxial substrate and a compound semiconductor device concerning a 1st embodiment. It is a figure which shows the Ids-Vds characteristic of a compound semiconductor device. It is sectional drawing which shows the modification of 1st Embodiment. It is a figure which shows the relationship between N / Ga ratio and drain current ratio. It is a schematic diagram which shows the structure of the heat processing apparatus. It is a figure which shows the AFM image of the surface of a GaN substrate. It is a figure which shows the mechanism in which a dislocation | rearrangement generate | occur | produces in an epitaxial layer. It is sectional drawing which shows the manufacturing method of the compound semiconductor epitaxial substrate which concerns on 1st Embodiment, and a compound semiconductor device in process order. It is sectional drawing which shows the other modification of 1st Embodiment. It is a figure which shows the discrete package which concerns on 2nd Embodiment. It is a connection diagram which shows the PFC circuit which concerns on 3rd Embodiment. It is a connection diagram which shows the power supply device which concerns on 4th Embodiment. It is a connection diagram which shows the amplifier which concerns on 5th Embodiment.

  The inventors of the present application conducted various experiments to solve the above problems. These experiments will be described.

  The inventors of the present application focused on the relationship between leakage current and threading dislocation, and performed current AFM observation using an atomic force microscope (AFM). Unlike normal AFM observation, the current AFM observation uses a conductive cantilever coated with a conductive metal, and applies a constant bias between the probe and the sample, for example, a bias of about 10 V or less. Scan the surface. By performing this scanning while measuring the current, an image representing the current distribution can be obtained together with the image representing the shape of the surface of the sample. For this reason, according to the current AFM observation, the relationship between the micro leak current path and the surface shape can be obtained directly. FIG. 1 shows an image obtained by current AFM observation. FIG. 1A shows an image reflecting the shape of the surface of the sample, and FIG. 1B shows an image reflecting the current distribution. FIG. 1A and FIG. 1B show images of the same field of view. Pits were observed at locations indicated by arrows in FIG. 1A, and leakage current paths were observed at locations indicated by arrows in FIG. As shown in FIG. 1, the position of the pit coincides with the position of the leakage current path.

  The inventors of the present application performed cross-sectional TEM analysis of the pits using a transmission electron microscope (TEM). FIG. 2 shows an image obtained by cross-sectional TEM analysis. As shown in FIG. 2, screw dislocations or mixed dislocations of screw dislocations and edge dislocations were observed under the pits appearing on the surface of the sample. Hereinafter, screw dislocations and mixed dislocations are sometimes collectively referred to as dislocations.

  Thus, it has been clarified that the dislocation is a leakage current path.

Further, as a result of investigating the magnitude of the influence of the dislocation on the leakage current, the shape of the pit caused by the dislocation on the sample surface can be approximated to a circle having a radius r of 25 nm on average, and the unit via the dislocation The magnitude of the leakage current per area was found to be about 1000 times the magnitude of the leakage current per unit area through the portion other than the dislocation. Based on these, the relationship between the dislocation density and the magnitude of the leak current via the dislocation and the magnitude of the leak current via the portion other than the dislocation was obtained. When the dislocation density is set to "1" the magnitude of the leakage current of the sample surface 1 cm ² per in the case of 0 cm ^-2, if the dislocation density ρ (cm ^-2), in the area of the sample surface 1 cm ^2, the dislocation The magnitude of the leakage current passing through is expressed by “1000 × πr ² × ρ” (cm ⁻² ), and the magnitude of the leakage current passing through the remainder is “1 × (1-πr ² × ρ)” (cm ⁻² ) It is represented by The results of graphing these are shown in FIG. As shown in FIG. 3, as the dislocation density increases, the leakage current via the dislocation increases monotonously. On the other hand, the leakage current through the balance is almost constant when the dislocation density is 1 × 10 ⁹ cm ⁻² or less, and gradually decreases when the dislocation density exceeds 1 × 10 ⁹ cm ⁻² . This is because when the dislocation density exceeds 1 × 10 ⁹ cm ⁻² , dislocations are present in most of the sample. Furthermore, as shown in FIG. 3, it has been clarified that the magnitude of the leakage current via the dislocation is larger than the magnitude of the leakage current via the remainder in the range where the dislocation density exceeds 7 × 10 ⁷ cm ⁻² . This means that if the dislocation density is 7 × 10 ⁷ cm ⁻² or less, the influence of the leakage current via the dislocation is smaller than the influence of the leakage current via the remainder. Therefore, in order to reduce the leakage current, it is important to set the dislocation density to 7 × 10 ⁷ cm ⁻² or less.

The inventors of the present application have made extensive studies to achieve a dislocation density of 7 × 10 ⁷ cm ⁻² or less. In order to reduce the dislocation density of the GaN-based epitaxial layer, it is effective to use a GaN substrate. However, as shown in FIG. 4 (a), a large number of polishing flaws caused by polishing after cutting are present on the surface of the conventional GaN substrate, so that a GaN-based epitaxial layer with high crystallinity is grown as it is. I can't let you. Polishing flaws can be removed by performing heat treatment in a high-temperature environment using hydrogen (H ₂ ) gas or a mixed gas of nitrogen (N ₂ ) gas and ammonia (NH ₃ ) gas. As shown in FIG. 4B, Ga particles are present on the surface of the GaN substrate. 4A and 4B show AFM images.

Here, the mechanism by which Ga grains are formed will be described. FIG. 5 is a schematic diagram showing the mechanism by which Ga grains are formed. The GaN substrate 1 is placed on the stage 10 and subjected to heat treatment. NH ₃ gas is used for supplying atomic nitrogen to the surface of the GaN substrate 1, but NH ₃ molecules are chemically stable, and the thermal decomposition efficiency of NH ₃ molecules is low. For example, atomic nitrogen 12 is obtained from a part of the supplied NH ₃ molecule 11 and is adsorbed on the surface of the GaN substrate 1, but a part of the NH ₃ molecule 11 is discharged as it is. On the other hand, N atoms 13 are desorbed from the surface of the GaN substrate 1 in a high temperature environment. For this reason, when the supply amount of atomic nitrogen 12 to the surface of the GaN substrate 1 is smaller than the desorption amount of N atoms 13, Ga atoms remain on the surface of the GaN substrate 1 and aggregate to form Ga droplets. To do. When the Ga droplet is solidified, Ga particles 14 are formed. In addition, N vacancy defects are generated on the surface of the GaN substrate 1 as the N atoms 13 are desorbed.

  If a GaN-based epitaxial layer is grown on a GaN substrate where Ga grains remain and N-vacancy defects exist, good crystallinity cannot be obtained. That is, as shown in FIG. 6, when Ga grains 14 exist on the surface of the GaN substrate 1 and there are low N regions 15 containing N vacancy defects at high density, dislocations 16 included in the GaN substrate 1 Even if few, the GaN epitaxial layer 2 contains a large number of dislocations 17 starting from Ga grains 14 or N-vacancy defects.

FIG. 7 shows the relationship between the N / Ga ratio on the surface of the GaN substrate and the dislocation density of the epitaxial layer. The N / Ga ratio indicates the amount of N atoms when the amount of Ga atoms is 1, and is ideally 1. As shown in FIG. 7, when the N / Ga ratio is 0.95, the dislocation density changes greatly. If the N / Ga ratio is 0.95 or more, the dislocation density is 7 × 10 ⁷ cm ⁻² or less. It is feasible.

Thus, by using a GaN substrate having an N / Ga ratio of 0.95 or more on the surface, an epitaxial layer having a dislocation density of 7 × 10 ⁷ cm ⁻² or less can be obtained, and the leakage current can be sufficiently suppressed. It turns out that you can. Although details will be described later, supplying atomic nitrogen from the plasma apparatus into the furnace in the heat treatment for removing the polishing flaws is effective in realizing an N / Ga ratio of 0.95 or more. found.

  As a result of further intensive studies based on these new findings, the inventors have arrived at the following embodiment.

  Hereinafter, embodiments will be described in detail with reference to the accompanying drawings.

(First embodiment)
First, the first embodiment will be described. The first embodiment relates to a compound semiconductor epitaxial substrate and an example of a HEMT using the same. FIG. 8 is a diagram illustrating the compound semiconductor epitaxial substrate and the compound semiconductor device according to the first embodiment.

As shown in FIG. 8A, the compound semiconductor epitaxial substrate 100 according to the first embodiment includes a GaN substrate 101, a channel layer 104 on the substrate 101, a spacer layer 105 on the channel layer 104, and a spacer layer. A carrier supply layer 106 on 105 is included. The channel layer 104 is, for example, a GaN layer (i-GaN layer) having a thickness of about 1 μm and not intentionally doped with impurities. The spacer layer 105 is, for example, an AlN layer (i-AlN layer) having a thickness of about 1 nm and not intentionally doped with impurities. The carrier supply layer 106 is, for example, an In _0.17 Al _0.83 N layer (i-InAlN layer) having a thickness of about 10 nm and not intentionally doped with impurities. The spacer layer 105 or the carrier supply layer 106 or both of them may be doped with an n-type impurity such as Si. The channel layer 104, the spacer layer 105, and the carrier supply layer 106 are included in the GaN-based epitaxial layer 109. The dislocation density of the epitaxial layer 109 is 7 × 10 ⁷ cm ⁻² or less, preferably 1 × 10 ⁵ cm ⁻² or less. Preferably, the N / Ga ratio in part of the substrate 101 on the epitaxial layer 109 side is 0.95 or more.

  As shown in FIG. 8B, the compound semiconductor device 120 according to the first embodiment includes a compound semiconductor epitaxial substrate 100, and a source electrode 110s, a gate electrode 110g, and a drain electrode 110d on the compound semiconductor epitaxial substrate 100. included. The source electrode 110s and the drain electrode 110d include, for example, a Ti film and an Al film thereon, and are in ohmic contact with the compound semiconductor epitaxial substrate 100. The gate electrode 110g includes, for example, a Ni film and an Au film thereon, and is in Schottky contact with the compound semiconductor epitaxial substrate 100.

  According to the first embodiment, the leakage current can be reduced as is apparent from the above experimental results.

In the compound semiconductor device 120 according to the first embodiment, the current collapse can be reduced. FIG. 9A shows the Ids-Vds characteristics of the compound semiconductor device 120, and FIG. 9B shows the Ids-Vds characteristics of the compound semiconductor device of the reference example. In the reference example, the N / Ga ratio in a part of the epitaxial layer side of the GaN substrate is less than 0.95, and the dislocation density of the epitaxial layer is more than 7 × 10 ⁷ cm ⁻² . In DC measurement, DC voltage measurement was performed, and in pulse measurement, the drain current was measured by instantaneously changing the voltage from the stress application holding bias to each measurement point. The stress application holding bias was off-stress, the source-gate voltage Vgs was -5V, and the source-drain voltage Vds was 50V. As shown in FIG. 9, the difference between the DC measurement result and the pulse measurement result in the compound semiconductor device 120 is significantly smaller than that in the reference example. This means that current collapse is greatly suppressed in the compound semiconductor device 120. The effect of suppressing current collapse is obtained when the N / Ga ratio in a part of the substrate on the epitaxial layer side is 0.95 or more and the concentration of N vacancy defects in the vicinity of the interface with the epitaxial layer is low. Since electrons are not easily trapped in the defect level of the N vacancy during the operation of the HEMT, current collapse is suppressed.

  As shown in FIG. 10A, a cap layer 107 may be formed on the carrier supply layer 106 in any of the compound semiconductor epitaxial substrate and the compound semiconductor device. The cap layer 107 is an n-type GaN layer (n-GaN layer) having a thickness of about 5 nm, for example. The GaN cap layer may be a GaN layer (i-GaN layer) that is not intentionally doped with impurities. As shown in FIG. 10B, an insulating film 108 may be formed on the cap layer 107 in both the compound semiconductor epitaxial substrate and the compound semiconductor device. The insulating film 108 is, for example, an aluminum oxide film. In the compound semiconductor device, an opening for the source electrode 110 s and an opening for the drain electrode 110 d are formed in the insulating film 108, and the source electrode 110 s and the drain electrode 110 d are in contact with the cap layer 107. As shown in FIG. 10C, an opening for the source electrode 110s and an opening for the drain electrode 110d are also formed in the cap layer 107, and the source electrode 110s and the drain electrode 110d are in contact with the carrier supply layer 106. Also good.

  As described above, the N / Ga ratio on the surface of the substrate 1 of GaN is 0.95 or more, and the N / Ga ratio of 1.00 or less is sufficient for suppressing dislocation accompanying the desorption of N atoms. is there. On the other hand, if the N / Ga ratio is greater than 1.05, the stability of the current flowing through the HEMT tends to be reduced. For this reason, it is preferable that N / Ga ratio is 1.05 or less. An N / Ga ratio exceeding 1.00 means that Ga vacancy defects exist on the surface of the substrate 1, and the Ga vacancy defects are negatively captured by capturing electrons as acceptor-type point defects. Charge up and HEMT current stability decreases.

Here, the simulation performed by the present inventors will be described. In this simulation, the source-gate distance is 1 μm, the gate length is 1.5 μm, the gate-drain distance is 3 μm, the source-gate voltage Vgs before stress application is −1 V, and the source-drain distance The voltage Vds was 30 V, the voltage Vgs at the time of applying stress was −10 V, and the voltage Vds was 100 V. The stress application time was 10 msec. The voltage was returned to the voltage before applying stress after applying stress, and the current value after 1 msec was taken as the drain current value I _d after applying stress, and the ratio (I _d / I _d0 ) to the drain current value I _d0 before applying stress was calculated. The result is shown in FIG. The closer the value of this ratio is to 1.0, the smaller the fluctuation of the drain current value and the higher the current stability.

As shown in FIG. 11, the drain current ratio changes greatly with an N / Ga ratio of 1.05 as a boundary. If the N / Ga ratio is 1.05 or less, a significantly high drain current ratio can be obtained. The higher the N / Ga ratio, the higher the density of Ga vacancy defects, the more easily electrons are captured by Ga vacancy defects, and the potential at the interface with the epitaxial layer is raised. When the density of Ga vacancy defects reaches a certain critical value, the interface potential reaches the two-dimensional electron gas (2DEG), and the drain current ratio rapidly decreases. From the result of this simulation, the critical value is about 1.05. Therefore, from the viewpoint of the stability of the current flowing through the HEMT, the N / Ga ratio is preferably 1.05 or less. When the N / Ga ratio is 1.06 or more, the change in drain current ratio is gradual. However, if the potential at the interface rises to some extent, holes are generated at the interface thereafter, and the potential fluctuation further increases. This is because it is suppressed. Even if the N / Ga ratio is 1.00, the drain current ratio is less than 1.0. This is unavoidably caused by the carbon contained in the channel layer at a concentration of about 5 × 10 ¹⁵ cm ^−3. This is due to current collapse.

  Next, a heat treatment apparatus used for manufacturing the compound semiconductor epitaxial substrate and the compound semiconductor device according to the first embodiment will be described. FIG. 12 is a schematic diagram showing the configuration of the heat treatment apparatus.

The heat treatment apparatus includes a plasma generator 30, an ion trap 40, and a metal organic chemical vapor deposition (MOCVD) apparatus 50. In the plasma generator 30, atomic nitrogen 31 is generated using NH ₃ gas. It is preferable to use an electron cyclotron resonance (ECR) plasma generator as the plasma generator 30. This is because plasma can be generated at a high density. In order to stabilize the plasma state, it is preferable to introduce, for example, argon (Ar) gas and N ₂ gas into the plasma generator 30 at a ratio of 8 to 2. If the plasma state is stable, only N ₂ gas may be introduced without introducing Ar gas. The ion trap 40 includes a cathode 41 and an anode 42. By applying a voltage of about several volts to several tens of volts between them, the charged ions 43 are removed. Since the atomic nitrogen 31 is not charged, it passes through the ion trap 40. The atomic nitrogen 31 that has passed through the ion trap 40 is supplied to the MOCVD apparatus 50. The MOCVD apparatus 50 is also supplied with a H ₂ gas or a mixed gas of N ₂ gas and NH ₃ gas. In the MOCVD apparatus 50, the GaN substrate 1 is placed on the stage 10 and heat treatment is performed. For example, the heat treatment temperature is about 1000 ° C. and the time is about 10 minutes. By using this heat treatment apparatus, the density of the atomic nitrogen 12 adsorbed on the surface of the GaN substrate 1 is dramatically improved, and polishing scratches on the surface of the GaN substrate 1 can be removed while suppressing the generation of Ga particles. . The MOCVD apparatus 50 is an example of a chamber. FIG. 13 shows an AFM image of the surface of the GaN substrate after the heat treatment using the heat treatment apparatus shown in FIG. As shown in FIG. 13, the polishing scratches observed in FIG. 4 (a) and the Ga particles observed in FIG. 4 (b) are not observed. For this reason, as shown in FIG. 14, dislocations starting from the interface between the GaN substrate 1 and the epitaxial layer 2 hardly occur. If the dislocations 16 included in the GaN substrate 1 are small, the dislocations included in the epitaxial layer 2 are present. There are few.

  Next, a method for manufacturing a compound semiconductor epitaxial substrate and a compound semiconductor device according to the first embodiment will be described. FIG. 15 is a cross-sectional view illustrating the compound semiconductor epitaxial substrate and the method for manufacturing the compound semiconductor device according to the first embodiment in the order of steps.

  First, a GaN substrate 101 is prepared, and polishing scratches existing on the surface of the substrate 101 are removed by heat treatment using a heat treatment apparatus shown in FIG. According to this heat treatment, polishing flaws can be removed while suppressing the formation of Ga grains and the formation of a low N region having an N / Ga ratio of less than 0.95.

Next, as shown in FIG. 15A, an epitaxial layer 109 including a channel layer 104, a spacer layer 105, and a carrier supply layer 106 is formed on the substrate 101. The channel layer 104, the spacer layer 105, and the carrier supply layer 106 can be formed by a crystal growth method such as an MOCVD method or a molecular beam epitaxy (MBE) method. For example, a mixed gas of trimethylaluminum (TMA) gas, trimethylgallium (TMG) gas, trimethylindium (TMI) gas, and ammonia (NH ₃ ) gas is used as the source gas, and nitrogen (N ₂ ) gas is used as the carrier gas. The presence / absence of supply of TMA gas, TMG gas, and TMI gas and the flow rate are appropriately set according to the compound semiconductor layer to be formed. The supply amount of NH ₃ gas is, for example, about 100 ccm (cubic centimeter per minute) to 10 Lm (liter per minute). The growth pressure is about 50 Torr to 300 Torr, and the growth temperature is about 1000 ° C. to 1200 ° C.

In this way, the compound semiconductor epitaxial substrate 100 according to the first embodiment can be manufactured. Since the epitaxial layer 109 is formed after the heat treatment using the heat treatment apparatus shown in FIG. 12, the dislocation density of the epitaxial layer 109 is 7 × 10 ⁷ cm ⁻² or less.

  The channel layer 104 may be doped with Fe or C. In the portion doped with Fe or C, the potential is raised and the wraparound of electrons can be suppressed. When impurities are doped on the channel layer 104, current collapse is likely to occur. For this reason, Fe or C may be doped at the initial stage of formation of the channel layer 104, and then doping may be stopped.

  When a GaN layer is formed at a low pressure or a low V / III ratio or both, it is easy to grow in the lateral direction, and thus high flatness is easily obtained. Therefore, at the initial stage of formation of the channel layer 104, the pressure in the chamber and the V / III ratio of the source gas may be lowered, and then the pressure in the chamber and the V / III ratio of the source gas may be increased.

When manufacturing a compound semiconductor device, an element isolation region that defines an element region is formed in the compound semiconductor epitaxial substrate 100. In the formation of the element isolation region, for example, a photoresist pattern exposing the region where the element isolation region is to be formed is formed on the carrier supply layer 106, and ion implantation of Ar or the like is performed using this pattern as a mask. Dry etching using a chlorine-based gas may be performed using this pattern as an etching mask. Thereafter, in the element region, as illustrated in FIG. 15B, the source electrode 110 s and the drain electrode 110 d are formed on the carrier supply layer 106. The source electrode 110s and the drain electrode 110d can be formed by, for example, a lift-off method. That is, a region where the source electrode 110s is to be formed and a region where the drain electrode 110d is to be formed are exposed, and a photoresist pattern covering the other region is formed. Then, the pattern is removed together with the metal film thereon. In the formation of the metal film, for example, a Ti film having a thickness of about 100 nm is formed, and an Al film having a thickness of about 300 nm is formed thereon. Next, for example, heat treatment such as rapid thermal annealing (RTA) is performed at 400 ° C. to 800 ° C. (for example, 600 ° C.) in an N ₂ gas atmosphere to obtain ohmic contact. Further, as shown in FIG. 15C, a gate electrode 110g is formed on the carrier supply layer 106 between the source electrode 110s and the drain electrode 110d. The gate electrode 110g can be formed by, for example, a lift-off method. That is, a photoresist pattern exposing a region where the gate electrode 110g is to be formed is formed, a metal film is formed by vapor deposition using this pattern as a growth mask, and this pattern is removed together with the metal film thereon. In the formation of the metal film, for example, a Ni film having a thickness of about 50 nm is formed, and an Au film having a thickness of about 300 nm is formed thereon.

  And a protective film, wiring, etc. are formed as needed and a compound semiconductor device is completed.

  As shown in FIG. 16A, the epitaxial layer 109 preferably includes a doping layer 201 doped with Fe, Mg, C, or any combination thereof below the channel layer 104. This is because even if the substrate 101 is conductive, off-leakage can be reduced.

  In the heat treatment of the substrate 101, it is preferable to supply TMI into the MOCVD apparatus 50. Since the surface migration length of In is longer than that of Ga, the surfactant effect can be obtained by supplying TMI, and more excellent flatness can be obtained. The bond between In and N is weak, and the InN film does not substantially grow under a high temperature environment of about 1000 ° C., but a small amount of In202 remains segregated on the GaN substrate as shown in FIG. obtain.

  It is preferable to supply TMA into the MOCVD apparatus 50 for the heat treatment of the substrate 101. Since the bond between Al and N is strong, as shown in FIG. 16C, an AlN-containing layer 203 containing Al and N is formed on the surface of the substrate 101 by supplying TMA, and the AlN-containing layer 203 is formed of GaN. Detachment of N atoms from the surface of the substrate 101 is suppressed. For this reason, generation | occurrence | production of Ga droplet is suppressed and formation of Ga particle is suppressed. The compound semiconductor epitaxial substrate formed in this way includes the AlN-containing layer 203 on the substrate 101.

(Second Embodiment)
Next, a second embodiment will be described. The second embodiment relates to a HEMT discrete package. FIG. 17 is a diagram illustrating a discrete package according to the second embodiment.

  In the second embodiment, as shown in FIG. 17, the back surface of the HEMT chip 1210 of the HEMT of the first embodiment is fixed to a land (die pad) 1233 using a die attach agent 1234 such as solder. A wire 1235d such as an Al wire is connected to the drain pad 1226d to which the drain electrode 110d is connected, and the other end of the wire 1235d is connected to a drain lead 1232d integrated with the land 1233. A wire 1235 s such as an Al wire is connected to the source pad 1226 s connected to the source electrode 110 s, and the other end of the wire 1235 s is connected to a source lead 1232 s independent of the land 1233. A wire 1235g such as an Al wire is connected to the gate pad 1226g connected to the gate electrode 110g, and the other end of the wire 1235g is connected to a gate lead 1232g independent of the land 1233. The land 1233, the HEMT chip 1210, and the like are packaged with the mold resin 1231 so that a part of the gate lead 1232g, a part of the drain lead 1232d, and a part of the source lead 1232s protrude.

  Such a discrete package can be manufactured as follows, for example. First, the HEMT chip 1210 is fixed to the land 1233 of the lead frame using a die attach agent 1234 such as solder. Next, by bonding using wires 1235g, 1235d, and 1235s, the gate pad 1226g is connected to the gate lead 1232g of the lead frame, the drain pad 1226d is connected to the drain lead 1232d of the lead frame, and the source pad 1226s is connected to the source of the lead frame. Connect to lead 1232s. Thereafter, sealing using a mold resin 1231 is performed by a transfer molding method. Subsequently, the lead frame is separated.

(Third embodiment)
Next, a third embodiment will be described. The third embodiment relates to a PFC (Power Factor Correction) circuit including a HEMT. FIG. 18 is a connection diagram illustrating a PFC circuit according to the third embodiment.

  The PFC circuit 1250 is provided with a switch element (transistor) 1251, a diode 1252, a choke coil 1253, capacitors 1254 and 1255, a diode bridge 1256, and an AC power supply (AC) 1257. The drain electrode of the switch element 1251 is connected to the anode terminal of the diode 1252 and one terminal of the choke coil 1253. A source electrode of the switch element 1251 is connected to one terminal of the capacitor 1254 and one terminal of the capacitor 1255. The other terminal of the capacitor 1254 and the other terminal of the choke coil 1253 are connected. The other terminal of the capacitor 1255 and the cathode terminal of the diode 1252 are connected. A gate driver is connected to the gate electrode of the switch element 1251. An AC 1257 is connected between both terminals of the capacitor 1254 via a diode bridge 1256. A direct current power supply (DC) is connected between both terminals of the capacitor 1255. In this embodiment, the HEMT of the first embodiment is used for the switch element 1251.

  In manufacturing the PFC circuit 1250, the switch element 1251 is connected to the diode 1252, the choke coil 1253, and the like using, for example, solder.

(Fourth embodiment)
Next, a fourth embodiment will be described. The fourth embodiment relates to a power supply device including a HEMT. FIG. 19 is a connection diagram illustrating a power supply device according to the fourth embodiment.

  The power supply device is provided with a high-voltage primary circuit 1261 and a low-voltage secondary circuit 1262, and a transformer 1263 disposed between the primary circuit 1261 and the secondary circuit 1262.

  The primary circuit 1261 is provided with an inverter circuit connected between both terminals of the PFC circuit 1250 according to the third embodiment and the capacitor 1255 of the PFC circuit 1250, for example, a full bridge inverter circuit 1260. The full bridge inverter circuit 1260 is provided with a plurality (here, four) of switch elements 1264a, 1264b, 1264c, and 1264d.

  The secondary side circuit 1262 is provided with a plurality (three in this case) of switch elements 1265a, 1265b, and 1265c.

  In the present embodiment, the HEMT of the first embodiment is used for the switch element 1251 of the PFC circuit 1250 and the switch elements 1264a, 1264b, 1264c, and 1264d of the full bridge inverter circuit 1260 that constitute the primary circuit 1261. . On the other hand, normal MIS type FETs (field effect transistors) using silicon are used for the switch elements 1265a, 1265b, and 1265c of the secondary side circuit 1262.

(Fifth embodiment)
Next, a fifth embodiment will be described. The fifth embodiment relates to an amplifier including a HEMT. FIG. 20 is a connection diagram illustrating an amplifier according to the fifth embodiment.

  The amplifier is provided with a digital predistortion circuit 1271, mixers 1272a and 1272b, and a power amplifier 1273.

  The digital predistortion circuit 1271 compensates for nonlinear distortion of the input signal. The mixer 1272a mixes the input signal compensated for nonlinear distortion and the AC signal. The power amplifier 1273 includes the HEMT according to the first embodiment, and amplifies the input signal mixed with the AC signal. In the present embodiment, for example, by switching the switch, the signal on the output side can be mixed with the AC signal by the mixer 1272b and sent to the digital predistortion circuit 1271. This amplifier can be used as a high-frequency amplifier or a high-power amplifier. The high-frequency amplifier can be used in, for example, a mobile phone base station transceiver device, a radar device, and a microwave generator.

  Hereinafter, various aspects of the present invention will be collectively described as supplementary notes.

(Appendix 1)
A GaN substrate;
A GaN-based epitaxial layer on the substrate;
Have
A compound semiconductor epitaxial substrate, wherein the dislocation density of the epitaxial layer is 7 × 10 ⁷ cm ⁻² or less.

(Appendix 2)
The compound semiconductor epitaxial substrate according to appendix 1, wherein an N / Ga ratio in a part of the substrate on the epitaxial layer side is 0.95 or more.

(Appendix 3)
The compound semiconductor epitaxial substrate according to appendix 1 or 2, wherein the epitaxial layer includes a channel layer and a carrier supply layer.

(Appendix 4)
The compound semiconductor epitaxial substrate according to appendix 3, wherein the epitaxial layer has a layer doped with Fe, Mg, C, or any combination thereof between the channel layer and the substrate.

(Appendix 5)
The compound semiconductor epitaxial substrate according to any one of appendices 1 to 4, wherein In is segregated on the substrate.

(Appendix 6)
5. The compound semiconductor epitaxial substrate according to any one of appendices 1 to 4, further comprising a layer containing Al and N on the substrate.

(Appendix 7)
The compound semiconductor epitaxial substrate according to any one of appendices 1 to 6, wherein an N / Ga ratio in a part of the substrate on the epitaxial layer side is 0.95 or more and 1.05 or less.

(Appendix 8)
The compound semiconductor epitaxial substrate according to any one of appendices 1 to 7,
A source electrode, a gate electrode and a drain electrode above the compound semiconductor epitaxial substrate;
A compound semiconductor device comprising:

(Appendix 9)
A power supply device comprising the compound semiconductor device according to appendix 8.

(Appendix 10)
An amplifier comprising the compound semiconductor device according to appendix 8.

(Appendix 11)
Heat treating the surface of the GaN substrate in the chamber;
Forming a GaN-based epitaxial layer on the substrate;
Have
The step of performing the heat treatment includes
Generating atomic nitrogen outside the chamber;
Supplying the atomic nitrogen into the chamber;
A method for producing a compound semiconductor epitaxial substrate, comprising:

(Appendix 12)
The method of manufacturing a compound semiconductor epitaxial substrate according to appendix 11, wherein the step of forming the epitaxial layer includes a step of forming a channel layer and a carrier supply layer.

(Appendix 13)
The step of forming the epitaxial layer includes a step of forming a layer doped with Fe, Mg, C, or any combination thereof between the channel layer and the substrate. The manufacturing method of the compound semiconductor epitaxial substrate of description.

(Appendix 14)
14. The method of manufacturing a compound semiconductor epitaxial substrate according to any one of appendices 11 to 13, wherein in the step of supplying the atomic nitrogen into the chamber, an In raw material is also supplied into the chamber.

(Appendix 15)
14. The method of manufacturing a compound semiconductor epitaxial substrate according to any one of appendices 11 to 13, wherein in the step of supplying the atomic nitrogen into the chamber, an Al raw material is also supplied into the chamber.

(Appendix 16)
A step of manufacturing a compound semiconductor epitaxial substrate by the method according to any one of appendices 11 to 15,
Forming a source electrode, a gate electrode and a drain electrode above the compound semiconductor epitaxial substrate;
A method for producing a compound semiconductor device, comprising:

30: Plasma generator 31: Atomic nitrogen 40: Ion trap 50: MOCVD apparatus 100: Compound semiconductor epitaxial substrate 101: Substrate 104: Channel layer 105: Spacer layer 106: Carrier supply layer 107: Cap layer 108: Insulating film 109: Epitaxial layer 110s: source electrode 110d: drain electrode 110g: gate electrode 120: compound semiconductor device

Claims (10)

A GaN substrate;
A GaN-based epitaxial layer on the substrate;
Have
A compound semiconductor epitaxial substrate, wherein the dislocation density of the epitaxial layer is 7 × 10 ⁷ cm ⁻² or less.   2. The compound semiconductor epitaxial substrate according to claim 1, wherein an N / Ga ratio in a part of the substrate on the epitaxial layer side is 0.95 or more.   The compound semiconductor epitaxial substrate according to claim 1, wherein the epitaxial layer includes a channel layer and a carrier supply layer.   4. The compound semiconductor epitaxial substrate according to claim 3, wherein the epitaxial layer includes a layer doped with Fe, Mg, C, or any combination thereof between the channel layer and the substrate. The compound semiconductor epitaxial substrate according to any one of claims 1 to 4,
A source electrode, a gate electrode and a drain electrode above the compound semiconductor epitaxial substrate;
A compound semiconductor device comprising:   A power supply device comprising the compound semiconductor device according to claim 5.   An amplifier comprising the compound semiconductor device according to claim 5. Heat treating the surface of the GaN substrate in the chamber;
Forming a GaN-based epitaxial layer on the substrate;
Have
The step of performing the heat treatment includes
Generating atomic nitrogen outside the chamber;
Supplying the atomic nitrogen into the chamber;
A method for producing a compound semiconductor epitaxial substrate, comprising:   9. The method of manufacturing a compound semiconductor epitaxial substrate according to claim 8, wherein the step of forming the epitaxial layer includes a step of forming a channel layer and a carrier supply layer. Producing a compound semiconductor epitaxial substrate by the method according to claim 8 or 9,
Forming a source electrode, a gate electrode and a drain electrode above the compound semiconductor epitaxial substrate;
A method for producing a compound semiconductor device, comprising: