JP2014179096A5 - - Google Patents

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Publication number
JP2014179096A5
JP2014179096A5 JP2014050469A JP2014050469A JP2014179096A5 JP 2014179096 A5 JP2014179096 A5 JP 2014179096A5 JP 2014050469 A JP2014050469 A JP 2014050469A JP 2014050469 A JP2014050469 A JP 2014050469A JP 2014179096 A5 JP2014179096 A5 JP 2014179096A5
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JP
Japan
Prior art keywords
reorder buffer
checkpoint
data
rename
renaming
Prior art date
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Application number
JP2014050469A
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English (en)
Japanese (ja)
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JP6399772B2 (ja
JP2014179096A (ja
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Priority claimed from US13/831,488 external-priority patent/US9448799B2/en
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Publication of JP2014179096A publication Critical patent/JP2014179096A/ja
Publication of JP2014179096A5 publication Critical patent/JP2014179096A5/ja
Application granted granted Critical
Publication of JP6399772B2 publication Critical patent/JP6399772B2/ja
Active legal-status Critical Current
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JP2014050469A 2013-03-14 2014-03-13 マイクロプロセッサ及び装置 Active JP6399772B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/831,488 US9448799B2 (en) 2013-03-14 2013-03-14 Reorder-buffer-based dynamic checkpointing for rename table rebuilding
US13/831,488 2013-03-14

Publications (3)

Publication Number Publication Date
JP2014179096A JP2014179096A (ja) 2014-09-25
JP2014179096A5 true JP2014179096A5 (enExample) 2017-04-13
JP6399772B2 JP6399772B2 (ja) 2018-10-03

Family

ID=51419101

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2014050469A Active JP6399772B2 (ja) 2013-03-14 2014-03-13 マイクロプロセッサ及び装置

Country Status (4)

Country Link
JP (1) JP6399772B2 (enExample)
KR (1) KR102010317B1 (enExample)
CN (1) CN104050027B (enExample)
DE (1) DE102014103183A1 (enExample)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9448800B2 (en) * 2013-03-14 2016-09-20 Samsung Electronics Co., Ltd. Reorder-buffer-based static checkpointing for rename table rebuilding

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5630149A (en) 1993-10-18 1997-05-13 Cyrix Corporation Pipelined processor with register renaming hardware to accommodate multiple size registers
WO1996025705A1 (en) * 1995-02-14 1996-08-22 Fujitsu Limited Structure and method for high-performance speculative execution processor providing special features
JP2000285082A (ja) * 1999-03-31 2000-10-13 Toshiba Corp 中央演算装置及びコンパイル方法
US6742112B1 (en) * 1999-12-29 2004-05-25 Intel Corporation Lookahead register value tracking
US6629233B1 (en) 2000-02-17 2003-09-30 International Business Machines Corporation Secondary reorder buffer microprocessor
US20060149931A1 (en) * 2004-12-28 2006-07-06 Akkary Haitham Runahead execution in a central processing unit
US20070043934A1 (en) * 2005-08-22 2007-02-22 Intel Corporation Early misprediction recovery through periodic checkpoints
US7747841B2 (en) 2005-09-26 2010-06-29 Cornell Research Foundation, Inc. Method and apparatus for early load retirement in a processor system
US7809926B2 (en) * 2006-11-03 2010-10-05 Cornell Research Foundation, Inc. Systems and methods for reconfiguring on-chip multiprocessors
US8909902B2 (en) * 2008-11-24 2014-12-09 Intel Corporation Systems, methods, and apparatuses to decompose a sequential program into multiple threads, execute said threads, and reconstruct the sequential execution
US9052890B2 (en) 2010-09-25 2015-06-09 Intel Corporation Execute at commit state update instructions, apparatus, methods, and systems

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