JP2014174431A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal display device capable of improving display quality.SOLUTION: The liquid crystal display device comprises: a first substrate including a first signal wiring, a second signal wiring intersecting the first signal wiring, a switching element electrically connected to the first signal wiring and the second signal wiring, a pixel electrode electrically connected to the switching element, and a first alignment film covering the pixel electrode; a second substrate including an insulating substrate, a color filter positioned on an inner surface of the insulating substrate opposite to the first substrate and facing the pixel electrode, an inner light-shielding layer positioned closer to the first substrate than the color filter and facing the first signal wiring and the second signal wiring, and a second alignment film covering the inner light-shielding layer and facing the first alignment film; and a liquid crystal layer containing liquid crystal molecules held in a cell gap between the first substrate and the second substrate.

Description

  Embodiments described herein relate generally to a liquid crystal display device.

  Liquid crystal display devices are used in various fields as display devices. A color display type liquid crystal display device includes blue, green, and red color filters formed in a stripe shape. The light shielding film is disposed between the color filters of different colors and plays a role of preventing color mixture in an oblique visual field.

  In recent years, there has been an increasing demand for a wider viewing angle for liquid crystal display devices. For this reason, color mixing countermeasures in an oblique visual field are extremely important, and various proposals have been made. On the other hand, color mixing countermeasures that increase the width of the light-shielding film cause a reduction in the area of the pixel opening, which may hinder high definition and high luminance.

JP 2010-271442 A

  An object of the present embodiment is to provide a liquid crystal display device capable of improving display quality.

According to this embodiment,
A first signal line; a second signal line intersecting the first signal line; a switching element electrically connected to the first signal line and the second signal line; and electrically connected to the switching element A first substrate having a pixel electrode and a first alignment film covering the pixel electrode, an insulating substrate, and an inner surface of the insulating substrate facing the first substrate, and facing the pixel electrode. A color filter, an inner light shielding layer positioned on the first substrate side with respect to the color filter and facing the first signal wiring and the second signal wiring, and covering the inner light shielding layer and facing the first alignment film There is provided a liquid crystal display device comprising: a second substrate including a second alignment film; and a liquid crystal layer including liquid crystal molecules held in a cell gap between the first substrate and the second substrate. .

FIG. 1 is a diagram schematically showing a configuration and an equivalent circuit of a liquid crystal display panel LPN constituting the liquid crystal display device of the present embodiment. FIG. 2 is a schematic plan view of the pixel structure of the array substrate AR shown in FIG. 1 as viewed from the counter substrate CT side. FIG. 3 is a diagram schematically showing a cross-sectional structure of the pixel PX1 shown in FIG. 2 cut along the line AB. FIG. 4 is a schematic cross-sectional view of a liquid crystal display panel LPN for explaining the limit angle of viewing angle color mixing. FIG. 5 is a diagram schematically showing another cross-sectional structure of the liquid crystal display panel LPN. FIG. 6 is a plan view schematically showing a structural example applicable to the liquid crystal display panel LPN of the present embodiment. FIG. 7 is a diagram schematically showing a cross-sectional structure of the liquid crystal display panel LPN cut along the line CD shown in FIG. FIG. 8 is a diagram schematically showing a cross-sectional structure of the liquid crystal display panel LPN cut along line EF shown in FIG.

  Hereinafter, the present embodiment will be described in detail with reference to the drawings. In each figure, the same reference numerals are given to components that exhibit the same or similar functions, and duplicate descriptions are omitted.

  FIG. 1 is a diagram schematically showing a configuration and an equivalent circuit of a liquid crystal display panel LPN constituting the liquid crystal display device of the present embodiment.

  That is, the liquid crystal display device includes an active matrix transmissive liquid crystal display panel LPN. The liquid crystal display panel LPN has an array substrate AR that is a first substrate, a counter substrate CT that is a second substrate disposed to face the array substrate AR, and a cell gap between the array substrate AR and the counter substrate CT. And a held liquid crystal layer LQ. The array substrate AR and the counter substrate CT are bonded together with a seal material SE. Such a liquid crystal display panel LPN is provided with an active area ACT for displaying an image on the inner side surrounded by the seal material SE. The active area ACT is composed of a plurality of pixels PX arranged in a matrix.

  In the active area ACT, the array substrate AR includes gate lines G (G1 to Gn) and auxiliary capacitance lines C (C1 to Cn) that extend in the first direction X, and a second direction that intersects the first direction X. The source line S (S1 to Sm) extending along Y, the switching element SW electrically connected to the gate line G and the source line S in each pixel PX, and the switching element SW in each pixel PX are electrically connected to the switching element SW. And a common electrode CE facing the pixel electrode PE. For example, the gate line G and the source line S correspond to a first signal line and a second signal line.

  Each gate line G is drawn outside the active area ACT and connected to the gate driver GD. Each source line S is drawn outside the active area ACT and connected to the source driver SD. Each auxiliary capacitance line C is drawn outside the active area ACT and is electrically connected to a voltage application unit VCS to which an auxiliary capacitance voltage is supplied. The common electrode CE is electrically connected to a power supply unit VS to which a common voltage is supplied. For example, at least a part of the gate driver GD and the source driver SD is formed on the array substrate AR, and is connected to the driving IC chip 2 as a signal source necessary for driving the liquid crystal display panel LPN. In the illustrated example, the drive IC chip 2 is mounted on the array substrate AR outside the active area ACT of the liquid crystal display panel LPN.

  Further, the liquid crystal display panel LPN of the illustrated example has a configuration applicable to the FFS mode or the IPS mode, and includes a pixel electrode PE and a common electrode CE on the array substrate AR. The common electrode CE is formed in common across the plurality of pixels PX. The pixel electrode PE is formed in an island shape in each pixel PX. In the liquid crystal display panel LPN having such a configuration, a horizontal electric field (for example, an electric field substantially parallel to the main surface of the substrate in the fringe electric field) formed between the pixel electrode PE and the common electrode CE is mainly used. The liquid crystal molecules constituting the liquid crystal layer LQ are switched.

  FIG. 2 is a schematic plan view of the pixel structure of the array substrate AR shown in FIG. 1 as viewed from the counter substrate CT side. Here, only main parts necessary for the description are shown.

  The gate wiring G1 and the gate wiring G2 extend along the first direction X, respectively. The source line S1 and the source line S2 extend along the second direction Y, respectively, and intersect the gate line G1 and the gate line G2. The pixel PX1 defined by the gate line G1, the gate line G2, the source line S1, and the source line S2 has a vertically long rectangular shape whose length along the first direction X is shorter than the length along the second direction Y. is there. The pixel PX2 is adjacent to the first direction X of the pixel PX1.

  In the pixel PX1, the switching element SW1 is located near the intersection between the gate line G2 and the source line S1, and is electrically connected to the gate line G2 and the source line S1. In the pixel PX2, the switching element SW2 is located near the intersection between the gate line G2 and the source line S2, and is electrically connected to the gate line G2 and the source line S2. The switching element SW1 and the switching element SW2 are, for example, thin film transistors (TFTs), and each includes a semiconductor layer SC.

  Here, the structure will be described by focusing on the switching element SW1. The switching element SW1 includes a gate electrode WG integrated with the gate line G2, a source electrode WS integrated with the source line S1, and a drain electrode WD. The source electrode WS is in contact with the semiconductor layer SC through the contact hole CH1. Drain electrode WD is in contact with semiconductor layer SC through contact hole CH2.

  For example, the common electrode CE extends along the first direction X, and is formed in common across a plurality of pixels PX adjacent in the first direction X. In the illustrated example, the common electrode CE passes above the source wirings S1 and S2, and is disposed in the pixel PX1 and the pixel PX2, respectively. Although not shown, the common electrode CE may be formed in common across a plurality of pixels PX adjacent in the second direction Y.

  The pixel electrode PE1 of the pixel PX1 and the pixel electrode PE2 of the pixel PX2 are respectively disposed above the common electrode CE. In the illustrated example, the pixel electrode PE1 and the pixel electrode PE2 are formed in a substantially rectangular shape whose length along the first direction X is shorter than the length along the second direction Y. The pixel electrode PE1 is in contact with the drain electrode WD of the switching element SW1 through the contact hole CH3. Similarly, the pixel electrode PE2 is electrically connected to the switching element SW2. The pixel electrode PE1 and the pixel electrode PE2 are formed with a plurality of slits SL that face the common electrode CE. In the illustrated example, each of the slits SL extends along the second direction Y and has a long axis parallel to the second direction Y.

  FIG. 3 is a diagram schematically showing a cross-sectional structure of the pixel PX1 shown in FIG. 2 cut along the line AB.

  The array substrate AR is formed using a first insulating substrate 10 having optical transparency such as a glass substrate. The array substrate AR includes a switching element SW1, a common electrode CE, a pixel electrode PE1, and the like on the side of the first insulating substrate 10 facing the counter substrate CT.

  The semiconductor layer SC of the switching element SW1 is located on the first insulating substrate 10 and is covered with the first insulating film 11. The first insulating film 11 is also disposed on the first insulating substrate 10. The gate electrode WG of the switching element SW1 is formed integrally with the gate wiring G1 on the first insulating film 11, and is located above the semiconductor layer SC. The gate electrode WG is covered with the second insulating film 12 together with the gate wiring G1. The second insulating film 12 is also disposed on the first insulating film 11.

  The source electrode WS and the drain electrode WD of the switching element SW1 are formed on the second insulating film 12. Similarly, the source line S1 and the source line S2 are formed on the second insulating film 12. The source electrode WS is formed integrally with the source line S1. The source electrode WS is in contact with the semiconductor layer SC through a contact hole 1 that penetrates the first insulating film 11 and the second insulating film 12. The drain electrode WD is in contact with the semiconductor layer SC through a contact hole 2 that penetrates the first insulating film 11 and the second insulating film 12. The switching element SW1 having such a configuration is covered with the third insulating film 13 together with the source line S1 and the source line S2. The third insulating film 13 is also disposed on the second insulating film 12.

  The common electrode CE is formed on the third insulating film 13. The common electrode CE is formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). The common electrode CE is covered with the fourth insulating film 14. The fourth insulating film 14 is also disposed on the third insulating film 13.

  The pixel electrode PE1 is formed on the fourth insulating film 14 and faces the common electrode CE. A slit SL is formed in the pixel electrode PE1. Each slit is located above the common electrode CE. The pixel electrode PE is formed of a transparent conductive material, for example, ITO or IZO. Such a pixel electrode PE1 is in contact with the drain electrode WD of the switching element SW1 through the contact hole CH3. The contact hole CH3 includes a contact hole CH31 that penetrates the third insulating film 13 to the drain electrode WD and a contact hole CH32 that penetrates the fourth insulating film 14 to the drain electrode WD.

  The pixel electrode PE1 is covered with the first alignment film AL1. The first alignment film AL1 also covers the fourth insulating film 14. The first alignment film AL1 is formed of a material exhibiting horizontal alignment and is disposed on the surface in contact with the liquid crystal layer LQ of the array substrate AR.

  On the other hand, the counter substrate CT is formed using a second insulating substrate 30 having optical transparency such as a glass substrate. The counter substrate CT includes a color filter 32, an overcoat layer 33, an inner light shielding layer BM1, and the like on the inner surface (that is, the side facing the array substrate AR) 30A side of the second insulating substrate 30.

  The color filter 32 is formed on the inner surface 30 </ b> A of the second insulating substrate 30. The color filter 32 is formed of a resin material colored in a plurality of different colors, for example, red, blue, and green. The red color filter is arranged corresponding to the red pixel, the green color filter is arranged corresponding to the green pixel, and the blue color filter is arranged corresponding to the blue pixel.

  The overcoat layer 33 covers the color filter 32. The overcoat layer 33 flattens the unevenness on the surface of the color filter 32. Such an overcoat layer 33 is formed of a transparent resin material.

  The inner light shielding layer BM1 is located closer to the array substrate AR than the color filter 32. The inner light shielding layer BM1 is formed so as to partition each pixel PX, and includes a gate line G, an auxiliary capacitance line C, a source line S, and a wiring part such as a switching element SW and contacts provided on the array substrate AR. It is formed so as to face the hole CH3 and the like. Although not described in detail, the inner light shielding layer BM1 formed so as to face the gate line G and the source line S has a lattice shape. The boundary between the color filters 32 of different colors is at a position overlapping the inner light shielding layer BM1. The inner light shielding layer BM1 is covered with the second alignment film AL2. The second alignment film AL2 also covers the overcoat layer 33. The second alignment film AL2 is formed of a material exhibiting horizontal alignment, and is disposed on the surface in contact with the liquid crystal layer LQ of the counter substrate CT.

  The array substrate AR and the counter substrate CT as described above are arranged so that the first alignment film AL1 and the second alignment film AL2 face each other. At this time, a predetermined cell gap is formed between the array substrate AR and the counter substrate CT by a spacer (not shown). The array substrate AR and the counter substrate CT are bonded together with a sealing material in a state where a cell gap is formed. The liquid crystal layer LQ is composed of a liquid crystal composition including liquid crystal molecules LM sealed in a cell gap formed between the first alignment film AL1 of the array substrate AR and the second alignment film AL2 of the counter substrate CT. ing.

  A backlight BL is arranged on the back side of the liquid crystal display panel LPN having such a configuration. As the backlight BL, various forms are applicable, and any of those using a light emitting diode (LED) or a cold cathode tube (CCFL) as a light source can be applied. The description of the structure is omitted.

  On the outer surface of the array substrate AR, that is, the outer surface 10B of the first insulating substrate 10, the first optical element OD1 including the first polarizing plate PL1 is disposed. The second optical element OD2 including the second polarizing plate PL2 is disposed on the outer surface of the counter substrate CT, that is, the outer surface 30B of the second insulating substrate 30. For example, the first absorption axis of the first polarizing plate PL1 and the second absorption axis of the second polarizing plate PL2 are in a crossed Nicols positional relationship.

  As shown in FIG. 2, the first alignment film AL1 and the second alignment film AL2 are subjected to alignment treatment in directions parallel to each other in a plane parallel to the substrate main surface (or XY plane). The first alignment film AL1 is subjected to an alignment process along a first alignment process direction R1 having an angle of 5 ° to 15 ° with respect to the second direction Y. The second alignment film AL2 is subjected to an alignment process along a second alignment process direction R2 parallel to the alignment process direction R1. The first alignment treatment direction R1 and the second alignment treatment direction R2 are opposite to each other.

  The operation of the liquid crystal display device having the above configuration will be briefly described below.

  In a state where no voltage is applied to the liquid crystal layer LQ, that is, a state where an electric field is not formed between the pixel electrode PE and the common electrode CE (when OFF), the liquid crystal molecules LM contained in the liquid crystal layer LQ are As shown by the solid line in FIG. 2, the initial alignment is performed in the XY plane (the direction in which the liquid crystal molecules LM are initially aligned is referred to as the initial alignment direction). Note that the first absorption axis of the first polarizing plate PL1 or the second absorption axis of the second polarizing plate PL2 is substantially parallel to the initial alignment direction of the liquid crystal molecules LM.

  Part of the backlight light from the backlight BL passes through the first polarizing plate PL1 and enters the liquid crystal display panel LPN. The light incident on the liquid crystal display panel LPN is linearly polarized light orthogonal to the first absorption axis of the first polarizing plate PL1. Such a polarization state of linearly polarized light hardly changes when it passes through the liquid crystal display panel LPN in the OFF state. For this reason, most of the linearly polarized light transmitted through the liquid crystal display panel LPN is absorbed by the second polarizing plate PL2 having a crossed Nicols positional relationship with respect to the first polarizing plate PL1 (black display).

  On the other hand, in a state where a voltage is applied to the liquid crystal layer LQ, that is, in a state where a fringe electric field is formed between the pixel electrode PE and the common electrode CE (when ON), the liquid crystal molecules LM are indicated by broken lines in FIG. As described above, in the XY plane, the orientation is different from the initial orientation direction. In the positive type liquid crystal material, the liquid crystal molecules LM are aligned so that the major axis thereof is oriented in a direction substantially parallel to the electric field in the XY plane.

  Of the backlight, linearly polarized light orthogonal to the first absorption axis is incident on the liquid crystal display panel LPN, and its polarization state changes according to the alignment state of the liquid crystal molecules LM when passing through the liquid crystal layer LQ. For this reason, at the time of ON, at least a part of the light that has passed through the liquid crystal layer LQ is transmitted through the second polarizing plate PL2 (white display).

  FIG. 4 is a schematic cross-sectional view of a liquid crystal display panel LPN for explaining the limit angle of viewing angle color mixing. Here, only the configuration necessary for the description is illustrated, and the other configurations are illustrated in a simplified manner.

  In the illustrated example, a color filter 32 of a different color is disposed in each of the adjacent pixels PX1 and PX2, and the boundary of the color filter 32 of a different color is positioned above the source line S that is one of the signal lines. This is equivalent to The limit angle of the viewing angle color mixture is defined as follows. That is, when the parallax between the pixel PX1 and the pixel PX2 is a and the distance between the source wiring S and the inner light shielding layer BM1 is b, the limit angle θ of the viewing angle color mixture is tan θ = (parallax a) / (distance b). Given in.

  In recent years, there is a growing demand for higher definition and higher aperture ratio (expansion of the area of the pixel aperture that contributes to display) associated with higher brightness. With such a demand, the width of the inner light-shielding layer BM1 that partitions each pixel tends to become narrower. However, the thinner the width of the inner light-shielding layer BM1, the more the misalignment between the array substrate AR and the counter substrate CT becomes. As a result, the allowable margin decreases and the limit angle θ decreases. That is, when the inner light shielding layer BM1 having a narrow width is applied, even when observed from an oblique direction slightly inclined with respect to the normal direction (front direction) of the liquid crystal display panel, It becomes easy to be visually recognized as a mixed color by influence.

  According to the comparative example indicated by the broken line in the figure, when the inner light shielding layer BM1 is formed on the inner surface 30A of the second insulating substrate 30, the distance b1 between the source wiring S and the inner light shielding layer BM1 is long, The angle θ1 cannot be secured sufficiently.

  On the other hand, according to the present embodiment indicated by a solid line in the drawing, the inner light shielding layer BM1 is located closer to the array substrate AR than the color filter 32, and as shown in the figure, the array substrate AR of the overcoat layer 33 and Since it is formed on the opposite side, the distance b2 between the source line S and the inner light shielding layer BM1 is shorter than the distance b1 in the comparative example. Thereby, limit angle (theta) 2 can be expanded rather than limit angle (theta) 2 of a comparative example. That is, by disposing the inner light shielding layer BM1 at a position close to the array substrate AR without increasing the width of the inner light shielding layer BM1, the distance between the source wiring S and the inner light shielding layer BM1 is shortened, and the limit angle θ2 It is possible to meet the demand for higher aperture ratio due to higher definition and higher brightness.

  As an example, in the comparative example, when the parallax a is 4.75 μm and the distance b1 is 8.7 μm, the limit angle θ1 is 28.6 °, whereas in the present embodiment, the parallax a Is 4.75 μm and the distance b2 is 5.2 μm, the limit angle θ2 is 42.4 °, which can be improved by 13.8 ° as the limit angle of viewing angle color mixing as compared with the comparative example. It was. Here, in each case, the film thickness of the inner light shielding layer BM1 is set to 0.9 μm.

  As described above, the limit angle θ increases as the distance b between the source line S and the inner light shielding layer BM1 is shortened. That is, the distance b can be shortened by increasing the thickness of the inner light shielding layer BM1. For example, when the film thickness of the inner light-shielding layer BM1 of this embodiment is set to 2.0 μm, the limit angle θ2 is expanded to 49.2 °, and the limit angle for viewing angle color mixing is 20. It was improved by 6 °.

  On the other hand, when the inner light-shielding layer BM1 is formed in a lattice shape facing each of the gate wiring G and the source wiring S, if the inner light-shielding layer BM1 is too thick, The light shielding layer BM1 may hinder the diffusion of the liquid crystal material. For this reason, it is desirable that at least a part of the inner light shielding layer BM1 is separated from the array substrate AR. That is, it is desirable to form a gap in which the liquid crystal material can be diffused between the inner light shielding layer BM1 and the array substrate AR.

  Next, another configuration example of this embodiment will be described.

  FIG. 5 is a diagram schematically showing another cross-sectional structure of the liquid crystal display panel LPN.

  The structure example shown here includes a first spacer part BM11 in which the inner light-shielding layer BM1 forms a cell gap and a second spacer part BM12 spaced from the array substrate AR, as compared to the structure example described above. Is different. The inner light shielding layer BM1 extends in the direction in which the gate line G extends and in the direction in which the source line S extends (normal direction in the drawing).

  In the illustrated example, the first spacer portion BM11 is located at the intersection of the gate line G and the source line S, is in contact with the array substrate AR, and functions as a so-called columnar spacer. The second spacer part BM12 is separated from the array substrate AR. In the illustrated example, the second spacer portion BM12 is formed along a position facing the gate line G except for the intersection of the gate line G and the source line S. Further, although not shown, the second spacer portion BM12 is also formed in a direction along the position facing the source wiring S (that is, the normal direction in the drawing).

  In the inner light shielding layer BM1, it is desirable that the first spacer part BM11 and the second spacer part BM12 are connected. As a result, it is possible to suppress light leakage at positions immediately above the gate line G and the source line S. In particular, the liquid crystal molecules located immediately above the gate line G do not always maintain the initial alignment state, and may cause light leakage near the gate line G. For this reason, it is desirable that the inner light shielding layer BM1 is disposed without interruption at a position facing the gate wiring G.

  The inner light shielding layer BM1 having different height portions such as the first spacer portion BM11 and the second spacer portion BM12 can be formed by using a technique such as halftone exposure.

  According to such a structural example, in addition to obtaining the same effect as described above, it is possible to omit a step of separately forming a columnar spacer for forming a cell gap, thereby reducing costs. It becomes. Further, by applying the inner light shielding layer BM1 including the first spacer part BM11 for forming the cell gap and the second spacer part BM12 spaced from the array substrate AR, the signal line such as the gate line and the source line is formed on the signal line. It is possible to reliably shield the light and reduce the diffusion obstacle of the liquid crystal material.

  Further, since the second spacer portion BM12 contacts the array substrate AR and acts as a cushion when a pressing force that is pressed from the outside is applied, it is possible to improve the strength against the pressing force from the outside. It becomes. In particular, even when a large impact is applied from the outside with the liquid crystal material contracted in a low temperature environment, the second spacer portion BM12 serves as a cushion, and suppresses the generation of bubbles (low temperature bubbles) in the liquid crystal layer LQ. Is possible.

  Note that the first spacer portion BM11 disposed at the intersection extends in a direction along the gate line G. This is based on the following reason. That is, as shown in FIG. 2, the inner light shielding layer BM1 facing the gate line G also faces the switching element SW and the contact hole CH3. For this reason, when the misalignment along the first direction X occurs when the array substrate AR and the counter substrate CT are bonded together, the contacts located on both sides of the first spacer portion BM11 from the position facing the source wiring S are located. There is a risk that the installation area will be insufficient due to slipping over the hall CH3. For this reason, by expanding the width of the first spacer portion BM11 along the first direction X, it is possible to reduce the shortage of the installation area even if misalignment occurs and the contact hole CH3 is displaced. .

  Next, another configuration example of this embodiment will be described.

  FIG. 6 is a plan view schematically showing a structural example applicable to the liquid crystal display panel LPN of the present embodiment.

  In the illustrated structural example, an outer light shielding layer BM2 is disposed in addition to the above-described inner light shielding layer BM1 as the light shielding layer provided in the counter substrate. The outer light shielding layer BM2 extends in the first direction X and the second direction Y, respectively. The outer light-shielding layer BM2 substantially corresponds to a light-shielding layer that partitions pixels, and is formed in a lattice shape without interruption. A portion of the outer light shielding layer BM2 extending in the first direction X faces the gate wiring G, the switching element SW, the contact hole CH3, and the like on the array substrate side. Further, a portion of the outer light shielding layer BM2 extending in the second direction Y is opposed to the source wiring S on the array substrate side, and overlaps the boundary of the color filters respectively disposed in the pixels adjacent to the first direction X. . In such an outer light shielding layer BM2, the width along the second direction Y of the portion extending in the first direction X is larger than the width along the first direction X of the portion extending in the second direction Y. .

  The inner light shielding layer BM1 is formed at a position overlapping the outer light shielding layer BM2. The first spacer portion BM11 is located at the intersection of the outer light shielding layer BM2 and extends in the first direction X. The second spacer portion BM12 overlaps with portions extending in the first direction X and the second direction Y of the outer light shielding layer BM2, and is formed in a line shape (or a dot shape, not shown). The second spacer part BM12 may be connected to the first spacer part BM11. However, in the illustrated example, the second spacer part BM12 is separated from the first spacer part BM11.

  FIG. 7 is a diagram schematically showing a cross-sectional structure of the liquid crystal display panel LPN cut along the line CD shown in FIG. FIG. 8 is a diagram schematically showing a cross-sectional structure of the liquid crystal display panel LPN cut along line EF shown in FIG.

  The outer light shielding layer BM2 is formed on the inner surface 30A of the second insulating substrate 30, is positioned above the source wiring S, and faces the inner light shielding layer BM1. A color filter 32 and an overcoat layer 33 are interposed between the outer light shielding layer BM2 and the inner light shielding layer BM1.

  In the example shown in FIG. 7, the outer light shielding layer BM2 faces the second spacer portion BM12 in the inner light shielding layer BM1.

  In the example illustrated in FIG. 8, the outer light shielding layer BM2 faces the first spacer portion BM11 in the inner light shielding layer BM1 at the intersection between the gate wiring G and the source wiring S. Further, the outer light shielding layer BM2 faces the second spacer portion BM12 of the inner light shielding layer BM1 at a position facing the gate wiring G other than the intersection. The outer light shielding layer BM2 further faces the gap between the first spacer part BM11 and the second spacer part BM12.

  According to such a structural example, in addition to obtaining the same effect as described above, light shielding between pixels is mainly performed by the outer light shielding layer BM2 formed without interruption, while the second spacer Since the part BM12 is separated from the array substrate AR and a gap is formed between the first spacer part BM1 and the second spacer part BM2, diffusion of the liquid crystal material can be promoted in the manufacturing process of the liquid crystal display panel. It becomes possible.

  The inner light shielding layer BM1 and the outer light shielding layer BM2 may be formed using the same material, or may be formed using different materials. The reflectance of the surface of the second insulating substrate 30 is determined by the refractive index of the interface between the outer light shielding layer BM2 and the second insulating substrate 30. For example, when the second insulating substrate 30 is made of glass, the refractive index of the glass is substantially constant, so that the reflectance is adjusted by changing the refractive index of the outer light shielding layer BM2. Therefore, as the optical density (OD value) of the outer light-shielding layer BM2 decreases, that is, as the light-shielding layer approaches transparency, the resin of the outer light-shielding layer BM2 has a refractive index close to that of the second insulating substrate 30. It is easy to transmit the outer light shielding layer BM2, and the surface reflection at the outer light shielding layer BM2 is reduced. For this reason, it is desirable that the optical density (OD value) of the outer light shielding layer BM2 is lower than the optical density of the inner light shielding layer BM1. As a result, it is possible to reduce the surface reflection of the external light incident through the second insulating substrate 30 on the outer light shielding layer BM2.

  As described above, according to this embodiment, a liquid crystal display device capable of improving display quality can be provided.

  In addition, although some embodiment of this invention was described, these embodiment is shown as an example and is not intending limiting the range of invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  For example, in the above embodiment, the slit SL of the pixel electrode PE is formed to have a long axis parallel to the second direction Y, but may be formed to have a long axis parallel to the first direction X. It may be formed so as to have a long axis parallel to a direction intersecting the first direction X and the second direction Y, or may be formed in a shape bent in a dogleg shape.

LPN ... Liquid crystal display panel AR ... Array substrate CT ... Counter substrate LQ ... Liquid crystal layer PE ... Pixel electrode SL ... Slit CE ... Common electrode G ... Gate wire S ... Source wire SW ... Switching element BM1 ... Inner light shielding layer BM11 ... First spacer Part BM12 ... second spacer part BM2 ... outer light shielding layer AL1 ... first alignment film AL2 ... second alignment film

Claims (6)

A first signal line; a second signal line intersecting the first signal line; a switching element electrically connected to the first signal line and the second signal line; and electrically connected to the switching element A first substrate comprising: the pixel electrode formed; and a first alignment film covering the pixel electrode;
An insulating substrate; a color filter positioned on an inner surface of the insulating substrate facing the first substrate and facing the pixel electrode; and the first signal wiring and the first filter positioned closer to the first substrate than the color filter. A second substrate including an inner light shielding layer facing two signal wirings, a second alignment film covering the inner light shielding layer and facing the first alignment film,
A liquid crystal layer comprising liquid crystal molecules held in a cell gap between the first substrate and the second substrate;
A liquid crystal display device.   2. The liquid crystal display device according to claim 1, wherein the inner light shielding layer includes a first spacer portion that forms the cell gap and a second spacer portion that is separated from the first substrate.   The liquid crystal display device according to claim 2, wherein the first spacer portion is located at an intersection of the first signal line and the second signal line.   4. The liquid crystal display device according to claim 1, further comprising an outer light shielding layer formed on an inner surface of the insulating substrate and facing the inner light shielding layer. 5.   The liquid crystal display device according to claim 4, wherein an optical density of the outer light-shielding layer is lower than an optical density of the inner light-shielding layer.   The liquid crystal display device according to claim 2, wherein the first spacer portion extends in a direction along the first signal wiring.

Images