JP2014170800A - Semiconductor device - Google Patents

Semiconductor device Download PDF

Info

Publication number
JP2014170800A
JP2014170800A JP2013040912A JP2013040912A JP2014170800A JP 2014170800 A JP2014170800 A JP 2014170800A JP 2013040912 A JP2013040912 A JP 2013040912A JP 2013040912 A JP2013040912 A JP 2013040912A JP 2014170800 A JP2014170800 A JP 2014170800A
Authority
JP
Japan
Prior art keywords
wiring board
conductive layer
semiconductor device
semiconductor
insulating substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2013040912A
Other languages
Japanese (ja)
Inventor
Hiroshi Nozu
浩史 野津
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to JP2013040912A priority Critical patent/JP2014170800A/en
Priority to PCT/JP2014/054209 priority patent/WO2014132897A1/en
Publication of JP2014170800A publication Critical patent/JP2014170800A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/49524—Additional leads the additional leads being a tape carrier or flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0405—Bonding areas specifically adapted for tape automated bonding [TAB] connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73269—Layer and TAB connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/86—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using tape automated bonding [TAB]
    • H01L2224/868—Bonding techniques
    • H01L2224/86801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/86—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using tape automated bonding [TAB]
    • H01L2224/868—Bonding techniques
    • H01L2224/8685—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/86—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using tape automated bonding [TAB]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device with high design flexibility.SOLUTION: A semiconductor device 10 comprises: a semiconductor chip 14 including a transistor; a chip mounting substrate 12 having a chip mounting surface 12a on which the semiconductor chip 14 is mounted; and a first wiring board 22 provided on the semiconductor chip 14. The first wiring board 22 comprises a first insulating substrate, and a first conductive layer provided on the first insulating substrate and electrically connected to the transistor.

Description

本発明は、半導体装置に関する。   The present invention relates to a semiconductor device.

半導体装置の例として、樹脂封止型の半導体装置が知られている（非特許文献１参照）。このような半導体装置では、ダイパッドに搭載された半導体チップが、ワイヤを介して電極端子に接続される。   As an example of a semiconductor device, a resin-sealed semiconductor device is known (see Non-Patent Document 1). In such a semiconductor device, a semiconductor chip mounted on a die pad is connected to an electrode terminal via a wire.

「Ｃｕワイヤを中心としたワイヤボンディングの不良原因と信頼性向上・評価技術」株式会社技術情報協会出版、２０１１年７月２９日、ｐ．２６３"Causes of wire bonding failure centering on Cu wire and reliability improvement / evaluation technology", published by Technical Information Association, July 29, 2011, p. 263

しかし、半導体チップと電極端子との間をワイヤで接続する場合、空間内でワイヤの形状を任意に設計することは困難であるので、半導体装置の設計の自由度を高めることができない。   However, when connecting the semiconductor chip and the electrode terminal with a wire, it is difficult to arbitrarily design the shape of the wire in the space, and thus the degree of freedom in designing the semiconductor device cannot be increased.

本発明は、設計の自由度が高い半導体装置を提供することを目的とする。   An object of the present invention is to provide a semiconductor device having a high degree of design freedom.

本発明の一側面に係る半導体装置は、トランジスタを含む少なくとも１つの半導体チップと、前記少なくとも１つの半導体チップが搭載されるチップ搭載面を有するチップ搭載基板と、前記少なくとも１つの半導体チップ上に設けられた第１配線板と、を備え、前記第１配線板は、第１絶縁基板と、前記第１絶縁基板上に設けられ、前記トランジスタに電気的に接続された第１導電層と、を備える。   A semiconductor device according to an aspect of the present invention is provided on at least one semiconductor chip including a transistor, a chip mounting substrate having a chip mounting surface on which the at least one semiconductor chip is mounted, and the at least one semiconductor chip. A first insulating layer, and a first conductive layer provided on the first insulating substrate and electrically connected to the transistor. Prepare.

この半導体装置では、第１配線板の厚み方向から見た第１配線板の形状を任意に設計できるので、半導体装置の設計の自由度が高い。   In this semiconductor device, since the shape of the first wiring board viewed from the thickness direction of the first wiring board can be arbitrarily designed, the degree of freedom in designing the semiconductor device is high.

一実施形態において、前記第１配線板がフレキシブルプリント配線板であってもよい。   In one embodiment, the first wiring board may be a flexible printed wiring board.

この場合、第１配線板をフレキシブルに変形させることができるので、半導体装置の設計の自由度が更に高くなる。例えば第１配線板の第１導電層とトランジスタとを接続する際に、第１配線板を変形させることができるので、作業性が向上する。例えば半導体チップの位置ずれがあっても、第１配線板を変形させることにより、第１配線板の第１導電層とトランジスタとを接続し易くなる。   In this case, since the first wiring board can be flexibly deformed, the degree of freedom in designing the semiconductor device is further increased. For example, when connecting the first conductive layer of the first wiring board and the transistor, the first wiring board can be deformed, so that workability is improved. For example, even if the semiconductor chip is misaligned, the first conductive layer of the first wiring board and the transistor can be easily connected by deforming the first wiring board.

一実施形態において、前記少なくとも１つの半導体チップが複数の半導体チップであってもよい。   In one embodiment, the at least one semiconductor chip may be a plurality of semiconductor chips.

複数の半導体チップのそれぞれにワイヤを接続する場合、ワイヤの本数が増えるため、ワイヤ同士が接触する可能性が高まる。配線としてワイヤに代えて第１配線板が用いられているので、配線同士が接触する可能性を低減できる。   When wires are connected to each of a plurality of semiconductor chips, the number of wires increases, so the possibility that the wires come into contact with each other increases. Since the 1st wiring board is used instead of a wire as wiring, possibility that wiring will contact can be reduced.

一実施形態において、前記少なくとも１つの半導体チップの材料が、ワイドバンドギャップ半導体を含んでもよい。   In one embodiment, the material of the at least one semiconductor chip may include a wide band gap semiconductor.

シリコン（Ｓｉ）では、半導体チップに小さい電流しか流れないので、多数の配線を使用する必要性は低い。しかし、ワイドバンドギャップ半導体では、半導体チップに流れる電流がシリコンよりも大きいので、電流の集中を抑制するために配線の本数を増やす必要性が高い。また、ワイドバンドギャップ半導体では、シリコンよりも低い製造歩留まりに起因して半導体チップの大型化が難しい。このため、ワイドバンドギャップ半導体では、小型の半導体チップに多数の配線が接続される。そのような場合でも、配線としてワイヤに代えて第１配線板が用いられているので、配線同士が接触する可能性を低減できる。   In silicon (Si), only a small current flows through the semiconductor chip, so the necessity for using a large number of wirings is low. However, in a wide bandgap semiconductor, the current flowing through the semiconductor chip is larger than that in silicon, so that there is a high need to increase the number of wirings in order to suppress current concentration. Further, in the wide band gap semiconductor, it is difficult to increase the size of the semiconductor chip due to the manufacturing yield lower than that of silicon. For this reason, in the wide band gap semiconductor, a large number of wirings are connected to a small semiconductor chip. Even in such a case, since the 1st wiring board is used instead of a wire as wiring, possibility that wiring will contact can be reduced.

一実施形態において、前記第１導電層の材料が、銅を含んでもよい。   In one embodiment, the material of the first conductive layer may include copper.

この場合、第１導電層の放熱性が高くなる。   In this case, the heat dissipation of the first conductive layer is increased.

一実施形態において、前記第１導電層が前記トランジスタのソース又はエミッタに電気的に接続されてもよい。   In one embodiment, the first conductive layer may be electrically connected to the source or emitter of the transistor.

この場合、第１導電層に大電流が流れることによって、熱が発生する。そのような場合であっても、第１導電層の表面積を大きくすることによって、第１導電層の放熱性を高くすることができる。   In this case, heat is generated by a large current flowing through the first conductive layer. Even in such a case, the heat dissipation of the first conductive layer can be increased by increasing the surface area of the first conductive layer.

一実施形態において、前記トランジスタの第１端子が前記チップ搭載基板に電気的に接続されており、前記トランジスタの第２端子が前記第１導電層に電気的に接続されており、前記第１絶縁基板が前記チップ搭載基板と前記第１導電層との間に配置されてもよい。   In one embodiment, a first terminal of the transistor is electrically connected to the chip mounting substrate, a second terminal of the transistor is electrically connected to the first conductive layer, and the first insulation A substrate may be disposed between the chip mounting substrate and the first conductive layer.

この場合、第１絶縁基板によってチップ搭載基板と第１導電層との間の絶縁性を高めることができる。   In this case, the insulation between the chip mounting substrate and the first conductive layer can be enhanced by the first insulating substrate.

一実施形態において、前記第１配線板が、第２絶縁基板を更に備え、前記第１導電層が前記第１絶縁基板と前記第２絶縁基板との間に配置されてもよい。   In one embodiment, the first wiring board may further include a second insulating substrate, and the first conductive layer may be disposed between the first insulating substrate and the second insulating substrate.

この場合、第２絶縁基板によって第１導電層の酸化が抑制される。   In this case, oxidation of the first conductive layer is suppressed by the second insulating substrate.

一実施形態において、前記第１導電層の厚みが１２〜５０μｍであってもよい。   In one embodiment, the first conductive layer may have a thickness of 12 to 50 μm.

この場合、第１導電層の放熱性が高くなる。   In this case, the heat dissipation of the first conductive layer is increased.

一実施形態において、前記第１絶縁基板の材料が、ポリイミド又はソルダレジストを含んでもよい。   In one embodiment, the material of the first insulating substrate may include polyimide or a solder resist.

この場合、第１絶縁基板の放熱性が高くなるので、第１導電層に大電流が流れることによって発生した熱が第１絶縁基板を通しても放出され易くなる。   In this case, since the heat dissipation of the first insulating substrate is increased, heat generated by a large current flowing through the first conductive layer is easily released through the first insulating substrate.

一実施形態において、前記第１導電層と前記少なくとも１つの半導体チップとの間にめっき層が配置され、前記めっき層が、前記第１導電層のうち前記第１絶縁基板に覆われていない領域にコーティングされており、前記めっき層が、前記第１導電層及び前記少なくとも１つの半導体チップに電気的に接続されており、前記めっき層が、ニッケル層及び金層を含むか、又はニッケル層を含んでもよい。   In one embodiment, a plating layer is disposed between the first conductive layer and the at least one semiconductor chip, and the plating layer is not covered with the first insulating substrate in the first conductive layer. And the plating layer is electrically connected to the first conductive layer and the at least one semiconductor chip, and the plating layer includes a nickel layer and a gold layer, or a nickel layer is formed. May be included.

この場合、第１導電層と半導体チップとの間の電気的な接続安定性が向上する。   In this case, the electrical connection stability between the first conductive layer and the semiconductor chip is improved.

一実施形態において、前記第１導電層が前記トランジスタのソース又はエミッタに電気的に接続されており、前記少なくとも１つの半導体チップ上に設けられた第２配線板を更に備え、前記第２配線板は、ゲート用絶縁基板と、前記ゲート用絶縁基板上に設けられ、前記トランジスタのゲートに電気的に接続された第２導電層と、を備えてもよい。   In one embodiment, the first conductive layer is further connected to a source or an emitter of the transistor, and further includes a second wiring board provided on the at least one semiconductor chip, and the second wiring board May comprise a gate insulating substrate and a second conductive layer provided on the gate insulating substrate and electrically connected to the gate of the transistor.

この場合、第２配線板の厚み方向から見た第２配線板の形状を任意に設計できるので、半導体装置の設計の自由度が更に高まる。   In this case, since the shape of the second wiring board viewed from the thickness direction of the second wiring board can be arbitrarily designed, the degree of freedom in designing the semiconductor device is further increased.

一実施形態において、前記第１配線板の厚み方向から見て、前記第１配線板と前記第２配線板とが少なくとも部分的に重なっていてもよい。   In one embodiment, when viewed from the thickness direction of the first wiring board, the first wiring board and the second wiring board may overlap at least partially.

この場合、第１配線板の厚み方向から見て半導体装置を小型化できる。   In this case, the semiconductor device can be downsized as viewed from the thickness direction of the first wiring board.

一実施形態において、前記第１配線板と前記第２配線板とが一体化されていてもよい。   In one embodiment, the first wiring board and the second wiring board may be integrated.

この場合、半導体装置を小型化できる。   In this case, the semiconductor device can be reduced in size.

一実施形態において、前記少なくとも１つの半導体チップが複数の半導体チップであり、前記複数の半導体チップのそれぞれに前記第１配線板が分岐しており、分岐した前記第１配線板が前記複数の半導体チップのそれぞれに電気的に接続されていてもよい。   In one embodiment, the at least one semiconductor chip is a plurality of semiconductor chips, the first wiring board is branched to each of the plurality of semiconductor chips, and the branched first wiring board is the plurality of semiconductors. It may be electrically connected to each of the chips.

一実施形態において、前記少なくとも１つの半導体チップが複数の半導体チップであり、前記複数の半導体チップにわたって前記第１配線板が延在しており、前記第１配線板が前記複数の半導体チップのそれぞれに電気的に接続されていてもよい。   In one embodiment, the at least one semiconductor chip is a plurality of semiconductor chips, the first wiring board extends over the plurality of semiconductor chips, and the first wiring board is each of the plurality of semiconductor chips. May be electrically connected.

一実施形態において、前記第１導電層が前記トランジスタのゲートに電気的に接続されてもよい。   In one embodiment, the first conductive layer may be electrically connected to the gate of the transistor.

本発明によれば、設計の自由度が高い半導体装置が提供され得る。   According to the present invention, a semiconductor device having a high degree of design freedom can be provided.

第１実施形態に係る半導体装置を模式的に示す平面図である。1 is a plan view schematically showing a semiconductor device according to a first embodiment. 図１のＩＩａ−ＩＩａ線又はＩＩｂ−ＩＩｂ線に沿った半導体装置の断面図である。It is sectional drawing of the semiconductor device along the IIa-IIa line | wire or IIb-IIb line | wire of FIG. 第１実施形態に係る半導体装置の第１配線板を模式的に示す図である。It is a figure which shows typically the 1st wiring board of the semiconductor device which concerns on 1st Embodiment. 第１実施形態に係る半導体装置の第２配線板を模式的に示す図である。It is a figure which shows typically the 2nd wiring board of the semiconductor device which concerns on 1st Embodiment. 第２実施形態に係る半導体装置を模式的に示す平面図である。It is a top view which shows typically the semiconductor device which concerns on 2nd Embodiment. 第２実施形態に係る半導体装置の第１配線板を模式的に示す図である。It is a figure which shows typically the 1st wiring board of the semiconductor device which concerns on 2nd Embodiment. 第３実施形態に係る半導体装置を模式的に示す平面図である。It is a top view which shows typically the semiconductor device which concerns on 3rd Embodiment. 第３実施形態に係る半導体装置の各部品を模式的に示す図である。It is a figure which shows typically each component of the semiconductor device which concerns on 3rd Embodiment.

以下、添付図面を参照しながら本発明の実施形態が詳細に説明される。図面の説明において、同一又は同等の要素には同一符号が用いられ、重複する説明は省略される。   Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the description of the drawings, the same reference numerals are used for the same or equivalent elements, and redundant descriptions are omitted.

（第１実施形態）
図１は、第１実施形態に係る半導体装置を模式的に示す平面図である。図１には、ＸＹＺ直交座標系が示されている。図２（ａ）は、図１のＩＩａ−ＩＩａ線に沿った半導体装置の断面図である。図２（ｂ）は、図１のＩＩｂ−ＩＩｂ線に沿った半導体装置の断面図である。図１及び図２に示される半導体装置１０は、樹脂封止型の半導体装置である。半導体装置１０は、チップ搭載基板としてのダイパッド１２と、複数の半導体チップ（又は半導体素子）１４と、半導体チップ１４上に設けられた第１配線板２２及び第２配線板３０とを備える。 (First embodiment)
FIG. 1 is a plan view schematically showing the semiconductor device according to the first embodiment. FIG. 1 shows an XYZ orthogonal coordinate system. FIG. 2A is a cross-sectional view of the semiconductor device along the line IIa-IIa in FIG. FIG. 2B is a cross-sectional view of the semiconductor device along the line IIb-IIb in FIG. A semiconductor device 10 shown in FIGS. 1 and 2 is a resin-encapsulated semiconductor device. The semiconductor device 10 includes a die pad 12 as a chip mounting substrate, a plurality of semiconductor chips (or semiconductor elements) 14, and a first wiring board 22 and a second wiring board 30 provided on the semiconductor chip 14.

半導体装置１０は、電極端子としてのリード１６，１８及び２０を備えてもよい。リード１６，１８，２０はＸ方向に沿って配列される。リード１６は、リード１８，２０の間に位置する。リード１６，１８、２０及びダイパッド１２は、リードフレームを構成し得る。半導体装置１０は、例えば電源等に使用される電力用半導体装置である。半導体装置１０のパッケージ形態の例は一般的なＴＯシリーズである。ＴＯシリーズの例はＴＯ−２４７、ＴＯ−２２０、ＴＯ−２６３（Ｄ２―ＰＡＫ）、ＴＯ−２５２（Ｄ−ＰＡＫ）を含む。   The semiconductor device 10 may include leads 16, 18 and 20 as electrode terminals. The leads 16, 18, and 20 are arranged along the X direction. The lead 16 is located between the leads 18 and 20. The leads 16, 18, 20 and the die pad 12 may constitute a lead frame. The semiconductor device 10 is a power semiconductor device used for a power source or the like, for example. An example of the package form of the semiconductor device 10 is a general TO series. Examples of TO series include TO-247, TO-220, TO-263 (D2-PAK), and TO-252 (D-PAK).

ダイパッド１２は、半導体チップ１４が搭載されるチップ搭載面１２ａを有する。ダイパッド１２は、半導体チップ１４と電気的に接続され得る。ダイパッド１２は例えば板状を呈している。チップ搭載面１２ａは、例えば長方形である。ダイパッド１２の材料の例は、銅（Ｃｕ）及び銅合金等の金属を含む。ダイパッド１２には、板厚方向にダイパッド１２を貫通する貫通孔２６が形成され得る。貫通孔２６は、例えば螺子によって半導体装置１０を他の部材に固定する際に、螺子を通すための孔である。   The die pad 12 has a chip mounting surface 12a on which the semiconductor chip 14 is mounted. The die pad 12 can be electrically connected to the semiconductor chip 14. The die pad 12 has a plate shape, for example. The chip mounting surface 12a is, for example, a rectangle. Examples of the material of the die pad 12 include metals such as copper (Cu) and a copper alloy. A through-hole 26 that penetrates the die pad 12 in the thickness direction can be formed in the die pad 12. The through hole 26 is a hole through which a screw is passed when the semiconductor device 10 is fixed to another member by, for example, a screw.

半導体チップ１４は、チップ搭載面１２ａの所定位置に搭載される。半導体チップ１４の例は、バイポーラトランジスタ、ＭＯＳ−ＦＥＴ、絶縁ゲートバイポーラトランジスタ（ＩＧＢＴ）等のトランジスタを含む。トランジスタは、縦型トランジスタであってもよいし、横型トランジスタであってもよい。半導体チップ１４は、鉛入り金属半田、鉛を含まない金属半田又は導電性樹脂等を含む材料から構成される接着層３２を介してチップ搭載面１２ａに実装され得る。半導体チップ１４の材料の例は、ワイドバンドギャップ半導体、シリコンその他の半導体を含む。ワイドバンドギャップ半導体は、シリコンのバンドギャップよりも大きいバンドギャップを有する。ワイドバンドギャップ半導体の例は、シリコンカーバイド（ＳｉＣ）、窒化ガリウム（ＧａＮ）、ダイヤモンドを含む。   The semiconductor chip 14 is mounted at a predetermined position on the chip mounting surface 12a. Examples of the semiconductor chip 14 include transistors such as bipolar transistors, MOS-FETs, and insulated gate bipolar transistors (IGBTs). The transistor may be a vertical transistor or a horizontal transistor. The semiconductor chip 14 can be mounted on the chip mounting surface 12a via an adhesive layer 32 made of a material containing lead-containing metal solder, lead-free metal solder, conductive resin, or the like. Examples of the material of the semiconductor chip 14 include a wide band gap semiconductor, silicon and other semiconductors. A wide band gap semiconductor has a band gap larger than that of silicon. Examples of wide band gap semiconductors include silicon carbide (SiC), gallium nitride (GaN), and diamond.

リード１６の内側端部は、ダイパッド１２に機械的に一体的に連結されている。ダイパッド１２は導電性を有するので、リード１６とダイパッド１２とは電気的に接続されている。リード１６の材料の例はダイパッド１２の材料と同じ材料を含む。リード１８，２０の材料の例は、銅及び銅合金等の金属を含む。   The inner end of the lead 16 is mechanically and integrally connected to the die pad 12. Since the die pad 12 has conductivity, the lead 16 and the die pad 12 are electrically connected. Examples of the material of the lead 16 include the same material as that of the die pad 12. Examples of the material of the leads 18 and 20 include metals such as copper and copper alloys.

リード２０は、第１配線板２２を介して半導体チップ１４に接続される。第１配線板２２は、半導体チップ１４のそれぞれに分岐している。分岐した第１配線板２２は、半導体チップ１４のそれぞれに電気的に接続されている。第１配線板２２の分岐した第１端部は半導体チップ１４の電極パッドＳＰにそれぞれ接続される。第１配線板２２の第２端部はリード２０の内側端部に接続される。   The lead 20 is connected to the semiconductor chip 14 via the first wiring board 22. The first wiring board 22 is branched to each of the semiconductor chips 14. The branched first wiring board 22 is electrically connected to each of the semiconductor chips 14. The branched first end of the first wiring board 22 is connected to the electrode pad SP of the semiconductor chip 14. The second end of the first wiring board 22 is connected to the inner end of the lead 20.

リード１８は、第２配線板３０を介して半導体チップ１４に接続される。第２配線板３０は、半導体チップ１４のそれぞれに分岐している。分岐した第２配線板３０は、半導体チップ１４のそれぞれに電気的に接続されている。第２配線板３０の分岐した第１端部は半導体チップ１４の電極パッドＧＰに接続される。第２配線板３０の第２端部はリード１８の内側端部に接続される。第１配線板２２及び第２配線板３０は、フレキシブルプリント配線板（フレキシブルプリント回路：ＦＰＣ）であってもよいし、リジッド配線板であってもよい。   The lead 18 is connected to the semiconductor chip 14 via the second wiring board 30. The second wiring board 30 is branched to each of the semiconductor chips 14. The branched second wiring board 30 is electrically connected to each of the semiconductor chips 14. The branched first end of the second wiring board 30 is connected to the electrode pad GP of the semiconductor chip 14. The second end of the second wiring board 30 is connected to the inner end of the lead 18. The first wiring board 22 and the second wiring board 30 may be a flexible printed wiring board (flexible printed circuit: FPC), or may be a rigid wiring board.

図１、図２（ａ）及び図３に示される第１配線板２２は、第１絶縁基板２２ａと、第１絶縁基板２２ａ上に設けられた第１導電層２２ｂとを備える。第１配線板２２は、第２絶縁基板２２ｃを更に備え得る。第１導電層２２ｂは第１絶縁基板２２ａと第２絶縁基板２２ｃとの間に配置される。これにより、第１導電層２２ｂの酸化が抑制される。第１導電層２２ｂは、半導体チップ１４のトランジスタに電気的に接続される。第１導電層２２ｂの分岐した第１端部は、接着層３４を介して半導体チップ１４に電気的に接続され得る。接着層３４の材料の例は、鉛入り金属半田、鉛を含まない金属半田又は導電性樹脂等を含む。金属半田のリフロー温度は例えば３００℃である。第１導電層２２ｂの第２端部は、接着層を介してリード２０に電気的に接続され得る。接着層の材料の例は、接着層３４と同じ材料を含む。   The first wiring board 22 shown in FIGS. 1, 2A and 3 includes a first insulating substrate 22a and a first conductive layer 22b provided on the first insulating substrate 22a. The first wiring board 22 may further include a second insulating substrate 22c. The first conductive layer 22b is disposed between the first insulating substrate 22a and the second insulating substrate 22c. Thereby, the oxidation of the first conductive layer 22b is suppressed. The first conductive layer 22b is electrically connected to the transistor of the semiconductor chip 14. The branched first end portion of the first conductive layer 22 b can be electrically connected to the semiconductor chip 14 through the adhesive layer 34. Examples of the material of the adhesive layer 34 include lead-containing metal solder, lead-free metal solder, or conductive resin. The reflow temperature of the metal solder is 300 ° C., for example. The second end portion of the first conductive layer 22b can be electrically connected to the lead 20 through an adhesive layer. Examples of the material of the adhesive layer include the same material as the adhesive layer 34.

図１、図２（ｂ）及び図４に示される第２配線板３０は、第３絶縁基板３０ａ（ゲート用絶縁基板）と、第３絶縁基板３０ａ上に設けられた第２導電層３０ｂとを備える。第２配線板３０は、第４絶縁基板３０ｃを更に備え得る。第２導電層３０ｂは第３絶縁基板３０ａと第４絶縁基板３０ｃとの間に配置される。これにより、第２導電層３０ｂの酸化が抑制される。第２導電層３０ｂは、半導体チップ１４のトランジスタに電気的に接続される。第２導電層３０ｂの分岐した第１端部は、接着層３６を介して半導体チップ１４に電気的に接続され得る。接着層３６の材料の例は、接着層３４と同じ材料を含む。第２導電層３０ｂの第２端部は、接着層を介してリード１８に電気的に接続され得る。接着層の材料の例は、接着層３６と同じ材料を含む。   The second wiring board 30 shown in FIGS. 1, 2B and 4 includes a third insulating substrate 30a (gate insulating substrate), and a second conductive layer 30b provided on the third insulating substrate 30a. Is provided. The second wiring board 30 may further include a fourth insulating substrate 30c. The second conductive layer 30b is disposed between the third insulating substrate 30a and the fourth insulating substrate 30c. Thereby, the oxidation of the second conductive layer 30b is suppressed. The second conductive layer 30b is electrically connected to the transistor of the semiconductor chip 14. The branched first end of the second conductive layer 30 b can be electrically connected to the semiconductor chip 14 via the adhesive layer 36. An example of the material of the adhesive layer 36 includes the same material as the adhesive layer 34. The second end of the second conductive layer 30b can be electrically connected to the lead 18 via an adhesive layer. Examples of the material of the adhesive layer include the same material as the adhesive layer 36.

半導体チップ１４のトランジスタのドレイン又はコレクタ（第１端子）はダイパッド１２に電気的に接続され得る。ドレイン又はコレクタは、半導体チップ１４の下面に形成される。半導体チップ１４のトランジスタのソース又はエミッタ（第２端子）は、第１導電層２２ｂに電気的に接続され得る。ソース又はエミッタは、半導体チップ１４の上面に形成される。半導体チップ１４のトランジスタのゲート（第３端子）は、第２導電層３０ｂに電気的に接続され得る。ゲートは、半導体チップ１４の上面に形成される。   The drain or collector (first terminal) of the transistor of the semiconductor chip 14 can be electrically connected to the die pad 12. The drain or collector is formed on the lower surface of the semiconductor chip 14. The source or emitter (second terminal) of the transistor of the semiconductor chip 14 can be electrically connected to the first conductive layer 22b. The source or emitter is formed on the upper surface of the semiconductor chip 14. The gate (third terminal) of the transistor of the semiconductor chip 14 can be electrically connected to the second conductive layer 30b. The gate is formed on the upper surface of the semiconductor chip 14.

第１絶縁基板２２ａはダイパッド１２と第１導電層２２ｂとの間に配置され得る。これにより、ダイパッド１２と第１導電層２２ｂとの間の絶縁性を高めることができる。第３絶縁基板３０ａはダイパッド１２と第２導電層３０ｂとの間に配置され得る。これにより、ダイパッド１２と第２導電層３０ｂとの間の絶縁性を高めることができる。   The first insulating substrate 22a may be disposed between the die pad 12 and the first conductive layer 22b. Thereby, the insulation between the die pad 12 and the first conductive layer 22b can be enhanced. The third insulating substrate 30a may be disposed between the die pad 12 and the second conductive layer 30b. Thereby, the insulation between the die pad 12 and the second conductive layer 30b can be enhanced.

第１導電層２２ｂと半導体チップ１４との間にはめっき層２２ｄが配置され得る。めっき層２２ｄは、第１導電層２２ｂのうち第１絶縁基板２２ａに覆われていない領域にコーティングされている。めっき層２２ｄは、第１導電層２２ｂ及び半導体チップ１４に電気的に接続されている。第２導電層３０ｂと半導体チップ１４との間にはめっき層３０ｄが配置され得る。めっき層３０ｄは、第２導電層３０ｂのうち第３絶縁基板３０ａに覆われていない領域にコーティングされている。めっき層３０ｄは、第２導電層３０ｂ及び半導体チップ１４に電気的に接続されている。めっき層２２ｄ及び３０ｄは例えばニッケル層及び金層を含む。めっき層２２ｄ及び３０ｄは例えばニッケル層を含む。この場合、第１導電層２２ｂ及び第２導電層３０ｂと半導体チップ１４との間の電気的な接続安定性が向上する。めっき層２２ｄは、第１導電層２２ｂとリード２０との間に配置されてもよい。めっき層３０ｄは、第２導電層３０ｂとリード１８との間に配置されてもよい。めっき層２２ｄは、第１導電層２２ｂの一方の面全体にコーティングされてもよいし、第１導電層２２ｂのうち第１絶縁基板２２ａに覆われていない領域に選択的にコーティングされてもよい。めっき層３０ｄは、第２導電層３０ｂの一方の面全体にコーティングされてもよいし、第２導電層３０ｂのうち第３絶縁基板３０ａに覆われていない領域に選択的にコーティングされてもよい。   A plating layer 22d may be disposed between the first conductive layer 22b and the semiconductor chip 14. The plating layer 22d is coated on a region of the first conductive layer 22b that is not covered with the first insulating substrate 22a. The plating layer 22d is electrically connected to the first conductive layer 22b and the semiconductor chip 14. A plating layer 30d may be disposed between the second conductive layer 30b and the semiconductor chip 14. The plating layer 30d is coated on a region of the second conductive layer 30b that is not covered with the third insulating substrate 30a. The plating layer 30d is electrically connected to the second conductive layer 30b and the semiconductor chip 14. The plating layers 22d and 30d include, for example, a nickel layer and a gold layer. The plating layers 22d and 30d include, for example, a nickel layer. In this case, the electrical connection stability between the first conductive layer 22b and the second conductive layer 30b and the semiconductor chip 14 is improved. The plating layer 22 d may be disposed between the first conductive layer 22 b and the lead 20. The plating layer 30 d may be disposed between the second conductive layer 30 b and the lead 18. The plating layer 22d may be coated on one whole surface of the first conductive layer 22b, or may be selectively coated on a region of the first conductive layer 22b that is not covered with the first insulating substrate 22a. . The plating layer 30d may be coated on one whole surface of the second conductive layer 30b, or may be selectively coated on a region of the second conductive layer 30b that is not covered with the third insulating substrate 30a. .

第１導電層２２ｂ及び第２導電層３０ｂの材料の例は、銅、アルミニウム等の金属を含む。第１導電層２２ｂ及び第２導電層３０ｂの材料が銅を含むと、第１導電層２２ｂ及び第２導電層３０ｂの放熱性が高くなる。第１導電層２２ｂ及び第２導電層３０ｂの厚みは例えば１２〜５０μｍである。この場合、第１導電層２２ｂ及び第２導電層３０ｂの放熱性が高くなる。第１絶縁基板２２ａ、第２絶縁基板２２ｃ、第３絶縁基板３０ａ、及び第４絶縁基板３０ｃの材料の例は、ポリイミド又はソルダレジスト等の樹脂を含む。この場合、第１絶縁基板２２ａ、第２絶縁基板２２ｃ、第３絶縁基板３０ａ、及び第４絶縁基板３０ｃの放熱性が高くなる。よって、第１導電層２２ｂに大電流が流れることによって発生した熱が第１絶縁基板２２ａ及び第２絶縁基板２２ｃを通しても放出され易くなる。第２導電層３０ｂに大電流が流れることによって発生した熱が第３絶縁基板３０ａ及び第４絶縁基板３０ｃを通しても放出され易くなる。   The example of the material of the 1st conductive layer 22b and the 2nd conductive layer 30b contains metals, such as copper and aluminum. When the material of the first conductive layer 22b and the second conductive layer 30b includes copper, the heat dissipation of the first conductive layer 22b and the second conductive layer 30b is increased. The thickness of the 1st conductive layer 22b and the 2nd conductive layer 30b is 12-50 micrometers, for example. In this case, the heat dissipation of the first conductive layer 22b and the second conductive layer 30b is enhanced. Examples of the material of the first insulating substrate 22a, the second insulating substrate 22c, the third insulating substrate 30a, and the fourth insulating substrate 30c include a resin such as polyimide or solder resist. In this case, the heat dissipation of the first insulating substrate 22a, the second insulating substrate 22c, the third insulating substrate 30a, and the fourth insulating substrate 30c is enhanced. Therefore, heat generated by a large current flowing through the first conductive layer 22b is easily released through the first insulating substrate 22a and the second insulating substrate 22c. Heat generated by a large current flowing through the second conductive layer 30b is easily released through the third insulating substrate 30a and the fourth insulating substrate 30c.

第１配線板２２の厚み方向（Ｚ方向）から見て、第１配線板２２と第２配線板３０とは少なくとも部分的に重なっていてもよい。この場合、Ｚ方向から見て半導体装置１０を小型化できる。例えば第１配線板２２が第２配線板３０上に設けられる。第１配線板２２と第２配線板３０とが一体化されていてもよい。これにより、半導体装置を小型化できる。例えば、第１絶縁基板２２ａと第４絶縁基板３０ｃとが一体化されていてもよい。   When viewed from the thickness direction (Z direction) of the first wiring board 22, the first wiring board 22 and the second wiring board 30 may overlap at least partially. In this case, the semiconductor device 10 can be reduced in size as viewed from the Z direction. For example, the first wiring board 22 is provided on the second wiring board 30. The first wiring board 22 and the second wiring board 30 may be integrated. Thereby, a semiconductor device can be reduced in size. For example, the first insulating substrate 22a and the fourth insulating substrate 30c may be integrated.

半導体チップ１４がＭＯＳ−ＦＥＴを含む場合、リード１６はドレイン電極端子に対応し、リード１８はゲート電極端子に対応し、リード２０はソース電極端子に対応し、電極パッドＧＰはゲート電極パッドに対応し、電極パッドＳＰはソース電極パッドに対応する。半導体チップ１４がＩＧＢＴを含む場合、リード１６はコレクタ電極端子に対応し、リード１８はゲート電極端子に対応し、リード２０はエミッタ電極端子に対応し、電極パッドＧＰはゲート電極パッドに対応し、電極パッドＳＰはエミッタ電極パッドに対応する。   When the semiconductor chip 14 includes a MOS-FET, the lead 16 corresponds to the drain electrode terminal, the lead 18 corresponds to the gate electrode terminal, the lead 20 corresponds to the source electrode terminal, and the electrode pad GP corresponds to the gate electrode pad. The electrode pad SP corresponds to the source electrode pad. When the semiconductor chip 14 includes an IGBT, the lead 16 corresponds to the collector electrode terminal, the lead 18 corresponds to the gate electrode terminal, the lead 20 corresponds to the emitter electrode terminal, the electrode pad GP corresponds to the gate electrode pad, The electrode pad SP corresponds to the emitter electrode pad.

ダイパッド１２及び半導体チップ１４は、樹脂部２４によって封止され得る。リード１６，１８，２０の内側端部は、樹脂部２４に固定される。リード１６，１８，２０のうち樹脂部２４の内側の部分は、いわゆるインナーリード部である。リード１６，１８，２０のうち樹脂部２４の外側の部分は、アウターリード部である。樹脂部２４の外形形状の一例は、略直方体である。樹脂部２４の材料の例は、ポリフェニレンサルファイド樹脂（ＰＰＳ樹脂）、液晶ポリマー等の熱可塑性樹脂を含む。樹脂部２４は、ダイパッド１２及び半導体チップ１４を熱可塑性樹脂でモールドすることによって形成され得る。樹脂部２４には、ダイパッド１２の貫通孔２６の中心軸線を中心軸線とする貫通孔２８が形成されている。貫通孔２８は、貫通孔２６と同様に螺子止めなどの際などに螺子が通される孔である。貫通孔２８の直径は、貫通孔２６の直径より小さい。   The die pad 12 and the semiconductor chip 14 can be sealed by the resin portion 24. Inner ends of the leads 16, 18, and 20 are fixed to the resin portion 24. Of the leads 16, 18, and 20, the portion inside the resin portion 24 is a so-called inner lead portion. Of the leads 16, 18, and 20, the portion outside the resin portion 24 is an outer lead portion. An example of the outer shape of the resin portion 24 is a substantially rectangular parallelepiped. Examples of the material of the resin portion 24 include thermoplastic resins such as polyphenylene sulfide resin (PPS resin) and liquid crystal polymer. The resin portion 24 can be formed by molding the die pad 12 and the semiconductor chip 14 with a thermoplastic resin. A through hole 28 is formed in the resin portion 24 with the central axis of the through hole 26 of the die pad 12 as the central axis. The through hole 28 is a hole through which a screw is passed in the case of screwing or the like, like the through hole 26. The diameter of the through hole 28 is smaller than the diameter of the through hole 26.

一実施形態において、ダイパッド１２のチップ搭載面１２ａと反対側の面である底面１２ｆは開放され得る。換言すれば、底面１２ｆは樹脂部２４によって覆われていない面であり得る。この場合、底面１２ｆは放熱面として機能し得る。   In one embodiment, the bottom surface 12f of the die pad 12 opposite to the chip mounting surface 12a can be opened. In other words, the bottom surface 12 f may be a surface that is not covered by the resin portion 24. In this case, the bottom surface 12f can function as a heat dissipation surface.

半導体装置１０では、Ｚ方向から見た第１配線板２２及び第２配線板３０の形状を任意に設計できるので、半導体装置１０の設計の自由度が高い。また、第１導電層２２ｂ及び第２導電層３０ｂでは、ワイヤに比べて表面積を大きくできるので、放熱性が向上する。例えば、第１導電層２２ｂ及び第２導電層３０ｂの断面形状が矩形であると、同じ断面積を有する断面形状が円形のワイヤに比べて第１導電層２２ｂ及び第２導電層３０ｂの表面積が大きくなる。さらに、第１絶縁基板２２ａ及び第２絶縁基板２２ｃによって第１導電層２２ｂが他の導電部材と接触する可能性を低減できる。第３絶縁基板３０ａ及び第４絶縁基板３０ｃによって第２導電層３０ｂが他の導電部材と接触する可能性を低減できる。   In the semiconductor device 10, since the shapes of the first wiring board 22 and the second wiring board 30 viewed from the Z direction can be arbitrarily designed, the degree of freedom in designing the semiconductor device 10 is high. Further, since the surface area of the first conductive layer 22b and the second conductive layer 30b can be made larger than that of the wire, the heat dissipation is improved. For example, if the cross-sectional shapes of the first conductive layer 22b and the second conductive layer 30b are rectangular, the surface areas of the first conductive layer 22b and the second conductive layer 30b are larger than those of a wire having the same cross-sectional area and a circular cross-section. growing. Further, the possibility of the first conductive layer 22b coming into contact with another conductive member by the first insulating substrate 22a and the second insulating substrate 22c can be reduced. The third insulating substrate 30a and the fourth insulating substrate 30c can reduce the possibility that the second conductive layer 30b is in contact with other conductive members.

第１配線板２２及び第２配線板３０がフレキシブルプリント配線板である場合、第１配線板２２及び第２配線板３０をフレキシブルに変形させることができるので、半導体装置１０の設計の自由度が更に高くなる。例えば第１配線板２２の第１導電層２２ｂと半導体チップ１４のトランジスタとを接続する際に、第１配線板２２を変形させることができるので、作業性が向上する。例えば半導体チップ１４の位置ずれがあっても、第１配線板２２を変形させることにより、第１配線板２２の第１導電層２２ｂと半導体チップ１４のトランジスタとを接続し易くなる。   When the first wiring board 22 and the second wiring board 30 are flexible printed wiring boards, the first wiring board 22 and the second wiring board 30 can be flexibly deformed, so that the degree of freedom in designing the semiconductor device 10 is increased. It gets even higher. For example, when the first conductive layer 22b of the first wiring board 22 and the transistor of the semiconductor chip 14 are connected, the first wiring board 22 can be deformed, so that workability is improved. For example, even if the semiconductor chip 14 is misaligned, the first conductive layer 22b of the first wiring board 22 and the transistor of the semiconductor chip 14 can be easily connected by deforming the first wiring board 22.

通常、複数の半導体チップのそれぞれにワイヤを接続する場合、ワイヤの本数が増えるため、ワイヤ同士が接触する可能性が高まる。しかし、半導体装置１０では、配線としてワイヤに代えて第１配線板２２及び第２配線板３０が用いられているので、配線同士が接触する可能性を低減できる。   Normally, when wires are connected to each of a plurality of semiconductor chips, the number of wires increases, so that the possibility that the wires come into contact with each other increases. However, in the semiconductor device 10, since the first wiring board 22 and the second wiring board 30 are used as the wirings instead of the wires, the possibility that the wirings contact each other can be reduced.

シリコン（Ｓｉ）では、半導体チップ１４に小さい電流しか流れないので、多数の配線を使用する必要性は低い。しかし、ワイドバンドギャップ半導体では、半導体チップ１４に流れる電流がシリコンよりも大きいので、電流の集中を抑制するために配線の本数を増やす必要性が高い。また、ワイドバンドギャップ半導体では、シリコンよりも低い製造歩留まりに起因して半導体チップ１４の大型化が難しい。このため、ワイドバンドギャップ半導体では、小型の半導体チップ１４に多数の配線が接続される。そのような場合でも、配線としてワイヤに代えて第１配線板２２及び第２配線板３０が用いられているので、配線同士が接触する可能性を低減できる。   In silicon (Si), since only a small current flows through the semiconductor chip 14, the necessity of using a large number of wirings is low. However, in the wide band gap semiconductor, since the current flowing through the semiconductor chip 14 is larger than that in silicon, it is highly necessary to increase the number of wirings in order to suppress current concentration. Further, in the wide band gap semiconductor, it is difficult to increase the size of the semiconductor chip 14 due to the manufacturing yield lower than that of silicon. For this reason, in the wide band gap semiconductor, a large number of wirings are connected to the small semiconductor chip 14. Even in such a case, since the 1st wiring board 22 and the 2nd wiring board 30 are used instead of a wire as wiring, possibility that wiring will contact can be reduced.

第１導電層２２ｂが半導体チップ１４のトランジスタのソース又はエミッタに電気的に接続される場合、第１導電層２２ｂに大電流が流れることによって、熱が発生する。そのような場合であっても、第１導電層２２ｂの表面積を大きくすることによって、第１導電層２２ｂの放熱性を高くすることができる。   When the first conductive layer 22b is electrically connected to the source or emitter of the transistor of the semiconductor chip 14, heat is generated by a large current flowing through the first conductive layer 22b. Even in such a case, the heat dissipation of the first conductive layer 22b can be increased by increasing the surface area of the first conductive layer 22b.

（第２実施形態）
図５は、第２実施形態に係る半導体装置を模式的に示す平面図である。図５に示される半導体装置１１０は、第１配線板２２に代えて第１配線板１２２を備えること以外は半導体装置１０と同様の構成を備える。 (Second Embodiment)
FIG. 5 is a plan view schematically showing the semiconductor device according to the second embodiment. The semiconductor device 110 shown in FIG. 5 has the same configuration as the semiconductor device 10 except that the first wiring board 122 is provided instead of the first wiring board 22.

本実施形態において、第１配線板１２２は、複数の半導体チップ１４にわたって延在し、開口部１２２ｈを有すること以外は第１配線板２２と同様の構造を有する。第１配線板１２２は、半導体チップ１４のそれぞれに電気的に接続されている。第２配線板３０は、第１配線板１２２上に設けられる。第２配線板３０の分岐した第１端部は、開口部１２２ｈを通って半導体チップ１４に接続される。   In the present embodiment, the first wiring board 122 has the same structure as the first wiring board 22 except that it extends over the plurality of semiconductor chips 14 and has the opening 122h. The first wiring board 122 is electrically connected to each of the semiconductor chips 14. The second wiring board 30 is provided on the first wiring board 122. The branched first end of the second wiring board 30 is connected to the semiconductor chip 14 through the opening 122h.

図６は、第２実施形態に係る半導体装置の第１配線板を模式的に示す図である。図６に示される第１配線板１２２は、第１絶縁基板１２２ａ、第１導電層１２２ｂ、及び第２絶縁基板１２２ｃを備える。第１導電層１２２ｂは第１絶縁基板１２２ａと第２絶縁基板１２２ｃとの間に配置される。第１導電層１２２ｂは、半導体チップ１４のトランジスタに電気的に接続される。第１導電層１２２ｂと半導体チップ１４との間には、めっき層１２２ｄが配置され得る。めっき層１２２ｄは、第１導電層１２２ｂのうち第１絶縁基板１２２ａに覆われていない領域にコーティングされている。めっき層１２２ｄは、第１導電層１２２ｂ及び半導体チップ１４に電気的に接続されている。   FIG. 6 is a diagram schematically illustrating the first wiring board of the semiconductor device according to the second embodiment. The first wiring board 122 shown in FIG. 6 includes a first insulating substrate 122a, a first conductive layer 122b, and a second insulating substrate 122c. The first conductive layer 122b is disposed between the first insulating substrate 122a and the second insulating substrate 122c. The first conductive layer 122b is electrically connected to the transistor of the semiconductor chip 14. A plating layer 122d may be disposed between the first conductive layer 122b and the semiconductor chip 14. The plated layer 122d is coated on a region of the first conductive layer 122b that is not covered with the first insulating substrate 122a. The plating layer 122d is electrically connected to the first conductive layer 122b and the semiconductor chip 14.

半導体装置１１０では、少なくとも半導体装置１０と同様の作用効果が得られる。   In the semiconductor device 110, at least the same effects as the semiconductor device 10 can be obtained.

（第３実施形態）
図７は、第３実施形態に係る半導体装置を模式的に示す平面図である。図８は、第３実施形態に係る半導体装置の各部品を模式的に示す図である。図７に示される半導体装置２１０は、ケース型の半導体装置である。半導体装置２１０は、チップ搭載基板としての配線基板４０と、複数の半導体チップ１４と、半導体チップ１４上に設けられた第１配線板２２２及び第２配線板３０と、ケース５２とを備える。 (Third embodiment)
FIG. 7 is a plan view schematically showing the semiconductor device according to the third embodiment. FIG. 8 is a diagram schematically showing each part of the semiconductor device according to the third embodiment. A semiconductor device 210 shown in FIG. 7 is a case-type semiconductor device. The semiconductor device 210 includes a wiring board 40 as a chip mounting board, a plurality of semiconductor chips 14, a first wiring board 222 and a second wiring board 30 provided on the semiconductor chip 14, and a case 52.

配線基板４０は、半導体チップ１４が搭載されるチップ搭載面４６ａを有する。半導体チップ１４は、接着層３２を介してチップ搭載面４６ａに搭載される。配線基板４０は、絶縁性基板４２と、絶縁性基板４２の表面に設けられた配線パターン４６，４６Ｓ，４６Ｇとを備える。半導体チップ１４は配線パターン４６上に配置される。配線パターン４６は、接着層３２を介して半導体チップ１４に電気的に接続される。配線パターン４６Ｓは、第１配線板２２２を介して半導体チップ１４に電気的に接続される。配線パターン４６Ｇは、第２配線板３０を介して半導体チップ１４に電気的に接続される。配線パターン４６，４６Ｓ，４６Ｇの材料の例は、銅及び銅合金等の金属を含む。絶縁性基板４２の材料の例は、アルミナ等のセラミックを含む。   The wiring substrate 40 has a chip mounting surface 46a on which the semiconductor chip 14 is mounted. The semiconductor chip 14 is mounted on the chip mounting surface 46 a via the adhesive layer 32. The wiring substrate 40 includes an insulating substrate 42 and wiring patterns 46, 46 </ b> S, and 46 </ b> G provided on the surface of the insulating substrate 42. The semiconductor chip 14 is disposed on the wiring pattern 46. The wiring pattern 46 is electrically connected to the semiconductor chip 14 through the adhesive layer 32. The wiring pattern 46S is electrically connected to the semiconductor chip 14 via the first wiring board 222. The wiring pattern 46G is electrically connected to the semiconductor chip 14 via the second wiring board 30. Examples of the material of the wiring patterns 46, 46S, and 46G include metals such as copper and copper alloys. An example of the material of the insulating substrate 42 includes ceramic such as alumina.

絶縁性基板４２の裏面には放熱層が設けられてもよい。放熱層の材料の例は、銅及び銅合金等の金属を含む。放熱層は、例えば半田等からなる接着層を介してヒートシンクに接着される。ヒートシンクの材料の例は、金属を含む。   A heat dissipation layer may be provided on the back surface of the insulating substrate 42. Examples of the material of the heat dissipation layer include metals such as copper and copper alloys. The heat dissipation layer is bonded to the heat sink through an adhesive layer made of, for example, solder. Examples of heat sink materials include metals.

第１配線板２２２は、めっき層の位置が異なること以外は第１配線板２２と同様の構成を備える。第１配線板２２２は、第１絶縁基板２２２ａ、第１導電層２２２ｂ、及び第２絶縁基板２２２ｃを備える。第１導電層２２２ｂは第１絶縁基板２２２ａと第２絶縁基板２２２ｃとの間に配置される。第１導電層２２２ｂは、半導体チップ１４のトランジスタに電気的に接続される。第１導電層２２２ｂと半導体チップ１４との間には、めっき層２２２ｄが配置され得る。めっき層２２２ｄは、第１導電層２２２ｂのうち第１絶縁基板２２２ａに覆われていない領域にコーティングされている。めっき層２２２ｄは、第１導電層２２２ｂ及び半導体チップ１４に電気的に接続されている。   The first wiring board 222 has the same configuration as the first wiring board 22 except that the position of the plating layer is different. The first wiring board 222 includes a first insulating substrate 222a, a first conductive layer 222b, and a second insulating substrate 222c. The first conductive layer 222b is disposed between the first insulating substrate 222a and the second insulating substrate 222c. The first conductive layer 222b is electrically connected to the transistor of the semiconductor chip 14. A plating layer 222d may be disposed between the first conductive layer 222b and the semiconductor chip 14. The plated layer 222d is coated on a region of the first conductive layer 222b that is not covered with the first insulating substrate 222a. The plating layer 222d is electrically connected to the first conductive layer 222b and the semiconductor chip 14.

半導体装置２１０は、ドレイン端子ＤＴ、ソース端子ＳＴ、及びゲート端子ＧＴを備え得る。ドレイン端子ＤＴは、例えばＦＰＣ等の配線板４８Ｄを介して配線パターン４６に電気的に接続される。ソース端子ＳＴは、例えばＦＰＣ等の配線板４８Ｓを介して配線パターン４６Ｓに電気的に接続される。ゲート端子ＧＴは、例えばＦＰＣ等の配線板４８Ｇを介して配線パターン４６Ｇに電気的に接続される。配線板４８Ｇ、４８Ｄ，４８Ｓはワイヤ又はボンディングリボンに置き換えられてもよい。   The semiconductor device 210 can include a drain terminal DT, a source terminal ST, and a gate terminal GT. The drain terminal DT is electrically connected to the wiring pattern 46 via a wiring board 48D such as an FPC. The source terminal ST is electrically connected to the wiring pattern 46S via a wiring board 48S such as an FPC. The gate terminal GT is electrically connected to the wiring pattern 46G via a wiring board 48G such as an FPC. The wiring boards 48G, 48D, and 48S may be replaced with wires or bonding ribbons.

半導体チップ１４、配線基板４０、第１配線板２２２、及び第２配線板３０は、ケース５２に収容される。ケース５２は、例えば筒状である。ケース５２の一方の開口はヒートシンクによって封止され得る。ケース５２の他方の開口は蓋によって封止され得る。ケース５２の材料の例は、ポリブチレンテレフタレート（ＰＢＴ）又はポリフェニレンサルファイド（ＰＰＳ）樹脂といったエンジニヤリングプラスチック等の樹脂を含む。蓋の材料の例は熱可塑性樹脂を含む。ケース５２の内側には、応力緩和のため、例えばシリコーンゲル等のゲルが注入され得る。   The semiconductor chip 14, the wiring board 40, the first wiring board 222, and the second wiring board 30 are accommodated in the case 52. The case 52 has a cylindrical shape, for example. One opening of the case 52 can be sealed by a heat sink. The other opening of the case 52 can be sealed with a lid. Examples of the material of the case 52 include resins such as engineering plastics such as polybutylene terephthalate (PBT) or polyphenylene sulfide (PPS) resin. Examples of the lid material include a thermoplastic resin. For example, a gel such as a silicone gel can be injected into the case 52 for stress relaxation.

ゲート端子ＧＴ、ドレイン端子ＤＴ、及びソース端子ＳＴはケース５２の内壁に取り付けられる。ゲート端子ＧＴ、ドレイン端子ＤＴ、及びソース端子ＳＴは、ケース５２の内壁に沿って延びており、蓋に形成された開口を通って外部に突出する。ゲート端子ＧＴ、ドレイン端子ＤＴ、及びソース端子ＳＴは、プレス加工等により作製され得る。   The gate terminal GT, the drain terminal DT, and the source terminal ST are attached to the inner wall of the case 52. The gate terminal GT, the drain terminal DT, and the source terminal ST extend along the inner wall of the case 52 and project outside through an opening formed in the lid. The gate terminal GT, the drain terminal DT, and the source terminal ST can be manufactured by press working or the like.

半導体装置２１０では、少なくとも半導体装置１０と同様の作用効果が得られる。   In the semiconductor device 210, at least the same effects as the semiconductor device 10 can be obtained.

以上、本発明の好適な実施形態について詳細に説明されたが、本発明は上記実施形態に限定されない。各実施形態の構成要素は任意に組み合わされ得る。   As mentioned above, although preferred embodiment of this invention was described in detail, this invention is not limited to the said embodiment. The components of each embodiment can be arbitrarily combined.

例えば、半導体装置１０，１１０，２１０は、単一の半導体チップ１４を備えてもよい。半導体装置１０では、第２配線板３０が第１配線板２２上に設けられてもよい。半導体装置１１０では、第１配線板１２２が第２配線板３０上に設けられてもよい。この場合、第１配線板１２２の開口部１２２ｈは不要になる。半導体装置２１０では、第２配線板３０が第１配線板２２２上に設けられてもよい。この場合、第１配線板２２２には、開口部１２２ｈと同様の開口部が形成される。   For example, the semiconductor devices 10, 110, and 210 may include a single semiconductor chip 14. In the semiconductor device 10, the second wiring board 30 may be provided on the first wiring board 22. In the semiconductor device 110, the first wiring board 122 may be provided on the second wiring board 30. In this case, the opening 122h of the first wiring board 122 is not necessary. In the semiconductor device 210, the second wiring board 30 may be provided on the first wiring board 222. In this case, the first wiring board 222 has an opening similar to the opening 122h.

第１配線板２２、第１配線板１２２、又は第１配線板２２２がワイヤ又はボンディングリボンに置き換えられてもよい。この場合、半導体装置１０，１１０，２１０は、第２配線板３０を備える。第２配線板３０がワイヤ又はボンディングリボンに置き換えられてもよい。ワイヤ又はボンディングリボンは、例えば超音波又は加圧等を用いたワイヤボンディングによりリード１８，２０、配線パターン４６Ｇ，４６Ｓ及び半導体チップ１４に電気的に接続され得る。   The first wiring board 22, the first wiring board 122, or the first wiring board 222 may be replaced with a wire or a bonding ribbon. In this case, the semiconductor devices 10, 110, and 210 include the second wiring board 30. The second wiring board 30 may be replaced with a wire or a bonding ribbon. The wire or the bonding ribbon can be electrically connected to the leads 18 and 20, the wiring patterns 46 </ b> G and 46 </ b> S, and the semiconductor chip 14 by wire bonding using, for example, ultrasonic waves or pressure.

半導体チップ１４が横型トランジスタを含む場合、半導体装置１０，１１０は、半導体チップ１４とリード１６とを接続する第３配線板を備え得る。半導体装置２１０は、半導体チップ１４と配線パターン４６とを接続する第３配線板を備え得る。第３配線板は、第１配線板２２と同様の構成を備える。   When the semiconductor chip 14 includes a lateral transistor, the semiconductor devices 10 and 110 may include a third wiring board that connects the semiconductor chip 14 and the leads 16. The semiconductor device 210 may include a third wiring board that connects the semiconductor chip 14 and the wiring pattern 46. The third wiring board has the same configuration as the first wiring board 22.

１０，１１０，２１０…半導体装置、１２…ダイパッド（チップ搭載基板）、１２ａ，４６ａ…チップ搭載面、１４…半導体チップ、２２，１２２，２２２…第１配線板、２２ａ，１２２ａ，２２２ａ…第１絶縁基板、２２ｂ，１２２ｂ，２２２ｂ…第１導電層、２２ｃ，１２２ｃ，２２２ｃ…第２絶縁基板、２２ｄ，１２２ｄ，２２２ｄ…めっき層、３０…第２配線板、３０ａ…第３絶縁基板（ゲート用絶縁基板）、３０ｂ…第２導電層、４０…配線基板（チップ搭載基板）。   DESCRIPTION OF SYMBOLS 10,110,210 ... Semiconductor device, 12 ... Die pad (chip mounting substrate), 12a, 46a ... Chip mounting surface, 14 ... Semiconductor chip, 22, 122, 222 ... 1st wiring board, 22a, 122a, 222a ... 1st Insulating substrate, 22b, 122b, 222b ... first conductive layer, 22c, 122c, 222c ... second insulating substrate, 22d, 122d, 222d ... plating layer, 30 ... second wiring board, 30a ... third insulating substrate (for gate) Insulating substrate), 30b, second conductive layer, 40, wiring substrate (chip mounting substrate).

Claims (17)

トランジスタを含む少なくとも１つの半導体チップと、
前記少なくとも１つの半導体チップが搭載されるチップ搭載面を有するチップ搭載基板と、
前記少なくとも１つの半導体チップ上に設けられた第１配線板と、
を備え、
前記第１配線板は、第１絶縁基板と、前記第１絶縁基板上に設けられ、前記トランジスタに電気的に接続された第１導電層と、を備える、半導体装置。 At least one semiconductor chip including a transistor;
A chip mounting substrate having a chip mounting surface on which the at least one semiconductor chip is mounted;
A first wiring board provided on the at least one semiconductor chip;
With
The first wiring board includes a first insulating substrate and a first conductive layer provided on the first insulating substrate and electrically connected to the transistor. 前記第１配線板がフレキシブルプリント配線板である、請求項１に記載の半導体装置。   The semiconductor device according to claim 1, wherein the first wiring board is a flexible printed wiring board. 前記少なくとも１つの半導体チップが複数の半導体チップである、請求項１又は２に記載の半導体装置。   The semiconductor device according to claim 1, wherein the at least one semiconductor chip is a plurality of semiconductor chips. 前記少なくとも１つの半導体チップの材料が、ワイドバンドギャップ半導体を含む、請求項１〜３のいずれか一項に記載の半導体装置。   The semiconductor device according to claim 1, wherein the material of the at least one semiconductor chip includes a wide band gap semiconductor. 前記第１導電層の材料が、銅を含む、請求項１〜４のいずれか一項に記載の半導体装置。   The semiconductor device according to claim 1, wherein a material of the first conductive layer includes copper. 前記第１導電層が前記トランジスタのソース又はエミッタに電気的に接続される、請求項１〜５のいずれか一項に記載の半導体装置。   The semiconductor device according to claim 1, wherein the first conductive layer is electrically connected to a source or an emitter of the transistor. 前記トランジスタの第１端子が前記チップ搭載基板に電気的に接続されており、
前記トランジスタの第２端子が前記第１導電層に電気的に接続されており、
前記第１絶縁基板が前記チップ搭載基板と前記第１導電層との間に配置される、請求項１〜６のいずれか一項に記載の半導体装置。 A first terminal of the transistor is electrically connected to the chip mounting substrate;
A second terminal of the transistor is electrically connected to the first conductive layer;
The semiconductor device according to claim 1, wherein the first insulating substrate is disposed between the chip mounting substrate and the first conductive layer. 前記第１配線板が、第２絶縁基板を更に備え、前記第１導電層が前記第１絶縁基板と前記第２絶縁基板との間に配置される、請求項１〜７のいずれか一項に記載の半導体装置。   The first wiring board further includes a second insulating substrate, and the first conductive layer is disposed between the first insulating substrate and the second insulating substrate. A semiconductor device according to 1. 前記第１導電層の厚みが１２〜５０μｍである、請求項１〜８のいずれか一項に記載の半導体装置。   The semiconductor device according to claim 1, wherein the first conductive layer has a thickness of 12 to 50 μm. 前記第１絶縁基板の材料が、ポリイミド又はソルダレジストを含む、請求項１〜９のいずれか一項に記載の半導体装置。   The semiconductor device according to claim 1, wherein the material of the first insulating substrate includes polyimide or solder resist. 前記第１導電層と前記少なくとも１つの半導体チップとの間にめっき層が配置され、
前記めっき層が、前記第１導電層のうち前記第１絶縁基板に覆われていない領域にコーティングされており、
前記めっき層が、前記第１導電層及び前記少なくとも１つの半導体チップに電気的に接続されており、
前記めっき層が、ニッケル層及び金層を含むか、又はニッケル層を含む、請求項１〜１０のいずれか一項に記載の半導体装置。 A plating layer is disposed between the first conductive layer and the at least one semiconductor chip;
The plating layer is coated on a region of the first conductive layer that is not covered with the first insulating substrate,
The plating layer is electrically connected to the first conductive layer and the at least one semiconductor chip;
The semiconductor device according to claim 1, wherein the plating layer includes a nickel layer and a gold layer, or includes a nickel layer. 前記第１導電層が前記トランジスタのソース又はエミッタに電気的に接続されており、
前記少なくとも１つの半導体チップ上に設けられた第２配線板を更に備え、
前記第２配線板は、ゲート用絶縁基板と、前記ゲート用絶縁基板上に設けられ、前記トランジスタのゲートに電気的に接続された第２導電層と、を備える、請求項１〜１１のいずれか一項に記載の半導体装置。 The first conductive layer is electrically connected to a source or emitter of the transistor;
A second wiring board provided on the at least one semiconductor chip;
The said 2nd wiring board is provided with the insulating substrate for gates, and the 2nd conductive layer provided on the said insulating substrate for gates, and was electrically connected to the gate of the said transistor, The any one of Claims 1-11 The semiconductor device according to claim 1. 前記第１配線板の厚み方向から見て、前記第１配線板と前記第２配線板とが少なくとも部分的に重なっている、請求項１２に記載の半導体装置。   The semiconductor device according to claim 12, wherein the first wiring board and the second wiring board at least partially overlap each other when viewed from the thickness direction of the first wiring board. 前記第１配線板と前記第２配線板とが一体化されている、請求項１２又は１３に記載の半導体装置。   The semiconductor device according to claim 12 or 13, wherein the first wiring board and the second wiring board are integrated. 前記少なくとも１つの半導体チップが複数の半導体チップであり、
前記複数の半導体チップのそれぞれに前記第１配線板が分岐しており、
分岐した前記第１配線板が前記複数の半導体チップのそれぞれに電気的に接続されている、請求項１〜１４のいずれか一項に記載の半導体装置。 The at least one semiconductor chip is a plurality of semiconductor chips;
The first wiring board is branched to each of the plurality of semiconductor chips;
The semiconductor device according to claim 1, wherein the branched first wiring board is electrically connected to each of the plurality of semiconductor chips. 前記少なくとも１つの半導体チップが複数の半導体チップであり、
前記複数の半導体チップにわたって前記第１配線板が延在しており、
前記第１配線板が前記複数の半導体チップのそれぞれに電気的に接続されている、請求項１〜１４のいずれか一項に記載の半導体装置。 The at least one semiconductor chip is a plurality of semiconductor chips;
The first wiring board extends across the plurality of semiconductor chips;
The semiconductor device according to claim 1, wherein the first wiring board is electrically connected to each of the plurality of semiconductor chips. 前記第１導電層が前記トランジスタのゲートに電気的に接続される、請求項１〜５のいずれか一項に記載の半導体装置。   The semiconductor device according to claim 1, wherein the first conductive layer is electrically connected to a gate of the transistor.
JP2013040912A 2013-03-01 2013-03-01 Semiconductor device Pending JP2014170800A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2013040912A JP2014170800A (en) 2013-03-01 2013-03-01 Semiconductor device
PCT/JP2014/054209 WO2014132897A1 (en) 2013-03-01 2014-02-21 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2013040912A JP2014170800A (en) 2013-03-01 2013-03-01 Semiconductor device

Publications (1)

Publication Number Publication Date
JP2014170800A true JP2014170800A (en) 2014-09-18

Family

ID=51428165

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2013040912A Pending JP2014170800A (en) 2013-03-01 2013-03-01 Semiconductor device

Country Status (2)

Country Link
JP (1) JP2014170800A (en)
WO (1) WO2014132897A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6604183B2 (en) * 2015-12-16 2019-11-13 富士電機株式会社 Semiconductor module

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05283582A (en) * 1992-04-03 1993-10-29 Sharp Corp Positive and negative stabilized power supply
JP2009164240A (en) * 2007-12-28 2009-07-23 Panasonic Corp Semiconductor device
JP2010003858A (en) * 2008-06-20 2010-01-07 Sumitomo Electric Ind Ltd Semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05283582A (en) * 1992-04-03 1993-10-29 Sharp Corp Positive and negative stabilized power supply
JP2009164240A (en) * 2007-12-28 2009-07-23 Panasonic Corp Semiconductor device
JP2010003858A (en) * 2008-06-20 2010-01-07 Sumitomo Electric Ind Ltd Semiconductor device

Also Published As

Publication number Publication date
WO2014132897A1 (en) 2014-09-04

Similar Documents

Publication Publication Date Title
JP5272191B2 (en) Semiconductor device and manufacturing method of semiconductor device
US7846779B2 (en) Power device package and method of fabricating the same
KR101493865B1 (en) Semiconductor power module package with simplified structure and method of fabricating the same
JP5930070B2 (en) Semiconductor device
KR101555300B1 (en) Semiconductor power module package having external boding area
JP2015142072A (en) semiconductor device
US20130249008A1 (en) Semiconductor device
US8896114B2 (en) Semiconductor device
KR101388857B1 (en) Semiconductor package and method of manufacturing the semiconductor package
WO2014132826A1 (en) Semiconductor device
JP2007027404A (en) Semiconductor device
KR100585896B1 (en) Semiconductor device and hybrid integrated circuit device
WO2013150890A1 (en) Semiconductor device
JP5341339B2 (en) Circuit equipment
JP5172290B2 (en) Semiconductor device
WO2013172139A1 (en) Semiconductor device
WO2014132897A1 (en) Semiconductor device
US9123710B2 (en) Semiconductor device having a semiconductor chip and wiring
JP2010219554A (en) Semiconductor device and electronic controller using the same
WO2018012281A1 (en) Semiconductor device
JP6866913B2 (en) Semiconductor device
JP2007027403A (en) Semiconductor device
KR200176241Y1 (en) Structure of semiconductor package
JP2014220329A (en) Semiconductor device manufacturing method
JP2014187146A (en) Semiconductor device

Legal Events

Date Code Title Description
A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20150428