JP2014165362A - Printed wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a printed wiring board which can supply stable electric power to IC chips.SOLUTION: A printed wiring board is formed by a first printed wiring board having a first electric circuit and a second printed wiring board having a second electric circuit. A solenoid coil is formed by the first and second electric circuits.

Description

The present invention relates to a printed wiring board including a first printed wiring board and a second printed wiring board, and a helical coil is formed by the electric circuit of the first printed wiring board and the electric circuit of the second printed wiring board. ing.

Forming a voltage adjustment VRM on a printed wiring board on which an IC chip is mounted is required for shortening the power supply line. Generally, an inductor for decoupling is provided between the VRM and the IC chip. Patent document 1 is disclosing the printed wiring board which incorporates an inductor. Patent Document 1 discloses manufacturing an inductor from a metal plate. And in patent document 1, the inductor is adhere | attached on a board | substrate, and as FIG. 6 of patent document 1 shows, the board | substrate with a built-in inductor is manufactured. Patent Document 1 states that the thickness of the inductor can be increased by manufacturing the inductor by press working.

JP 2008-270532 A

In Patent Document 1, since a thick inductor is bonded on a substrate, it is considered that an interlayer insulating layer for incorporating the inductor becomes thick. Therefore, it is assumed that the thickness of the substrate with built-in inductor is increased.
Since the inductor is thick, the thickness of the interlayer insulating layer for incorporating the inductor is considered to be thicker than the thickness of the other interlayer insulating layers. Therefore, it is considered that warpage occurs in the inductor built-in substrate.
As shown in FIG. 11 of Patent Literature 1, the inductor-embedded substrate of Patent Literature 1 has via conductors in an interlayer insulating layer for incorporating the inductor and other interlayer insulating layers. Since the thickness of the interlayer insulating layer for incorporating the inductor is considered to be thicker than the thickness of the other interlayer insulating layers, it is considered that the opening for the via conductor formed in the interlayer insulating layer for incorporating the inductor becomes deep. . Therefore, it is considered that connection reliability is lowered.
In addition, since the inductor component is bonded to the substrate, the degree of freedom in wiring design is expected to decrease.
In Patent Document 1, an inductor is bonded to a substrate. Therefore, with the method of Patent Document 1, it is considered difficult to stack inductors. Therefore, in Patent Document 1, it is considered difficult to obtain a high inductance.

An object of the present invention is to provide a printed wiring board having a built-in inductor having high inductance and Q value. Another object is to reduce the amount of warping of the printed wiring board containing the inductor.

The printed wiring board according to the present invention includes a first printed wiring board having a first electric circuit, a second printed wiring board having a second electric circuit, the first printed wiring board, and the second printed circuit board. And a plurality of connecting members connecting the first electric circuit and the second electric circuit. A helical coil is formed by the first electric circuit, the connection member, and the second electric circuit.

Process drawing which shows the manufacturing method of the 1st printed wiring board which concerns on 1st Embodiment of this invention. Process drawing which shows the manufacturing method of the 1st printed wiring board of 1st Embodiment. Process drawing which shows the manufacturing method of the 1st printed wiring board of 1st Embodiment. Process drawing which shows the manufacturing method of the 1st printed wiring board of 1st Embodiment. Sectional drawing of the 1st printed wiring board which concerns on 1st Embodiment. Sectional drawing of the printed wiring board of 1st Embodiment. 7A shows the electric circuit of the first printed wiring board, FIG. 7B shows the electric circuit of the second printed wiring board, and FIG. 7C shows the solenoid coil in the printed wiring board. Show. Sectional drawing of the printed wiring board which concerns on another example. Sectional drawing of the printed wiring board which concerns on another example. Sectional drawing of the printed wiring board which concerns on another example. Sectional drawing of the printed wiring board which concerns on another example. 12A and 12C show an electric circuit of a first printed wiring board according to another example, and FIGS. 12B and 12D show an electric circuit of a second printed wiring board. The figure which shows the horizontal wiring and vertical wiring in a solenoid coil.

[First embodiment]
FIG. 6 is a cross-sectional view of the printed wiring board 100 according to the first embodiment.
The printed wiring board 100 includes a printed wiring board (first printed wiring board) 10 on which the IC chip 90 is mounted and a mother board (second printed wiring board) 210 on which the printed wiring board 10 is mounted.

The first printed wiring board 10 of the first embodiment is shown in FIG. The first printed wiring board has a core substrate 30. The core substrate includes an insulating substrate 20z having a first surface F and a second surface S opposite to the first surface, a first conductor layer 34F formed on the first surface F of the insulating substrate, and the insulating substrate. A second conductor layer 34S formed on the second surface, and a through-hole conductor 36 connecting the first conductor layer and the second conductor layer are provided. The first conductor layer 34F includes through-hole conductor lands 36FR, and the second conductor layer 34S includes through-hole conductor lands 36SR. The land of the through-hole conductor is formed by a conductor covering the through-hole 28 for the through-hole conductor and a conductor around the through-hole conductor. The first surface of the core substrate and the first surface of the insulating substrate are the same surface, and the second surface of the core substrate and the second surface of the insulating substrate are the same surface.

An interlayer resin insulation layer (uppermost interlayer resin insulation layer) 50F is formed on first surface F of core substrate 30. A conductor layer (uppermost conductor layer) 58F is formed on this interlayer resin insulation layer 50F. The uppermost conductor layer (58F), the first conductor layer (34F), and the through-hole conductor are connected by a via conductor (uppermost via conductor) 60F that penetrates the uppermost interlayer resin insulation layer (50F). The upper buildup layer 55F is formed by the interlayer resin insulation layer 50F, the conductor layer 58F, and the via conductor 60F. In the first embodiment, the upper buildup layer is one layer.

An interlayer resin insulation layer (lowermost interlayer resin insulation layer) 50S is formed on the second surface S of the core substrate 30. A conductor layer (lowermost conductor layer) 58S is formed on the interlayer resin insulation layer 50S. The lowermost conductor layer (58S), the second conductor layer (34S), and the through-hole conductor are connected by a via conductor (lowermost via conductor) 60S that penetrates the lowermost interlayer resin insulation layer (50S). A lower buildup layer 55S is formed by the interlayer resin insulation layer 50S, the conductor layer 58S, and the via conductor 60S. In the first embodiment, the lower buildup layer is one layer.

An upper solder resist layer 70F is formed on the upper buildup layer, and a lower solder resist layer 70S is formed on the lower buildup layer. The solder resist layer 70F has an opening 71F that exposes the upper surfaces of the conductor layer 58F and the via conductor 60F. The conductor layer 58F and the via conductor 60F exposed from the opening 71F are pads. In particular, the pad formed on the uppermost conductor layer functions as a C4 pad. The solder resist layer 70S has an opening 71S that exposes the upper surfaces of the conductor layer 58S and the via conductor 60S. The conductor layer 58S and the via conductor 60S exposed from the opening 71S are pads. The pad formed on the lowermost conductor layer functions as a BGA pad.

The first printed wiring board has a first electric circuit constituting an inductor. An example of this is shown in FIG. FIG. 7A is a plan view showing a part of the lowermost conductor layer and a part of the lowermost interlayer resin insulation layer of the first printed wiring board 10. The first electric circuit shown in FIG. 7A is a part of the lowermost conductor layer 58S, and the lowermost conductor layer includes the first electric circuit. The first electric circuit includes a pad 58SR constituting the inductor in the first printed wiring board and a wiring 58 (wiring constituting the inductor in the first printed wiring board) 58SL formed between the pads.

Another example is shown in FIG. In this example, the first electric circuit includes a pad 58SR connected to the connection member (the pad 58SR is included in the lowermost conductor layer), a pad 34SP, a pad 58SR, and a pad 34SP included in the second conductor layer. Are formed by a via conductor 60SL (the via conductor 60SL is included in the lowermost via conductor) and a wiring 34SL between the pad 34SP and the pad 34SP (the wiring 34SL is included in the second conductor layer).
The first electric circuit exists immediately below the C4 pad. That is, an IC chip is mounted immediately above the solenoid coil. A cross section between X1 and X1 shown in FIG. 12A is shown in FIG.

A solder bump (C4 bump) 76F is formed on the C4 pad. Solder bumps (BGA bumps) 76S are formed on the BGA pads. An IC chip is mounted on the first printed wiring board via the C4 bump.

The mother board 210 according to the first embodiment is formed of a plurality of conductors for interlayer connection that penetrate through the interlayer insulation layers and connect the adjacent conductor layers through the plurality of conductor layers that are alternately stacked. Has been. The motherboard shown in FIG. 6 has four conductor layers 158A, 158B, 158C, 158D and three interlayer insulation layers 150A, 150, 150C. The conductor layer 158A is the uppermost conductor layer, is closest to the first printed wiring board, and opposes the solder resist layer on the lower side of the first printed wiring board. The conductor layer 158D is the lowermost conductor layer and is farthest from the first printed wiring board. The conductor layer and the interlayer insulating layer are laminated in the order of the conductor layer 158D, the interlayer insulating layer 150C, the conductor layer 158C, the interlayer insulating layer 150B, the conductor layer 158B, the interlayer insulating layer 150A, and the conductor layer 158A. The mother board shown in FIG. 6 further penetrates the interlayer connection conductor (via conductor) 160A passing through the interlayer insulating layer 150A and connecting the conductor layers 158A and 158B and the interlayer insulating layer 150B, and the conductor layers 158B and conductors. Interlayer connection conductor (via conductor) 160B connecting the layer 158C and the interlayer connection conductor (via conductor) 160C passing through the interlayer insulating layer 150C and connecting the conductor layer 158C and the conductor layer 158D ing. Upper solder resist layer 170F is formed on conductive layer (158A) and interlayer insulating layer (150A). The solder resist layer 170F has an opening 171F for exposing the uppermost conductor layer 158A. The uppermost conductor layer 158A exposed through the opening 171F is a pad. The pad formed on the uppermost conductor layer 158A functions as an external terminal. The second printed wiring board and the first printed wiring board are connected via part of the external terminals. Further, the first electric circuit and the second electric circuit are connected through a part of the external terminal.
A lower solder resist layer 170S having an opening 171S is formed on the conductor layer 158D and the interlayer insulating layer 150C.

The motherboard has a second electrical circuit that constitutes an inductor. An example of this is shown in FIG. FIG. 7B is a plan view showing a part of the uppermost conductor layer 158A and a part of the uppermost interlayer insulating layer 150A of the second printed wiring board 10. FIG. The second electric circuit shown in FIG. 7B is a part of the uppermost conductor layer 158A, and the uppermost conductor layer 158 includes the second electric circuit. The second electric circuit is an external terminal (pad) 158AR constituting the inductor in the second printed wiring board and a wiring formed between the external terminal (pad) (constituting the inductor in the second printed wiring board). Wiring 158AL.

Another example is shown in FIG. In this example, the second electric circuit includes pads 158AR (pads included in the uppermost conductive layer 158A) of the second printed wiring board, pads 158BP, pads 158AR, and pads 158BP included in the inner conductive layer 158B. The via conductor 160AL to be connected (via conductor formed in the uppermost interlayer insulating layer 150A) and the wiring 158BL (wiring included in the inner conductive layer 158B) connecting the pad 158BP and the pad 158BP are formed. A cross section between X2 and X2 shown in FIG. 12 (B) is shown in FIG. 12 (D).
The second electric circuit exists immediately below the C4 pad.

The pads formed on the lowermost conductor layer of the first printed wiring board and the pads formed on the uppermost conductor layer of the second printed wiring board have a protrusion PrP as shown in FIG. May be. If the pad is a pad having the protrusion PrP, the distance between the first and second printed wiring boards is ensured, and the inductance value increases. It is preferable that the pad formed on the lowermost conductor layer of the first printed wiring board and the pad formed on the uppermost conductive layer of the second printed wiring board are both pads having protrusions. Furthermore, when both pads are connected by metal core bumps described later, the distance between the first and second printed wiring boards becomes longer.

FIG. 7C schematically shows a solenoid coil formed of a connecting member that connects the first electric circuit, the second electric circuit, the first electric circuit, and the second electric circuit. Yes. The connecting member 76S in FIG. 7C is formed between the BGA pad in the first electric circuit and the external terminal in the second electric circuit. The connection member is formed of solder or the like, and the connection member is formed on the BGA pad or the external terminal.
As shown in FIG. 7C, the solenoid coil of the embodiment advances in a direction parallel to the surface of the first printed wiring board while rotating. Here, the surface of the first printed wiring board is the surface of the solder resist layer on the lower side of the first printed wiring board, and the surface substantially parallel to the surface is shown in FIGS. 7A and 7B. These are the surfaces of the interlayer resin insulation layer and interlayer insulation layer shown in FIG. The coil of the embodiment includes a helical coil.
As shown in FIG. 7C, the solenoid coil (inductor) of the embodiment is a connecting member that connects the horizontal wiring in the first electric circuit, the first electric circuit, and the second electric circuit. And a horizontal wiring in the second electric circuit. Here, the horizontal direction is a direction parallel to the surface of the first printed wiring board. Further, the first electric circuit may have a vertical wiring such as a via conductor. The second electrical circuit may also have vertical wiring such as via conductors. An example in which both have vertical wiring is shown in FIG.

In the printed wiring board of the first embodiment, an inductor is formed by a first electric circuit formed on the first printed wiring board 10 and a second electric circuit formed on the motherboard. The first and second electric circuits are formed on separate printed wiring boards. A connecting member is formed between the two. The first and second electric circuits are preferably connected by a direct connection member. As a result, the diameter of the coil increases. The inductance value increases. In addition, by arranging the first and second electric circuits constituting the inductor immediately below the IC chip, the wiring distance between the IC chip 90 and the inductor is shortened. Power supply noise can be reduced. Stable power is supplied to the IC chip. Electric power is instantaneously supplied to the IC chip.
When the wiring constituting the inductor is formed on the printed wiring board, the volume of the conductor in that portion tends to be low. As a result, the conductor volume becomes unbalanced in the printed wiring board. Therefore, the printed wiring board is likely to warp. However, in the embodiment, the inductor is formed across the first printed wiring board and the second printed wiring board. Therefore, according to the embodiment, the portion with a small conductor volume is reduced in the first and second printed wiring boards. The warp of the first and second printed wiring boards of the embodiment is reduced. Connection reliability between the first printed wiring board and the second printed wiring board is increased. Similarly, the connection reliability between the first electric circuit and the second electric circuit is increased.

In the embodiment, since the inductor is divided into the first and second printed wiring boards, the volume of the wiring configuring the inductor included in each printed wiring board is reduced.
In the embodiment, the first and second electric circuits are manufactured separately. Therefore, the thickness of the wiring in the second electric circuit can be made larger than the thickness of the wiring in the first electric circuit. A low-resistance inductor can be obtained.
The length of the vertical wiring (for example, via conductor) in the first electric circuit is preferably shorter than the length of the vertical wiring (for example, via conductor) in the second electric circuit. Since the warp of the first printed wiring board is reduced, it becomes easy to mount the first printed wiring board on the second printed wiring board. The number of interlayer resin insulating layers in which the vertical wiring of the first electric circuit is formed is smaller than the number of interlayer insulating layers in which the vertical wiring of the second electric circuit is formed. For example, the vertical wiring of the first electric circuit is formed in two interlayer resin insulation layers, and the vertical wiring of the second electric circuit is formed in three interlayer insulation layers. The vertical wiring of the second electric circuit may be a through-hole conductor that penetrates a plurality of interlayer insulating layers or a through-hole conductor that penetrates all interlayer insulating layers (FIG. 13B).

In the first embodiment, as shown in FIG. 10, the distance P1 between the pads connecting the first electric circuit and the second electric circuit is set to the first printed wiring board and the second printed wiring board. It can be made smaller than the distance P2 between the pads to be connected. Here, the distance between the pads is the distance between the center of the adjacent pad and the center of the pad.
The number of windings of the inductor increases. The inductance value increases.
In an embodiment, power is transferred through an inductor to a load such as an IC chip. Stable power is transmitted to the IC chip.

[Method for Manufacturing Printed Wiring Board of First Embodiment]
A manufacturing method of the first printed wiring board 10 of the first embodiment is shown in FIGS. 1 to 5. (1) A starting substrate 20 having a first surface F and a second surface S opposite to the first surface is prepared. Is done. The starting substrate is preferably a double-sided copper clad laminate. The double-sided copper-clad laminate includes an insulating substrate 20z having a first surface F and a second surface S opposite to the first surface, and metal foils 22 and 22 laminated on both surfaces (FIG. 1A). ). Blackening treatment is performed on the surface of the copper foil 22.

(2) The first surface F (upper surface) of the starting substrate is irradiated with CO2 laser, and a first opening 28a for forming a through hole for a through-hole conductor is formed on the first surface F side of the starting substrate ( FIG. 1 (B)). Here, the first opening 28 a is tapered from the first surface F toward the second surface S.

(3) The second surface S of the starting substrate is irradiated with the CO2 laser to form the second opening 28b connected to the first opening 28a. A through hole 28 for a through hole conductor is formed (FIG. 1C). Here, the second opening 28 b is tapered from the second surface S toward the first surface F.

(4) An electroless plating film 31 as a seed layer is formed on the surface of the starting material and the inner wall of the through hole by the electroless plating process (FIG. 1D).

(5) A plating resist 40 is formed on the seed layer 31 (FIG. 1E).

(6) An electrolytic plating film 32 is formed on the seed layer exposed from the plating resist 40 by electrolytic plating. At the same time, the through hole 28 is filled by plating to form a through hole conductor 36 (FIG. 2A).

(7) The plating resist is removed. The electroless plating film 31 and the copper foil 22 between the electrolytic plating films 32 are removed, and the core substrate 30 having the first conductor layer 34F and the second conductor layer 34S is completed (FIG. 2B). The surfaces of the conductor layers 34F and 34S are roughened.

(8) On the first surface F and the second surface S of the core substrate 30, a glass cloth, a prepreg containing inorganic particles such as silica, and a thermosetting resin such as epoxy, and a metal foil (copper foil) 48 are sequentially laminated. Is done. The thickness of the metal foil is about 2 μm. Thereafter, interlayer resin insulation layer 50F and interlayer resin insulation layer 50S are formed from the prepreg by heating press. Copper foil 48 is formed on interlayer resin insulation layers (50F, 50S) (FIG. 2 (C)). As the interlayer resin insulating layer, an interlayer resin insulating layer that does not include a reinforcing material but includes inorganic particles can also be used.

(9) Next, via conductor openings 51F and 51S are formed in the interlayer resin insulation layers 50F and 50S by a CO2 gas laser, respectively (FIG. 2D).

(10) Electroless plating films 52 and 52 are formed on the copper foil 48 and on the inner walls of the openings 51F and 51S (FIG. 2E). The thickness of the electroless plating films 52 and 52 is 0.5 μm.

(11) A plating resist 54 is formed on the electroless plating film 52 (FIG. 3A).

(12) An electrolytic plating film 56 is formed on the electroless plating film exposed from the plating resist 54 by electrolytic plating treatment. At this time, the openings 51F and 51S are filled with the electrolytic plating film 56. Via conductors 60F and 60S are formed (FIG. 3B).

(13) The plating resist 54 is removed. The metal foil 48 and the electroless plating film 52 exposed from the electrolytic plating film 56 are removed. The uppermost conductor layer 58F is formed on the interlayer resin insulation layer 50F, and the lowermost conductor layer 58S is formed on the interlayer resin insulation layer 50S (FIG. 3C). The lowermost conductor layer 58S includes the first electric circuit shown in FIG. The upper and lower buildup layers are completed. The surfaces of the uppermost and lowermost conductor layers 58F and 58S are roughened.

(14) An upper solder resist layer 70F having an opening 71F is formed on the upper buildup layer, and a lower solder resist layer 70S having an opening 71S is formed on the lower buildup layer (FIG. 4). (A)).

(15) The nickel plating layer 72 is formed on the pads 71FP and 71SP, and the gold plating layer 74 is further formed on the nickel plating layer 72 (FIG. 4B). A nickel-palladium-gold layer or an OSP film may be formed instead of the nickel-gold layer.

(16) The solder ball 76f is mounted on the C4 pad 71FP, and the solder ball 76s is mounted on the BGA pad 71SP. At this time, solder balls and conductive paste are also formed on the pads of the first electric circuit (FIG. 4C).

(17) C4 bumps 76F are formed on the C4 pads 71FP by reflow. BGA bumps 76S are formed on the BGA pads 71SP. A connection member 76S such as a solder bump is formed on the pad of the first electric circuit. The first printed wiring board 10 is completed (FIG. 5).
An IC chip 90 is mounted on the first printed wiring board 10 via C4 bumps 76F.

(Second printed wiring board manufacturing method)
A double-sided board having conductor layers 158B and 158C formed on both surfaces of the interlayer insulating layer 150B and the interlayer insulating layer B and a via conductor 160B is prepared.
An interlayer insulating layer 150A and a copper foil are laminated on the interlayer insulating layer 150B and the conductor layer 158B. Further, the interlayer insulating layer 150C and the copper foil are laminated on the interlayer insulating layer 150B and the conductor layer 158C. Thereafter, openings for via conductors are formed in the interlayer insulating layer 150A and the interlayer insulating layer 150C.
Then, a plating film is formed in the via conductor opening and on the copper foil. Then, an etching resist is formed on the plating film. Thereafter, the plating film and the copper foil exposed from the etching resist are removed. An uppermost conductor layer 158A is formed on the interlayer insulating layer 150A. The uppermost conductor layer 158A includes the second electric circuit. At the same time, the lowermost conductor layer 158D is formed on the interlayer insulating layer 150C. In addition, the uppermost via conductor (160A) connecting the conductor layer (158A) and the inner conductor layer (158B) is formed in the interlayer insulating layer (150A), and the lowermost via connecting the lowermost conductor layer (158D) and the inner conductor layer (158C) to the interlayer insulating layer (150C). A conductor 160C is formed.

(Printed wiring board manufacturing method)
The first printed wiring board 10 is mounted on the mother board 210 via the BGA bumps 76S. At the same time, the pads of the first electric circuit and the pads of the second electric circuit are connected via the connection member. A printed wiring board is completed (FIG. 6).
The BGA bump and the connecting member may be a metal core bump 76SS composed of a metal ball 76C such as copper and solder 76SL formed around the metal ball (FIG. 8). Since the distance between the first and second printed wiring boards is ensured, the inductance value increases.
A resin 91 containing magnetic particles can be filled between the first printed wiring board and the mother board. Since a coil is formed around the resin 91 having magnetism, the value of inductance increases.

In the first embodiment, as shown in FIG. 10, a chip capacitor 98 can be mounted between the first and second printed wiring boards. The chip capacitor 98 is mounted on the first printed wiring board or the second printed wiring board. As shown in FIG. 10, the power electrode of the chip capacitor may be connected to the first printed wiring board, and the ground electrode may be connected to the second printed wiring board. Since the chip capacitor has electrodes formed on the front and back sides of the dielectric and side electrodes connecting them, the mounting shown in FIG. 10 is possible. The chip capacitor may be mounted between the first electric circuit and the second electric circuit (FIG. 11).

FIG. 13 shows an example of the first electric circuit and the second electric circuit. In FIG. 13A, the vertical wiring of the first and second electric circuits is formed by stack vias. In the first electric circuit, one interlayer resin insulating layer is formed between the pads, and in the second electric circuit, one interlayer insulating layer is formed between the pads.
FIG. 13B illustrates an example of the vertical wiring of the second electric circuit. In FIG. 13B, the vertical wiring is a through-hole conductor and penetrates all interlayer insulating layers. The through-hole conductor functioning as a vertical wiring may penetrate a predetermined number of interlayer insulating layers without penetrating all layers.
FIG. 13C shows an example of horizontal wiring and vertical wiring of the first and second electric circuits. In this example, current is transmitted in the horizontal direction through a plurality of horizontal wirings formed in different layers. With such wiring, a solenoid coil is formed on the printed wiring board.

DESCRIPTION OF SYMBOLS 10 1st printed wiring board 30 Core board 34F 1st conductor layer 34S 2nd conductor layer 36 Through-hole conductor 50F, 50S Interlayer resin insulation layer 58F Top conductor layer 58S Bottom conductor layer 58SL wiring 76S Solder bump 100 Print wiring Board 158A Conductor layer 210 Motherboard

Claims (5)

A first printed wiring board having a first electrical circuit;
A second printed wiring board having a second electrical circuit;
A printed wiring board, which is located between the first printed wiring board and the second printed wiring board, and includes a plurality of connecting members connecting the first electric circuit and the second electric circuit. There,
A solenoid coil is formed by the first electric circuit, the connection member, and the second electric circuit. 2. The printed wiring board according to claim 1, wherein the first printed wiring board further includes a plurality of pads for connection to the connection member, and the second printed wiring board further includes the first printed wiring board. A plurality of pads for mounting one printed wiring board is provided, and a distance between the pads for connecting to the connection member is smaller than a distance between the pads for mounting the first printed wiring board. 2. The printed wiring board according to claim 1, wherein the connecting member is formed of a metal ball and solder covering the metal ball. The printed wiring board according to claim 1, further comprising a resin containing magnetic particles between the first printed wiring board and the second printed wiring board. 2. The printed wiring board according to claim 1, wherein the first printed wiring board has a first surface and a second surface opposite to the first surface, and the second printed wiring board is a third surface. And the fourth surface opposite to the third surface, the second surface and the third surface are opposed to each other, and the second surface of the first printed wiring board or the second printed wiring A chip capacitor is mounted on the third surface of the plate.

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