JP2014160966A - Communication system, receiving device, communication method, and receiving method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the occurrence of EMI while suppressing an increase in capacity of a buffer in a communication system that establishes communication between communication devices connected opposite to each other.SOLUTION: A communication system comprises: a first communication device having a transmission unit that transfers data including a first clock signal generated on the basis of a clock generated by a first clock generating device; and a second communication device having a first modulation removing unit that removes a modulation component of the first clock signal from the data, a second modulation removing unit that generates a second clock in which a modulation component is removed from a clock generated by a second clock generating device, a clock recovery unit that synchronizes with a clock generated on the basis of the second clock to output data in which the modulation component of the first clock signal is removed by the first modulation removing unit, and an asynchronous absorption unit that synchronizes with the second clock to adjust the number of dummy data included in the data output from the clock recovery unit.

Description

  The present invention relates to a communication system.

  When two devices operating with different clock sources communicate with each other, communication may become impossible due to the frequency deviation of the clock. In order to prevent communication from being lost, a technique is used in which dummy data inserted on the transmission side is increased or decreased by an elastic buffer provided on the reception side.

  The capacity of the elastic buffer required on the receiving side is set according to the definition of the allowable frequency deviation of the clock defined by the communication standard, the dummy data insertion interval, and the number of increase / decrease. However, the capacity of the elastic buffer required on the receiving side is often the minimum necessary in view of the device cost. The clock source assumed in this case is a fixed frequency clock (CFC). However, the CFC generates a large amount of electromagnetic noise as a whole system.

  As an effective means for suppressing electromagnetic noise (EMI) generated by a digital circuit such as a fixed frequency clock, a method using a spread spectrum clock (SSC) as a clock signal for operating the digital circuit is known.

  A clock signal (CFC) with a constant frequency concentrates electromagnetic energy at a specific frequency, whereas SSC that slowly and slightly fluctuates the frequency of the clock slowly disperses the electromagnetic energy in the fluctuation frequency range, thereby reducing EMI. Can be reduced.

  It is known to determine a SKIPOS (SKIP Ordered Set) interval at the time of normal reception by monitoring a reception error caused by a clock frequency deviation, and to notify the transmission block in the same device of the SKIPOS interval. By notifying the transmission block in the same device of the SKIPOS interval, SKIPOS is transmitted at a transmission interval that can be received by the opposite device (see, for example, Patent Document 1).

  If SSC is used for both clock sources of the communicating devices, EMI generation can be reduced. However, since the SSC has a larger frequency deviation of the clock than the CFC, it is necessary to increase the capacity of the elastic buffer provided on the receiving side. Since the capacity of the elastic buffer needs to be increased, the size of the device increases and the cost increases.

  Accordingly, an object of the present invention is to reduce the generation of EMI while suppressing an increase in the capacity of a buffer in a communication system that performs communication between communication devices that are connected to face each other.

The disclosed communication system is:
A communication system having a first communication device and a second communication device connected to the first communication device by an IF,
The first communication device is:
A transmission unit for transferring data including a first clock signal generated based on a clock generated by the first clock generator;
The second communication device is:
A first modulation removing unit that removes a modulation component of the first clock signal from data transmitted by the first communication device;
A second modulation removing unit for generating a second clock obtained by removing a modulation component from the clock generated by the second clock generation device;
A clock recovery unit that outputs data in which a modulation component of the first clock signal is removed by the first modulation removal unit in synchronization with a clock generated based on the second clock;
An asynchronous absorber that adjusts the number of dummy data included in the data output by the clock recovery unit in synchronization with the second clock.

  According to the embodiments of the disclosure, in a communication system that performs communication between communication devices that are connected to face each other, generation of EMI can be reduced while suppressing an increase in buffer capacity.

It is a figure which shows an example of a spread spectrum clock. It is a figure which shows one Example of a communication system. It is a figure which shows one Example of a 1st communication apparatus. It is a figure which shows one Example of a 2nd communication apparatus. It is a figure which shows one Example of operation | movement of a communication system. 1 is a diagram illustrating an example of a print system. FIG. 3 is a diagram illustrating an example of a server and a printer. It is a figure which shows one Example of the topology of a tree structure. It is a figure which shows one Example of a server. It is a figure which shows one Example of a server. 1 is a diagram illustrating an example of a printer. FIG. It is a figure which shows one Example of a card adapter. It is a figure which shows one Example of the terminal of a card edge connector. It is a figure which shows one Example of the terminal of a transceiver socket. It is a figure which shows one Example of a card connector. It is a figure which shows one Example of the wiring pattern of a connector. It is a figure which shows one Example of a connector. It is a figure which shows one Example of a transceiver socket. It is a figure which shows one Example of a connector. It is a figure which shows one Example of the switch of a card adapter. It is a figure which shows one Example of an optical transceiver. It is a figure which shows one Example of an optical transceiver. It is a figure which shows the example of mounting | wearing of the card adapter to a motherboard. It is a figure which shows the example of mounting | wearing of the card adapter to a motherboard. It is a figure which shows one Example of a conversion element. It is a figure which shows one Example of a conversion element.

Next, the form for implementing this invention is demonstrated, referring drawings based on the following Examples.
In all the drawings for explaining the embodiments, the same reference numerals are used for those having the same function, and repeated explanation is omitted.

<Example>
<Communication system>
In high-speed serial communication, data in which a clock is embedded is transmitted on the transmission side, and serial data is extracted on the reception side using the clock recovered (regenerated) by the clock data recovery (CDR) unit.

  A phase locked loop circuit (PLL) is used for the CDR section. The phase-locked loop circuit adjusts the clock so that the frequency and phase match the received signal. By adjusting the clock so that the frequency and phase coincide with the received signal, correct CDR data can be extracted by the CDR unit.

  If the same clock source is used on the transmission side and the reception side, the clock recovered on the reception side and the operation clock on the reception side have the same frequency, and duplication or loss of data due to frequency deviation occurs. There is no. However, when different clock sources are used on the transmission side and the reception side, duplication or loss of data due to frequency deviation may occur.

  The high-speed serial communication standard stipulates that dummy data is inserted on the transmission side and deletion or additional insertion of dummy data is performed on the reception side according to the frequency deviation. That is, the high-speed serial communication standard defines a mechanism that can absorb a certain range of frequency deviation by deleting or adding dummy data.

  For example, in the PCI Express standard, 100 MHz ± 300 ppm is specified as the frequency range of the clock source. At the Gen1 / Gen2 speed, 3 dummy data called SKPOS (SKP Ordered Set) are issued together at an interval of 1180 to 1560 symbol time. At the Gen3 speed, SKPOS is executed once every 370 to 375 blocks. Is issued. On the receiving side, it is stipulated that the number of SKPOS is adjusted according to the frequency deviation, and the frequency deviation that can be absorbed is the same (± 300 ppm) for both Gen1 / Gen2 speed and Gen3 speed.

  An elastic buffer for temporarily storing data is provided on the receiving side. A FIFO memory is preferably used for the elastic buffer. There is no provision for buffer capacity in the standard, and it is left to implementation.

  Regarding the buffer size (the number of FIFO stages), in order to prevent data duplication and data loss due to the insufficient number of stages, the next data needs to be already stored in the FIFO when SKPOS deletion is completed. Furthermore, regarding the buffer size, there must be an area for storing received data when SKPOS is inserted. These conditions are satisfied if the number of stages of “maximum number-1” of SKPOS is satisfied. In the case of PCI Express, a 4-stage buffer is the minimum capacity.

  The above is based on the assumption that a fixed frequency clock (CFC) of 100 MHz ± 300 ppm is used. In the case of the opposite system using separate SSC (spread spectrum clock) on the transmission side and the reception side, it can be dealt with by appropriately changing the frequency deviation to be absorbed and the SKPOS insertion / deletion rules as necessary.

  In gigabit-level high-speed serial communication, it is also important to suppress electromagnetic noise (EMI: Electro-Magnetic Interference) generated by high-speed driving circuits. In order to suppress electromagnetic noise, a standard that assumes the use of SSC has been established.

  FIG. 1 shows an example of a spread spectrum clock (SSC) and a fixed frequency clock (non-SSC). In FIG. 1, the horizontal axis represents frequency. Further, FIG. 1 shows a time domain waveform used for modulation and a frequency domain waveform when the modulation is applied in the case of a triangular wave profile and a Hershey Kiss profile.

  The spread spectrum clock (SSC) spreads the frequency distribution by slowly and slightly modulating the clock signal. SSC reduces EMI by avoiding concentration of EMI at specific frequencies. It is preferable to superimpose a waveform called a triangular wave profile or a Hershey Kiss profile on the reference clock. Good frequency dispersion can be obtained by using a triangular wave profile or Hershey Kiss profile waveform.

  SSC that can be used in the PCI Express standard is defined as a modulation frequency of 30 kHz to 33 kHz and a modulation range of -5000 ppm to 0 ppm. However, the use of SSC assumes that the entire system uses the same clock source.

  In the case of an opposing system that uses separate SSCs on the transmission side and the reception side, the frequency deviation of the absorbed clock is -5300 ppm to +300 ppm, greatly exceeding the frequency deviation (± 300 ppm) assumed in the current standard. It is necessary to modify the SKPOS insertion or deletion rules in order to absorb the frequency deviation in the opposite system using separate SSCs on the transmitting side and the receiving side. There are two options for correction. One is a method for shortening the time interval for inserting SKPOS, and the other is a method for increasing the number of SKPOS to be inserted or deleted. Although it is most effective to use both in combination, the following problems arise.

  In the method of shortening the time interval for inserting SKPOS, the use efficiency of the communication path is reduced by the increase in the frequency of inserting SKPOS on the transmission side, which leads to a reduction in effective communication speed. That is, transmission efficiency is reduced.

  In the method of increasing the number of SKPOS to be inserted or deleted, the use efficiency of the communication path is lowered by increasing the number of SKPOS, leading to a decrease in effective communication speed. Further, since it is necessary to mount the FIFO stage number “maximum number of SKPOS−1” in the elastic buffer, the size of the apparatus increases and the cost increases.

  A problem common to the method of shortening the time interval for inserting SKPOS and the method of increasing the number of SKPOS to be inserted or deleted is that the PCI Express standard needs to be changed. If the PCI Express standard is changed, even a system that does not use SSC will be installed according to the SKPOS specification corresponding to SSC. Even in a system that does not use SSC, implementation according to the SKPOS specification corresponding to SSC is very wasteful in terms of both communication efficiency and elastic buffer capacity.

  It is also possible to separate the configuration in which different clock sources are used in the first area for processing the high-speed serial communication protocol and the second area other than the first area. CFC is used for the first area, and SSC is used for the second area. In this case, an electrical signal based on CFC is generated in a transmission path for transmitting a high frequency signal of a gigahertz level. Since electrical signals based on CFC are generated in the transmission path, EMI generated in the transmission path is a major problem. In addition, it is necessary to install two types of clock sources (SSC and CFC) on the transmitting side and on the receiving side, resulting in an increase in device size and cost.

  In one embodiment of the communication system, an electrical signal in which a spread spectrum clock is embedded is transmitted on a transmission line for high-speed serial communication.

  On the receiving side, the SSC modulation component is removed from the data signal. Further, on the receiving side, the CFC is input to the clock recovery unit. The clock recovered by the clock recovery unit is CFC. Accordingly, the data extracted in synchronization with the clock is data that does not include the SSC modulation component.

  Further, when the frequency deviation is absorbed by the elastic buffer, a clock from which the SSC modulation component is removed is used. That is, both the clock used in the first area and the clock used in the second area are CFCs.

  By providing an elastic buffer with a capacity capable of absorbing the frequency deviation, communication without data duplication and loss can be performed without changing the SKPOS insertion rules. In addition, since data including SSC modulation components is transmitted and received on a transmission path through which high-speed signals are transmitted, EMI generation can be greatly suppressed.

  FIG. 2 shows an embodiment of a communication system.

  The communication system includes a first communication device 100 and a second communication device 200.

  The first communication device 100 and the second communication device 200 perform high-speed serial communication via the transmission line 300. For example, the first communication device 100 and the second communication device 200 perform high-speed serial transmission via a serial interface (IF) such as PCI-Express, USB, and Serial ATA. In one embodiment of the communication system, the first communication device 100 and the second communication device 200 perform serial transmission via an interface compliant with PCI-Express. This can be applied when the first communication device 100 and the second communication device 200 perform serial communication. Full-duplex communication is performed between the first communication device 100 and the second communication device 200.

  The first communication device 100 includes a first clock generation device 102 and a first transmission / reception circuit 104.

  The second communication device 200 includes a second clock generation device 202 and a second transmission / reception circuit 204.

<First communication apparatus 100>
FIG. 3 shows an embodiment of the first communication device 100 as a transmission device.

  The first clock generator 102 generates a spread spectrum clock (SSC). This clock is set to fall within the range of 100 MHz (+300 ppm to -5300 ppm). Hereinafter, the frequency including the frequency deviation of the clock is expressed as f1. The first clock generation device 102 supplies a clock to each unit of the first communication device 100. The first clock generator 102 supplies a clock to the first transmission / reception circuit 104.

  The first transmission / reception circuit 104 includes a transmission circuit as a transmission unit and a reception circuit as a reception unit. In the example shown in FIG. 3, the receiving circuit is omitted. The receiving circuit is substantially the same as the receiving circuit of the second communication device 200.

  The first transmission / reception circuit 104 includes a first PLL 302, a serializer 304, and a differential driver 306.

  The first PLL 302 is connected to the first clock generator 102. The first PLL 302 generates a clock necessary for serial transfer according to the clock from the first clock generator 102 and inputs the clock to the serializer 304. In the case of PCI-Express (Gen3) having a transfer rate of 8 GT / s, the first PLL 302 generates a 4 GHz clock multiplied by 400. This clock is a signal obtained by applying the same spread spectrum clock (SSC1) as the clock source to 4 GHz ± 300 ppm. In FIG. 3, the frequency including the frequency deviation of the clock is denoted as F1.

  The serializer 304 is connected to the first PLL 302. Transmission data is input to the serializer 304. The serializer 304 embeds the clock from the first PLL 302 in the transmission data. The serializer 304 outputs transmission data in which the clock from the first PLL 302 is embedded to the differential driver 306.

  The differential driver 306 is connected to the serializer 304. The differential driver 306 converts transmission data from the serializer 304 into a differential signal. The transmission data amplified by the differential driver 306 is output to the transmission line 300. The signal on the transmission line 300 is a signal in which a 4 GHz clock (hereinafter also referred to as “SSC1”) is embedded. When a signal including a spread spectrum clock is transmitted through the transmission line 300, the generation of noise due to EMI is greatly suppressed.

<Second communication apparatus 200>
FIG. 4 shows an embodiment of the second communication device 200 as a receiving device.

  The second clock generator 202 generates a spread spectrum clock. This clock is set to fall within the range of 100 MHz (+300 ppm to -5300 ppm). Hereinafter, the frequency including the frequency deviation of the clock is expressed as f2. The second clock generation device 202 supplies a clock to each unit of the second communication device 200. The second clock generator 202 supplies a clock to the second transmission / reception circuit 204.

  The second transmission / reception circuit 204 includes a transmission circuit as a transmission unit and a reception circuit as a reception unit. In the example shown in FIG. 4, the transmission circuit is omitted. The transmission circuit is substantially the same as the transmission circuit of the first communication device 100.

  The second transmission / reception circuit 204 includes a first modulation removal unit 402, a clock recovery unit 412, an asynchronous absorption unit 418, and a second modulation removal unit 426.

  The second modulation removal unit 426 removes the modulation component of the clock from the clock (SSC2) supplied from the second clock generator 202, and generates a fixed frequency clock (CFC2). CFC2 is a clock with a frequency range of 100Hz ± 300ppm. In FIG. 4, f2 (not equal f1) including the frequency deviation of the clock is described. The second modulation removal unit 426 inputs the fixed frequency clock (CFC2) to the asynchronous absorption unit 418 and the clock recovery unit 412.

  The second modulation removal unit 426 includes a second LPF 430, a second phase inverter 428, and a second signal superimposer 432.

  The second LPF 430 is connected to the second clock generator 202. The second LPF 430 extracts the modulation component superimposed on the clock from the second clock generator 202. The second LPF 430 preferably has a characteristic that allows the modulation component of the spread spectrum clock of 30 kHz to 33 kHz superimposed on the spread spectrum clock (SSC2) of 100 MHz to be extracted without attenuation. The modulation component of the spread spectrum clock (SSC2) extracted by the second LPF 430 is input to the second phase inverter 428.

  The second phase inverter 428 is connected to the second LPF 430. The second phase inverter 428 inverts the phase of the modulation component of the spread spectrum clock (SSC2). That is, the second phase inverter 428 reverses the amplitude of the modulation component of the spread spectrum clock (SSC2). The modulation component of the spread spectrum clock (SSC2) whose phase is inverted by the second phase inverter 428 is input to the second signal superimposing device 432.

  The second signal superimposer 432 is connected to the second phase inverter 428 and the second clock generator 202. The second signal superimposing unit 432 receives the modulation component of the spread spectrum clock (SSC2) obtained by inverting the phase from the second phase inverter 428 and the spread spectrum clock (SSC2) from the second clock generator 202. Superimpose. Since modulation in the spread spectrum clock is frequency modulation, an original signal that is not frequency-modulated can be obtained by superimposing a frequency-modulated signal and a signal having an opposite phase to the frequency-modulated signal. In this way, the second modulation removal unit 426 can obtain a fixed frequency clock (CFC2 (f2)) from which the modulation component of the spread spectrum clock (SSC2) has been removed. The second modulation removal unit 426 supplies a fixed frequency clock (CFC2 (f2)) to the clock recovery unit 412 and the asynchronous absorption unit 418.

  The first modulation removal unit 402 includes a differential receiver 404, a first LPF 406, a first phase inverter 408, and a first signal superimposer 410.

  The differential receiver 404 converts the high-speed data signal from the first communication device 100 from a differential signal to a single-ended signal. The high-speed data signal converted by the differential receiver 404 is input to the first LPF 406 and the first signal superimposing unit 410.

  The first LPF 406 is connected to the differential receiver 404. The first LPF 406 extracts a modulation component of the output signal (SSC1) of the differential receiver 404. The modulation component of the output signal (SSC1) extracted by the first LPF 406 is input to the first phase inverter 408. The first LPF 406 preferably has a characteristic that allows the modulation component of the 30 kHz to 33 kHz spread spectrum clock (SSC1) superimposed on the 100 MHz spread spectrum clock to be extracted without attenuation.

  The first phase inverter 408 inverts the phase of the modulation component of the spread spectrum clock (SSC1). That is, the first phase inverter 408 reverses the amplitude of the modulation component of SSC1. The modulation component of SSC1 whose phase is inverted by the first phase inverter 408 is input to the first signal superimposer 410.

  The first signal superimposing unit 410 superimposes the modulation component of SSC 1 obtained by inverting the phase from the first phase inverter 408 and the output signal of the differential receiver 404. Since modulation in the spread spectrum clock is frequency modulation, an original signal that is not frequency-modulated can be obtained by superimposing a frequency-modulated signal and a signal having an opposite phase to the frequency-modulated signal. By doing so, the first modulation removal section 402 can obtain a high-speed data signal from which the modulation component of SSC1 has been removed. The first modulation removal unit 402 supplies the data signal from which the modulation component of SSC1 has been removed to the clock recovery unit 412.

  The clock recovery unit 412 includes a deserializer 414 and a second PLL 416.

  A fixed frequency clock (CFC2 (f2)) is supplied from the second modulation removal unit 426 to the second PLL 416. The second PLL 416 generates (recovers) a clock signal (4 GHz) multiplied by 400.

  The deserializer 414 is connected to the first signal superimposer 410. The deserializer 414 receives a data signal from which the SSC1 modulation component has been removed from the first signal superimposer 410. The deserializer 414 converts serial data into parallel data in synchronization with the clock generated by the second PLL 416.

  The data signal used for recovery has the SSC1 modulation component removed, and the clock input from the second PLL 416 is a fixed clock (CFC2), so clock recovery is possible. At the time of clock recovery, a clock that is synchronized with the data signal from which the modulation component of SSC1 is removed is generated. In FIG. 4, the recovery clock is expressed as CFC1. The deserializer 414 inputs parallel data to the asynchronous absorption unit 418.

  The asynchronous absorption unit 418 includes an elastic buffer 420, a decoding unit 422, and a descrambler 424.

  The elastic buffer 420 is connected to the deserializer 414. The output signal of the deserializer 414 is input to the elastic buffer 420 in synchronization with CFC1. The elastic buffer 420 stores the output signal of the deserializer 414. The elastic buffer 420 delivers the signal to the decoding unit 422 in synchronization with the CFC2. The elastic buffer 420 adds or deletes SKPOS when delivering a signal. Absorb frequency deviation between CFC1 and CFC2 by adding or deleting SKPOS.

  The decoding unit 422 is connected to the elastic buffer 420. Data from the first communication device is encoded by an encode block (not shown) provided in the transmission circuit, and the decoding unit 422 decodes data from the elastic buffer 420. The decoding unit 422 inputs the decoded data to the descrambler 424.

  The descrambler 424 is connected to the decoding unit 422. The data from the first communication device is scrambled (stirred) by a scrambler (not shown) provided in the transmission circuit, and the descrambler 424 receives the decoded data from the decoding unit 422 before scrambled. Convert to data.

<Operation of communication system>
FIG. 5 shows an embodiment of the operation of the communication system.

  In step S502, the first communication device 100 generates transmission data according to the spread spectrum clock SSC1 generated by the first clock generator 102. The transmission data is a parallel signal.

  In step S504, the first communication device 100 converts the transmission data generated in step S502 into a serial signal. The first PLL 302 generates a clock necessary for serial transfer in accordance with the spread spectrum clock (SSC1) from the first clock generator 102 and inputs it to the serializer 304. The serializer 304 embeds the clock from the first PLL 302 in the transmission data.

  In step S <b> 506, the first communication device 100 transmits a serial signal to the second communication device 200.

  In step S <b> 508, the second communication device 200 receives the serial signal from the first communication device 100.

  In step S510, the second communication device 200 extracts the SSC1 modulation component included in the serial signal and inverts the phase thereof.

  In step S512, the second communication device 200 superimposes the modulation component of SSC1 whose phase is inverted and the data signal from the first communication device 100. This process generates reception data (serial signal) from which the modulation component of SSC1 has been removed.

  In step S514, the second communication device 200 converts the received data (serial signal) from which the modulation component of SSC1 has been removed into a parallel signal.

  In step S516, the second communication device 200 generates a spread spectrum clock (SSC2).

  In step S518, the second communication device 200 inverts the phase of the modulation component of the spread spectrum clock (SSC2).

  In step S520, the second communication device 200 superimposes the modulation component of SSC2 whose phase is inverted in step S518 and the spread spectrum clock (SSC2) from the second clock generator 202. This process generates a fixed frequency clock (CFC2).

  In step S522, a signal converted into parallel data in step S514 is generated in synchronization with the fixed frequency clock (CFC2).

  In one embodiment of the communication system, stable communication is possible using a clock source that generates a spread spectrum clock without changing the SKIPOS transmission interval defined in the high-speed serial communication standard. In other words, it is possible to achieve EMI suppression by using SSC without reducing the communication efficiency and increasing the capacity of the elastic buffer necessary for frequency deviation absorption. Since this can be realized without increasing the capacity of the elastic buffer, it is possible to suppress an increase in device size and cost.

  Conventionally, when a clock source that generates a spread spectrum clock is used, it is necessary to increase the elastic buffer capacity on the receiving side in response to an increase in the frequency deviation to be absorbed.

  In one embodiment of the communication system, a received signal is generated by removing the spread spectrum clock modulation component by superimposing the spread spectrum clock (SSC1) modulation component on the received signal in reverse phase before being input to the clock recovery unit. To do. Furthermore, the clock signal used in the elastic buffer is used by removing the spread spectrum clock (SSC2) modulation component by superimposing the spread spectrum clock modulation component on the spread spectrum clock (SSC2) in the opposite phase. . By doing so, the two clocks used in the asynchronous absorber are non-SSC (CFC). That is, since the two clocks used in the asynchronous absorption unit do not include the modulation component of the spread spectrum clock, the frequency deviation to be absorbed can be reduced, so that it is not necessary to increase the elastic buffer capacity. In addition, since high-speed data communication is performed between the first communication device and the second communication device using the spread spectrum clock, a sufficient EMI suppression effect can be obtained.

  Specifically, an SSC that conforms to the PCI Express standard is used for the first clock generation device 102 of the first communication device 100 and the second clock generation device 202 of the second communication device 200. In the asynchronous absorption unit in the communication apparatus 200, a fixed frequency clock (CFC2) of 100 MHz ± 300 ppm can be used. For this reason, in the PCI Express standard, there is no change between the first communication device 100 and the second communication device 200 without changing the SKPOS insertion interval specification on the transmission side and the SKPOS addition or deletion specification on the reception side. The frequency deviation can be absorbed.

<Modification (Part 1)>
In a modification of the communication system, the first clock generator 102 and the second clock generator 202 both generate a fixed frequency clock (CFC) in the embodiment described above.

  CFC does not have a low frequency component. Therefore, the CFC LPF output is always zero (DC). In the second communication device 200, the outputs of the first LPF 406 and the second LPF 430 are zero.

  A high-speed data signal including CFC is output from the first modulation removal unit 402. Further, a fixed frequency clock is input from the second modulation removal unit 426 to the clock recovery unit 412 and the asynchronous absorption unit 418.

  According to a modification of the communication system, the first clock generation device 102 and the second clock generation device 202 are both fixed frequency without changing the configuration of the first communication device 100 and the second communication device 200. This is applicable even when generating a clock of.

<Modification (Part 2)>
A modification of the communication system shows an application example to a printing system.

  FIG. 6 shows a modification of the printing system.

  The print system includes a server 600, a printer 400, an optical cable 500, a plurality of terminals 800, a network 900, and the like.

  The server 600 is a so-called print server, and is connected to a plurality of terminals (for example, personal computers) 800 via the network 900.

  FIG. 7 shows an embodiment of the server 600 and the printer 400.

  The server 600 and the printer 400 each have a group of devices connected according to a tree structure topology defined by the PCI Express standard.

  FIG. 8 shows an example of a tree structure topology.

  The topology of the tree structure defined by the PCI Express standard is a tree-type configuration with the root complex as a vertex, and the root complex and the end point are connected.

  FIG. 9 shows an embodiment of the server 600.

  In the server 600, a socket (PCI Express socket) that conforms to the PCI Express standard is mounted on a motherboard. A card adapter 602 is attached to the PCI Express socket.

  In the printer 400, a socket (PCI Express socket) that conforms to the PCI Express standard is mounted on a motherboard. A card adapter 402 is attached to the PCI Express socket.

  Optical transceivers 520 and 540 are attached to the card adapters 602 and 402, respectively. The first communication device 100 and the second communication device 200 described above are applied to the optical transceivers 520 and 540.

  The optical transceiver 520 on the server side and the optical transceiver 540 on the printer side are connected by an optical cable 500.

  In one embodiment of the printing system, image information (black image information, cyan image information, magenta image information, and yellow image information) is transferred from the server 600 to the printer 400 in the form of lossless compression data of a raster image. Is transmitted.

  The printer 400 forms and outputs a color image according to the received image information.

  FIG. 10 shows an embodiment of the server 600.

  The server 600 includes a controller 650 that outputs image information from the terminal 800 to the printer 400 in response to a request from the terminal 800.

  The controller 650 includes two communication control circuits (602, 612), an image processing circuit 604, a data compression circuit 606, a memory 608, a memory control circuit 610, and the like.

  The communication control circuit 602 controls communication with a plurality of terminals 800 via the network 900.

  The image processing circuit 604 converts the image information from the terminal 800 received by the communication control circuit 602 into raster image data.

  The data compression circuit 606 reversibly compresses the raster image data from the image processing circuit 604 and temporarily stores it in the memory 608.

  The memory control circuit 610 monitors the data stored in the memory 608 and outputs the data via the communication control circuit 612 when the data is ready.

  FIG. 11 shows an embodiment of the printer 400.

  The printer 400 includes a controller 450 that outputs reversible compression data of a raster image from the server 600 to a printing apparatus.

  The controller 450 includes a communication control circuit 402, a memory 404, a memory control circuit 406, a data expansion circuit 408, a print control circuit 410, and the like.

  The communication control circuit 402 temporarily stores the received reversible compression data of the raster image in the memory 404.

  The memory control circuit 406 monitors the data stored in the memory 404 and outputs it to the data decompression circuit 408 when the data is ready.

  The data decompression circuit 408 decompresses the lossless compressed data of the raster image from the memory 404.

  The print control circuit 410 outputs the raster image expanded by the data expansion circuit 408 to the printing apparatus.

  FIG. 12 shows an embodiment of the card adapter 350.

  FIG. 12 shows a plan view of the card adapter 350.

  In the card adapter 350, two transceiver sockets (312A, 312B), four connectors (311, 313, 314, 316), a conversion element 317, and the like are mounted on the board 310. When there is no need to distinguish between the two transceiver sockets, they are also collectively referred to as a transceiver socket 312.

  Card edge connectors 315 are formed on both sides near one end of the board 310. Here, for convenience, the surface on which the transceiver socket 312 is mounted is referred to as an A surface, and the surface opposite to the A surface is referred to as a B surface. Note that reference numerals L11 and L12 in FIG. 12 indicate the size of the card adapter 350. In one embodiment of the card adapter 350, the length of the code L11 is 105 mm, and the length of the code L12 is 130 mm.

  In FIG. 12, the area where the serial signal lines on the board 310 are wired with the highest priority is hatched. The serial signal line is a PCI Express transmission line, specifically, between the card edge connector 315 and the conversion element 317, between the conversion element 317 and the transceiver socket 312A, and between the conversion element 317 and the transceiver socket 312B. Wiring between. Note that a region on the B surface side corresponding to the wiring region is also a wiring region.

  The connector 316 is a connector for supplying electric power to the cooling fan when the cooling fan is attached. The power is supplied from the server 600 or the printer 400 via the card edge connector 315.

  In one embodiment of the card adapter 350, the card edge connector 315 corresponds to 8 lanes. Each transceiver socket corresponds to 4 lanes.

  FIG. 13 shows an example of the terminals of the card edge connector 315.

  FIG. 13 shows a plurality of terminals in the card edge connector 315. There are four serial signal terminals in the first lane: PET0P, PET0N, PER0P, and PER0N. PET0P and PET0N are for transmission, and PER0P and PER0N are for reception.

  There are four serial signal terminals in the second lane: PET1P, PET1N, PER1P, and PER1N. PET1P and PET1N are for transmission, and PER1P and PER1N are for reception.

  There are four serial signal terminals in the third lane: PET2P, PET2N, PER2P, and PER2N. PET2P and PET2N are for transmission, and PER2P and PER2N are for reception.

  The fourth lane has four serial signal terminals, PET3P, PET3N, PER3P, and PER3N. PET3P and PET3N are for transmission, and PER3P and PER3N are for reception.

  There are four serial signal terminals in the fifth lane: PET4P, PET4N, PER4P, and PER4N. PET4P and PET4N are for transmission, and PER4P and PER4N are for reception.

  There are four serial signal terminals in the sixth lane: PET5P, PET5N, PER5P, and PER5N. PET5P and PET5N are for transmission, and PER5P and PER5N are for reception.

  The seventh lane has four serial signal terminals, PET6P, PET6N, PER6P, and PER6N. PET6P and PET6N are for transmission, and PER6P and PER6N are for reception.

  The eight lane serial signal terminals are PET7P, PET7N, PER7P, and PER7N. PET7P and PET7N are for transmission, and PER7P and PER7N are for reception.

  FIG. 14 illustrates one embodiment of the terminals of the transceiver socket 312. FIG. 14 shows a plurality of terminals in the transceiver socket 312.

  There are four serial signal terminals in the first lane, TX1p, TX1n, RX1p, and RX1n. TX1p and TX1n are for transmission, and RX1p and RX1n are for reception.

  There are four serial signal terminals in the second lane: TX2p, TX2n, RX2p, RX2n. TX2p and TX2n are for transmission, and RX2p and RX2n are for reception.

  There are four serial signal terminals in the third lane, TX3p, TX3n, RX3p, and RX3n. TX3p and TX3n are for transmission, and RX3p and RX3n are for reception.

  The fourth lane has four serial signal terminals, TX4p, TX4n, RX4p, and RX4n. TX4p and TX4n are for transmission, and RX4p and RX4n are for reception.

  FIG. 15 shows an embodiment of the card connector.

  FIG. 15 shows a wiring group A composed of a plurality of wiring patterns that electrically connect the serial signal terminals (32 in total) in the card edge connector 315 and the conversion element 317. Further, FIG. 15 shows a wiring group B composed of a plurality of wiring patterns that electrically connect the conversion element 317 and the serial signal terminals (16 in total) in the transceiver socket 312A. Further, FIG. 15 shows a wiring group C composed of a plurality of wiring patterns that electrically connect the conversion element 317 and the serial signal terminals (16 in total) in the transceiver socket 312B.

  In one embodiment of the card connector, the clocks in the wiring group A, the wiring group B, and the wiring group C are all 5 GHz.

  In the wiring group A, the wiring group B, and the wiring group C, the clock is a spread spectrum clock. The spread spectrum clock is a clock whose clock frequency is slightly changed in order to reduce the radiation noise by lowering the peak value of the frequency spectrum of the clock signal.

  The conversion element 317 is provided in the middle of a plurality of wiring patterns that electrically connect the card edge connector 315 and the two transceiver sockets.

  The conversion element 317 has a switch function. The switch function is a function for executing packet routing between a plurality of ports of the switch. Furthermore, the conversion element 317 also has a function as a bridge of a so-called non-transparent type (NT bridge: see FIG. 8). When the conversion element 317 functions as a non-transparent type bridge, the CPU on the server 600 side and the CPU on the printer 400 side can be individually initialized without being disturbed by each other. Each CPU can access each other's resources while operating separately.

  Each wiring length in the wiring group B and the wiring group C is set so as to be different from any of an integral multiple of the clock frequency, a half of the clock frequency and a quarter of the clock frequency. Specifically, since the clock frequency is 5 GHz, each wiring length is set not to be 1.5 cm, 3 cm, 6 cm, 12 cm, or the like. When the clock frequency is 2.5 GHz, each wiring length is set so as not to be 3 cm, 6 cm, 12 cm, 24 cm, or the like. Therefore, in order to cope with both 5 GHz and 2.5 GHz, for example, each wiring length is preferably 1 cm.

  The serial signal terminals (total 16) from the first lane to the fourth lane in the card edge connector 315 are connected to the serial signal terminals (total 16) in the transceiver socket 312A via the conversion element 317. The

  Specifically, PET0P and TX1p, PET0N and TX1p, PER0P and RX1p, and PER0N and RX1n are connected. Further, PET1P and TX2p, PET1N and TX2p, PER1P and RX2p, and PER1N and RX2n are connected. Further, PET2P and TX3p, PET2N and TX3p, PER2P and RX3p, and PER2N and RX3n are connected. Further, PET3P and TX4p, PET3N and TX4p, PER3P and RX4p, and PER3N and RX4n are connected.

  The serial signal terminals (a total of 16 terminals) from the fifth lane to the eighth lane in the card edge connector 315 are connected to the serial signal terminals (a total of 16 terminals) in the transceiver socket 312B via the conversion element 317. The

  Specifically, PET4P and TX1p, PET4N and TX1p, PER4P and RX1p, and PER4N and RX1n are connected. Further, PET5P and TX2p, PET5N and TX2p, PER5P and RX2p, and PER5N and RX2n are connected. Further, PET6P and TX3p, PET6N and TX3p, PER6P and RX3p, and PER6N and RX3n are connected. Further, PET7P and TX4p, PET7N and TX4p, PER7P and RX4p, and PER7N and RX4n are connected.

  FIG. 16 shows an embodiment of a connector wiring pattern. As the connector 311, an RJ (Registered Jack) 45 type modular jack can be used.

  FIG. 17 shows an embodiment of the connector.

  The connector 311 is connected to the two terminals (WAKE_N, PERST_N) for sideband signals in the card edge connector 315. Accordingly, a sideband signal that does not need to be transmitted at such a high speed can be transmitted via a transmission medium (for example, a cable that complies with the IEEE 802.3 standard) 700 different from the serial signal. As a result, cost reduction can be achieved.

  Connector 311 is connected to a terminal for + 3.3V in card edge connector 315. Thereby, it is possible to know whether or not the card adapters 402 and 602 are attached to the counterpart device.

  Two terminals of the connector 311 are looped on the board 310. Thereby, it is possible to know whether or not the card adapter 300 is attached to the device on its own side.

  FIG. 18 illustrates one embodiment of a transceiver socket.

  In FIG. 18, the optical transceiver control signal terminals (LPMode, IntL, ModPrsL, ModSelL, ResetL, SCL, SDA) and the two connectors (313, 314) in the two transceiver sockets (312A, 312B) are electrically connected. A plurality of wiring patterns to be connected to each other are shown.

  FIG. 19 shows an embodiment of the connector.

  The connector 313 is a connector for inputting a signal for controlling the optical transceiver inserted into the transceiver socket 312A from an external device (optical transceiver control device). The connector 314 is a connector for inputting a signal for controlling the optical transceiver inserted into the transceiver socket 312B from an external device (optical transceiver control device).

  LPMode is a terminal for setting a low power mode, and IntL is a terminal for setting an interrupt. ModPrsL is a terminal for setting the presence of the optical transceiver, and ModSelL is a terminal for setting the selection of the optical transceiver. ResetL is a terminal for resetting the optical transceiver. SCL is a terminal for setting the serial interface clock, and SDA is a terminal for setting the serial interface data.

  On the board 310, a chip jumper that can electrically connect a wiring pattern that electrically connects the connector 313 and the transceiver socket 312A and a wiring pattern that electrically connects the connector 314 and the transceiver socket 312B. (JP1 to JP5) are provided. Accordingly, it is possible to simultaneously control the optical transceivers inserted into the transceiver socket 312A and the transceiver socket 312B from an external device connected to either the connector 313 or the connector 314.

  On the board 310, two dip switches (SW2, SW5) are provided. The dip switch SW2 is used when setting the operating conditions of the optical transceiver inserted into the transceiver socket 312A on the board 310. The dip switch SW5 is used when setting the operating conditions of the optical transceiver inserted into the transceiver socket 312B on the board 310.

  FIG. 20 shows an embodiment of the switch of the card adapter.

  On the board 310, a switch (SW8) for setting whether the card adapter 300 is for 1 lane, 4 lanes, or 8 lanes is provided.

  Each of the optical transceivers 520 and 540 is an optical transceiver conforming to a QSFP (Quad Small Form-factor Pluggable) standard.

  21 and 22 show an embodiment of the optical transceiver. The first communication device 100 and the second communication device 200 described above are preferably applied to the optical transceiver.

  The optical transceiver converts a signal (electric signal) input to TX1n to TX4n and TX1p to TX4p into an optical signal and outputs the optical signal to the optical cable 500, and a signal (optical signal) input from the optical cable 500. ) Are converted into electrical signals and output to RX1n to RX4n and RX1p to RX4p.

  Thus, the data output from the server side TX1n to TX4n is transmitted to the printer side RX1n to RX4n, respectively, and the data output from the server side TX1p to TX4p is respectively transmitted to the printer side RX1p to RX4p. Is transmitted.

  Similarly, each data output from TX1n to TX4n on the printer side is transmitted to RX1n to RX4n on the server side, and each data output from TX1p to TX4p on the printer side is transmitted to RX1p to RX4p on the server side, respectively. Is transmitted.

  In one embodiment of the printing system, the server 600 and the printer 400 are connected by an optical cable 500.

  Each of the server 600 and the printer 400 includes a PCI Express socket conforming to the PCI Express standard. The card adapter 300 is inserted into each PCI Express socket.

  The card adapter 300 includes a board 310, a card edge connector 315 provided near one end of the board 310, two transceiver sockets (312A, 312B) mounted on the board 310, a conversion element 317, four connectors (311, 313, 314, 316) and the like.

  The conversion element 317 is provided in the middle of a plurality of wiring patterns that electrically connect the card edge connector 315 and the two transceiver sockets. The clock domain of the plurality of wiring patterns is a spread spectrum clock. The clock domain is divided into a clock domain whose clock is a non-spread spectrum clock.

  A clock between the motherboard and the conversion element 317 can be a spread spectrum clock, and a domain in which the clock is a non-spread spectrum clock can be shortened.

  FIG. 23 is a diagram illustrating an example of mounting the card adapter to the motherboard.

  When a PCI Express switch is mounted on the motherboard and a card adapter that does not have the conversion element 317 is mounted, a domain in which the clock is a non-spread spectrum clock is set between the PCI Express switch and the socket of the card adapter.

  FIG. 24 shows an example of mounting the card adapter to the motherboard.

  When the card adapter 350 is attached, a domain in which the clock is a spread spectrum clock can be formed between the motherboard and the conversion element 317.

  Therefore, unnecessary radiation (EMI) can be reduced in information communication.

  The card adapter 350 does not require a chip for converting transmission information and reception information at high speed, and can reduce costs. Further, since transmission and reception conforming to the PCI Express standard is possible, transmission and reception while maintaining the effective transfer rate of PCI Express is possible.

That is, information communication between devices having an interface compliant with the PCI Express standard can be performed without causing an increase in price and a decrease in effective transfer rate.
The mounting position of the connector or the like is an example and is not limited to this.

  25 and 26 show an embodiment of the conversion element.

  For example, when the serial data clock output from the server 600 is 2.5 GHz and the serial data is transferred to the printer 400 with the 5 GHz clock, the function of changing the clock frequency instead of the conversion element 317, It is preferable to use a conversion element 317 ′ to which a bridge function is added. In this case, there is preferably one transceiver socket.

  In the embodiment of the printing system, the case where each optical transceiver is an optical transceiver conforming to the QSFP standard has been described. However, the present invention is not limited to this. For example, each optical transceiver may correspond to any one of the SFP (Small Form-factor Pluggable) standard, the SFP + standard, the QSFP + standard, and the XFP (10 Gigabit Small Form-factor Pluggable) standard.

  Moreover, although the case where the card edge connector 315 respond | corresponds to 8 lane was demonstrated, it is not limited to this.

  The clock frequency is an example and is not limited to this.

  Further, the present invention is not limited to information communication based on the PCI Express standard.

  According to one embodiment of the printing system, unnecessary radiation (EMI) can be reduced in information communication between devices without causing an increase in cost and a decrease in effective transfer rate.

  Although the present invention has been described with reference to particular embodiments, each embodiment is merely illustrative, and those skilled in the art will appreciate various variations, modifications, alternatives, substitutions, and the like. . For convenience of explanation, an apparatus according to an embodiment of the present invention has been described using a functional block diagram, but such an apparatus may be implemented in hardware, software, or a combination thereof. The present invention is not limited to the above-described embodiments, and various variations, modifications, alternatives, substitutions, and the like are included without departing from the spirit of the present invention.

DESCRIPTION OF SYMBOLS 100 1st communication apparatus 102 1st clock generation apparatus 104 1st transmission / reception circuit 200 2nd communication apparatus 202 2nd clock generation apparatus 204 2nd transmission / reception circuit

JP 2012-63913 A

Claims (10)

A communication system having a first communication device and a second communication device connected to the first communication device by an IF,
The first communication device is:
A transmission unit for transferring data including a first clock signal generated based on a clock generated by the first clock generator;
The second communication device is:
A first modulation removing unit that removes a modulation component of the first clock signal from data transmitted by the first communication device;
A second modulation removing unit for generating a second clock obtained by removing a modulation component from the clock generated by the second clock generation device;
A clock recovery unit that outputs data in which a modulation component of the first clock signal is removed by the first modulation removal unit in synchronization with a clock generated based on the second clock;
And an asynchronous absorber that adjusts the number of dummy data included in the data output by the clock recovery unit in synchronization with the second clock. The first modulation removal unit includes:
A first LPF for extracting a modulation signal included in data from the first communication device;
A first phase inverter for inverting the phase of the modulation signal extracted by the first LPF;
The communication system according to claim 1, further comprising: a first signal superimposing unit that superimposes the modulation signal whose phase is inverted by the first phase inverter and the data from the first communication device. The second modulation removal unit includes:
A second LPF for extracting a modulation signal included in the clock generated by the second clock generator;
A second phase inverter for inverting the phase of the modulation signal extracted by the second LPF;
The communication according to claim 1, further comprising: a second signal superimposing unit that superimposes the modulation signal whose phase is inverted by the second phase inverter and the clock generated by the second clock generation device. system. The clock recovery unit
A deserializer that converts the data from which the modulation component of the first clock signal is removed into a parallel signal;
A PLL that generates a clock to be used when converting the data from which the modulation component of the first clock signal is removed into a parallel signal by the deserializer based on the second clock. The communication system according to any one of the above. The first clock generator generates a spread spectrum clock;
The communication system according to claim 1, wherein the second clock generator generates a spread spectrum clock. The first clock generator generates a fixed frequency clock;
The communication system according to claim 1, wherein the second clock generator generates a fixed frequency clock.   The communication system according to any one of claims 1 to 6, wherein the first communication device and the second communication device perform communication in accordance with a PCI Express standard. A receiving device for receiving data from a first communication device,
The first communication device transfers data including a first clock signal generated based on a clock generated by the first clock generator,
The receiving device is:
A first modulation removing unit that removes a modulation component of the first clock signal from data transmitted by the first communication device;
A second modulation removing unit for generating a second clock obtained by removing a modulation component from the clock generated by the second clock generation device;
A clock recovery unit that outputs data in which a modulation component of the first clock signal is removed by the first modulation removal unit in synchronization with a clock generated based on the second clock;
An asynchronous absorber that adjusts the number of dummy data included in the data output by the clock recovery unit in synchronization with the second clock. A communication method in a communication system having a first communication device and a second communication device connected to the first communication device by an IF,
The first communication device is:
Transferring data including a first clock signal generated based on the clock generated by the first clock generator;
The second communication device is:
Removing the modulation component of the first clock signal from the data transmitted by the first communication device;
Generating a second clock obtained by removing the modulation component from the clock generated by the second clock generator;
When the data from which the modulation component of the first clock signal output in synchronization with the clock generated based on the second clock is removed is output in synchronization with the second clock, A communication method that adjusts the number of dummy data contained in data. A receiving method in a receiving device for receiving data from a first communication device, comprising:
The first communication device transfers data including a first clock signal generated based on a clock generated by the first clock generator,
Removing the modulation component of the first clock signal from the data transmitted by the first communication device;
Generating a second clock obtained by removing the modulation component from the clock generated by the second clock generator;
When the data from which the modulation component of the first clock signal output in synchronization with the clock generated based on the second clock is removed is output in synchronization with the second clock, A reception method that adjusts the number of dummy data contained in the data.

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