JP2014160872A - Method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a p-type group III nitride semiconductor exhibiting a lower resistance p-type characteristic than a conventional p-type semiconductor composed of a p-type group III nitride semiconductor superlattice, and having a desired refractive index and a band gap.SOLUTION: A p-type group III nitride semiconductor is a p-type group III nitride semiconductor 23 composed of a superlattice structure of an InAlGaN layer and a p-type InAlGaN layer which are epitaxially grown on a laminate structure with a low-temperature GaN buffer layer 21 and a GaN layer 22 sequentially laminated on a sapphire substrate 20.

Description

  The present invention relates to a semiconductor light-emitting device, a semiconductor electronic device, a semiconductor light-receiving device, a light source for optical pickup such as DVD and CD, a writing light source for electrophotography, a light source for optical communication, an ultraviolet sensor, and a high-temperature operating transistor. The present invention relates to a device manufacturing method.

  Conventionally, a high-intensity blue LED using a group III nitride semiconductor typified by GaN and a purple LD that oscillates with an output of about 30 mW have been put into practical use. For the practical use of these group III nitride semiconductor devices, a p-type group III nitride fabrication technique is an important basic technique.

  In the p-type group III nitride, hydrogen is bonded to the p-type impurity (acceptor) and the acceptor is inactivated, so that crystal growth in an atmosphere containing hydrogen, hydrogen gas, or in a gas that generates hydrogen When the heat treatment is performed at, the resistance is increased. Therefore, in a method such as MOCVD using hydrogen as a carrier gas, it is not easy to produce a p-type group III nitride as-grown (as it is in a crystal grown state without any special post-treatment such as heat treatment). Absent. As a method for producing the p-type group III nitride, a special method is applied to the high-resistance group III nitride to make it p-type, and the crystal growth process is devised. This is roughly divided into a second method for producing a p-type group III nitride by as-grown.

In the first method, as a special treatment for p-type conversion, as shown in Patent Document 1, an atmosphere gas containing no hydrogen or a hydride gas (NH ₃ or the like) that generates hydrogen is used. Among them, a heat treatment is performed, and a part of hydrogen contained in the crystal is diffused and discharged out of the crystal to form a low resistance p-type, or as disclosed in Patent Document 2, There is known a method of irradiating an electron beam to cut a bond between hydrogen and p-type impurities contained in a crystal to form a low resistance p-type.

  Further, as the second method, as shown in Patent Document 3, the cooling process after the completion of crystal growth is performed in a gas atmosphere containing no hydrogen such as nitrogen or an inert gas. There is known a method of making the resistance p-type.

  In addition, there is a method in which crystal growth is performed in a system that does not contain hydrogen gas. This is an MOCVD method using nitrogen as a carrier gas instead of hydrogen, or an MBE method using a raw material not containing hydrogen.

  In these methods, it is known that p-type GaN can be obtained as-grown (in a state where only a crystal is grown but no special treatment for p-type conversion is performed).

Another method is the above method, Patent Document _{4, In x Al y Ga (} 1-xy) N, III nitride represented by (0 <x <1,0 ≦ y <1) A method for producing a p-type group III nitride semiconductor by growing a physical layer and then doping Mg as a p-type dopant in the range of 1 × 10 ¹⁷ cm ^{−3 to} 3 × 10 ²⁰ cm ⁻³ is shown. ing. This _{method, In x Al y Ga (1} -xy) N, the distortion of by using a (0 <x <1,0 ≦ y <1) layer as a buffer layer, p-type GaN layer grown thereon By relaxing and preventing deterioration of crystallinity, p-type GaN is produced as-grown. According to this method, p-type GaN having a carrier concentration of 5 × 10 ¹⁷ cm ⁻³ can be produced by doping GaN with 3 × 10 ²⁰ cm ⁻³ as a p-type dopant.

  Thus, at present, the p-type group III nitride semiconductor is manufactured by the method as described above.

By the way, a p-type group III nitride semiconductor used for a semiconductor device such as a light emitting element that requires a high current density is required to have a high carrier concentration, but a group III nitride semiconductor having a wide band gap is described above. Even if the p-type is used, a high carrier concentration cannot be obtained. For example, with AlGaN used for the cladding layer of a semiconductor laser, it is difficult to produce one with a carrier concentration exceeding 10 ¹⁸ cm ⁻³ . The cause is that the impurity level of the p-type impurity of the group III nitride semiconductor is deep. In AlGaN used in conventional light emitting diodes and semiconductor lasers, the greater the band gap, the deeper the impurity level of the p-type impurity, and the lower the activation rate of the acceptor at room temperature. For example, in GaN, it is 1% or less. Therefore, even if p-type impurities of about 10 ²⁰ cm ⁻³ are doped in GaN, the carrier concentration is only about 10 ¹⁸ cm ⁻³ . Since the activation rate is further reduced in AlGaN, the carrier concentration is further reduced. When the doping amount of the p-type impurity is increased to increase the carrier concentration (for example, when the doping amount exceeds 10 ²⁰ cm ⁻³ ), the p-type impurity enters the interstitial position and acts as a donor. As a result, the carrier concentration decreases. Therefore, even if the doping amount is increased, there is an upper limit on the carrier concentration. For example, it is about 10 ¹⁸ cm ^{−3 with} GaN.

As a method for solving this, Patent Document 5 discloses that Mg and Si are in a ratio of 2: 1, Mg and O in a ratio of 2: 1, Be and Si in a ratio of 2: 1, or Be and O in a ratio of 2: 1. by co-doping of about 10 ¹⁹ cm ^-3 ~10 ²⁰ cm ^-3 to GaN, shallower impurity level, and raises the KataHiroshi limit of impurities, a method of manufacturing a p-type GaN with a high carrier concentration It is shown.

  Patent Document 6 proposes a method of increasing the effective carrier concentration while increasing the band gap by using a superlattice structure of GaN / InGaN and InGaN / AlGaN. In the superlattice structure, by making the doping amount of one layer of the superlattice structure high and making the other low, so-called modulation doping, the layer with a large amount of doping becomes a carrier generation layer with a high carrier concentration, Since the low layer acts as a layer with high carrier mobility, the entire superlattice has low resistance. Further, even if the doping amount of both layers is increased, the carrier concentration is increased, so that the entire superlattice structure has a low resistance. Patent Document 6 discloses a light emitting diode in which these superlattice structures are applied to a p-type contact layer and a clad layer.

24 and 25 are diagrams showing a light emitting diode disclosed in Patent Document 6. FIG. FIG. 25 is an enlarged view of portion A of FIG. Referring to FIGS. 24 and 25, this light-emitting diode is formed on a sapphire substrate 1, a buffer layer 2 made of GaN, a first n-type nitride semiconductor layer 3 made of undoped n-type GaN, and a modulation-doped n-type. The second n-type nitride semiconductor layer 4 made of GaN, the third n-type nitride semiconductor layer 5 made of undoped n-type GaN, the quantum well active layer 6 made of undoped In _0.4 Ga _0.6 N, and the p-type Al _0.1 Ga _A p-side cladding layer 7 made of _0.9 N / GaN superlattice, a superlattice contact layer 8 made of undoped In _0.1 Ga _0.9 N (8b) and p-type GaN (8a) are sequentially laminated.

  24 and 25, the n-side electrode 11 is formed on the second n-type nitride semiconductor layer 4 exposed by etching. A p-side electrode 9 is formed on the p-side contact layer 8, and a p-side pad electrode 10 is formed on the p-side electrode 9.

  In Patent Document 6, after the crystal growth of the laminated structure is completed, the temperature is lowered to room temperature, and then the resistance in the p-type layer is reduced by annealing at 700 ° C. in a nitrogen atmosphere in a reaction vessel.

  As described above, it is difficult to produce a low-resistance p-type group III nitride semiconductor having a high carrier concentration. Therefore, although a high-intensity blue LED and a purple LD using a group III nitride semiconductor have been put into practical use, a violet laser operating at a higher output, a light emitting diode or semiconductor laser emitting in the ultraviolet region shorter than 400 nm, or A light receiving element having sensitivity characteristics in the ultraviolet wavelength region has not been put into practical use. For example, in the case of a semiconductor laser, since the resistance of the p-type clad layer and the contact resistance of the p-side ohmic electrode are still high, the operating voltage increases and the heat generated during a large current operation causes a high output operation. Not put into practical use. Moreover, in the case of a light emitting element or a light receiving element used in the ultraviolet wavelength region, the resistance does not become lower as the Al composition ratio of the p-type AlGaN layer serving as the cladding layer increases, so a practical one has not been realized. . In addition, a violet semiconductor laser that has been put into practical use also has a high manufacturing cost due to a processing step for making it p-type.

  Hereinafter, the problems of Patent Documents 1 to 6 described above will be specifically described. First, the III-type nitride semiconductor p-type method disclosed in Patent Document 1 is a method of discharging hydrogen that has deactivated p-type impurities to the outside of the crystal by heat treatment at about 700 ° C. The heat treatment is performed in an atmosphere that does not contain nitrogen, generally in a nitrogen gas atmosphere. However, since nitrogen gas consisting of nitrogen molecules is not a raw material for the production of group III nitrides, degradation of characteristics may occur, such as decomposition of the crystal surface and increase in surface resistance at temperatures exceeding 700 ° C. It was. The increase in the surface resistance leads to an increase in the contact resistance of the ohmic electrode, which causes a significant deterioration in the characteristics of the semiconductor device. In addition, since time and heat treatment equipment for the p-type heat treatment step are required, it is industrially expensive.

  Moreover, the low energy electron beam irradiation of patent document 2 has a shallow penetration depth of the electron beam, and can be made p-type only near the crystal surface. Further, since the area that can be irradiated with an electron beam at a time is small, it takes time to make the entire wafer surface p-type, and there is a problem that it is industrially expensive.

  In addition, Patent Document 3 does not require a heat treatment step, and thus can be reduced in cost. However, since cooling from a crystal growth temperature of about 1000 ° C. to room temperature is performed in an atmosphere of only nitrogen gas or inert gas, In the same manner as in Literature 1, the crystal surface may be decomposed and the surface resistance may be increased.

Further, the method of Patent Document 4, _{i.e., In x Al y Ga (1} -xy) N, after growing the III-nitride layer represented by (0 <x <1,0 ≦ y <1) Mg In the method for producing p-type GaN by doping in the range of 1 × 10 ¹⁷ cm ⁻³ to 1 × 10 ²⁰ cm ⁻³ , the crystal layer directly above is relaxed and exhibits p-type characteristics. In the case of forming, the effect decreases as the layer thickness increases. Therefore, there is a problem that the degree of freedom in device design is small.

  Regarding the crystal growth method in an atmosphere not containing hydrogen, first, in the MBE method, since crystal growth is performed in a high vacuum, it is difficult to perform high-quality crystal growth, such as formation of defects due to dissociation of nitrogen. In addition, there is a problem in the supply of nitrogen, the growth rate is slow, and it is not suitable for mass production as much as MOCVD.

  On the other hand, when crystal growth is performed by MOCVD in an atmosphere containing as little hydrogen as in the MBE method, in the GaN experiment by the inventor of the present application, only rugged surfaces can be grown, and those with good crystallinity are I couldn't grow. That is, it is considered that the conditions under which high-quality p-type GaN can be grown in an atmosphere containing no hydrogen are narrow.

Further, in the method of Patent Document 5 for producing a low-resistance p-type group III nitride semiconductor, Mg and Si are 2: 1, Mg and O are 2: 1, Be and Si are 2: 1, or Be. And O are simultaneously doped to GaN at a ratio of 2: 1 to about 10 ¹⁹ cm ⁻³ to 10 ²⁰ cm ⁻³ to produce p-type GaN having a high carrier concentration. However, as the doping amount is increased, the surface morphology becomes worse. Therefore, it has been difficult to produce a device such as a semiconductor laser that requires a flat waveguide structure.

Further, in the light emitting diode of Patent Document 6, the p-type Al _0.1 Ga _0.9 N / GaN superlattice is used to effectively increase the carrier concentration of the p-type cladding layer. However, in order to grow a high quality AlGaN crystal, the growth temperature needs to be higher than the growth temperature of GaN. The higher the mixed crystal ratio of Al, the higher the growth required. Conversely, in the case of GaN, if the growth temperature is increased, the crystal surface is decomposed, and crystal growth becomes difficult at the growth temperature of AlGaN having a high Al mixed crystal ratio. Therefore, in a GaN / AlGaN superlattice, it is necessary to grow AlGaN having a small Al mixed crystal ratio (close to GaN) or to perform crystal growth at the expense of either crystallinity. As a result, there are some restrictions in controlling the effective refractive index and the band gap as a whole of the GaN / AlGaN superlattice. That is, it is difficult to manufacture a low-resistance p-type superlattice having a large band gap. Accordingly, a clad layer having a large band gap is required for a light emitting element in the ultraviolet region, but it is difficult to produce such a light emitting element with a GaN / AlGaN superlattice.

Similarly, regarding the reduction in resistance of the contact layer by the In _0.1 Ga _0.9 N / GaN superlattice, the optimum crystal growth temperature of In _0.1 Ga _0.9 N and GaN is different, and in this case, the crystallinity of GaN is sacrificed. Has been. In InGaN / GaN superlattices, since the acceptor level of InGaN is shallow, a p-type semiconductor with low resistance can be obtained. However, the InGaN / GaN superlattice has a large band gap required for the cladding layer of the light emitting device in the ultraviolet region. It is impossible to get. Furthermore, both p-type superlattice structures require heat treatment at 700 ° C. or higher to reduce the resistance, so that the crystal surface is decomposed and the surface resistance is increased due to the deterioration of crystallinity. The In addition, the heat treatment may cause solid phase diffusion of p-type impurities and constituent elements, which may impair the p-type impurity concentration and the steepness of the composition at the superlattice interface. Furthermore, the temperature increase / decrease during the heat treatment causes thermal distortion of the group III nitride crystal and causes crystal defects. Therefore, the resistance reduction process by heat treatment may be a factor that deteriorates the characteristics of the p-type semiconductor.

  The present invention provides a method for manufacturing a semiconductor device having a desired refractive index and a band gap (particularly a large band gap) exhibiting a p-type characteristic having a lower resistance than a p-type semiconductor made of a conventional p-type group III nitride semiconductor superlattice. The purpose is to provide.

  In order to achieve the above object, the invention according to claim 1 includes a first group III nitride semiconductor containing In and Al as constituent elements and a band gap smaller than that of the first group III nitride semiconductor. On a p-type group III nitride semiconductor having a superlattice structure in which second group III nitride semiconductors containing selenium as a constituent element are alternately stacked and having a thickness of at least a hydrogen diffusion depth or more A layer III nitride semiconductor is stacked, and after cooling from the film forming temperature of the group III nitride semiconductor to room temperature, a part or all of the region where hydrogen diffuses is removed to form the superlattice structure. A predetermined semiconductor device is formed by exposing the p-type group III nitride semiconductor laminated on the p-type group III nitride semiconductor, and forming an electrode on the exposed p-type group III nitride semiconductor. It is characterized by manufacturing.

  As described above, according to the first aspect of the present invention, the first group III nitride semiconductor containing In and Al as constituent elements and the band gap is smaller than that of the first group III nitride semiconductor, A p-type group III nitride semiconductor having a superlattice structure in which second group III nitride semiconductors containing In as a constituent element are alternately stacked has a thickness greater than the hydrogen diffusion depth After laminating at least one layer of group III nitride semiconductor and cooling from the film forming temperature of the group III nitride semiconductor to room temperature, a part or all of the region where hydrogen diffuses is removed, and the superlattice structure is formed. A predetermined semiconductor is formed by exposing the p-type group III nitride semiconductor laminated on the p-type group III nitride semiconductor, and forming an electrode on the exposed p-type group III nitride semiconductor. Since the equipment is manufactured, there is no post-treatment such as conventional heat treatment. , It is possible to crystal growth of low resistivity p-type group III nitride semiconductor. Thus, since a long-time heat treatment at a high temperature is not required, the p-type group III nitride semiconductor superlattice has no diffusion of atoms at the interface of the superlattice due to the heat treatment, and has a mixed crystal composition and dopant concentration profile. This steepness is maintained in a state immediately after crystal growth. In addition, since no distortion is caused by raising or lowering the temperature during the heat treatment, the occurrence of crystal defects is suppressed. Therefore, a low-resistance p-type group III nitride semiconductor in which high-quality crystallinity is maintained immediately after crystal growth can be manufactured. By manufacturing a semiconductor device using the p-type group III nitride semiconductor manufactured in this way, the electrical characteristics are higher than when using a p-type group III nitride semiconductor whose resistance is reduced by conventional heat treatment. And a highly reliable semiconductor device can be manufactured.

It is a figure which shows the structural example of the p-type group III nitride semiconductor which concerns on this invention. It is the elements on larger scale of FIG. It is a figure which shows the other structural example of the p-type group III nitride semiconductor which concerns on this invention. FIG. 4 is a partially enlarged view of FIG. 3. It is a figure which shows the other structural example of the p-type group III nitride semiconductor which concerns on this invention. It is the elements on larger scale of FIG. It is a figure which shows the structural example of the semiconductor device which concerns on this invention. It is the elements on larger scale of FIG. It is sectional drawing in a surface parallel to the light-projection end surface of the semiconductor device of FIG. It is a figure which shows the other structural example of the semiconductor device which concerns on this invention. It is the elements on larger scale of FIG. It is the elements on larger scale of FIG. It is a figure which shows the other structural example of the semiconductor device which concerns on this invention. It is the elements on larger scale of FIG. It is the elements on larger scale of FIG. It is a figure (perspective view) which shows the other structural example of the semiconductor device which concerns on this invention. It is sectional drawing of the semiconductor device of FIG. It is the elements on larger scale of FIG. It is the elements on larger scale of FIG. It is a figure (perspective view) which shows the other structural example of the semiconductor device which concerns on this invention. FIG. 21 is a cross-sectional view of the semiconductor device of FIG. 20. It is the elements on larger scale of FIG. It is the elements on larger scale of FIG. It is a figure which shows the conventional light emitting diode. It is the elements on larger scale of FIG.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. The p-type group III nitride semiconductor of the present invention has a smaller band gap than the first group III nitride semiconductor containing In (indium) and Al (aluminum) as constituent elements and the first group III nitride semiconductor. And a superlattice structure in which second group III nitride semiconductors containing In (indium) as constituent elements are alternately stacked.

  Here, the first group III nitride semiconductor is N (containing at least In and Al among the group III elements of B (boron), Al (aluminum), Ga (gallium), and In (indium)). Nitrogen). For example, a ternary system of InAlN, a quaternary system of InAlGaN or BInAlN, or a ternary mixed crystal semiconductor of BInAlGaN.

  The second group III nitride semiconductor is N (nitrogen) containing at least In among group III elements of B (boron), Al (aluminum), Ga (gallium), and In (indium). It is a semiconductor consisting of the compound. For example, a ternary system of InAlN, InGaN, or InBN, a quaternary system of InAlGaN, BInAlN, or BInGaN, or a ternary mixed crystal semiconductor of BInAlGaN.

  Both the first and second group III nitride semiconductors can have a desired band gap by changing the mixed crystal ratio of group III elements.

  The superlattice structure is formed by alternately laminating the first and second group III nitride semiconductors with a thickness that does not cause cracks. In general, the first and second semiconductor layers having a thickness of several nanometers to several tens of nanometers are alternately stacked on the order of several tens to hundreds of tens of layers. Is not particularly limited. Each layer does not need to have the same thickness, and can be appropriately selected depending on the application. In the p-type group III nitride semiconductor having the above structure, the apparent refractive index of the p-type group III nitride semiconductor is determined by the ratio of each group III element contained in the entire superlattice structure. Therefore, the apparent refractive index of the p-type group III nitride semiconductor of the present invention can be controlled by controlling the thickness and composition of each layer.

  The superlattice structure is doped with a p-type dopant. As the p-type dopant, Mg or Be is generally used, but any dopant other than Mg or Be can be used as long as it becomes an acceptor. The p-type dopant may be doped into both the first and second group III nitride semiconductors, only the first group III nitride semiconductor, or only the second group III nitride semiconductor. Is possible. It is also possible to take the form of modulation doping in which the doping amount of one of the first and second group III nitride semiconductors is reduced.

  A superlattice structure doped with a p-type dopant exhibits a p-type conductivity type. In addition, the p-type conductivity type here means the conductivity type when the entire superlattice structure is regarded as one semiconductor layer. Therefore, it does not mean the electric conduction type of only each semiconductor layer constituting the superlattice structure. For example, even if the first group III nitride semiconductor is insulative (high resistance n-type or p-type), the second group III nitride semiconductor is p-type, and the entire superlattice structure is p-type. Those exhibiting type characteristics are regarded as p-type semiconductors. Also, when the first group III nitride semiconductor is p-type and the second group III nitride semiconductor is insulating (high resistance n-type or p-type), both the first and second semiconductors Are p-type semiconductors that exhibit p-type characteristics as a whole superlattice structure.

More specifically, in the p-type group III nitride semiconductor of the present invention, In _z Ga _(1-z) N (0 <z ≦ 1) can be used for the second group III nitride semiconductor. In this case, in order to effectively obtain a low-resistance p-type characteristic, it is desirable to dope a p-type dopant into at least the second group III nitride semiconductor. The reason is that the acceptor level of In _z Ga _(1-z) N (0 <z ≦ 1), which is the second group III nitride semiconductor, becomes shallower as the In mixed crystal ratio increases (that is, the acceptor's level). This is because the activation energy is reduced and a high carrier concentration can be obtained. Therefore, it is possible to increase the carrier concentration of the superlattice structure by doping the second group III nitride semiconductor In _z Ga _(1-z) N (0 <z ≦ 1) with the p-type dopant. Thus, p-type characteristics with low resistance can be exhibited.

  In the p-type group III nitride semiconductor of the present invention, the first group III nitride semiconductor and the second group III nitride semiconductor may have different lattice constants. Note that the lattice constants of the first group III nitride semiconductor and the second group III nitride semiconductor can be controlled by controlling the mixed crystal composition.

1 and 2 are diagrams showing a configuration example of a p-type group III nitride semiconductor according to the present invention. FIG. 2 is an enlarged view of portion B of FIG. Referring to FIGS. 1 and 2, the p-type group III nitride semiconductor on the sapphire substrate 20 is a low temperature GaN buffer layer 21, GaN layer 22 is epitaxially grown on the laminated structure which are sequentially stacked, an In _0.04 Al _0.2 This is a p-type group III nitride semiconductor 23 having a superlattice structure of a Ga _0.76 N layer 23a and a p-type In _0.1 Al _0.04 Ga _0.86 N layer 23b. Each layer 23a, 23b constituting the superlattice has a thickness of 5 nm, and is formed by growing each layer 23a, 23b in 50 cycles. The entire superlattice is 0.5 μm thick. The p-type In _0.1 Al _0.04 Ga _0.86 N layer 23b is doped with p-type impurity Mg (magnesium). The p-type group III nitride semiconductor layer 23 having a superlattice structure has a carrier concentration of 3 × 10 ¹⁸ cm ⁻³ , indicating a low-resistance p-type.

FIG. 3 and FIG. 4 are diagrams showing another configuration example of the p-type group III nitride semiconductor according to the present invention. 4 is an enlarged view of a portion C in FIG. 3 and 4 show an example in which In _z Ga _(1-z) N (0 <z ≦ 1) is used for the second group III nitride semiconductor. That is, Referring to FIGS. 3, 4, the p-type group III nitride semiconductor, the low-temperature GaN buffer layer 31 on the sapphire substrate 30, GaN layer 32 is epitaxially grown sequentially stacked laminated structure on, an In _0.04 This is a p-type group III nitride semiconductor having a superlattice structure of an Al _0.2 Ga _0.76 N layer 33a and a p-type In _0.2 Ga _0.8 N layer 33b. The thickness of each layer constituting the superlattice is 10 nm for the In _0.04 Al _0.2 Ga _0.76 N layer 33a and 5 nm for the In _0.2 Ga _0.8 N layer 33b, and is formed by growing each layer 33a, 33b in 30 cycles. . The entire superlattice is 0.45 μm thick. The p-type In _0.2 Ga _0.8 N layer 33b is doped with p-type impurity Mg (magnesium). The carrier concentration of the p-type group III nitride semiconductor layer 33 having a superlattice structure was 9 × 10 ¹⁸ cm ⁻³ , indicating a low-resistance p-type.

FIG. 5 and FIG. 6 are diagrams showing another configuration example of the p-type group III nitride semiconductor according to the present invention. FIG. 6 is an enlarged view of a portion D in FIG. FIGS. 5 and 6 show examples in which the first group III nitride semiconductor and the second group III nitride semiconductor have different lattice constants. That is, FIG. 5, 6, the p-type group III nitride semiconductor, a sapphire substrate 40 on the low-temperature GaN buffer layer 41, GaN layer 42 is epitaxially grown sequentially stacked laminated structure on, an In _0.05 This is a p-type group III nitride semiconductor 43 having a superlattice structure of an Al _0.24 Ga _0.71 N layer 43a and a p-type In _0.2 Ga _0.8 N layer 43b. Each of the layers 43a and 43b constituting the superlattice has a thickness of 5 nm, and is formed by growing the layers 43a and 43b in 50 cycles. The entire superlattice is 0.5 μm thick. The In _0.05 Al _0.24 Ga _0.71 N layer 43a and the p-type In _0.2 Ga _0.8 N layer 43b are doped with p-type impurity Mg (magnesium). The p-type group III nitride semiconductor layer 43 having a superlattice structure has a carrier concentration of 9 × 10 ¹⁸ cm ⁻³ , indicating a low-resistance p-type.

  In addition, a semiconductor device having a stacked structure including the p-type group III nitride semiconductor of the present invention can be configured. In this case, the semiconductor device can take any form such as a light emitting element, a light receiving element, and an electronic device as long as it functions using the characteristics of the p-type group III nitride semiconductor of the present invention.

  For example, when the semiconductor device is a light emitting element, the light emitting element may be one using the p-type group III nitride semiconductor of the present invention as a cladding layer. Here, the structure of the light emitting device is not particularly limited, and the p-type group III nitride semiconductor of the present invention is used as a cladding layer, and has at least one pn junction, Any device that emits light by recombination of carriers and can extract light to the outside may be used. That is, any of a light emitting diode, a super luminescence diode, and a semiconductor laser may be used. Further, either an edge-emitting type or a surface-emitting type structure may be used.

  Specifically, when the light-emitting element is a semiconductor laser, the semiconductor laser should oscillate in a wavelength region shorter than 400 nm when the p-type group III nitride semiconductor of the present invention is used for the cladding layer. Can do. Here, the semiconductor laser has a structure in which a p-type cladding layer made of a p-type superlattice and an active layer made of a group III nitride semiconductor having a band gap corresponding to a wavelength of 400 nm or less are stacked. Any structure can be adopted as long as it has a laminated structure. The semiconductor laser may take either an edge-emitting type or a surface-emitting type.

  In the semiconductor laser having the above configuration, current is injected into the active layer by applying a voltage between the positive and negative electrodes, where carrier recombination occurs, light is amplified by the resonator mirror, and the wavelength is shorter than 400 nm. Laser oscillation in the area.

  In the present invention, as the first method for manufacturing the above-described semiconductor device, a first group III nitride semiconductor containing In (indium) and Al (aluminum) as constituent elements, and a first group III nitride semiconductor A p-type group III nitride semiconductor having a superlattice structure in which a band gap is smaller than that of the first group III nitride semiconductor and the second group III nitride semiconductor containing In (indium) as a constituent element is alternately stacked. A predetermined semiconductor device can be manufactured by stacking one group III nitride semiconductor.

  It is said that the reason why the p-type group III nitride semiconductor immediately after crystal growth has high resistance is that hydrogen is bonded to the acceptor and inactivated. The inventor of the present application investigated the cause of inactivation by experiment. As a result, the increase in resistance of the p-type group III nitride semiconductor is caused mainly by the diffusion of hydrogen contained in the atmospheric gas into the p-type group III nitride semiconductor crystal during the cooling process after crystal growth. I understood it.

  In this first manufacturing method, in order to prevent hydrogen from diffusing into the p-type group III nitride semiconductor in the cooling process after crystal growth, the crystal growth of the p-type group III nitride semiconductor is continued thereon. A hydrogen diffusion prevention layer made of a group III nitride semiconductor is formed to suppress an increase in resistance of the p-type group III nitride semiconductor. The composition and electrical conductivity type of the group III nitride semiconductor serving as the hydrogen diffusion preventing layer are not particularly limited. Further, the thickness may be greater than the hydrogen diffusion depth. According to the experiment by the inventors of the present application, when p-type GaN is used as the diffusion preventing layer, it is confirmed that the p-type GaN may have a thickness of about 0.5 μm.

  As described above, the p-type group III nitride semiconductor produced by the first production method does not require a special p-type activation treatment such as annealing, and is as-grown (state of crystal growth only). Shows p-type characteristics. That is, in the first manufacturing method, a semiconductor device having a p-type group III nitride semiconductor that exhibits p-type characteristics in as-grown can be manufactured. In the case of manufacturing a semiconductor device using the group III nitride semiconductor multilayer structure manufactured as described above, the diffusion prevention layer can be used as it is, or the diffusion prevention layer can be used as it is. It is also possible to manufacture a semiconductor device by removing all or part thereof.

  In the present invention, as the second method for manufacturing the semiconductor device described above, a first group III nitride semiconductor and a first group III nitride semiconductor containing In (indium) and Al (aluminum) as constituent elements are used. Layer structure including a p-type group III nitride semiconductor having a superlattice structure in which a band gap is smaller than that and second group III nitride semiconductors containing In (indium) as a constituent element are alternately stacked. After crystal is formed by crystal growth, cooling from the growth temperature is performed in a cooling gas atmosphere containing a nitrogen source, and a predetermined semiconductor device can be manufactured.

  The inventor of the present application performed cooling after crystal growth in a nitrogen atmosphere containing no hydrogen at all in order to obtain low-resistance p-type GaN. However, the grown GaN had high resistance. Further, after the crystal growth was completed, the gas atmosphere was switched to nitrogen and held at the growth temperature for 10 minutes. As a result, it was found that a large number of steps were formed on the surface, and that it was clearly decomposed. Furthermore, even if hydrogen is contained in the cooling atmosphere after crystal growth, as long as the concentration is up to a certain level, there is little hydrogen diffusion into the crystal and the concentration is not high enough to make the entire crystal highly resistant. Was confirmed by experiments. From the above experimental results, the inventor of the present application caused the deterioration of the crystallinity due to the decomposition of the crystal surface rather than the inactivation of the acceptor by hydrogen passivation in the cooling with the atmospheric gas having a low hydrogen gas concentration. Thus, it was concluded that a low resistance p-type crystal could not be obtained.

  This second production method of the present invention will be described in more detail. First, crystal growth of a laminated structure containing the above-described p-type group III nitride semiconductor of the present invention or the p-type group III nitride semiconductor of the present invention on the surface of a substrate heated in a gas atmosphere containing hydrogen such as MOCVD. I do. Next, the crystal-grown substrate is cooled from the growth temperature. The cooling atmosphere at this time is a gas atmosphere containing a nitrogen raw material.

  As the gas atmosphere at the time of cooling, specifically, a mixed gas of an inert gas such as nitrogen or argon and a nitrogen raw material, or only a nitrogen raw material gas can be used. Also, a mixed gas obtained by adding hydrogen to several percent to about 30% to these atmospheric gases can be used.

  If the nitrogen source gas is contained in the atmosphere gas by about several percent, decomposition of the crystal surface is suppressed, but it is more effective if the majority (more than 50%) is nitrogen source.

  As the nitrogen raw material, organic compounds such as monomethyl hydrazine and dimethyl hydrazine, ammonia and the like can be used.

  The p-type group III nitride semiconductor manufactured by such a method exhibits p-type characteristics of as-grown and low resistance without performing a post-process such as annealing. That is, in the second manufacturing method, a low-resistance p-type group III nitride semiconductor can be manufactured as-grown.

The case where ammonia (NH ₃ ) is used as the nitrogen source contained in the cooling gas atmosphere in the second manufacturing method described above will be particularly described. Conventionally, it has been reported that when a low-resistance p-type GaN is heat-treated in an NH ₃ gas atmosphere, the resistance is increased, and the atmosphere when a high-resistance p-type group III nitride semiconductor is reduced in resistance by heat treatment is reported. It has been considered undesirable to include NH ₃ gas in the gas. However, the inventors of the present application have found that a low-resistance p-type group III nitride semiconductor can be obtained as-grown in the cooling process after crystal growth even if NH ₃ gas is contained. Furthermore, it was found that a low-resistance p-type group III nitride semiconductor can be obtained as-grown even if cooling is performed in a gas atmosphere containing NH ₃ as 100%.

That is, when the atmosphere of the cooling process after crystallization termination to an atmosphere containing NH _3, and at the time of cooling, even if the hydrogen is produced by decomposition of NH _3, a high resistance across the crystal diffuses into the crystal interior Rather, the active nitrogen generated by the decomposition of NH ₃ suppresses the decomposition of the crystal surface, so that the resistance of the crystal surface is prevented from increasing, and the low-resistance p-type group III nitride semiconductor becomes as-grown. It is thought that it is obtained by. Note that the effect can be obtained if the NH ₃ gas is contained in the atmosphere gas by about several percent, but it is more effective if the majority (more than 50%) is NH ₃ gas.

  7, 8, and 9 are diagrams showing a configuration example of a semiconductor device according to the present invention (a semiconductor device using the above-described p-type group III nitride semiconductor of the present invention). Here, the semiconductor devices of FIGS. 7, 8, and 9 are configured as light emitting / receiving elements in which edge-emitting light emitting diodes and edge-receiving photodiodes are monolithically integrated. 7 is a cross-sectional view taken along a plane perpendicular to the light emitting end face of the light emitting diode of the light emitting / receiving element, FIG. 8 is an enlarged view of a portion E in FIG. 7, and FIG. It is sectional drawing in a surface parallel to an output end surface.

  Referring to FIG. 7, FIG. 8, and FIG. 9, the light emitting diode and the photodiode are substantially in the shape of a rectangular parallelepiped, and spatially so that one light emitting end face of the light emitting diode faces the light receiving end face of the photodiode. It is formed separately.

The light emitting diode and the photodiode have the same laminated structure. The stacked structure is that an AlN low-temperature buffer layer 51, an n-type Al _0.03 Ga _0.97 N contact layer 52, an n-type Al _0.07 Ga _0.93 N cladding layer 53, an In _0.17 Ga _0.83 N active layer 54, an In _0.05 on a sapphire substrate 50. A p-type cladding layer 55 made of a superlattice of an Al _0.24 Ga _0.71 N layer 55a and a p-type In _0.15 Ga _0.85 N layer 55b and a p-type GaN contact layer 56 are sequentially laminated. Here, the p-type cladding layer 55 and the p-type GaN contact layer 56 are doped with Mg as a p-type dopant.

The light emitting diode and the photodiode are spatially separated by etching the stacked structure from the surface of the p-type GaN contact layer 56 to the n-type Al _0.03 Ga _0.97 N contact layer 52. The surface of the n-type Al _0.03 Ga _0.97 N contact layer 52 is exposed by this etching, and an n-side ohmic electrode 59 made of Ti / Al is formed on the exposed n-type Al _0.03 Ga _0.97 N contact layer 52. Yes. A p-side ohmic electrode 58 made of Ni / Au is formed on the p-type GaN contact layer 56 of the light emitting diode and the photodiode. Further, an insulating protective film 57 made of SiO ₂ is deposited on the portion other than the ohmic electrode. A wiring electrode 60 made of Ti / Al is formed on the insulating protective film 57. The wiring electrode 60 is electrically connected to the p-side ohmic electrode 58 of each of the light emitting diode and the photodiode. The side surfaces of the light emitting diode and the photodiode are formed substantially perpendicular to the substrate.

  The side surfaces facing each other through the grooves of the light emitting diode and the photodiode become the light emitting end surface 502 and the light receiving surface 503, respectively. In addition, the end surface of the light emitting diode opposite to the side surface facing the photodiode is a light emitting end surface 501 that emits light to the outside.

  This integrated light emitting / receiving element operates by injecting a forward current into the light emitting diode and applying a reverse bias to the photodiode. That is, when a bias is applied in the forward direction or the reverse direction to the p-side and n-side ohmic electrodes of each element, the light emitting diode emits light from the two light emitting end faces 501 and 502. Then, light emitted from the light emitting end face 502 facing the photodiode is incident on the light receiving surface 503 of the photodiode, and a photoelectromotive force corresponding to the intensity is generated in the photodiode and is taken out as a photocurrent to the outside. By monitoring the photocurrent of the photodiode, the current injected into the light emitting diode can be adjusted to control the light output. When light was emitted by injecting current into the light emitting diode, the peak wavelength of light emission was about 412 nm.

Next, an example of a manufacturing process of the integrated light emitting / receiving element shown in FIGS. 7, 8, and 9 will be described. In this manufacturing process example, the stacked structure of the integrated light emitting / receiving element was manufactured by crystal growth by MOCVD. In this manufacturing process example, first, the sapphire substrate 50 was set in a reaction tube and heated in hydrogen gas at 1120 ° C. to clean the surface of the substrate 50. Next, the temperature was lowered to 520 ° C., the growth atmosphere was changed to a mixed gas atmosphere of NH ₃ , nitrogen and hydrogen, TMA was flown, and the low temperature AlN buffer 51 was deposited.

Next, the temperature is raised to 1070 ° C., and TMG, TMA, and SiH ₄ are supplied in accordance with the composition using hydrogen as a carrier gas, and the n-type Al _0.03 Ga _0.97 N contact layer 52 is 3 μm thick, n-type Al _0.07 Ga _0.93. N clad layers 53 were sequentially laminated to a thickness of 0.5 μm. Next, the supply of hydrogen gas is stopped, the atmosphere is changed to a mixed gas atmosphere of NH ₃ and nitrogen, the temperature is lowered to 810 ° C., TMG and TMI are supplied using hydrogen as a carrier gas, and the In _0.17 Ga _0.83 N active layer 54 is formed to 50 nm. Grown to a thickness of. Next, TMG, TMA, TMI, (EtCp) ₂ Mg are supplied in accordance with the composition, and a p-type cladding layer 55 made of a superlattice of an In _0.05 Al _0.24 Ga _0.71 N layer 55a and a p-type In _0.15 Ga _0.85 N layer 55b. Was grown by 0.5 μm. The thickness of each layer 55a, 55b was 5 nm, and each layer 55a, 55b was grown 50 cycles. Next, the temperature was raised to 1050 ° C., TMG, (EtCp) ₂ Mg was supplied, and the p-type GaN contact layer 56 was laminated to a thickness of 0.2 μm. After crystal growth was completed, heat treatment was performed at 750 ° C. for 15 minutes in a nitrogen atmosphere in order to reduce the resistance of the p-type layer.

Next, a pattern in which two rectangular patterns with a width of 30 μm and a length of 50 μm were arranged 5 μm apart in the length direction was formed with a resist. Using this resist pattern as a mask, dry etching was performed to form a rectangular parallelepiped shape with a height of about 1.5 μm to be a light emitting diode and a photodiode, and the n-type Al _0.03 Ga _0.97 N contact layer 52 was exposed. Next, SiO _{2 serving} as the insulating protective film 57 was deposited on the surface of the laminated structure to a thickness of about 0.5 μm.

Next, the p-side ohmic electrode 58 was formed. The formation process of the p-side ohmic electrode 58 is as follows. That is, first, after forming a stripe pattern with resist on the light emitting diode and the photodiode, SiO ₂ is etched to expose the p-type GaN contact layer 56 on the ridge. Next, Ni / Au as a p-side ohmic electrode material was deposited. Thereafter, the wafer was immersed in an organic solvent, the resist was dissolved, and the electrode material deposited on the resist was lifted off to form a p-side ohmic electrode pattern on the light emitting diode and the photodiode. Thereafter, heat treatment was performed at 600 ° C. in a nitrogen atmosphere to form a p-side ohmic electrode 58 on the p-type GaN contact layer 56.

Next, an n-side ohmic electrode 59 and a wiring electrode 60 were formed. The formation process of the n-side ohmic electrode 59 and the wiring electrode 60 is as follows. That is, first, on the SiO ₂ film 57 above the n-type Al _0.03 Ga _0.97 N contact layer 52, a resist stripe pattern having a width of about 100 μm is formed with a resist, and then SiO ₂ is etched to form n-type Al _0.03 Ga _0.97 N The contact layer 52 is exposed. Next, the resist is removed, and a lift-off pattern of the wiring electrode 60 and the n-side ohmic electrode 59 is formed again with the resist. Next, Ti / Al, which is a material for the n-side ohmic electrode 59 and the wiring electrode 60, was deposited. Thereafter, the wafer was immersed in an organic solvent, the resist was dissolved, and the electrode material deposited on the resist was lifted off to form an n-side ohmic electrode and a wiring electrode pattern. Thereafter, the n-side ohmic electrode 59 was formed by heat treatment at 450 ° C. in a nitrogen atmosphere. Next, dicing was performed to separate the integrated light emitting / receiving element into chips.

  10, FIG. 11, and FIG. 12 are diagrams showing another configuration example of the semiconductor device according to the present invention. 10 is a cross-sectional view of the semiconductor device (semiconductor laser) on a plane perpendicular to the light emitting direction, FIG. 11 is an enlarged view of a portion F in FIG. 10, and FIG. FIG. The semiconductor device shown in FIGS. 10, 11 and 12 is configured as a light emitting element using the above-described p-type group III nitride semiconductor of the present invention as a cladding layer. More specifically, it is configured as a semiconductor laser.

10, 11, and 12, this semiconductor laser includes an AlGaN low-temperature buffer layer 71, an n-type Al _0.03 Ga _0.97 N contact layer 72, an In _0.05 Al _0.24 Ga _0.7 1N layer 73 a on a sapphire substrate 70. an n-type cladding layer 73 formed of a superlattice with an n-type In _0.2 Ga _0.80 N layer 73b, an n-type GaN guide layer 74, an In _0.15 Ga _0.85 N / In _0.02 Ga _0.98 N multiple quantum well active layer (2 pairs) 75, a p-type cladding layer 78 made of a superlattice of a p-type Al _0.2 Ga _0.8 N layer 76, a p-type GaN guide layer 77, a p-type In _0.05 Al _0.24 Ga _0.71 N layer 78a and a p-type In _0.2 Ga _0.80 N layer 78b, A p-type GaN contact layer 79 is sequentially laminated. Here, the p-type Al _0.2 Ga _0.8 N layer 76, the p-type GaN guide layer 77, the p-type cladding layer 78, and the p-type GaN contact layer 79 are doped with Mg as a p-type dopant.

Then, the laminated structure is etched from the surface of the p-type GaN contact layer 79 until the n-type Al _0.03 Ga _0.97 N contact layer 72 to expose the surface of n-type Al _0.03 Ga _0.97 N contact layer 72, the exposed n An n-side ohmic electrode 82 made of Ti / Al is formed on the type Al _0.03 Ga _0.97 N contact layer 72. Further, the current confinement ridge structure 400 is formed by etching from the surface of the p-type GaN contact layer 79 to the middle of the p-type cladding layer 78. A p-side ohmic electrode 81 made of Ni / Au is formed on the p-type GaN contact layer 79 on the outermost surface of the ridge 400. Further, SiO ₂ is deposited as the insulating protective film 80 except for the electrode forming portion. A wiring electrode 83 drawn from the p-side electrode is formed on the insulating protective film 80. An optical resonator end face is formed substantially perpendicular to the laminated structure and the current confinement ridge structure.

  When a forward current is injected into the electrode of this semiconductor laser, light is emitted, and when the current is further increased, laser oscillation occurs. The oscillation wavelength is about 409 nm.

  Next, an example of a manufacturing process of the semiconductor laser shown in FIGS. 10, 11, and 12 will be described. In this manufacturing process example, the crystal growth of the laminated structure of the semiconductor laser was performed by the MOCVD method. Further, the second manufacturing method described above (that is, the first group III nitride semiconductor containing In (indium) and Al (aluminum) as constituent elements, and the band gap is smaller than that of the first group III nitride semiconductor. A stacked structure including a p-type group III nitride semiconductor composed of a superlattice structure in which second group III nitride semiconductors containing In (indium) as a constituent element are alternately stacked is formed by crystal growth. Later, cooling from the growth temperature was performed in a cooling gas atmosphere containing a nitrogen raw material to produce a semiconductor laser. Here, the nitrogen source contained in the atmospheric gas during cooling after crystal growth was monomethylhydrazine.

In this manufacturing process example, first, the sapphire substrate 70 was set in a reaction tube and heated in hydrogen gas at 1120 ° C. to clean the surface of the substrate 70. Next, the temperature was lowered to 520 ° C., the atmosphere was changed to a mixed gas atmosphere of MMHy (monomethylhydrazine), NH ₃ , nitrogen and hydrogen, TMG and TMA were flowed, and a low temperature AlGaN buffer layer 71 was deposited. Next, the temperature was raised to 1050 ° C., TMG, TMI, and SiH ₄ were supplied according to the composition using hydrogen as a carrier gas, and an n-type Al _0.03 Ga _0.97 N contact layer 72 was grown to a thickness of 2 μm.

Next, the supply of hydrogen gas is stopped, the atmosphere is changed to a mixed gas atmosphere of MMHy (monomethylhydrazine), NH ₃ and nitrogen, the temperature is lowered to 810 ° C., and TMG, TMI, TMA, SiH ₄ are supplied using hydrogen as a carrier gas. An n-type cladding layer 73 made of a superlattice of In _0.05 Al _0.24 Ga _0.71 N layer 73a and In _0.2 Ga _0.80 N layer 73b was grown to a thickness of 0.6 μm. The thickness of each layer 73a, 73b was 6 nm, and each layer 73a, 73b was grown 50 cycles.

Next, the temperature was raised to 1050 ° C., the atmosphere was changed to a mixed gas atmosphere of MMHy (monomethylhydrazine), NH ₃ , nitrogen and hydrogen, and the n-type GaN guide layer 74 was laminated to a thickness of 0.1 μm.

Next, the supply of hydrogen gas is stopped, the atmosphere is changed to a mixed gas atmosphere of MMHy, NH ₃ and nitrogen, the temperature is lowered to 810 ° C., TMG and TMI are supplied using hydrogen as a carrier gas, and In _0.15 Ga _0.85 N / In _0.02 A Ga _0.98 N multiple quantum well active layer 75 (2 pairs) was grown. Next, the growth atmosphere is a mixed gas atmosphere of MMHy, NH ₃ , nitrogen and hydrogen, the temperature is raised to 1070 ° C., and TMG, TMA, (EtCp) ₂ Mg is supplied according to the composition using hydrogen as a carrier gas, and p-type The Al _0.2 Ga _0.8 N layer 76 was grown to a thickness of 20 nm, and the p-type GaN guide layer 77 was grown to a thickness of 0.1 μm.

Next, the supply of hydrogen gas is stopped, the atmosphere is made a mixed gas atmosphere of MMHy, NH ₃ and nitrogen, the temperature is lowered to 810 ° C., and TMG, TMI, TMA, (EtCp) ₂ Mg are supplied using hydrogen as a carrier gas, A p-type cladding layer 78 made of a superlattice of In _0.05 Al _0.24 Ga _0.71 N layer 78a and In _0.2 Ga _0.80 N layer 78b was grown to a thickness of 0.6 μm. The thickness of each layer 78a, 78b was 6 nm, and 50 cycles of each layer 78a, 78b were grown. Finally, the temperature was raised to 1050 ° C., and the p-type GaN contact layer 79 was laminated to a thickness of 0.2 μm.

  After the completion of crystal growth, the supply of the group III material and the p-type dopant material was stopped, and the mixture was cooled to room temperature in a mixed gas atmosphere of nitrogen gas, MMHy, and hydrogen gas (about 6% of the whole). After cooling, it was confirmed that when the surface of the laminated structure was filled with a tester, there was conduction and the p-type GaN contact layer 79 on the surface had a low resistance.

Subsequently, a stripe pattern having a width of 4 μm was repeatedly formed with a pitch of 1 mm using a resist. Using this resist pattern as a mask, a depth of about 0.7 μm was dry etched to form a ridge structure 400. After removing the resist mask, a stripe pattern having a width of 500 μm covering the ridge structure 400 with a resist was repeatedly formed at a pitch of 1 mm. Using this resist pattern as a mask, the n-type Al _0.03 Ga _0.97 N contact layer 72 was exposed by dry etching to a depth of about 1.5 μm. Next, SiO _{2 serving} as an insulating protective film 80 was deposited on the surface of the laminated structure to a thickness of about 0.5 μm.

Next, a p-side ohmic electrode 81 was formed. The formation process of the p-side ohmic electrode 81 is as follows. First, after forming a blank stripe pattern on the ridge structure 400 with a resist, SiO ₂ is etched to expose the p-type GaN contact layer 79 on the ridge structure 400. Next, the resist was removed, and a resist stripe pattern with a width of about 450 μm was formed again. Ni / Au as a p-side ohmic electrode material was deposited on the ridge structure 400. Thereafter, the wafer was immersed in an organic solvent, the resist was dissolved, and the electrode material deposited on the resist was lifted off to form a p-side ohmic electrode pattern only on the semiconductor laser laminated structure. Thereafter, heat treatment was performed at 600 ° C. in a nitrogen atmosphere, and a p-side ohmic electrode 81 was formed on the p-type GaN contact layer 79.

Next, an n-side ohmic electrode 82 and a wiring electrode 83 were formed. The formation process of the n-side ohmic electrode 82 and the wiring electrode 83 is as follows. First, on the SiO ₂ film on the n-type Al _0.03 Ga _0.97 N contact layer 72, a stripe pattern having a width of about 100 μm is formed with a resist, and then SiO ₂ is etched to form an n-type Al _0.03 Ga _0.97 N contact layer 72. To expose. After removing the resist, the resist is applied again to form a lift-off electrode pattern on the p-side ohmic electrode 81 and the portion where the n-side ohmic electrode is to be formed. Next, the n-side ohmic electrode material and the wiring electrode material Ti / Al are vapor-deposited, the wafer is immersed in an organic solvent, the resist is dissolved, the electrode material deposited on the resist is lifted off, and the n-side ohmic electrode pattern A wiring electrode pattern was formed. Thereafter, heat treatment was performed at 450 ° C. in a nitrogen atmosphere to form an n-side ohmic electrode 82.

  Next, the sapphire substrate 70 was thinly polished and divided so as to be substantially perpendicular to the ridge 400 to form an optical resonator end face.

  FIG. 13, FIG. 14, and FIG. 15 are diagrams showing another configuration example of the semiconductor device according to the present invention. 13 is a cross-sectional view taken along a plane perpendicular to the light emitting end face of the semiconductor device (edge-emitting light emitting diode), FIG. 14 is an enlarged view of a portion H in FIG. 13, and FIG. It is the figure which expanded the part I. FIG. The semiconductor device shown in FIGS. 13, 14, and 15 is configured as a light emitting element (edge emitting light emitting diode) using the above-described p-type group III nitride semiconductor of the present invention as a cladding layer.

Referring to FIGS. 13, 14, and 15, the light emitting diode has a substantially rectangular parallelepiped shape, and one side surface of the light emitting diode is a light emitting end surface. The stacked structure of the light emitting diode is composed of a superlattice of an n-type Al _0.07 Ga _0.93 N low-temperature buffer layer 91, an In _0.02 Al _0.34 Ga _0.64 N layer 92a and an In _0.18 Ga _0.82 N layer 92b on an n-type GaN substrate 90. n-type cladding layer 92, Al _0.07 Ga _0.93 N active layer 93, In _0.02 Al _0.34 Ga _0.64 N layer 94a and In _0.18 Ga _0.82 N layer 94b superlattice p-type cladding layer 94, p-type GaN contact layer 95 Are sequentially stacked. Here, Mg, which is a p-type impurity, is added to the p-type cladding layer 94 and the p-type GaN contact layer 95, respectively.

  A p-side ohmic electrode 96 made of Ni / Au is formed on the p-type GaN contact layer 95 of the light emitting diode. An n-side ohmic electrode 97 made of Ti / Al is formed on the back surface of the substrate 90. The side surface of the light emitting diode is formed perpendicular to the substrate. When a forward bias is applied to the p-side and n-side ohmic electrodes 96 and 97 of the light emitting diode, light is emitted to the outside from the light emitting end face 700 that is one side surface of the light emitting diode. The peak wavelength of light emission of this light emitting diode was about 350 nm.

  Next, an example of a manufacturing process of the light emitting diode of FIGS. 13, 14 and 15 will be described. In this manufacturing process example, the stacked structure of the light-emitting diode was manufactured by crystal growth using the MOCVD method. Further, the second manufacturing method described above (that is, the first group III nitride semiconductor containing In (indium) and Al (aluminum) as constituent elements, and the band gap is smaller than that of the first group III nitride semiconductor. A stacked structure including a p-type group III nitride semiconductor composed of a superlattice structure in which second group III nitride semiconductors containing In (indium) as a constituent element are alternately stacked is formed by crystal growth. Later, cooling from the growth temperature was performed in a cooling gas atmosphere containing a nitrogen raw material to produce a light emitting diode. At this time, the nitrogen raw material contained in the cooling gas atmosphere was ammonia.

In this manufacturing process example, first, the n-type GaN substrate 90 was set in a reaction tube and heated in ammonia gas at 1120 ° C. to clean the surface of the substrate 90. Next, the temperature is lowered to 600 ° C., the atmosphere is changed to a mixed gas atmosphere of NH ₃ , nitrogen, and hydrogen, TMA, TMG, and SiH ₄ gas that is an n-type dopant gas are flowed, and an n-type low-temperature Al _0.07 Ga _0.93 N buffer layer 91 Deposited. Next, the temperature is raised to 810 ° C., and TMG, TMA, TMI, and SiH ₄ as an n-type impurity gas are supplied in accordance with the composition, and an In _0.02 Al _0.34 Ga _0.64 N layer 92a, an In _0.18 Ga _0.82 N layer 92b, An n-type clad layer 92 made of a superlattice was laminated to a thickness of 0.3 μm. The thicknesses of the layers 92a and 92b were 10 nm for the In _0.02 Al _0.34 Ga _0.64 N layer 92a and 5 nm for the In _0.18 Ga _0.82 N layer 92b, and the layers 92a and 92b were grown for 20 periods. Next, the temperature was raised to 1070 ° C., and an Al _0.07 Ga _0.93 N active layer 93 was laminated to a thickness of 0.05 μm. Next, the temperature is lowered to 810 ° C., TMG, TMA, TMI, and (EtCp) ₂ Mg as a p-type impurity gas are supplied in accordance with the composition, and the In _0.02 Al _0.34 Ga _0.64 N layer 94a and In _0.18 Ga _0.82 N A p-type cladding layer 94 made of a superlattice with the layer 94b was laminated to a thickness of 0.3 μm. The thicknesses of the layers 94a and 94b were 10 nm for the In _0.02 Al _0.34 Ga _0.64 N layer 94a and 5 nm for the In _0.18 Ga _0.82 N layer 94b, and the layers 94a and 94b were grown for 20 cycles. Next, the temperature was raised to 1050 ° C., and the p-type GaN contact layer 95 was laminated to a thickness of 0.2 μm.

  After completion of the crystal growth, the reaction tube was cooled to the room temperature from the growth temperature to a mixed gas atmosphere of 60% ammonia gas and 40% nitrogen gas. After cooling, when a tester was filled on the surface of the laminated structure, it was confirmed that there was conduction and the p-type GaN contact layer 95 on the surface had a low resistance.

  Next, Ni / Au as a p-side ohmic electrode material was deposited on the top surface of the laminated structure. Thereafter, heat treatment was performed at 600 ° C. in a nitrogen atmosphere, and a p-side ohmic electrode 96 was formed on the p-type GaN contact layer 95. Next, the back surface of the GaN substrate 90 was polished to a thickness of about 100 μm. Next, Ti / Al, which is an n-side ohmic electrode material, was deposited and heat-treated at 450 ° C. in a nitrogen atmosphere to form an n-side ohmic electrode 97. Next, the substrate was cleaved to form the emission end face 700 and to perform chip separation.

  16, FIG. 17, FIG. 18 and FIG. 19 are diagrams showing another configuration example of the semiconductor device according to the present invention. 16 is a perspective view of the semiconductor laser, FIG. 17 is a cross-sectional view taken along a plane perpendicular to the light emitting direction of the semiconductor laser, and FIG. 18 is an enlarged view of a portion J in FIG. FIG. 18 is an enlarged view of a portion K in FIG. The semiconductor device shown in FIGS. 16, 17, 18, and 19 is configured as a light emitting element (semiconductor laser) using the above-described p-type group III nitride semiconductor of the present invention as a cladding layer.

Referring to FIGS. 16, 17, 18, and 19, this semiconductor laser laminated structure 1000 includes an n-type AlGaN low-temperature buffer layer 101 and an n-type Al _0.03 Ga _0.97 N high-temperature buffer layer on an n-type GaN substrate 100. 102, an n-type cladding layer 103 composed of a superlattice of an In _0.05 Al _0.24 Ga _0.71 N layer 103a and an In _0.2 Ga _0.80 N layer 103b, an n-type GaN guide layer 104, an In _0.02 Ga _0.98 N / In _0.17 Ga _0.85 N multiplex quantum well active layer 105, p-type Al _0.2 Ga _0.8 N layer 106, p-type GaN guide layer _{107, in 0.0 5Al 0.24 Ga 0.71} p -type cladding layer composed of superlattices with N layer 108a and an in _0.2 Ga _0.80 N layer 108b 108, a p-type GaN contact layer 109, and an insulating GaN layer 110 are sequentially stacked. The p-type Al _0.2 Ga _0.8 N layer 106, the p-type GaN guide layer 107, the p-type cladding layer 108, the p-type GaN contact layer 109, and the insulating GaN layer 110 are doped with Mg as a p-type impurity. Yes.

  The insulating GaN layer 110 is etched in a stripe shape until the surface of the p-type GaN contact layer 109 is exposed. A p-side ohmic electrode material made of Ni / Au is formed on the insulating GaN layer 110 and the exposed p-type GaN contact layer 109, and the p-side ohmic electrode 111 is striped on the p-type GaN contact layer 109. Is formed.

  Optical resonator end faces 801 and 802 are formed substantially perpendicular to the multilayer structure 1000 and the stripes of the p-side ohmic electrode 111. An n-side ohmic electrode 112 made of Ti / Al is formed on the back surface of the GaN substrate 100. When a forward current was injected into the electrodes 111 and 112 of the semiconductor laser, light was emitted, and when the current was further increased, laser oscillation occurred. The oscillation wavelength was about 409 nm.

  Next, an example of manufacturing steps of the semiconductor laser shown in FIGS. 16, 17, 18, and 19 will be described. In this manufacturing process example, the crystal growth of the laminated structure of the semiconductor laser was performed by the MOCVD method. In addition, the first manufacturing method described above (that is, the first group III nitride semiconductor containing In (indium) and Al (aluminum) as constituent elements and the band gap is smaller than that of the first group III nitride semiconductor). At least one group III nitride is formed on a p-type group III nitride semiconductor having a superlattice structure in which second group III nitride semiconductors containing In (indium) as a constituent element are alternately stacked. A manufacturing method of manufacturing a semiconductor device by stacking physical semiconductors was used.

In this manufacturing process example, first, the n-type GaN substrate 100 was set in a reaction tube, heated to 1120 ° C. in a mixed gas of hydrogen, nitrogen, and ammonia gas to clean the surface of the substrate 100. Next, the temperature was lowered to 600 ° C., and TMA, TMG, and SiH ₄ gas that is an n-type dopant gas were allowed to flow in a mixed gas atmosphere of NH ₃ , nitrogen, and hydrogen to deposit an n-type low-temperature AlGaN buffer layer 101. Next, the temperature is raised to 1070 ° C., TMG, TMA and SiH ₄ as n-type impurity gas are supplied according to the composition using hydrogen as a carrier gas, and the n-type Al _0.03 Ga _0.97 N high-temperature buffer layer 102 is formed to a thickness of 1 μm. Laminated. The temperature was then reduced to 810 ° C., TMG, TMA, TMI, and supplies the combined SiH ₄ to the composition as an n-type impurity gas, and In _0.05 Al _0.24 Ga _0.71 N layer 103a and an In _0.2 Ga _0.80 N layer 103b Ultra An n-type cladding layer 103 made of a lattice was laminated to a thickness of 0.5 μm. Next, the temperature is raised to 1050 ° C., the n-type GaN guide layer 104 is laminated to a thickness of 0.1 μm, then the temperature is lowered to 810 ° C., and TMG and TMI are supplied in accordance with the composition, In _0.02 Ga _0.98 N / In _0.17 Ga _0.85 N multiple quantum well active layers 105 (2 pairs) were stacked.

Next, the temperature is increased to 1070 ° C., TMG, TMA, and p-type impurity source (EtCp) ₂ Mg are supplied in accordance with the composition, and the p-type Al _0.2 Ga _0.8 N layer 106 is formed to a thickness of 20 nm, and p A type GaN guide layer 107 was laminated to a thickness of 0.1 μm. Next, the temperature is lowered to 810 ° C., TMG, TMA, TMI, and p-type impurity source (EtCp) ₂ Mg are supplied in accordance with the composition, and the In _0.05 Al _0.24 Ga _0.71 N layer 108a and the In _0.2 Ga _0.80 N layer 108b are supplied. And a p-type cladding layer 108 having a thickness of 0.5 μm. Next, the temperature is raised to 1050 ° C., the p-type GaN contact layer 109 is laminated to a thickness of 0.2 μm, and finally, the supply amount of (EtCp) ₂ Mg is reduced to form the insulating GaN layer 110 with a thickness of 0.5 μm. Laminated to thickness. After completion of crystal growth, it was cooled from the growth temperature to room temperature in a mixed gas atmosphere of hydrogen, nitrogen, and ammonia gas.

  Next, a resist pattern having a width of 5 μm was repeatedly formed at a pitch of 300 μm. Using this resist pattern as a mask, the p-type GaN contact layer 109 was exposed by dry etching to a depth of about 0.5 μm. After removing the resist mask, a striped p-side ohmic electrode 111 was formed on the p-type GaN contact layer 109. The P-side ohmic electrode 111 was formed by depositing Ni / Au as a p-side ohmic electrode material on the wafer surface and then heat-treating it at 600 ° C. in a nitrogen atmosphere. Next, the back surface of the substrate 100 was polished to a thickness of about 100 μm, and Ti / Al as an n-side ohmic electrode material was then deposited. Thereafter, the n-side ohmic electrode 112 was formed by heat treatment at 450 ° C. in a nitrogen atmosphere. Next, the wafer on which the semiconductor laser structure was formed was cleaved so as to be substantially perpendicular to the stripe-shaped electrode 111 to form optical resonator end faces 801 and 802.

  20, FIG. 21, FIG. 22, and FIG. 23 are diagrams showing other configuration examples of the semiconductor device according to the present invention. 20 is a perspective view of the semiconductor laser, FIG. 21 is a cross-sectional view taken along a plane perpendicular to the light emitting direction of the semiconductor laser, and FIG. 22 is an enlarged view of a portion L in FIG. FIG. 22 is an enlarged view of a portion M in FIG. 21. 20, 21, 22, and 23 are configured as light emitting elements (semiconductor lasers) using the above-described p-type group III nitride semiconductor of the present invention as a cladding layer. In particular, this light emitting device is configured as a semiconductor laser that oscillates in a wavelength region shorter than 400 nm in which the above-described p-type group III nitride semiconductor of the present invention is used for a cladding layer.

20, 21, 22, and 23, the stacked structure 2000 of the semiconductor laser includes an n-type AlGaN low-temperature buffer layer 121 and an n-type Al _0.03 Ga _0.97 N high-temperature buffer layer 122 on an n-type GaN substrate 120. , In _0.04 Al _0.24 Ga _0.72 N layer 123a and In _0.18 Ga _0.82 N layer 123b n-type cladding layer 123, n-type Al _0.1 Ga _0.9 N guide layer 124, GaN / Al _0.1 Ga _0.9 N multiple quantum P consisting of a superlattice of a well active layer 125, a p-type Al _0.2 Ga _0.8 N layer 126, a p-type Al _0.1 Ga _0.9 N guide layer 127, an In _0.04 Al _0.24 Ga _0.72 N layer 128a and an In _0.18 Ga _0.82 N layer 128b. A type cladding layer 128 and a p-type GaN contact layer 129 are sequentially stacked. The p-type Al _0.2 Ga _0.8 N layer 126, the p-type Al _0.1 Ga _0.9 N guide layer 127, the p-type cladding layer 128, and the p-type GaN contact layer 129 are doped with Mg as a p-type impurity.

The stacked structure 2000 is etched from the surface of the p-type GaN contact layer 129 to the middle of the p-type cladding layer 128 to form a current confinement ridge structure 900. A p-side ohmic electrode 131 made of Ni / Au is formed on the p-type GaN contact layer 129 on the outermost surface of the ridge structure 900. Further, SiO ₂ is deposited as the insulating protective film 130 except for the p-side electrode forming portion. Optical resonator end faces 901 and 902 are formed substantially perpendicular to the laminated structure 2000 and the current confinement ridge structure 900. An n-side ohmic electrode 132 made of Ti / Al is formed on the back surface of the GaN substrate 120. When a forward current was injected into the electrodes 131 and 132 of the semiconductor laser, light was emitted, and when the current was further increased, laser oscillation occurred. The oscillation wavelength was about 365 nm.

  Next, an example of manufacturing steps of the semiconductor laser shown in FIGS. 20, 21, 22, and 23 will be described. In this manufacturing process example, the crystal growth of the laminated structure of the semiconductor laser was performed by the MOCVD method. Further, the second manufacturing method described above (that is, the first group III nitride semiconductor containing In (indium) and Al (aluminum) as constituent elements, and the band gap is smaller than that of the first group III nitride semiconductor. A stacked structure including a p-type group III nitride semiconductor composed of a superlattice structure in which second group III nitride semiconductors containing In (indium) as a constituent element are alternately stacked is formed by crystal growth. Later, cooling from the growth temperature was performed in a cooling gas atmosphere containing a nitrogen source, and a manufacturing method for manufacturing a semiconductor device was used. At this time, the nitrogen raw material contained in the cooling gas atmosphere was ammonia.

In this manufacturing process example, first, the n-type GaN substrate 120 was set in a reaction tube, heated to 1120 ° C. in a mixed gas of hydrogen, nitrogen, and ammonia gas, and the surface of the substrate 120 was cleaned. Next, the temperature was lowered to 600 ° C., and TMA, TMG, and SiH ₄ gas, which is an n-type dopant gas, were flowed in a mixed gas atmosphere of NH ₃ , nitrogen, and hydrogen to deposit an n-type low-temperature AlGaN buffer layer 121. Next, the temperature is raised to 1070 ° C., TMG, TMA using hydrogen as a carrier gas, and SiH ₄ as n-type impurity gas are supplied in accordance with the composition, and the n-type Al _0.03 Ga _0.97 N high-temperature buffer layer 122 is formed to a thickness of 1 μm. Laminated.

The temperature was then reduced to 810 ° C., TMG, TMA, TMI, and supplies the combined SiH ₄ to the composition as an n-type impurity gas, and In _0.04 Al _0.24 Ga _0.72 N layer 123a and an In _0.18 Ga _0.82 N layer 123b Ultra An n-type cladding layer 123 made of a lattice was laminated to a thickness of 0.6 μm. The thickness of each layer 123a, 123b was 10 nm for the In _0.04 Al _0.24 Ga _0.72 N layer 123a and 5 nm for the In _0.18 Ga _0.82 N layer 123b, and the layers 123a, 123b were grown for 40 cycles. Next, the temperature is raised to 1070 ° C., an n-type Al _0.1 Ga _0.9 N guide layer 124 is stacked to a thickness of 0.1 μm, and then a GaN / Al _0.1 Ga _0.9 N multiple quantum well active layer 125 (3 pairs) is formed. Laminated. Next, TMG, TMA, and p-type impurity source (EtCp) ₂ Mg are supplied in accordance with the composition, the p-type Al _0.2 Ga _0.8 N layer 126 is formed to a thickness of 20 nm, and the p-type Al _0.1 Ga _0.9 N guide Layer 127 was laminated to a thickness of 0.1 μm. Next, the temperature is lowered to 810 ° C., and TMG, TMA, TMI, and p-type impurity source (EtCp) ₂ Mg are supplied in accordance with the composition, and the In _0.04 Al _0.24 Ga _0.72 N layer 128 a and the In _0.18 Ga _0.82 N layer 128 b And a p-type cladding layer 128 made of a superlattice with a thickness of 0.6 μm. The thickness of each layer 128a, 128b was 10 nm for the In _0.04 Al _0.24 Ga _0.72 N layer 128a and 5 nm for the In _0.18 Ga _0.82 N layer 128b, and each layer 128a, 128b was grown for 40 periods. Next, the temperature was raised to 1050 ° C., and the p-type GaN contact layer 129 was laminated to a thickness of 0.2 μm. After the completion of crystal growth, the reaction tube was cooled to room temperature from the growth temperature in an atmosphere containing only ammonia gas.

  After cooling, it was confirmed that when the surface of the laminated structure was filled with a tester, there was conduction and the p-type GaN contact layer 129 on the surface had a low resistance.

Subsequently, a stripe pattern having a width of 4 μm was repeatedly formed with a resist at a pitch of 300 μm. Using this resist pattern as a mask, a depth of about 0.7 μm was dry etched to form a ridge 900. After removing the resist mask, SiO _{2 serving} as the insulating protective film 130 was deposited on the surface of the laminated structure to a thickness of about 0.5 μm.

Next, a p-side ohmic electrode 131 was formed. The formation process of the p-side ohmic electrode 131 is as follows. First, after forming a stripe pattern with resist on the ridge 900, the SiO ₂ insulating protective film 130 is etched to expose the p-type GaN contact layer 129 on the ridge. Next, the resist was removed, and Ni / Au as a p-side ohmic electrode material was deposited on the wafer surface. Thereafter, heat treatment was performed at 600 ° C. in a nitrogen atmosphere to form the p-side ohmic electrode 131 on the p-type GaN contact layer 129.

  Next, the back surface of the substrate 120 was polished to a thickness of about 100 μm, and Ti / Al as an n-side ohmic electrode material was then deposited. Thereafter, the n-side ohmic electrode 132 was formed by heat treatment at 450 ° C. in a nitrogen atmosphere. Next, the wafer on which the semiconductor laser structure was formed was cleaved so as to be substantially perpendicular to the ridge 900 to form optical resonator end faces 901 and 902.

1, 20, 30, 40, 50, 70 Sapphire substrate 2 Buffer layer 3 First n-side nitride semiconductor layer 4 Second n-side nitride semiconductor layer 5 Third n-side nitride semiconductor layer 6 Active layer 7 p-side cladding layer 8 p-side contact layer 9 p-side electrode 10 p-side pad electrode 11 n-side electrode 21, 31, 41 low-temperature GaN buffer layer 22, 32, 42 GaN layer 23, 33, 43 p-type having a superlattice structure Group III nitride semiconductor 23a, 33a In _0.04 Al _0.2 Ga _0.76 N layer 23b p-type In _0.1 Al _0.04 Ga _0.86 N layer 33b, 43b In _0.2 Ga _0.8 N layer ”
43a In _0.05 Al _0.24 Ga _0.71 N layer 51 AlN low temperature buffer layer 52,72 n-type Al _0.03 Ga _0.97 N contact layer 53 n-type Al _0.07 Ga _0.93 N clad layer 54 In _0.17 Ga _0.83 N active layer 55 p composed of superlattice Type cladding layer 55a In _0.05 Al _0.24 Ga _0.71 N layer 55b p type In _0.15 Ga _0.85 N layer 56 p type GaN contact layer 57, 80, 130 Insulating protective film 58, 81, 96, 131 p-side ohmic electrode 59, 82, 97, 112, 132 n-side ohmic electrode 60, 83 Wiring electrode 71, 101 AlGaN low-temperature buffer layer 73 n-type cladding layer made of superlattice 73a In _0.05 Al _0.24 Ga _0.71 N layer 73b n-type In _0.2 Ga _0.80 N layer
74 n-type GaN guide layer 75 In _0.15 Ga _0.85 N / In _0.02 Ga _0.98 N multiple quantum well active layer (2 pairs)
76 p-type Al _0.2 Ga _0.8 N layer 77 p-type GaN guide layer 78 p-type cladding layer made of superlattice 78a p-type In _0.05 Al _0.24 Ga _0.71 N layer 78b p-type In _0.2 Ga _0.80 N layer 78b
79, 95, 109 p-type GaN contact layer 90, 100, 120 n-type GaN substrate 91 n-type Al _0.07 Ga _0.93 N low-temperature buffer layer 92 n-type cladding layer 92a In _0.02 Al _0.34 Ga _0.64 N layer 92b In _0.18 Ga _0.82 N layer 93 Al _0.07 Ga _0.93 N active layer 94 p-type cladding layer 94a In _0.02 Al _0.34 Ga _0.64 N layer 94b In _0.18 Ga _0.82 N layer 102 n-type Al _0.03 Ga _0.97 N high temperature buffer layer 103 Superlattice n-type cladding layer 103a In _0.05 Al _0.24 Ga _0.71 N layer 103b In _0.2 Ga _0.80 N layer 104 n-type GaN guide layer 105 In _0.02 Ga _0.98 N / In _0.17 Ga _0.85 N multiple quantum well active layer 106 p-type Al _0.2 Ga _0.8 N layer 107 p-type GaN guide layer 108 p-type cladding layer made of superlattice 108a In _0.05 Al _0.24 Ga _0.71 N layer 108b In _0.2 Ga _0.80 N layer 110 Insulating GaN layer 111 Striped p-side ohmic electrode 121 n-type AlGaN low-temperature buffer layer 122 n-type Al _0.03 Ga _0.97 N high-temperature buffer layer 123 superlattice N-type cladding layer 123a In _0.04 Al _0.24 Ga _0.72 N layer 123b In _0.18 Ga _0.82 N layer 123b
124 n-type Al _0.1 Ga _0.9 N guide layer 125 GaN / Al _0.1 Ga _0.9 N multiple quantum well active layer 126 p-type Al _0.2 Ga _0.8 N layer 127 p-type Al _0.1 Ga _0.9 N guide layer 128 p-type cladding made of superlattice Layer 128a In _0.04 Al _0.24 Ga _0.72 N layer 128b In _0.18 Ga _0.82 N layer 129 p-type GaN contact layer 400,900 Current confined ridge structure 401, 402, 801, 802 Optical resonator end face 501, 502, 700 Light emitting end face 503 Light receiving surface 1000, 2000 Laminated structure of semiconductor laser

JP-A-5-183189 JP-A-3-218625 JP-A-8-125222 JP-A-6-232451 JP-A-10-101696 JP 11-340509 A

Claims (1)

  The first group III nitride semiconductor containing In and Al as constituent elements and the second group III nitride semiconductor whose band gap is smaller than that of the first group III nitride semiconductor and containing In as constituent elements are alternated. And stacking at least one group III nitride semiconductor having a thickness equal to or greater than a hydrogen diffusion depth on a p-type group III nitride semiconductor having a superlattice structure stacked on After cooling from the deposition temperature of the physical semiconductor to room temperature, part or all of the region where hydrogen has diffused is removed, and the layer stacked on the p-type group III nitride semiconductor composed of the superlattice structure A method of manufacturing a semiconductor device, wherein a predetermined semiconductor device is manufactured by exposing a p-type group III nitride semiconductor and forming an electrode on the exposed p-type group III nitride semiconductor.

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