JP2014157956A - Silicon carbide semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a silicon carbide semiconductor device manufacturing method which can manufacture a silicon carbide semiconductor device having a structure in which an impurity implantation region is comparatively deep and a whole length is long and clearance between impurity implantation regions is comparatively narrow with high accuracy.SOLUTION: A silicon carbide semiconductor device manufacturing method comprises exposing a part in a surface part on one side in a thickness direction of the silicon carbide semiconductor substrate 11, where a P-type impurity implantation region 14 is formed and forming an implantation mask 15 for covering the remaining part. The implantation mask 15 includes a linear part having an aspect ratio fo 3.33 and more. when forming the implantation mask 15, at least the linear part includes a lower layer mask 12 and an upper layer mask 13. At this time, the lower layer mask 12 is formed from at least one of an oxide film and a nitride film and the upper layer mask 13 is formed from a resist film.

Description

  The present invention relates to a method for manufacturing a silicon carbide semiconductor device such as a silicon carbide semiconductor power device.

  A silicon carbide semiconductor power device is provided with a termination structure such as a field limiting ring (abbreviation: FLR) structure that relaxes the electric field inside and on the surface of the device. A terminal structure such as an FLR structure and a P-well constituting a metal-oxide-semiconductor field effect transistor (abbreviation: MOSFET) are formed using an ion implantation method using a resist as a mask. It is formed by implanting impurities into a necessary region (for example, see Patent Document 1).

  As the FLR structure, in order to obtain the function of relaxing the electric field, it is necessary to form a structure in which the interval between the impurity implantation regions, that is, the width of the impurity non-implanted region is relatively narrow. In particular, in a silicon carbide semiconductor, implanted impurities hardly thermally diffuse. Therefore, in order to obtain a structure in which the width of an unimplanted region of impurities is relatively narrow, the remaining width (hereinafter sometimes referred to as “remaining width”) is required. A relatively thin resist pattern is required.

  Further, when forming the FLR structure, it is necessary to implant impurities relatively deeply into the silicon carbide semiconductor. In order to implant impurities relatively deeply, it is necessary to perform implantation with relatively high energy. Therefore, a relatively thick resist pattern that can withstand relatively high energy implantation is required.

  Furthermore, since the power device passes a relatively large current, the size of the chip constituting the power device is relatively large. The FLR structure is formed along the periphery of the chip. For example, when the chip is rectangular, the P-well is formed in a substantially rectangular annular shape including line-shaped portions parallel to the four sides constituting the peripheral edge of the chip. Therefore, when forming the FLR structure, a resist pattern including a relatively long line-shaped portion corresponding to the chip size is required.

  In forming the P-well, in order to reduce the energy loss during device operation, in order to form as many MOSFETs as possible per unit area, the intervals between the impurity implantation regions serving as P-wells are compared. It is necessary to form a narrow structure.

  As in the case of forming the above-described FLR structure, when forming the P-well, it is necessary to implant impurities relatively deeply into the silicon carbide semiconductor, so that it can withstand relatively high energy implantation. A thick resist pattern is required.

  Further, as described above, since the power device passes a relatively large current, the size of the chip constituting the power device is relatively large. The P-well constituting the MOSFET portion extends in one direction in the chip and is formed in a line shape. For example, when the chip is rectangular, the P-well extends in parallel to one side of the peripheral edge of the chip and is formed in a line shape. Therefore, when forming the P-well, a resist pattern including a relatively long line-shaped portion corresponding to the size of the chip is required as in the case of forming the FLR structure described above.

  As described above, when forming a termination structure such as an FLR structure and a P-well, a resist pattern that is relatively thin, thick, and includes a long line-shaped portion is required.

JP 2010-245281 A

  A resist pattern including a thin, thick, and long line-shaped portion required for forming the termination structure such as the FLR structure and the P-well is likely to collapse structurally. If a fallen resist pattern is used, impurities cannot be implanted into a necessary region.

  Therefore, there is a limitation in the design of the structure of the silicon carbide semiconductor device having the termination structure such as the FLR structure and the P-well. This is not limited to the case where the termination structure such as the FLR structure and the P-well are formed, but the impurity implantation region of the structure to be formed is relatively deep and long, and the distance between the impurity implantation regions is compared. The same applies when forming a narrow structure.

  An object of the present invention is to provide a silicon carbide semiconductor device capable of accurately manufacturing a silicon carbide semiconductor device having a structure in which an impurity implantation region is relatively deep, has a long overall length, and a distance between impurity implantation regions is relatively narrow. It is to provide a manufacturing method.

  A method for manufacturing a silicon carbide semiconductor device of the present invention is a method for manufacturing a silicon carbide semiconductor device having an effective region in a part of a surface portion on one side in the thickness direction of a silicon carbide semiconductor substrate, and having a semiconductor element in the effective region. An implantation mask forming step of exposing a predetermined implantation planned region in a surface portion on one side in the thickness direction of the silicon carbide semiconductor substrate and forming an implantation mask covering a remaining region excluding the implantation planned region; An ion implantation step of forming an impurity implantation region by implanting impurity ions into the implantation implantation region that is exposed without being covered with the implantation mask, and the implantation mask includes one side in a thickness direction of the silicon carbide semiconductor substrate. A line-shaped portion extending in a line shape in an extending direction that is a direction parallel to the surface portion on the side, and the line-shaped portion is a direction perpendicular to the extending direction and is A dimension in a direction parallel to the surface portion on one side in the thickness direction of the silicon carbide semiconductor substrate is defined as a width, and a direction perpendicular to the extending direction and perpendicular to the surface portion on one side in the thickness direction of the silicon carbide semiconductor substrate Where the aspect ratio, which is the ratio of the height to the width, is 3.33 or more, and in the implantation mask forming step, at least the line-shaped portion of the implantation mask is formed of the silicon carbide semiconductor. A lower layer mask made of at least one of an oxide film and a nitride film, and an upper layer mask made of a resist film, laminated on the surface part on one side of the thickness direction of the lower layer mask. It is characterized by being prepared.

  According to the method for manufacturing a silicon carbide semiconductor device of the present invention, at least the line-shaped portion of the implantation mask is formed including a lower layer mask made of at least one of an oxide film and a nitride film and an upper layer mask made of a resist film. . The lower layer mask is stacked on the surface portion on one side in the thickness direction of the silicon carbide semiconductor substrate, and the upper layer mask is stacked on the surface portion on one side in the thickness direction of the lower layer mask.

  Since the line-shaped portion has an aspect ratio of 3.33 or more, the line-shaped portion may fall to the surface portion side on one side in the thickness direction of the silicon carbide semiconductor substrate. By being provided with the lower layer mask and the upper layer mask made of a resist film, it is possible to make it more difficult to fall than when the whole is made of a resist film.

  Accordingly, the shape of the implantation mask formed in the implantation mask formation step can be maintained, and impurity ions can be implanted into the region to be implanted in the ion implantation step, so that a line-shaped portion having an aspect ratio of 3.33 or more is included. A structure requiring an implantation mask, for example, a structure having a relatively deep impurity implantation region, a long overall length, and a relatively narrow interval between impurity implantation regions can be formed with high accuracy. Therefore, a silicon carbide semiconductor device having such a structure can be manufactured with high accuracy.

It is a top view which shows the state in which the resist film 13 was formed in the manufacturing process by the manufacturing method of the silicon carbide semiconductor device which is the 1st Embodiment of this invention. It is a top view which expands and shows the termination | terminus area | region 10 of FIG. It is sectional drawing which shows the state in the stage where formation of the inorganic film | membrane 12 was complete | finished. It is sectional drawing which shows the state in the stage where formation of the resist film 13 was complete | finished. It is sectional drawing which shows the state of the stage which completed formation of the implantation mask. It is sectional drawing which shows the state of the stage which complete | finished implantation of impurity ion. It is sectional drawing which shows the state in the stage which the removal of the implantation mask 15 was complete | finished. It is a graph which shows the relationship between implantation depth and implantation concentration. It is sectional drawing which shows the case where an implantation mask is formed only with the resist film. FIG. 6 is a cross-sectional view showing the relationship between the thickness dimension of the lower layer mask 12 and the thickness dimension of the upper layer mask 13. FIG. 6 is a cross-sectional view showing the relationship between the thickness dimension of the lower layer mask 12 and the thickness dimension of the upper layer mask 13. FIG. 6 is a cross-sectional view showing the relationship between the thickness dimension of the lower layer mask 12 and the thickness dimension of the upper layer mask 13. It is a top view which shows the state in which the resist film 43 was formed in the manufacturing process by the manufacturing method of the silicon carbide semiconductor device of the 2nd Embodiment of this invention. It is a top view which expands and shows the opening part 43c of FIG. FIG. 10 is a cross-sectional view showing a state where the formation of a P-type impurity implantation region 44 is completed as a P well. It is sectional drawing which shows the state of the stage which completed formation of the P-well contact. It is sectional drawing which shows the state of the stage which completed formation of the gate wiring 47 and an electrode. It is sectional drawing which shows the state of each process of the manufacturing process in the manufacturing method of the silicon carbide semiconductor device which is the 3rd Embodiment of this invention. It is sectional drawing which shows the state of each process of the manufacturing process in the manufacturing method of the silicon carbide semiconductor device which is the 3rd Embodiment of this invention. It is sectional drawing which shows the state of each process of the manufacturing process in the manufacturing method of the silicon carbide semiconductor device which is the 3rd Embodiment of this invention. It is sectional drawing which shows the state of each process of the manufacturing process in the manufacturing method of the silicon carbide semiconductor device which is the 3rd Embodiment of this invention. It is sectional drawing which shows the state of each process of the manufacturing process in the manufacturing method of the silicon carbide semiconductor device which is the 3rd Embodiment of this invention. It is sectional drawing which shows the state of each process of the manufacturing process in the manufacturing method of the silicon carbide semiconductor device which is the 3rd Embodiment of this invention. It is a graph which shows the relationship between implantation depth and implantation concentration. It is a graph which shows the relationship between implantation depth and implantation concentration. It is sectional drawing which shows the state of each process in the manufacturing process of MPS at the time of applying the method of 2nd Embodiment to FLR structure. It is sectional drawing which shows the state of each process in the manufacturing process of MPS at the time of applying the method of 2nd Embodiment to FLR structure. It is sectional drawing which shows the state of each process in the manufacturing process of MPS at the time of applying the method of 2nd Embodiment to FLR structure. It is sectional drawing which shows the state of each process in the manufacturing process of MPS at the time of applying the method of 2nd Embodiment to FLR structure. It is sectional drawing which shows the state of each process in the modification of the 3rd Embodiment of this invention. It is sectional drawing which shows the state of each process in the modification of the 3rd Embodiment of this invention. It is sectional drawing which shows the state of each process in the modification of the 3rd Embodiment of this invention. It is sectional drawing which shows the state of each process of the manufacturing process in the manufacturing method of the silicon carbide semiconductor device which is the 4th Embodiment of this invention. It is sectional drawing which shows the state of each process of the manufacturing process in the manufacturing method of the silicon carbide semiconductor device which is the 4th Embodiment of this invention. It is sectional drawing which shows the state of each process of the manufacturing process in the manufacturing method of the silicon carbide semiconductor device which is the 4th Embodiment of this invention. It is sectional drawing which shows the state of each process of the manufacturing process in the manufacturing method of the silicon carbide semiconductor device which is the 4th Embodiment of this invention. It is sectional drawing which shows the state of each process in the modification of the 4th Embodiment of this invention. It is sectional drawing which shows the state of each process in the modification of the 4th Embodiment of this invention. It is sectional drawing which shows the state of each process in the modification of the 4th Embodiment of this invention. It is sectional drawing which shows the state of the stage which completed the formation of the resist pattern 13 used as an implantation mask by a prior art. It is sectional drawing which shows the state of the stage which completed the formation of the resist pattern 43 used as an implantation mask by a prior art.

<First Embodiment>
FIG. 1 is a plan view showing a state in which a resist film 13 is formed in a manufacturing process by the method for manufacturing a silicon carbide semiconductor device of the first embodiment of the present invention. FIG. 2 is an enlarged plan view showing the termination region 10 of FIG. 1 and 2 correspond to plan views of silicon carbide semiconductor substrate 11 as seen from one side in the thickness direction.

  A silicon carbide semiconductor device manufactured by the method for manufacturing a silicon carbide semiconductor device of the present embodiment has an effective region in a part of the surface portion on one side in the thickness direction of silicon carbide semiconductor substrate 11, and has a semiconductor element in the effective region. Prepare. In FIG. 1, the effective area corresponds to a portion of the resist film 13 where the effective area resist portion 13a is formed. In the present embodiment, the effective region has a substantially rectangular shape, and is formed inside the outer peripheral edge portion of the surface portion on one side in the thickness direction of silicon carbide semiconductor substrate 11.

  In the present embodiment, a silicon carbide semiconductor device includes a metal-oxide film-semiconductor field effect transistor (abbreviation: MOSFET) as a semiconductor element. The semiconductor element is not limited to a MOSFET, and may be, for example, an MPS (Merged Pin / Schottky) diode in which Schottky barrier diodes and PIN diodes are alternately arranged and connected in parallel.

  The silicon carbide semiconductor device includes at least one of a MOSFET and an MPS diode as a semiconductor element. That is, the silicon carbide semiconductor device may include one or both of a MOSFET and an MPS diode as a semiconductor element.

  A silicon carbide semiconductor device has a field limiting ring (abbreviation: FLR) structure as a termination structure in a termination region surrounding an effective region. The FLR structure relaxes the electric field inside and on the surface of the silicon carbide semiconductor device which is a silicon carbide semiconductor power device. In FIG. 1, the termination region corresponds to a portion of the resist film 13 where the termination region resist portion 13b is formed.

  In the present embodiment, silicon carbide semiconductor substrate 11 has a rectangular shape, more specifically, a square shape when viewed from one side in the thickness direction. In the present embodiment, of the surface portion on one side in the thickness direction of silicon carbide semiconductor substrate 11, the region inside the outer peripheral edge and excluding the above-described effective region is the termination region.

  Specifically, the termination region resist portion 13b includes a plurality of resist portions 21 to 24 as shown in FIG. In FIG. 2, four resist portions 21 to 24 are shown as an example. In the following description, the four resist portions 21 to 24 are arranged in order from the side closer to the effective region, that is, the side closer to the effective region resist portion 13a, the first resist portion 21, the second resist portion 22, and the third resist portion 23. And the fourth resist portion 24.

  As shown in FIG. 1, the plurality of resist portions 21 to 24 are formed in an annular shape so as to surround each effective region. In FIG. 1, the resist portions 21 to 24 are shown by thin lines for easy understanding, but each resist portion 21 to 24 actually has a width as shown in FIG. 2.

  Impurity ions, that is, P-type impurity ions in this embodiment are implanted between the resist portions 13 in an ion implantation step described later. As a result, a plurality of P-type impurity implanted regions 14 into which P-type impurities are implanted are formed. In FIG. 2, four P-type impurity implantation regions 14 are shown as an example.

  In the following description, the four P-type impurity implantation regions 14 are arranged in the order of the first implantation region 14a, the second implantation region 14b, and the third implantation region from the side closer to the effective region, that is, the side closer to the effective region resist portion 13a. 14c and the fourth implantation region 14d.

  In FIG. 2, four resist portions 21 to 24 and four P-type impurity implantation regions 14 are shown, but the number of resist portions 21 to 24 and P-type impurity implantation regions 14 is not limited to four. There may be five or more, or three or less.

  In the present embodiment, the resist film 13 constitutes an implantation mask together with the inorganic film 12 formed in the lower layer. In other words, the implantation mask includes a lower layer mask made of the inorganic film 12 and an upper layer mask made of the resist film 13.

  3 to 7 are cross-sectional views showing states in the respective manufacturing steps according to the method for manufacturing the silicon carbide semiconductor device of the present embodiment. FIG. 3 is a cross-sectional view showing a state at a stage where the formation of the inorganic film 12 is completed.

  In the method for manufacturing the silicon carbide semiconductor device of the present embodiment, first, as shown in FIG. 3, on silicon carbide semiconductor substrate 11, specifically, on the surface portion on one side in the thickness direction of silicon carbide semiconductor substrate 11, An inorganic film 12 to be a lower layer mask is formed. The dimension in the thickness direction of the inorganic film 12 (hereinafter sometimes referred to as “thickness dimension”) t1 is, for example, 1.5 μm.

  In this embodiment, an oxide film is formed as the inorganic film 12. The inorganic film 12 is not limited to an oxide film, and may be at least one of an oxide film and a nitride film. That is, the inorganic film 12 may be configured with either an oxide film or a nitride film, or may be configured by stacking both an oxide film and a nitride film.

  The inorganic film 12 is a deposited film formed by depositing an inorganic material, for example. The inorganic film 12 is formed by, for example, chemical vapor deposition (abbreviation: CVD). The method for forming the inorganic film 12 is not limited to this.

  FIG. 4 is a cross-sectional view showing a state in which the formation of the resist film 13 has been completed. Next, as shown in FIG. 4, an opening is formed on the inorganic film 12, specifically, on the surface portion on one side in the thickness direction of the inorganic film 12 at a portion corresponding to the P-type impurity implantation region 14 shown in FIGS. 1 and 2. A resist film 13 (hereinafter sometimes referred to as a “resist pattern”) 13 having the pattern is formed. As described above, the resist pattern 13 includes the effective region resist portion 13a and the termination region resist portion 13b.

  The termination region resist portion 13b includes first to fourth resist portions 21 to 24. In FIG. 4, the description of the fourth resist portion 24 is omitted. First to fourth resist portions 21 to 24 are formed to extend in a line shape in the extending direction, which is a direction parallel to the surface portion on one side in the thickness direction of silicon carbide semiconductor substrate 11. The first to fourth resist portions 21 to 24 correspond to line-shaped portions.

  The plurality of resist portions 21 to 24 constituting the termination region resist portion 13b have a width that is a dimension in a direction parallel to the surface portion on one side in the thickness direction of the silicon carbide semiconductor substrate, as it is closer to the effective region resist portion 13a. It is formed small. That is, the width decreases in the order of the first resist portion 21, the second resist portion 22, the third resist portion 23, and the fourth resist portion 24. The width w1 of the first resist portion 21 is, for example, 0.7 μm.

  The thickness dimension t2 of the resist film 13 at the stage where the formation of the resist film 13 is completed is, for example, 0.98 μm. In FIG. 4, for easy understanding, the thickness dimension t2 of the resist film 13 and the thickness dimension t1 of the inorganic film 12 at the stage where the formation of the inorganic film 12 shown in FIG. Actually, however, the thickness dimension t1 of the inorganic film 12 is larger than the thickness dimension t2 of the resist film 13.

  FIG. 5 is a cross-sectional view showing a state at the stage where the formation of the implantation mask is completed. Using the resist pattern 13 as a mask, the inorganic film 12 is etched to form an implantation mask 15. The inorganic film 12 is etched by anisotropic etching, for example, dry etching.

  By etching the inorganic film 12, the thickness dimension of the resist film 13 decreases. That is, the thickness dimension t3 of the resist film 13 at the stage when the etching of the inorganic film 12 is finished is smaller than the thickness dimension t2 of the resist film 13 when the formation of the resist film 13 shown in FIG. For example, the thickness dimension of the resist film 13 at the stage where the etching of the inorganic film 12 is completed is 0.59 μm.

  As described above, the implantation includes the lower layer mask made of the inorganic film 12 (hereinafter sometimes referred to as “lower layer mask 12”) and the upper layer mask made of the resist film 13 (hereinafter sometimes referred to as “upper layer mask 13”). A mask 15 is formed. The step of forming the inorganic film 12 and the step of forming the resist film 13 correspond to an implantation mask forming step.

  Implantation mask 15 exposes a planned implantation region, which is a region in which P-type impurity implantation region 14 shown in FIGS. 1 and 2 is formed, on the surface portion on one side in the thickness direction of silicon carbide semiconductor substrate 11. Cover the remaining area except the area. The implantation mask 15 has a thickness dimension that prevents impurities implanted in an ion implantation process described later from penetrating the implantation mask 15.

  FIG. 6 is a cross-sectional view showing a state at the stage where impurity ion implantation is completed. Impurities are implanted by ion implantation into a region to be implanted that is exposed without being covered with the implantation mask 15. That is, impurity ions are implanted. In this embodiment, a P-type impurity such as aluminum (Al) is ion-implanted as the impurity. For example, Al is implanted with an acceleration energy of 700 keV.

  As described above, the implantation mask 15 has a thickness dimension t4 so that impurities implanted in the ion implantation process do not penetrate the implantation mask 15. For example, the thickness dimension t3 of the resist film 13 after etching the inorganic film 12 is 0.59 μm, the inorganic film 12 is composed of an oxide film, and the thickness dimension t2 of the oxide film constituting the inorganic film 12 is 1.5 μm. In some cases, the thickness dimension t4 of the implantation mask 15 is 2.95 μm in terms of a film thickness when the implantation mask 15 is entirely composed of a resist film (hereinafter, sometimes referred to as “resist film thickness”).

  By configuring the implantation mask 15 with such a thickness dimension t4, it is possible to prevent Al implanted with an acceleration energy of 700 keV from penetrating through the implantation mask 15, that is, penetrating through the implantation mask 15 as described above.

  The P-type impurity implantation region 14 is formed by ion implantation of the P-type impurity as described above. The step of forming the P-type impurity implantation region 14 in this way corresponds to an ion implantation step.

  FIG. 7 is a cross-sectional view showing a state at the stage where the removal of the implantation mask 15 is completed. After the ion implantation, the remaining implantation mask 15, specifically, the resist film 13 and the inorganic film 12 constituting the implantation mask 15 are removed. As a result, the state shown in FIG. 7 is obtained. In the present embodiment, as an example, silicon carbide semiconductor substrate 11 is n-type, and impurities implanted into silicon carbide semiconductor substrate 11 (hereinafter sometimes referred to as “implanted impurities”) are p-type. The silicon carbide semiconductor substrate 11 may be p-type and the implanted impurity may be n-type.

  P-type impurity implantation region 14 formed as described above is formed in terminal region 10 of the silicon carbide semiconductor device which is a power device, as shown in FIGS. 1 and 2, and has an FLR structure (hereinafter referred to as “FLR”). Structure 14 ”). As shown in FIGS. 1 and 2, the FLR structure 14 has a structure surrounding an effective region through which current flows. Therefore, one side of the substantially rectangular ring constituting the FLR structure 14 is on the order of millimeters (mm). Spans the length of the size.

  Therefore, as shown in FIGS. 6 and 7, the P-type impurity implantation region 14 is relatively deep and long, and the interval between the P-type impurity implantation regions 14 is relatively narrow. In the process of forming such a structure, an implantation mask that is relatively thin, thick, and includes a long line-shaped portion is required. As described later, the line-shaped portion of the implantation mask has a high aspect ratio of 3.33 or more.

  FIG. 40 is a cross-sectional view showing a state in which the formation of the resist pattern 13 used as an implantation mask in the prior art has been completed. In the prior art, as shown in FIG. 40, a resist pattern 13 is formed as an implantation mask. As described above, when the aspect ratio is as high as 3.33 or more, the resist pattern 13 is easily collapsed. If a fallen resist pattern is used, impurities cannot be implanted into a necessary region.

  For example, a resist pattern on a silicon carbide semiconductor substrate having a length of 2.0 mm or more, a resist film thickness dimension of 2.0 μm, and an aspect ratio of 3.33 or more (width 0.60 μm or less). The resist fell down.

  On the other hand, it has been confirmed that in resists having an aspect ratio of 2.71 or less, there is no resist collapse and a resist pattern can be formed with a structure with a margin against the collapse.

  Therefore, in this embodiment, the implantation mask 15 is composed of a lower layer mask 12 composed of an inorganic film 12 composed of at least one of an oxide film and a nitride film, and an upper layer mask 13 composed of a resist film 13.

  Since the lower layer mask 12 of the implantation mask 15 is composed of the inorganic film 12 which is at least one of the oxide film and the nitride film as described above, it does not fall down. Further, in the present embodiment, the aspect ratio of the resist film 13 constituting the upper mask 13 of the implantation mask 15 can be reduced as compared with the case where the implantation mask is formed only by the resist film as in the prior art.

  This makes it possible to prevent the implantation mask 15 including a relatively thin, thick, and long line-shaped portion from falling down if it is formed only from the resist film. Therefore, according to the present embodiment, in the structure having the P-type impurity implantation region 14 having a relatively long overall length, the structure in which the distance between the P-type impurity implantation regions 14 is narrower than that in the prior art and the impurity is implanted deeply. Can be formed.

FIG. 8 is a graph showing the relationship between implantation depth and implantation concentration. In FIG. 8, the implantation depth when aluminum (Al) is ion-implanted into the oxide film and the resist film under the conditions of acceleration energy of 700 keV and dose of 2.00 × 10 ¹³ cm ⁻² , and implantation at that time Concentration. In FIG. 8, the horizontal axis represents the implantation depth [μm], and the vertical axis represents the implantation concentration [cm ⁻³ ].

  In FIG. 8, the result of the resist film is indicated by the symbol “Δ” indicated by the reference symbol “31”, and the result of the oxide film is indicated by the symbol “◇” indicated by the reference symbol “33”. A broken line indicated by reference numeral “32” indicates a predicted value obtained by extrapolating the result of the resist film, and a broken line indicated by reference numeral “34” indicates a predicted value obtained by extrapolating the result of the oxide film.

  From FIG. 8, it can be seen that when the implantation mask is changed from a resist film to an oxide film, the oxide film can mask implantation impurities with a thickness dimension of about 64% of the thickness dimension of the resist film.

Specifically, from FIG. 8, the impurity concentration in the SiC epitaxial layer of the silicon carbide semiconductor device is n-type 5.00 × 10 ¹⁵ cm ⁻³ , 1% of which is 5.00 × 10 ¹³ cm ⁻³ . The penetration of Al, which is an implanted impurity, can be ignored. In this case, the thickness of the implantation mask when the acceleration energy is 700 keV requires 2.75 μm for the resist film and 1.75 μm for the oxide film.

Further, when the implantation mask is formed only of the resist film, the thickness dimension of the resist film is required to be 2.95 μm. From FIG. 8, this is a film thickness of 2.75 μm to 0.2 μm, which is the thickness dimension of the resist film (hereinafter also referred to as “film thickness”) when the penetration amount is 5.00 × 10 ¹³ cm ^−2. It is designed with a margin of thickness.

  FIG. 9 is a cross-sectional view showing a case where an implantation mask is formed using only the resist film 13. When the resist width w1 necessary for manufacturing the FLR structure is 0.7 μm and the resist film thickness t10 is 2.95 μm, the aspect ratio is 4.21. Since this aspect ratio is larger than 3.33, which is the aspect ratio at which the resist falls, the resist pattern 13 falls.

  In this embodiment, as shown in FIGS. 3 to 6, as the inorganic film 12, for example, an oxide film is deposited by 1.5 μm, and a resist film is formed on the oxide film at 0.98 μm. Perform patterning with the opening. If the remaining width of the resist is 0.7 μm, the aspect ratio is 1.40 and the resist will not fall down.

  When the etching selectivity ratio between the oxide film and the resist is 1: 5 and the oxide film etching is performed under the condition of 30% over-etching, that is, etching of 1.95 μm in total in terms of oxide film, the resist film thickness after etching Is 0.59 μm.

  In the implantation mask 15, the oxide film constituting the lower layer mask 12 is 1.5 μm, the resist film constituting the upper layer mask 13 is 0.59 μm, and converted to the resist film thickness as the implantation mask 15 is 2.95 μm. With this implantation mask 15, there is no penetration of implanted impurities when Al is implanted with an acceleration energy of 700 keV.

  As a result, it is possible to form a structure in which the implantation region is deeper, the entire length is longer, and the interval between the implantation regions is narrower than that of the prior art without tilting the implantation mask. Therefore, since the degree of freedom in structural design can be increased, for example, in the termination structure, it is possible to design a termination structure in which the electric field strength is further lowered and the electric field distribution is made uniform. Further, in the P-well described later, as many MOSFET parts as possible can be manufactured in a certain area so as to reduce energy loss during device operation.

  As described above, according to the method for manufacturing the silicon carbide semiconductor device of the present embodiment, at least the line-shaped portion of implantation mask 15 has a lower layer mask 12 made of at least one of an oxide film and a nitride film, and an upper layer made of a resist film. And a mask 13. Lower layer mask 12 is stacked on the surface portion on one side in the thickness direction of silicon carbide semiconductor substrate 11, and upper layer mask 13 is stacked on the surface portion on one side in the thickness direction of lower layer mask 12.

  Since the line-shaped portion has an aspect ratio of 3.33 or more, the line-shaped portion may fall to the surface portion side on one side in the thickness direction of the silicon carbide semiconductor substrate 11, but in the present embodiment, as described above, the oxide film and A lower layer mask 12 made of at least one of the nitride films and an upper layer mask 13 made of a resist film are formed. As a result, it is possible to make the line-shaped portion less likely to fall than when the entire line-shaped portion is made of a resist film.

  As a result, the shape of the implantation mask 15 formed in the implantation mask forming step can be maintained, and impurity ions can be implanted into the region to be implanted in the ion implantation step. Therefore, a structure that requires an implantation mask including a line-shaped portion having an aspect ratio of 3.33 or more, for example, a structure in which an impurity implantation region is relatively deep and has a long overall length and a relatively small interval between impurity implantation regions, It can be formed with high accuracy. Moreover, the silicon carbide semiconductor device having such a structure can be manufactured with high accuracy.

  Further, according to the method for manufacturing the silicon carbide semiconductor device of the present embodiment, it is possible to prevent the implantation mask 15 including the line-shaped portion having an aspect ratio of 3.33 or more from falling down for forming the FLR structure in the termination region. The shape of the implantation mask 15 can be maintained. As a result, the FLR structure can be formed with high accuracy. Therefore, a silicon carbide semiconductor device having an FLR structure in the termination region can be manufactured with high accuracy.

  In the present embodiment, the FLR structure at the end of the power device semiconductor device and the P-well of the semiconductor device MOSFET are given as examples of the structure having a deep implantation region, a narrow space between the implantation regions, and a long total length. However, the manufacturing method of the present embodiment can be applied when manufacturing a structure having a deep implantation region, a narrow space between the implantation regions, and a long total length.

  10 to 12 are cross-sectional views showing the relationship between the thickness dimension of the lower layer mask 12 and the thickness dimension of the upper layer mask 13. FIG. 10 shows a case where the thickness dimension t11 of the upper layer mask 13 and the thickness dimension t21 of the lower layer mask 12 are equal. FIG. 11 shows a case where the thickness dimension t12 of the upper layer mask 13 is larger than the thickness dimension t22 of the lower layer mask 12. FIG. 12 shows a case where the thickness dimension t13 of the upper layer mask 13 is smaller than the thickness dimension t23 of the lower layer mask 12.

  The thickness of the resist film constituting the upper layer mask 13 can be controlled relatively easily and without changing the processing time depending on the viscosity of the resist and the rotational speed during coating coating. On the other hand, as the inorganic film constituting the lower layer mask 12 becomes thicker, the growth time of the inorganic film and the time required for etching become longer.

  That is, the inorganic film constituting the lower layer mask 12 is composed of at least one of an oxide film and a nitride film, and is formed, for example, by depositing a material of the inorganic film, and therefore, compared with the upper layer mask 13 formed by applying a resist. Therefore, it takes time to form. In addition, since the inorganic film constituting the lower layer mask 12 is etched using the upper layer mask 13 as a mask after formation to become the lower layer mask, the larger the thickness dimension of the lower layer mask 12, the more the etching of the inorganic film constituting the lower layer mask 12 is performed. Takes time.

  Therefore, as shown in FIG. 11, the processing time of the inorganic film constituting the lower layer mask 12 can be shortened by making the thickness dimension t22 of the lower layer mask 12 smaller than the thickness dimension t12 of the upper layer mask 13. Specifically, the growth time of the inorganic film constituting the lower layer mask 12, that is, the time required for forming the inorganic film and the time required for etching the inorganic film can be shortened.

  As a specific example of the configuration of FIG. 11, for example, an oxide film is deposited as a lower layer mask 12 by 0.85 μm, and a resist film is formed on the oxide film as an upper layer mask 13 with a thickness of 1.84 μm. The resist film is patterned so as to open the implantation region. When the remaining width of the resist is 0.7 μm, the aspect ratio is 2.63. Since this aspect ratio is 2.71 or less, which is an aspect ratio of a resist having a margin against the collapse, the resist pattern does not fall and a resist pattern can be formed stably.

  When the etching selectivity between the oxide film and the resist is 1: 5, and the oxide film is etched under the condition of 30% overetching, the resist film thickness after the etching is 1.61 μm.

  The implantation mask is 0.85 μm for the lower oxide film and 1.61 μm for the upper resist, and 2.95 μm in terms of the resist film thickness as the implantation mask. In this implantation mask, the acceleration energy is 700 keV. In the implantation of Al, there is no penetration of Al as an implanted impurity.

  In this case, the thickness dimension of the oxide film can be reduced by 44% compared to the case where the thickness dimension of the oxide film is 1.5 μm and the thickness dimension of the resist film is 0.98 μm. This means that when an oxide film is formed by deposition, the growth time of the oxide film can be reduced by about 1 hour. Further, as the etching time, assuming 25 sheets per lot, the processing time of about 30 minutes can be reduced.

  In FIG. 12, the thickness dimension t13 of the upper layer mask 13 is made smaller than the thickness dimension t23 of the lower layer mask 12, as described above. In order to form a fine pattern, the thickness t13 of the resist film is desirably small.

  As shown in FIG. 12, the thickness dimension t13 of the upper layer mask 13 is made smaller than the thickness dimension t23 of the lower layer mask 12, so that the thickness dimension of the lower layer mask 12 is less than or equal to the thickness dimension of the upper layer mask 13. Thus, a thin implantation mask pattern can be formed. As a result, the degree of freedom in designing the termination structure such as the FLR structure and the P-well described later can be increased, so that the characteristics of the silicon carbide semiconductor manufacturing apparatus can be improved.

  As a specific example of the configuration of FIG. 12, for example, an oxide film is deposited as 1.80 μm as the lower mask 12, and a resist film is formed as a top mask 13 with a film thickness of 0.59 μm on the oxide film, The resist film is patterned so as to open the implantation region. When the remaining width of the resist is 0.7 μm, the aspect ratio is 0.84, so that the resist does not fall down. When the etching selectivity between the oxide film and the resist is 1: 5, and the oxide film is etched under the condition of 30% overetching, the resist film thickness after etching is 0.12 μm.

  The implantation mask has a lower oxide film of 1.80 μm and an upper resist of 0.12 μm, which is 2.95 μm in terms of the resist film thickness as the implantation mask. In this implantation mask, the acceleration energy is 700 keV. In the implantation of Al, there is no penetration of Al as an implanted impurity.

  Further, by reducing the thickness dimension of the resist film 13 to 0.59 μm, an implantation mask having a small remaining width that can be resolved with the thickness can be formed. In this case, it should be noted that the processing time such as the growth time and etching time of the inorganic film constituting the lower layer mask 12 becomes longer.

<Second Embodiment>
FIG. 13 is a plan view showing a state in which resist film 43 is formed in the manufacturing process by the method for manufacturing the silicon carbide semiconductor device of the second embodiment of the present invention. FIG. 14 is an enlarged plan view showing the opening 43c of FIG. 13 and 14 correspond to plan views of silicon carbide semiconductor substrate 41 as seen from one side in the thickness direction.

  13 and 14 show a case where the silicon carbide semiconductor device has an effective region in a part of the surface portion on one side in the thickness direction of silicon carbide semiconductor substrate 41, and includes a MOSFET as a semiconductor element in the effective region. In FIG. 13, the effective region corresponds to a portion of the resist film 43 where the effective region resist portion 43a is formed. Also in the present embodiment, as in the first embodiment, the effective region has a substantially rectangular shape, and is on the inner side of the outer peripheral edge portion of the surface portion on one side in the thickness direction of silicon carbide semiconductor substrate 41. It is formed.

  Also in the present embodiment, the silicon carbide semiconductor device has an FLR structure as a termination structure in a termination region surrounding the effective region. In FIG. 13, the termination region corresponds to a portion of the resist film 43 where the termination region resist portion 43b is formed. In FIG. 13, the description of the FLR structure is omitted. The FLR structure is formed in the same manner as the FLR structure in the first embodiment described above.

  That is, in the present embodiment, the silicon carbide semiconductor device has an FLR structure in the termination region, and includes a MOSFET as a semiconductor element in the effective region. A P-type impurity implantation region 44 is formed as a P-well of the MOSFET in a portion of the effective region exposed through the opening 43c of the effective region resist portion 43a.

  FIG. 15 to FIG. 17 are cross-sectional views showing a state in which each step in the MOSFET manufacturing process is completed. FIG. 15 is a cross-sectional view showing a state where the formation of the P-type impurity implantation region 44 is completed as a P-well. In the present embodiment, as shown in FIG. 15, an implantation mask is formed by including an inorganic film 42 as a lower layer mask and a resist film as an upper layer mask, and a P-well is formed using the implantation mask. .

  FIG. 16 is a cross-sectional view showing a state in which the formation of the P-well contact is completed. After removing the implantation mask, the source 45, the channel 46, and the contact and termination structure of the P-type high concentration region which is a P-well are formed. Thereafter, annealing for activating the implanted impurities is performed.

  FIG. 17 is a cross-sectional view showing a state where the formation of the gate wiring 47 and the electrode is completed. Next, as shown in FIG. 17, gate wiring 47, interlayer insulating film 48, source / P-well contact 49, front surface electrode 50 and back surface electrode 51 are formed. Thereby, a silicon carbide semiconductor device is manufactured.

  As shown in FIG. 13, one side of the P-well of the MOSFET has a structure having the same size as one side of the effective region through which current flows. Thus, one side of the P-well spans a length on the order of millimeters (mm), similar to the FLR structure. In the process of forming such a structure, an implantation mask that is relatively thin, thick, and includes a long line-shaped portion is required. As described later, the line-shaped portion of the implantation mask has a high aspect ratio of 3.33 or more.

  FIG. 41 is a cross-sectional view showing a state where the formation of a resist pattern 43 used as an implantation mask in the prior art is completed. In the prior art, as shown in FIG. 41, a resist pattern 43 is formed as an implantation mask. As described above, the resist pattern 43 tends to fall when the aspect ratio is as high as 3.33 or more. If a fallen resist pattern is used, impurities cannot be implanted into a necessary region.

  Therefore, in the present embodiment, as shown in FIG. 15, the implantation mask is composed of a lower layer mask 42 composed of the inorganic film 12 composed of at least one of an oxide film and a nitride film, and an upper layer mask 43 composed of the resist film 43. It consists of.

  As a result, it is possible to prevent the implantation mask including the line-shaped portion having an aspect ratio of 3.33 or more from forming a P-well constituting the MOSFET, and to maintain the shape of the implantation mask. Therefore, since the P-well can be formed with high accuracy, a silicon carbide semiconductor device including a MOSFET configured with the P-well can be manufactured with high accuracy.

<Third Embodiment>
18 to 20 are cross-sectional views showing the states of the respective manufacturing steps in the method for manufacturing the silicon carbide semiconductor device according to the third embodiment of the present invention. 18 (a), 19 (a) and 20 (a) show the FLR structure 10 in the termination region, and FIGS. 18 (b), 19 (b) and 20 (b) show high concentrations. An area part 60 is shown.

  In the method for manufacturing a silicon carbide semiconductor device, when the P-type high concentration region is manufactured, the crystallinity is not recovered during the activation annealing unless the substrate temperature is raised to about 200 ° C. A mold high concentration region cannot be formed. Moreover, since the temperature is so high, a resist mask cannot be used. Therefore, in the manufacture of the P-type high concentration region, it is necessary to use a hard mask made of an inorganic film such as an oxide film and a nitride film as an implantation mask. The inorganic film is, for example, a deposited film. The hard mask corresponds to a P-type region mask.

  In this embodiment, the hard mask 12 used in manufacturing the P-type high concentration region 61 shown in FIG. 18 is left as it is and used as a lower layer mask of an implantation mask used in a subsequent ion implantation process.

  Specifically, as in the first embodiment described above, as shown in FIG. 19, a resist film 13 is formed on the hard mask 12 as a resist pattern having an implantation region opened. Further, as shown in FIG. 20, etching having anisotropy such as dry etching is performed. Next, impurities are implanted by ion implantation to form a P-type impurity region 14. Thereafter, the resist film 13 and the hard mask 12 constituting the lower layer mask are removed.

  The method of the present embodiment can also be applied when forming a P-well. FIGS. 21 to 23 are cross-sectional views showing the states of the respective manufacturing steps in the method for manufacturing the silicon carbide semiconductor device according to the third embodiment of the present invention.

  As shown in FIG. 21, after the P-type high concentration implantation region 61 is formed, a resist film 43 is formed as shown in FIG. Next, as shown in FIG. 23, patterning is performed by anisotropic etching to form an implantation mask. Next, ion implantation is performed to form a P-well 62.

  Conventionally, the hard mask 12 used to form the P-type high concentration region 61 is removed after the P-type high concentration region 61 is formed. In the present embodiment, the hard mask 12 is not removed after the P-type high concentration region 61 is formed, but is used as the lower layer mask 12 in the first embodiment. As a result, the step of forming the inorganic film to be the lower layer mask 12 implemented in the first embodiment can be omitted.

  That is, in the present embodiment, the hard mask 12 which is a P-type region mask used when forming the P-type high concentration region 61 is used as a lower layer mask, so that the step of forming the lower layer mask can be omitted. .

  Here, since the resist film is formed on the surface of the region where the high concentration region is formed, but the deposited film is removed, the implanted impurities penetrate the resist. It should be noted that depending on the design of the upper and lower layers of the implantation mask, impurities are implanted in the high concentration region or outside the high concentration region.

  In the case where the penetration of the implanted impurities remains in the high concentration region, there is no effect if the implantation is performed at a low concentration such as the FLR structure and the MOSFET or the P-well of the MPS (Merged Pin / Schottky) diode. When the implanted impurity penetrates deeply outside the high concentration region, it is necessary to design the structure in consideration of the influence on the device. Here, the MPS diode refers to an MPS diode in which Schottky barrier diodes and PIN diodes are alternately arranged and connected in parallel.

As a specific example in the case of forming the FLR structure of FIGS. 18 to 20, first, an oxide film is deposited at 1.00 μm, patterning is performed, and a P-type high concentration implantation region is formed by implantation. The implantation conditions were such that the implanted impurity was Al, the acceleration energy was 200 keV, and the dose was 5.00 × 10 ¹⁵ cm ⁻² .

Next, patterning was performed in which an implantation region was opened with a resist of 1.76 μm on the oxide film. When the remaining width of the resist is 0.7 μm, the aspect ratio is 2.51, and the resist does not fall down. When the oxide film etching is performed under the condition that the etching selectivity ratio between the oxide film and the resist is 1: 5 and overetching is performed at 30%, the resist film thickness after the etching is 1.50 μm. After etching the oxide film, Al was implanted under the implantation conditions of acceleration energy of 600 keV and dose amount of 2.00 × 10 ¹³ cm ⁻² to form an FLR structure.

FIG. 24 is a graph showing the relationship between implantation depth and implantation concentration. In FIG. 24, the implantation depth and the implantation concentration at the time when Al is ion-implanted into the oxide film and the resist film under the conditions of acceleration energy of 600 keV and dose amount of 2.00 × 10 ¹³ cm ⁻² are shown. Show. In FIG. 24, the horizontal axis represents the implantation depth [μm], and the vertical axis represents the implantation concentration [cm ⁻³ ].

  In FIG. 24, the result of the resist film is indicated by the symbol “□” indicated by the reference symbol “71”, and the result of the oxide film is indicated by the symbol “Δ” indicated by the reference symbol “73”. A broken line indicated by reference numeral “72” indicates a predicted value obtained by extrapolating the result of the resist film, and a broken line indicated by reference numeral “74” indicates a predicted value obtained by extrapolating the result of the oxide film.

Silicon carbide semiconductor substrate 11 constituting the silicon carbide semiconductor device includes, for example, a base substrate and a silicon carbide (SiC) epitaxial layer formed on the base substrate. The n-type impurity concentration in the SiC epitaxial layer of silicon carbide semiconductor substrate 11 is set to 5.00 × 10 ¹⁵ cm ^−3, and the penetration of Al, which is 1% of the implanted impurity of 5.00 × 10 ¹³ cm ⁻³ , is ignored. If possible, as shown in FIG. 24, the resist film needs to have a thickness of 2.55 μm and the oxide film needs to have a thickness of 1.55 μm as an implantation mask when the acceleration energy is 600 keV. I understand.

Further, when the implantation mask is formed of only a resist film, the thickness of the resist film needs to be 2.75 μm. FIG. 24 shows a design in which a margin of a film thickness of 0.2 μm is added from a resist film thickness of 2.55 μm when the penetration amount is 5.00 × 10 ¹³ cm ^−2. is there.

  The implantation mask has a lower oxide film thickness of 1.00 μm and an upper resist film thickness of 1.50 μm. In terms of the resist film thickness as an implantation mask, it is 3.15 μm, which is thicker than 2.75 μm. Therefore, in this implantation mask, when Al is implanted under the condition that the acceleration energy is 600 keV, there is no penetration of Al as an implantation impurity.

FIG. 25 is a graph showing the relationship between implantation depth and implantation concentration. In FIG. 25, an impurity implanted into silicon carbide by ion implantation under conditions of implantation of a P-type high concentration region, that is, an implanted impurity of Al, an acceleration energy of 200 keV, and a dose of 5.00 × 10 ¹⁵ cm ^−2. And a FLR structure implantation condition, that is, a resist having a film thickness of 1.5 μm by ion implantation under conditions of implantation of Al, an implantation impurity of 600 keV, and a dose of 2.00 × 10 ¹³ cm ^−2. 2 shows the depth distribution of impurities penetrating from the film and implanted into silicon carbide. In FIG. 25, the horizontal axis represents the implantation depth [μm], and the vertical axis represents the implantation concentration [cm ⁻³ ].

  In FIG. 25, the result of implantation under the implantation conditions of the P-type high concentration region is indicated by the symbol “Δ” indicated by the reference symbol “75”, and the FLR structure is indicated by the symbol “◯” indicated by the reference symbol “77”. The result when inject | pouring on injection | pouring conditions is shown. A broken line indicated by a reference sign “76” indicates a predicted value obtained by extrapolating a result when the injection is performed under the injection condition of the P-type high concentration region, and a broken line indicated by a reference sign “78” indicates an injection condition of the FLR structure The estimated value which extrapolated the result at the time of injecting by is shown.

  25, when the FLR structure is manufactured, the surface of the region where the P-type high-concentration region is formed is only the resist, and there is no underlying oxide film. If it is 50 μm or more, it can be seen that it is almost within the P-type high concentration region. From this, it can be seen that even if the FLR structure is manufactured according to this embodiment in the design of this example, it can be manufactured without affecting the device.

Here, if the penetration of Al, which is an implanted impurity of 5.00 × 10 ¹³ cm ⁻³ , is negligible, it can be seen from FIG. 25 that Al has an acceleration energy of 200 keV and a dose of 5.00 × 10 ¹⁵ cm ^{−. The} implantation depth for silicon carbide when implanted under the condition ² is 0.44 μm. Further, when Al is implanted under the conditions of an acceleration energy of 700 keV and a dose of 2.00 × 10 ¹³ cm ⁻² , Al silicon carbide, which is an implanted impurity that penetrates from a resist film having a thickness of 1.5 μm. The depth of implantation with respect to is 0.38 μm.

  Although the case where the FLR structure shown in FIGS. 18 to 20 is formed has been described above, the case where the P-well structure shown in FIGS. 21 to 23 is formed can be formed under the same conditions as described above. is there.

  26 to 29 are cross-sectional views showing the state of each step in the manufacturing process of the MPS when the method of the second embodiment is applied to the FLR structure. 26 (a), 27 (a), 28 (a), and 29 (a) show the FLR structure 10 in the termination region, and FIG. 26 (b), FIG. 27 (b), FIG. FIG. 29B and FIG. 29B show the high concentration region portion 60.

  After forming the P-type high concentration implantation region 61 as shown in FIG. 26, as shown in FIGS. 27 and 28, the implantation mask patterns 12 and 13 having the FLR structure are formed using the method of the present embodiment. To do. Next, ion implantation for manufacturing the FLR structure is performed to form a P-type impurity implantation region 14.

  Thereafter, annealing for activating the implantation layer, that is, the P-type high concentration implantation region 61 and the P-type impurity implantation region 14 is performed. Next, as shown in FIG. 29, a Schottky electrode 63, a surface electrode 50, and a protective film 64 are formed on the surface. The surface electrode 50 is exposed through the opening 64 a of the protective film 64. Next, the back electrode 51 is formed on the back surface.

  As described above, according to the present embodiment, the FLR structure formed in the termination region and the P-well constituting at least one of the MOSFET and the MPS diode formed in the effective region are formed in the same implantation mask forming step and It can be formed by an ion implantation process.

  30 to 32 are cross-sectional views showing the states of the respective steps in the modification of the third embodiment of the present invention. 30 to 32, the opening of the pattern for forming the FLR structure and the opening of the pattern for forming the P-well are performed on the implantation mask at the same time. 30 (a), 31 (a) and 32 (a) show the termination region 10, and FIGS. 30 (b), 31 (b) and 32 (b) show the high concentration region portion 60. Show.

  As shown in FIG. 30, after the P-type high concentration implantation region 61 is formed, a resist film 13 is formed as shown in FIG. In the high concentration region portion 60, a resist film 43A corresponding to the resist film 43 shown in FIG. Next, as shown in FIG. 32, the lower mask 12 is etched by anisotropic etching to form an implantation mask. Thereafter, ion implantation is performed to form the P-type impurity implantation region 14 and the P-well 62.

  According to this modification, the P-well can be formed simultaneously with the formation of the FLR structure. The termination region 10 and the high-concentration region 60 have the design restriction that the concentration of the implanted impurity and the depth of the implanted region are the same, but there is an advantage that the patterning and implantation can be omitted.

<Fourth embodiment>
33 to 36 are cross sectional views showing states of the respective manufacturing steps in the method for manufacturing the silicon carbide semiconductor device according to the fourth embodiment of the present invention. 33 (a), FIG. 34 (a), FIG. 35 (a) and FIG. 36 (a) show the FLR structure 10 in the termination region, and FIG. 33 (b), FIG. 34 (b), FIG. FIG. 36B and FIG. 36B show the high concentration region portion 60.

  In the present embodiment, the silicon carbide semiconductor device includes a MOSFET as a semiconductor element in the effective region. In the same manner as in the third embodiment described above, as shown in FIG. 33, a P-type high concentration region 61 and a P-type impurity implantation region 14 constituting an FLR structure as a termination structure are formed.

  Next, as shown in FIG. 34, a resist film 43 for forming a P-well is formed, and the resist film 43 is patterned. Next, the inorganic film 12 is etched to form a lower layer mask 42A. Next, ion implantation is performed to form a P-well 62. Thereafter, the resist film 43 is removed.

  Next, as shown in FIG. 35, the sidewall 81 is formed so as to contact the side surface of the lower layer mask 12 with respect to the remaining lower layer mask 12. Next, as shown in FIG. 36, after a resist film 82 is formed, patterning for forming the source of the MOSFET is performed, and the P-type high concentration region 6 is masked. Next, ion implantation is performed to form the source 83.

  When the P-well and the source are formed using the resist pattern, the overlay shift of about 0.2 μm occurs between the P-well and the source although the mark is superimposed by the exposure apparatus. As a result, the channel length of one MOSFET is short and the channel length of the other MOSFET is long.

  For example, if the channel length is designed to be about 0.7 μm, MOSFETs having different characteristics such as channel lengths of 0.9 μm and 0.5 μm, respectively, are generated when the overlay deviation is 0.2 μm. Is formed in the silicon carbide semiconductor device. If MOSFETs having different characteristics are present in the power device semiconductor device, it is impossible to allow a current to flow uniformly in the semiconductor device, which affects the current tolerance with respect to short-circuit tolerance.

  On the other hand, in this embodiment, the source is formed by attaching the sidewall 81 to the inorganic film 12 constituting the implantation mask used in the manufacture of the P-well. As a result, the channel lengths of the MOSFETs can be made equal, and the influence on the current withstand capability can be suppressed.

  In the present embodiment, the P-type high concentration region 61, the P-type impurity implantation region 14 constituting the FLR structure, and the inorganic film used as the lower layer mask 12 when forming the P-well are formed by forming the source. It is used for. Thereby, formation of the inorganic film before attaching the sidewall can be omitted.

  As a specific example of the present embodiment, an oxide film is deposited as a lower layer mask 12 by 1.0 μm to form a P-type high concentration implantation region 61, and then a resist film 13 is formed on the oxide film to a 1.76 μm film. The resist film 13 is patterned to have a thickness and to be opened at a portion corresponding to the P-type impurity implantation region 14 constituting the FLR structure.

  Thus, when the thickness dimension of the resist film 13 is 1.76 μm, as described in the third embodiment, the resist film collapses when the remaining width of the resist film 13 is 0.7 μm. In contrast, the implanted impurity does not penetrate through the formed implantation mask at an acceleration energy of 600 keV.

  Similarly, in order to form the P-well 62, the resist film is patterned and opened, and after removing the inorganic film constituting the lower layer mask 12 by etching, implantation is performed to remove the resist film.

  Thereafter, a deposited film as the lower layer mask 12 is grown and etched back to form the sidewall 81. Regions that do not require implantation, such as the P-type high concentration region 61 and the P-type impurity implantation region 14 constituting the FLR structure, are masked with a resist film 43, and implantation for forming a source is performed. Thus, a silicon carbide semiconductor device including power device MOSFETs having the same channel length in the semiconductor device can be manufactured.

  37 to 39 are cross-sectional views showing the states of the respective steps in the modification of the fourth embodiment of the present invention. 37 to 39, with respect to the implantation mask, a pattern opening for forming a P-well is formed simultaneously with the opening of the pattern for forming the FLR structure. FIGS. 37A, 38A, and 39A show the termination region 10, and FIGS. 37B, 38B, and 39B show the high-concentration region portion 60. FIG. Show.

  As shown in FIG. 37, after the P-type high concentration implantation region 61 and the P-type impurity implantation region 14 are formed, sidewalls 81 are formed as shown in FIG. Next, as shown in FIG. 39, a resist film 82 is formed. Thereafter, ion implantation is performed to form the source 83.

  According to this modification, since the P-well 62 is formed simultaneously with the formation of the FLR structure, the concentration of the implanted impurity and the depth of the implanted region are the same in the termination region 10 and the high concentration region 60. Although there are design constraints, there is an advantage that patterning and implantation can be omitted.

  As described above, according to the present embodiment, the inorganic film 12 used as the P-type region mask when forming the P-type high concentration region 61 includes the P-type impurity implanted region 14 and the P− It is used as a lower layer mask of an implantation mask for forming the well 62. Further, a sidewall 81 is formed in contact with the inorganic film 12 which is a lower layer mask, and is used as a mask for forming the source 83 together with the resist film 82 used as a source mask, and impurity ions are implanted. As a result, a MOSFET channel 61 is formed in a portion of the P-well 62 covered with the source mask, and a source 83 is formed on the side of the channel 61.

  That is, in this embodiment, the channel of the MOSFET can be formed by self-alignment using the inorganic film 12 used as the P-type region mask when forming the P-type high concentration region 61. Therefore, the step of forming a mask for forming a MOSFET channel by self-alignment can be omitted.

  In each of the embodiments described above, the aspect ratio of the line-shaped portion of the implantation mask is 3.33 or more. The upper limit value of the aspect ratio is not particularly limited, and is appropriately selected according to the size of the implantation region to be formed. In this case, it is about 6.00. If the aspect ratio of the line-shaped portion is 3.33 or more and 6.00 or less, the implantation region can be formed with high accuracy in each of the above-described embodiments.

  The present invention can be freely combined with each embodiment within the scope of the invention. In addition, any component in each embodiment can be changed or omitted as appropriate.

  10 termination region, 11, 41 silicon carbide semiconductor substrate, 12, 42 inorganic film, 13, 43, 43A, 82 resist film, 13a, 43a resist region for effective region, 13b, 43b resist region for termination region, 14, 44 P Type impurity implantation region, 14a first implantation region, 14b second implantation region, 14c third implantation region, 14d fourth implantation region, 15 implantation mask, 21-24 resist portion, 42A lower layer mask, 43c opening portion, 45 source, 46 channel, 47 gate wiring, 48 interlayer insulating film, 49 source / P-well contact, 50 surface electrode, 51 back electrode, 60 high concentration region, 61 P type high concentration region, 62 P-well, 63 Schottky electrode , 64 protective film, 81 sidewall.

Claims (7)

A method of manufacturing a silicon carbide semiconductor device having an effective region in a part of a surface portion on one side in the thickness direction of a silicon carbide semiconductor substrate, and comprising a semiconductor element in the effective region,
An implantation mask forming step of exposing a predetermined implantation planned region of the surface portion on one side in the thickness direction of the silicon carbide semiconductor substrate and forming an implantation mask covering the remaining region excluding the implantation planned region;
An ion implantation step of forming an impurity implantation region by implanting impurity ions into the implantation planned region exposed without being covered with the implantation mask,
The implantation mask is
Including a line-shaped portion extending in a line shape in the extending direction which is a direction parallel to the surface portion on one side of the thickness direction of the silicon carbide semiconductor substrate;
The line-shaped part is
A dimension in a direction perpendicular to the extending direction and parallel to a surface portion on one side in the thickness direction of the silicon carbide semiconductor substrate is defined as a width, and the direction perpendicular to the extending direction and the silicon carbide semiconductor substrate When the dimension in the direction perpendicular to the surface portion on one side of the thickness direction is height, the aspect ratio that is the ratio of the height to the width is 3.33 or more,
In the implantation mask forming step,
At least the line-shaped portion of the implantation mask is laminated on a surface portion on one side in the thickness direction of the silicon carbide semiconductor substrate, and a lower layer mask made of at least one of an oxide film and a nitride film, and one side in the thickness direction of the lower layer mask And a top layer mask made of a resist film.   2. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein a dimension in a thickness direction of the lower layer mask is smaller than a dimension in a thickness direction of the upper layer mask. In the ion implantation step, a plurality of the impurity implantation regions are formed as termination region implantation regions in a termination region surrounding the effective region,
A plurality of the impurity implantation regions formed as the termination region implantation regions are formed in an annular shape so as to surround the effective region and are separated from each other to form a field limiting ring structure. A method for manufacturing a silicon carbide semiconductor device according to claim 1 or 2. The semiconductor element includes a metal-oxide film-semiconductor field effect transistor,
4. The ion implantation process according to claim 1, wherein a plurality of the impurity implantation regions are formed in the effective region as P-wells constituting the metal-oxide film-semiconductor field effect transistor. The manufacturing method of the silicon carbide semiconductor device as described in any one of these. The semiconductor element includes at least one of a metal-oxide film-semiconductor field-effect transistor and an MPS (Merged Pin / Schottky) diode in which Schottky barrier diodes and PIN diodes are alternately arranged and connected in parallel. ,
The semiconductor element has a P-type high concentration region containing a P-type impurity at a higher concentration in a part of the effective region than in other portions,
Before the implantation mask forming step,
Among the effective regions, P comprising at least one of an oxide film and a nitride film is exposed so as to expose a P-type forming portion in which the P-type high concentration region is formed and cover the remaining portion excluding the P-type forming portion. A P-type region mask forming step of forming a mold region mask;
A P-type region forming step of forming the P-type high-concentration region by implanting P-type impurity ions into the P-type forming portion exposed without being covered with the P-type region mask;
In the implantation mask forming step, the P-type region mask is used as the lower layer mask, and an upper layer mask made of the resist film is formed on the surface portion on one side in the thickness direction of the mold region mask. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein a mask is formed. In the ion implantation step,
A plurality of the impurity implantation regions are formed as termination region implantation regions in the termination region surrounding the effective region, and a plurality of the impurity implantation regions are formed as P-wells in the effective region,
The plurality of impurity implantation regions formed as the termination region implantation region are formed in an annular shape so as to surround the effective region, and form a field limiting ring structure,
6. The plurality of impurity implantation regions formed as the P-well constitute at least one of the metal-oxide-semiconductor field effect transistor and the MPS diode. A method for manufacturing a silicon carbide semiconductor device. After the ion implantation step,
A sidewall forming step of forming a sidewall in contact with a side surface of the lower layer mask and covering a part of the P-well;
A source mask forming step of exposing a predetermined source forming portion of the P-well and forming a source mask covering a remaining portion excluding the source forming portion;
A source region is formed by implanting impurity ions into a portion of the surface portion on one side in the thickness direction of the silicon carbide semiconductor substrate that is exposed without being covered with the lower layer mask, the sidewall, and the source mask. A method for manufacturing a silicon carbide semiconductor device according to claim 6, further comprising: a source region forming step.

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