JP2014149458A - Method for designing photomask, and method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a photomask excellent in manufacturing stability of a semiconductor device.SOLUTION: A method for designing a photomask includes the steps of: reading out layout data for a mask pattern; extracting at least two hole patterns HP1 which are arrayed in a first direction and are separated from each other so as to have a space of a reference value or less, out of the layout data; and moving at least one of the at least two hole patterns HP1 in a second direction perpendicular to the first direction, and thereby arranging the at least two hole patterns HP1 so that the hole patterns are alternately positioned in the second direction.

Description

  The present invention relates to a photomask design method and a semiconductor device manufacturing method, and is a technique applicable to, for example, a photomask design method having a hole pattern and a semiconductor device manufacturing method using the same.

  In manufacturing a semiconductor device, patterning is performed by a lithography process using, for example, a photomask. Examples of techniques relating to such a photomask include those described in Patent Documents 1 to 4 and Non-Patent Document 1.

  Patent Document 1 and Non-Patent Document 1 propose a technique related to OPC (Optical Proximity Correction). Patent Documents 2 to 4 describe techniques related to a photomask for forming a hole pattern.

JP 2002-543470 JP 2011-44721 A Japanese Patent Laid-Open No. 11-102060 JP 2002-31883 A

Nick Cobb et al., Fast low complexity mask design, SPIE Symposium on Microlithography, USA, 1995, Vol. 2440, p.313-327

A photomask used for manufacturing a semiconductor device may have a plurality of hole patterns corresponding to a plurality of holes arranged in a row. The interval between these hole patterns has become shorter with the miniaturization of semiconductor devices. When adjacent hole patterns are close to each other, the shape of the hole formed corresponding to the hole pattern tends to be deformed so as to extend toward the adjacent hole, as compared with the shape of the hole pattern. For this reason, when forming a plurality of holes corresponding to the hole patterns arranged in a row, there is a possibility that a short circuit may occur between adjacent holes.
Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  According to an embodiment, at least two hole patterns arranged in the first direction and spaced apart from each other so as to have an interval equal to or smaller than a reference value are extracted from the layout data for the mask pattern. Then, by moving at least one of the extracted hole patterns in the second direction orthogonal to the first direction, the extracted hole patterns are arranged so that the positions in the second direction are staggered.

  According to the one embodiment, it is possible to provide a photomask excellent in manufacturing stability of a semiconductor device.

It is a top view which shows the structure of the photomask which concerns on this embodiment. It is a figure which shows the design method of the photomask shown in FIG. It is a figure for demonstrating the manufacturing method of the semiconductor device which concerns on this embodiment. It is a graph which shows the relationship between the movement amount of a hole pattern, and the movement amount of a hole. It is a graph which shows ratio of the movement amount of a hole with respect to the movement amount of a hole pattern. It is a graph which shows the relationship between the movement amount of a hole pattern, and the space | interval of two adjacent holes formed in the resist film. It is a graph which shows the relationship between the movement amount of a hole pattern, and the margin of an exposure amount. It is sectional drawing which shows the structure of the semiconductor device which concerns on this embodiment.

  Hereinafter, embodiments will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

FIG. 1 is a plan view showing a configuration of a photomask PM1 according to the present embodiment. FIG. 2 is a diagram showing a design method of the photomask PM1 shown in FIG.
The design method of the photomask PM1 according to this embodiment is performed as follows. First, layout data for a mask pattern is read. Next, at least two hole patterns HP1 arranged in the first direction and separated from each other so as to have an interval equal to or less than the reference value are extracted from the layout data. Next, by moving at least one of the extracted at least two hole patterns HP1 in the second direction orthogonal to the first direction, the extracted at least two hole patterns HP1 are positioned in the second direction. Are arranged in a staggered manner.

  According to the present embodiment, at least two hole patterns HP1 arranged in the first direction and spaced apart from each other so as to have an interval equal to or less than the reference value are alternately arranged in the second direction orthogonal to the first direction. To be placed. For this reason, with respect to at least two hole patterns HP1 arranged in a row, the interval between two adjacent hole patterns HP1 can be increased. Thereby, when forming the some hole corresponding to the hole pattern arrange | positioned in a line, it can suppress that a short circuit arises between adjacent holes. Therefore, it is possible to provide a photomask with excellent manufacturing stability of the semiconductor device.

  Hereinafter, the configuration of the photomask PM1, the design method of the photomask PM1, the configuration of the semiconductor device SM1, and the manufacturing method of the semiconductor device SM1 according to the present embodiment will be described in detail.

First, the configuration of the photomask PM1 will be described.
As shown in FIG. 1, a plurality of hole patterns HP1 are formed in the photomask PM1. In the present embodiment, at least two hole patterns HP1 are formed on the photomask PM1. The hole patterns HP1 are arranged in the first direction, for example. In FIG. 1, the X-axis direction in the drawing is the first direction. In the example shown in FIG. 1, a plurality of hole patterns HP1 are arranged in the X-axis direction in the drawing.
Note that a circuit pattern including, for example, a hole pattern and a wiring pattern is formed on the photomask PM1. The plurality of hole patterns HP1 are formed as a part of this circuit pattern, for example.

The photomask PM1 is used as a mask for patterning a photosensitive film by a lithography process including exposure and development.
The hole pattern HP1 is a pattern corresponding to, for example, a contact hole or a via hole constituting the semiconductor device SM1. In this case, after patterning a photosensitive resist film by a photolithography process using the photomask PM1, the insulating film is etched using the resist film as a mask, whereby contact holes or via holes corresponding to the hole pattern HP1 are formed in the insulating film. Will be formed. The contact hole is, for example, a hole for embedding a contact connected to a source / drain region or a gate wiring. The via hole is, for example, a hole for burying a via that connects wiring layers.

The plurality of hole patterns HP1 are arranged so that the positions in the second direction orthogonal to the first direction are staggered. Here, in the photomask PM1 plane formed in a flat plate shape, the direction orthogonal to the first direction is the second direction. In FIG. 1, the Y-axis direction in the drawing is the second direction. In the example shown in FIG. 1, the plurality of hole patterns HP1 are arranged so that the positions in the Y-axis direction in the drawing are staggered.
In the present embodiment, by moving at least one hole pattern HP1 along the second direction from the initial position stored in the mask pattern layout data (hereinafter also simply referred to as the initial position), a plurality of holes are obtained. The patterns HP1 are arranged so that the positions in the second direction are staggered. In FIG. 1, the position indicated by the dotted line is, for example, the initial position of the hole pattern HP1. At this time, the plurality of hole patterns HP1 arranged at the initial position are all arranged at the same position in the second direction, for example.

In FIG. 1, the positions of the plurality of hole patterns HP1 in the second direction are staggered by alternately giving movement to one side and movement to the other side in the second direction to the plurality of hole patterns HP1. The case where it arrange | positions to is illustrated. Further, by giving every other movement to one side in the second direction with respect to the plurality of hole patterns HP1, the plurality of hole patterns HP1 may be arranged so that the positions in the second direction are staggered. .
In FIG. 1, one side in the second direction is either the upper side or the lower side in FIG. 1, and the other side in the second direction is either the upper side or the lower side in FIG. Hereinafter, the same applies to the present embodiment.

In the example shown in FIG. 1, for a plurality of hole patterns HP1 arranged at the initial position, the center distance (pattern pitch) between two adjacent hole patterns HP1 is P. The movement amount of each hole pattern HP1 from the initial position is S / 2. In this case, the distance between the centers of two adjacent hole patterns HP1 after moving the hole pattern HP1 from the initial position is √ (P ² + S ² ). Thus, by arranging the hole patterns HP1 so that the positions in the second direction are staggered, the center-to-center distance of the hole patterns HP1 can be increased compared to the case where the hole patterns HP1 are arranged at the initial positions. I understand. For this reason, according to the present embodiment, when a plurality of holes corresponding to the hole pattern HP1 arranged in a row is formed, it is possible to suppress a short circuit from occurring between adjacent holes.

Next, a method for designing the photomask PM1 will be described.
First, layout data for a mask pattern is read. The mask pattern layout data is layout data of a circuit pattern formed on the photomask PM1.
As shown in FIG. 2A, the circuit pattern included in the mask pattern layout data includes at least two hole patterns HP1 arranged in the first direction and spaced apart from each other so as to have an interval equal to or smaller than a reference value. It is out.

Next, at least two hole patterns HP1 arranged in the first direction and spaced apart from each other so as to have an interval equal to or smaller than the reference value are extracted from the layout data for the mask pattern. The number of hole patterns HP1 is not particularly limited, and any number of three or more hole patterns HP1 may be extracted in this step. Also in this case, the plurality of hole patterns HP1 are arranged in the first direction and are provided apart from each other so as to have an interval equal to or smaller than the reference value.
The extracted hole pattern HP1 is arranged at the initial position stored in the layout data. At the initial position of the layout data, the plurality of hole patterns HP1 are arranged in the first direction, for example, and are all arranged at the same position in the second direction.
The layout data may include a hole pattern other than the hole pattern HP1. In this case, a part of the plurality of hole patterns that are arranged in the first direction and spaced apart from each other so as to have an interval equal to or less than the reference value is extracted as the hole pattern HP1.

In the present embodiment, the reference value can be set to 0.5 × λ / NA or more and 2 × λ / NA or less using, for example, the wavelength λ of exposure light and the numerical aperture NA of the lens.
The deformation of the holes due to the proximity between the adjacent hole patterns HP1 can be particularly noticeable when the interval between the adjacent hole patterns HP1 is near the resolution limit. By applying the photomask PM1 design method according to the present embodiment to the hole pattern HP1 having an interval equal to or smaller than a reference value determined within the above range, the hole pattern HP1 arranged at intervals near the resolution limit can be efficiently obtained. Can be extracted, and movement correction can be applied to this. Therefore, the deformation of the hole due to the proximity between the adjacent hole patterns HP1 can be efficiently and reliably suppressed. The reference value is not particularly limited and can be appropriately selected depending on the resolution of the lithography apparatus.

  In the example shown in FIG. 2A, two hole patterns HP2 are provided so as to sandwich the hole patterns HP1 arranged in the first direction. In this case, out of a plurality of hole patterns arranged in the first direction, two located at both ends are extracted as hole patterns HP2, and those sandwiched between the two hole patterns HP2 are extracted as hole patterns HP1. Become. In FIG. 2A, among the plurality of hole patterns arranged in the first direction, the one located in the region surrounded by the broken line is the hole pattern HP1. Further, a hole pattern HP2 is located outside the area surrounded by the broken line so as to sandwich the hole pattern HP1.

Next, the data is divided for the plurality of extracted hole patterns HP1. Here, the plurality of hole patterns HP1 are divided into a hole pattern HP11 and a hole pattern HP12. At this time, the data of the hole pattern HP1 is divided so that the hole pattern HP11 and the hole pattern HP12 are alternately arranged.
In the example shown in FIG. 2B, the plurality of hole patterns HP1 are divided into, for example, a hole pattern HP11 that moves to one side in the second direction and a hole pattern HP12 that moves to the other side. In FIG. 2, one side in the second direction is either the upper side or the lower side in FIG. 2, and the other side in the second direction is either the upper side or the lower side in FIG. Hereinafter, the same applies to the present embodiment.

  Next, by moving at least one of the at least two hole patterns HP1 in the second direction, the at least two hole patterns HP1 are arranged so that the positions in the second direction are staggered. In this case, all the hole patterns HP1 adjacent to the arbitrarily selected one hole pattern HP1 are shifted from the one hole pattern HP1 on the same side in the second direction.

In the present embodiment, for example, at least one of the hole pattern HP11 and the hole pattern HP12 is moved. Thereby, the plurality of hole patterns HP1 are arranged so that the positions in the second direction are staggered.
In the example shown in FIG. 2C, the hole pattern HP11 of the hole pattern HP1 is moved to one side in the second direction, and the hole pattern HP12 is moved to the other side in the second direction. In this case, adjacent hole patterns HP1 move to opposite sides in the second direction. In FIG. 2C, the initial position of the hole pattern HP1 stored in the layout data for the mask pattern, that is, the position of the hole pattern HP1 before movement is indicated by a dotted line.

In the example shown in FIG. 2C, for a plurality of hole patterns HP1 arranged at the initial position, the distance between the centers (pattern pitch) of two adjacent hole patterns HP1 is P. Further, the movement amount of the hole pattern HP1 from the initial position is S / 2. In this case, the distance between the centers of two adjacent hole patterns HP1 after moving the hole pattern HP1 from the initial position is √ (P ² + S ² ). Therefore, it can be seen that by disposing the hole patterns HP1 so that the positions in the second direction are staggered, the distance between the centers of the hole patterns HP1 can be increased compared to the case where the hole patterns HP1 are disposed at the initial positions.

The hole patterns HP1 are arranged close to each other. In this case, the shape of the hole formed corresponding to the hole pattern HP1 is deformed so as to extend toward another adjacent hole as compared with the shape of the hole pattern HP1. That is, the shape of the hole formed in the photosensitive film by lithography using the photomask PM1 is deformed so as to extend toward the side where the adjacent hole is located, as compared with the shape of the hole pattern HP1.
When the photosensitive film is a resist film, for example, holes are formed in the insulating film or the like by etching using the resist film as a mask. At this time, the position of the hole formed in the insulating film in the second direction approaches the adjacent hole as compared with the hole pattern HP1. That is, the positional deviation in the second direction between two adjacent holes is smaller than the positional deviation in the second direction between the two adjacent hole patterns HP1.
Therefore, it is possible to realize a configuration suitable for the design intention of suppressing the positional deviation of the holes formed corresponding to the hole pattern HP1 and forming the holes arranged in a line.

  Thus, according to the present embodiment, by arranging the hole patterns HP1 so that the positions in the second direction are staggered, a hole based on the design intention is suppressed while suppressing occurrence of a short circuit between adjacent holes. This arrangement can be realized. Thereby, the manufacturing stability of the semiconductor device can be improved.

  Here, the shift amount in the second direction between the two adjacent hole patterns HP1 after the above-described step of moving the hole pattern HP1 in the second direction is S. In this case, the shift amount S is preferably 5% or more and 20% or less of the distance P between the centers of the two hole patterns HP1 before movement. As a result, it is possible to easily realize the hole configuration based on the design concept while reliably suppressing a short circuit between adjacent holes.

In the present embodiment, before the step of moving the hole pattern HP1 in the second direction, a region in which holes are allowed to be arranged when forming a hole corresponding to the hole pattern HP1 in the insulating film (hereinafter, an allowable region). It may be further provided with a step of determining. The region in which the hole arrangement is allowed is determined based on, for example, a hole displacement that is allowed in consideration of the influence on the operation of the semiconductor device.
In this case, the hole pattern HP1 can be moved in the second direction so that the holes are formed in the allowable region in the insulating film. That is, the amount of movement of the hole pattern HP1 can be determined based on the allowable amount of hole displacement. Therefore, it is possible to further facilitate the arrangement of the holes based on the design intention.

In the present embodiment, in the above step of moving the hole pattern HP1 in the second direction, the hole pattern HP1 can be moved and the hole pattern HP2 can be moved. In this case, the two hole patterns HP2 move in the first direction so as to be separated from the adjacent hole patterns HP1, for example. Thereby, the center-to-center distance between the hole pattern HP1 and the hole pattern HP2 can be increased. Therefore, it is possible to further suppress the occurrence of a short circuit between the holes.
In the present embodiment, for example, the photomask PM1 is designed in this way.

Next, the configuration of the semiconductor device SM1 according to the present embodiment will be described in detail. FIG. 8 is a cross-sectional view showing the configuration of the semiconductor device SM1 according to this embodiment.
As shown in FIG. 8, the semiconductor device SM1 includes, for example, a semiconductor substrate SB1, a transistor TR1 provided on the semiconductor substrate SB1, and a multilayer wiring layer provided on the transistor TR1. The multilayer wiring layer includes, for example, a wiring IC1. For example, an element isolation film EL1 is provided on the semiconductor substrate SB1. The element isolation film EL1 has a function of isolating the transistor TR1 from other semiconductor elements. Also, the isolation layer EL1 is formed of, for example, an SiO _2.

The transistor TR1 includes, for example, a gate insulating film GI1, a gate electrode GE1, a sidewall SW1, and a source / drain region SD1. The gate insulating film GI1 is provided on the semiconductor substrate SB1. The gate insulating film GI1 is made of an insulating film such as SiO ₂ . The gate electrode GE1 is provided on the gate insulating film GI1. The gate electrode GE1 is made of, for example, a polycrystalline silicon film or a metal film. The sidewall SW1 is provided on the side surface of the gate electrode GE1. The source / drain region SD1 is provided in the semiconductor substrate SB1 so as to sandwich the gate electrode GE1.

On the semiconductor substrate SB1, an interlayer insulating film II1 is provided so as to cover the transistor TR1. A contact plug CO1 connected to the source / drain region SD1 is buried in the interlayer insulating film II1. The contact plug CO1 is made of W, for example.
On the interlayer insulating film II1, an etching stopper film ES1 and an interlayer insulating film II2 are sequentially stacked. A wiring IC1 is embedded in the etching stopper film ES1 and the interlayer insulating film II2. The wiring IC1 is connected to, for example, the contact plug CO1. Further, the wiring IC1 is made of, for example, a metal material whose main component is Cu.
A plurality of other wiring layers constituting a multilayer wiring layer may be further provided on the interlayer insulating film II2 together with the wiring layer including the wiring IC1.

  Next, a method for manufacturing the semiconductor device according to the present embodiment will be described. FIG. 3 is a view for explaining the method for manufacturing the semiconductor device according to the present embodiment.

  In the present embodiment, the semiconductor device SM1 is manufactured as follows. First, a photomask PM1 designed using the above-described photomask PM1 design method is prepared. Here, the preparation of the photomask PM1 includes a case where the photomask PM1 is manufactured. Next, the resist film RF1 is patterned using the photomask PM1. Next, by etching the insulating film IF1 using the resist film RF1 as a mask, holes HL2 corresponding to the hole pattern HP1 are formed in the insulating film IF1.

The insulating film IF1 is, for example, an interlayer insulating film that constitutes the semiconductor device SM1.
In the example shown in FIG. 8, for example, interlayer insulating film II1 is formed of insulating film IF1. In this case, the hole HL2 constitutes at least a part of a contact hole for embedding the contact plug CO1, for example. In the example shown in FIG. 8, another interlayer insulating film (not shown) formed on the interlayer insulating film II2 may be configured by the insulating film IF1. In this case, the hole HL2 constitutes at least a part of a via hole for embedding a via plug connecting the wiring layers including the wiring IC1.
Hereinafter, a method for manufacturing the semiconductor device SM1 according to the present embodiment will be described in detail.

First, a photomask PM1 is prepared.
The photomask PM1 is manufactured based on the layout data for the mask pattern. FIG. 3A illustrates layout data having a hole pattern HP1 corresponding to the hole HL2 in order to form the holes HL2 arranged in a row in the insulating film IF1.
In the present embodiment, movement correction based on the above-described design method of the photomask PM1 is performed on the layout data for the mask pattern. Thereby, the plurality of hole patterns HP1 are arranged so that the positions in the second direction are staggered. Then, the photomask PM1 is manufactured based on the corrected layout data. In addition, you may perform OPC (Optical Proximity Correction) with respect to the layout data for mask patterns.

  FIG. 3B shows an example of the configuration of the photomask PM1 to be manufactured. As shown in FIG. 3B, in the manufactured photomask PM1, the plurality of hole patterns HP1 are arranged so that the positions in the second direction are staggered. 3B to 3D, the initial position of the hole pattern HP1 in the layout data before movement correction, that is, the position of the hole pattern HP1 before movement is indicated by a dotted line.

  Next, the resist film RF1 is patterned using the photomask PM1. The resist film RF1 is formed on the insulating film IF1. The resist film RF1 is patterned by exposure and development using, for example, the photomask PM1 as a mask. Thereby, the circuit pattern including the hole pattern HP1 formed on the photomask PM1 is transferred to the resist film RF1. As shown in FIG. 3C, holes HL1 are formed in the resist film RF1 corresponding to the hole patterns HP1.

Here, the plurality of hole patterns HP1 are arranged close to each other. In this case, the hole HL1 formed corresponding to the hole pattern HP1 is deformed so as to extend toward the side where the adjacent hole HL1 is located as compared with the hole pattern HP1.
In the example shown in FIG. 3C, the hole HL1 is formed to extend to the side where another hole HL1 adjacent in the second direction is located. For this reason, the hole HL1 has, for example, a tapered shape on the side where another adjacent hole HL1 is located. FIG. 3C shows an example in which the upper end TE1 of the hole HL1 is positioned closer to another hole HL1 adjacent in the second direction than the lower end LE1. At this time, the upper end TE1 of the hole HL1 has a larger area than the lower end LE1 of the hole HL1.

Next, by etching the insulating film IF1 using the resist film RF1 as a mask, holes HL2 corresponding to the hole pattern HP1 are formed in the insulating film IF1. At this time, another circuit pattern is formed in the insulating film IF1, for example, simultaneously with the hole pattern HP1.
The hole HL2 is formed, for example, by dry etching the insulating film IF1.

As described above, the shape of the hole HL1 formed in the resist film RF1 is deformed so as to extend toward the side where the adjacent hole HL1 is located, as compared with the shape of the hole pattern HP1. For this reason, the position in the second direction of the hole HL2 formed by etching using the resist film RF1 as a mask is closer to another hole HL2 adjacent to the hole pattern HP1. Thereby, the positional shift in the second direction between the two adjacent holes HL2 is smaller than the positional shift in the second direction between the two adjacent hole patterns HP1.
FIG. 3D shows an example in which the hole HL2 is disposed within the initial position of the hole pattern HP1. Thus, it can be seen that a configuration suitable for the design intention of forming the holes HL2 arranged in a line can be realized.

For example, a conductive film is buried in the hole HL2 formed in the insulating film IF1. Thereby, contact plugs or via plugs are formed.
In the present embodiment, for example, the semiconductor device SM1 is manufactured in this way.

4 to 7, the experimental results show the configurations of the holes HL1 and HL2 when the hole patterns HP1 formed on the photomask PM1 are arranged so that the positions in the second direction are staggered.
Here, holes corresponding to the hole pattern HP1 were formed on a resist film having a thickness of 150 nm by a lithography process using normal illumination with a wavelength of 193 nm (ArF) and a numerical aperture NA = 1.2. For the hole pattern HP1 before movement, the center-to-center distance (pattern pitch) between adjacent hole patterns HP1 was set to 120 nm. At this time, the hole configuration at the resist threshold 20%, that is, 30 nm from the resist bottom was simulated as the configuration of the hole HL1 formed in the resist film RF1. Further, the above-described hole configuration at a resist threshold of 80%, that is, 120 nm from the resist bottom was simulated as the configuration of the hole HL2 formed in the insulating film IF1.

FIG. 4 is a graph showing the relationship between the movement amount of the hole pattern HP1 and the movement amount of the hole HL1, and the relationship between the movement amount of the hole pattern HP1 and the movement amount of the hole HL2. FIG. 5 is a graph showing the ratio of the movement amount of the hole HL1 to the movement amount of the hole pattern HP1, and the ratio of the movement amount of the hole HL2 to the movement amount of the hole pattern HP1.
4 to 7, the movement amount of the hole pattern HP1 is the movement amount from the initial position of the hole pattern HP1 stored in the layout data for the mask pattern. The amount of movement of the hole HL1 is formed corresponding to the hole pattern HP1 after the movement, with the position when the hole HL1 is formed corresponding to the hole pattern HP1 arranged at the initial position as a reference position. This is the distance from the reference position of the hole HL1. The amount of movement of the hole HL2 is the hole HL2 formed corresponding to the hole pattern HP1 after the movement, with the position when the hole HL2 is formed corresponding to the hole pattern HP1 arranged at the initial position as a reference position. The distance from the reference position.

In FIG. 4, the movement amount of the hole pattern HP1 is taken as the horizontal axis, and the movement amounts of the holes HL1 and HL2 are taken as the vertical axis. As shown in FIG. 4, the movement amount of the hole HL1 is smaller than the movement amount of the hole pattern HP1. Further, the movement amount of the hole HL2 is smaller than the movement amount of the hole HL1.
Thus, it can be seen that the positional deviation in the second direction between the adjacent holes HL1 decreases as compared with the positional deviation in the second direction between the adjacent hole patterns HP1. Further, it can be seen that the positional deviation in the second direction between the adjacent holes HL2 decreases as compared with the positional deviation in the second direction between the adjacent holes HL1.

In FIG. 5, the horizontal axis represents the amount of movement of the hole pattern HP1, and the vertical axis represents the ratio of the amount of movement of the holes HL1 and HL2 to the amount of movement of the hole pattern HP1. As shown in FIG. 5, the ratio of the movement amount of the hole HL2 to the movement amount of the hole pattern HP1 is smaller than the ratio of the movement amount of the hole HL1 to the movement amount of the hole pattern HP1.
For this reason, it can be seen from FIG. 5 that the positional deviation in the second direction between the adjacent holes HL2 is smaller than the positional deviation in the second direction between the adjacent holes HL1.

  As described above, according to the results shown in FIGS. 4 and 5, when the hole patterns HP1 are arranged so that the positions in the second direction are staggered, the design intention is to form the holes HL2 arranged in a line. It can be seen that a suitable configuration can be realized.

FIG. 6 is a graph showing the relationship between the movement amount of the hole pattern HP1 and the interval between two adjacent holes HL1. In FIG. 6, the movement amount of the hole pattern HP1 is taken as the horizontal axis, and the interval between two adjacent holes HL1 is taken as the vertical axis.
As shown in FIG. 6, it can be seen that the distance between two adjacent holes HL1 increases as the movement amount of the hole pattern HP1 increases. Thus, it can be seen that by moving the hole pattern HP1 according to the above-described design method, it is possible to increase the interval between the adjacent holes HL1 and suppress the occurrence of a short circuit between the holes HL1.

FIG. 7 is a graph showing the relationship between the movement amount of the hole pattern HP1 and the exposure amount margin. The exposure amount margin means a range of allowable exposure amount fluctuation. In FIG. 7, the movement amount of the hole pattern HP1 is taken as the horizontal axis, and the exposure amount margin is taken as the vertical axis.
In FIG. 7, a range of exposure amount fluctuation that gives a dimensional variation of less than 5 nm for the hole HL1 is used as one index of exposure amount margin (left vertical axis in FIG. 7). Further, as one index of exposure amount margin, a range of exposure amount fluctuation that gives a space dimension of 45 nm or more for the hole HL1 is used (right vertical axis in FIG. 7). The space dimension of the hole HL1 is the minimum interval between two adjacent holes HL1.
As shown in FIG. 7, it can be seen that, regardless of which index is used, the exposure amount margin increases as the movement amount of the hole pattern HP1 increases.

Next, the effect of this embodiment will be described.
According to the present embodiment, at least two hole patterns HP1 arranged in the first direction and spaced apart from each other so as to have an interval equal to or less than the reference value are alternately arranged in the second direction orthogonal to the first direction. To be placed. For this reason, with respect to at least two hole patterns HP1 arranged in a row, the interval between two adjacent hole patterns HP1 can be increased. Thereby, when forming the some hole corresponding to the hole pattern arrange | positioned in a line, it can suppress that a short circuit arises between adjacent holes. Therefore, it is possible to provide a photomask with excellent manufacturing stability of the semiconductor device. This also makes it possible to manufacture the semiconductor device stably.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

PM1 Photomask HP1, HP2, HP11, HP12 Hole pattern RF1 Resist film IF1 Insulating film HL1, HL2 Hole TE1 Upper end LE1 Lower end SM1 Semiconductor device TR1 Transistor GI1 Gate insulating film GE1 Gate electrode SW1 Side wall SD1 Source / drain region SB1 Substrate CO1 Contact Hole ES1, ES2 Etching stopper film II1, II2 Interlayer insulating film IC1 Wiring EL1 Element isolation film

Claims (5)

A process of reading layout data for a mask pattern;
Extracting at least two hole patterns arranged in the first direction and spaced apart from each other so as to have an interval equal to or less than a reference value from the layout data;
By moving at least one of the at least two hole patterns in a second direction orthogonal to the first direction, the at least two hole patterns are arranged so that the positions in the second direction are staggered. A process of
A photomask design method comprising: The photomask design method according to claim 1,
Before the step of moving the hole pattern in the second direction, further comprising a step of determining a region in which the hole is allowed to be arranged when forming a hole corresponding to the hole pattern in an insulating film;
The step of moving the hole pattern in the second direction is a photomask design method of moving the hole pattern so that the hole is formed in the region. The photomask design method according to claim 1,
In the step of moving the hole pattern in the second direction, the shift amount in the second direction of the two adjacent hole patterns after the movement is the distance between the centers of the two adjacent hole patterns before the movement. A photomask design method that is 5% or more and 20% or less. Preparing a photomask designed using the photomask design method according to claim 1;
Patterning a resist film using the photomask;
Etching the insulating film using the resist film as a mask to form holes corresponding to the hole pattern in the insulating film;
A method for manufacturing a semiconductor device comprising: A process of reading layout data for a mask pattern;
Extracting at least two hole patterns arranged in the first direction and spaced apart from each other so as to have an interval equal to or less than a reference value from the layout data;
By moving at least one of the at least two hole patterns in a second direction orthogonal to the first direction, the at least two hole patterns are arranged so that the positions in the second direction are staggered. A process of
Producing a photomask based on the layout data;
Patterning a resist film using the photomask;
Etching the insulating film using the resist film as a mask to form holes corresponding to the hole pattern in the insulating film;
A method for manufacturing a semiconductor device comprising:

Images