JP2014149443A - Pattern correction method, method for manufacturing mask, and method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve such a problem that a groove width in a portion facing a short wire out of a long wire is occasionally short compared with a groove width in other portions, in a pattern in which the long wire and the short wire are adjacent to each other.SOLUTION: A pattern correction method includes the step of: extracting first wire data and second wire data out of design data showing a design pattern of a planar view of a wiring groove IT1 (step of S104). The first wire data shows the arrangement and the shape of a first wire. The first wire includes a first edge portion formed into a linear shape. The second wire data shows the arrangement and the shape of a second wire. The second wire includes a second edge portion. The second edge portion is disposed parallel and opposite to the first edge portion, and is shorter than the first edge portion. The pattern correction method includes the steps of: moving a reference portion opposed to the second edge portion out of the first edge portion of the first wire to the side of the second edge portion, and thereby correcting the design data (step S106).

Description

  The present invention relates to a pattern correction method, a mask manufacturing method, and a semiconductor device manufacturing method, and is a technique applicable to, for example, a semiconductor device having a wiring pattern.

  With the miniaturization of wiring patterns, various wiring pattern forming methods have been proposed.

  Patent Document 1 describes a method of forming a wiring pattern by multiple projection exposure using two masks. Patent Document 2 describes a wiring pattern forming method including a step of extracting a pattern critical to a process in advance. Patent Document 3 describes a wiring pattern forming method including a step of correcting a pattern on a photomask by predicting a process conversion difference caused by the influence of etching in advance.

International Publication No. 01/063653 JP 2008-33277 A JP 2009-80349 A

  The wiring pattern may include a pattern in which a long wiring and a short wiring are adjacent to each other. The present inventor has found that in such a pattern, the etching progress speed in the portion where the long wiring and the short wiring face each other is higher than the progress speed in the other portions. Such a difference in the etching progress results in the result that the groove width of the portion facing the short wire among the long wires becomes shorter than the groove width of the other portions. There is a concern that such a phenomenon may lead to disconnection of the wiring, which leads to a decrease in the reliability of the wiring pattern.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  According to the embodiment, the first wiring data and the second wiring data are extracted from the design data indicating the design pattern of the wiring groove in plan view. The first wiring data indicates the arrangement and shape of the first wiring. The first wiring includes a first edge portion formed in a straight line. The second wiring data indicates the arrangement and shape of the second wiring. The second wiring includes a second edge. The second edge is parallel to the first edge and is shorter than the first edge. According to one embodiment, the design data is corrected by moving the reference portion facing the second edge portion of the first edge portion of the first wiring to the second edge side.

  According to the embodiment, it is possible to prevent the width of the reference portion of the first wiring from becoming shorter than the width of the other portion of the first wiring.

It is sectional drawing which shows the semiconductor device in 1st Embodiment. It is process sectional drawing which shows the manufacturing procedure of the semiconductor device in 1st Embodiment. It is process sectional drawing which shows the manufacturing procedure of the semiconductor device in 1st Embodiment. It is process sectional drawing which shows the manufacturing procedure of the semiconductor device in 1st Embodiment. It is a flowchart of the pattern correction method of the mask in 1st Embodiment. It is a top view which shows the reference | standard part vicinity of the wiring groove | channel formed in the process shown by FIG.3 (b). It is a top view which shows the reference | standard part vicinity of the wiring groove | channel formed in the process shown by FIG.3 (b). It is a block diagram which shows the structure of the pattern correction apparatus for performing the process shown in FIG. (A) is a figure which shows the 1st example of arrangement | positioning and a shape of 1st wiring and 2nd wiring in extraction design data, (b) is arrangement | positioning of 1st wiring and 2nd wiring in extraction design data. It is a figure which shows the 2nd example of shape. (A) is a figure which shows the 1st example of arrangement | positioning and shape of 1st wiring and 2nd wiring in correction | amendment extraction design data, (b) is 1st wiring and 2nd wiring in correction | amendment extraction design data, It is a figure which shows the 2nd example of arrangement | positioning and shape. It is a figure which shows the reference | standard data which the reference | standard storage part has memorize | stored in a table format. (A) is a figure which shows the specific example of a Line and Space (L & S) pattern, (b) is a graph which shows the process conversion difference of the L & S pattern in (a). (A) is a figure which shows the specific example of the abutting pattern of T-shaped wiring, (b) is a graph which shows the process conversion difference of the abutting pattern of T-shaped wiring in (a). It is a figure which shows the specific example of arrangement | positioning and a shape of the 1st wiring in the optical proximity effect correction design data which correct | amended the optical extraction effect design data shown by Fig.10 (a), and 2nd wiring. (A) is a figure for demonstrating the effect when the wiring data correction | amendment in 1st Embodiment is made, (b) is a figure for demonstrating the comparison with the effect shown by (a). It is. It is a figure which shows the example of arrangement | positioning and shape of the 1st wiring in the extraction design data, 2nd wiring, and 3rd wiring. It is a figure which shows the reference | standard data which the reference | standard storage part has memorize | stored in a table format.

  Hereinafter, embodiments will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

(First embodiment)
First, the configuration of the semiconductor device SM1 according to this embodiment will be described.
FIG. 1 is a cross-sectional view showing a semiconductor device SM1 according to this embodiment. As shown in FIG. 1, the semiconductor device SM1 has a multilayer wiring structure including, for example, a semiconductor substrate SB1, a transistor TR1 provided on the semiconductor substrate SB1, and a plurality of wiring layers WI1.

The semiconductor substrate SB1 is, for example, a silicon substrate. The semiconductor device SM1 is provided with an element isolation film EI1 for electrically isolating the transistor TR1 from other elements.
The transistor TR1 includes a gate insulating film GI1, a gate electrode GE1, a sidewall SW1, and a source / drain region SD1. The gate insulating film GI1 is provided on the semiconductor substrate SB1. The gate electrode GE1 is provided on the gate insulating film GI1. The sidewall SW1 is formed on the side surfaces of the gate insulating film GI1 and the gate electrode GE1. The source / drain region SD1 is formed in the semiconductor substrate SB1. The source / drain region SD1 is formed, for example, by ion implantation using the gate electrode GE1 and the sidewall SW1 as a mask. On the source / drain region SD1, for example, a silicide layer SC1 is formed.

  On the semiconductor substrate SB1, an etching stopper film ES1 is formed so as to cover the transistor TR1. An interlayer insulating film IL1 is formed on the etching stopper film ES1. In the interlayer insulating film IL1, a contact plug CP1 penetrating the interlayer insulating film IL1 and the etching stopper film ES1 and connected to the source / drain region SD1 is formed. In the present embodiment, for example, the contact plug CP1 is formed so as to be connected to the silicide layer SC1 provided on the source / drain region SD1.

On the interlayer insulating film IL1, a multilayer wiring layer formed by laminating a plurality of wiring layers WI1 is formed. The wiring layer WL1 includes an etching stopper film ES2, an interlayer insulating film IL2 provided on the etching stopper film ES2, and a wiring IC1 and a via plug VP1 formed in the interlayer insulating film IL2. The wiring IC is composed of a metal film ML1 (not shown in FIG. 1) and a barrier metal film BM1 (not shown in FIG. 1) that covers the side surfaces thereof.
The wiring IC1 and the via plug VP1 have, for example, a dual damascene structure in which they are integrally formed. The wiring IC1 and the via plug VP1 may each have a single damascene structure.

Next, a method for manufacturing the semiconductor device SM1 according to the present embodiment will be described in detail.
The semiconductor device SM1 according to the present embodiment is obtained by forming the transistor TR1 on the semiconductor substrate SB1 and then forming a multilayer wiring structure including a plurality of wiring layers WI1 on the transistor TR1.

  Each wiring layer WI1 is formed as shown in FIGS. 2 to 4 are process cross-sectional views illustrating the manufacturing procedure of the semiconductor device SM1 according to this embodiment.

  First, as shown in FIG. 2A, a hard mask HM1, an antireflection film AR1, a resist film RS1 are formed on an interlayer insulating film IL2 formed on a substrate SB1 (not shown in FIGS. 2 to 4). Are formed in this order. Next, as shown in FIG. 2B, the resist film RS1 is exposed to light LT1 through a mask MK1 on which a pattern is formed. By developing the exposed resist film RS1, a resist pattern RP1 is formed as shown in FIG. Next, as shown in FIG. 3B, a wiring trench IT1 is formed in the interlayer insulating film IL2 by etching using the resist film RS1 on which the resist pattern RP1 is formed as a mask. For this etching, dry etching may be used. Next, the resist film RS1, the antireflection film AR1, and the hard mask HM1 are removed from the interlayer insulating film IL2. Next, the barrier metal film BM1 is formed on the bottom and side surfaces of the wiring trench IT1 and the entire surface of the interlayer insulating film IL2 (FIG. 4A). The barrier metal film BM1 is made of, for example, titanium, titanium nitride, tantalum, tantalum nitride, or tungsten nitride. Next, as shown in FIG. 4B, a metal film ML1 (conductive film) is embedded in the wiring trench IT1. The metal film ML1 is made of copper, for example. The metal film ML1 may be formed by a plating process. As shown in FIG. 4B, the metal film ML1 is formed not only on the wiring trench IT1, but also on the interlayer insulating film IL2 outside the wiring trench IT. Such a metal film ML1 is removed by, for example, chemical mechanical polishing (CMP). As a result, as shown in FIG. 1, a wiring IC1 embedded in the wiring trench IT1 is obtained. As described above, each wiring layer WI1 is obtained.

  Next, the mask MS1 used for forming the resist pattern RP1 will be described in detail. In the present embodiment, the pattern of the mask MS1 is corrected. The pattern correction method for the mask MS1 will be described in detail with reference to FIGS.

  FIG. 5 is a flowchart showing the steps of the pattern correction method for the mask MS1 in the present embodiment. The pattern correction method according to the present embodiment includes a step of acquiring design data (step S102). The design data indicates a design pattern in plan view of the wiring trench IT1. Next, the pattern correction method according to the present embodiment extracts first wiring data and second wiring data from the acquired design data (step S104). The first wiring data is data indicating the arrangement and shape of the first wiring. The first wiring includes a first edge formed on a straight line. On the other hand, the second wiring data is data indicating the arrangement and shape of the second wiring. The second wiring includes a second edge. The second edge is parallel to the first edge and is shorter than the first edge. Next, the design data is corrected (step S106). Specifically, the design data is corrected by moving the reference portion of the first wiring to the second edge side. A reference | standard part is a part which opposes a 2nd edge part among the 1st edge parts of a 1st wiring.

  If a mask based on the design data corrected through the above steps is used, the etching progress rate in the reference portion of the first wiring is higher than the etching progress rate in other portions of the first wiring in the step of FIG. Even if it is high, it is possible to prevent the width of the reference portion of the first wiring from becoming shorter than the width of the other portion of the first wiring.

  In the flowchart in FIG. 5, the pattern correction method according to the present embodiment corrects the optical proximity effect of the design pattern corrected in step S106 after step S106 (step S108). At this time, the distance by which the reference portion is moved in step S106 is such that the distance between the first edge portion and the second edge portion in the wiring groove IT1 formed in the step shown in FIG. The reference portion and the other portions of the first edge may be determined to be substantially the same.

The meaning of the interval between the first edge and the second edge in the wiring groove IT1 being “substantially the same” in the reference portion of the first edge and the other portions of the first edge is shown in FIG. 6 will be described. FIG. 6 is a plan view showing the vicinity of the reference portion of the wiring trench IT1 formed in the step shown in FIG. The pattern drawn with diagonal lines in FIG. 6 shows the wiring trench IT1 formed in the step shown in FIG. Reference numerals IP1 and IP2 denote a first wiring and a second wiring, respectively. Reference numerals IE1 and IE2 denote a first edge and a second edge, respectively. The first edge portion IE1 and the second edge portion IE2 are actually not completely flat in the pattern of the wiring trench IT1 formed in the step shown in FIG. In the pattern of the wiring trench IT1, the first edge portion IE1 has a shape recessed in the reference portion REF on the side opposite to the second edge portion IE2. This is because the etching progress rate in the reference portion and its periphery is higher than the etching progress rate in other portions. The distance between the first edge portion IE1 and the second edge portion IE2 is “substantially the same” in the reference portion REF of the first edge portion IE1 and the other portions of the first edge portion IE1 is 0.9. ≦ d _min / d _MAX ≦ 1.0. d _min and d _MAX are defined as follows. That is, first, a virtual point P is defined. The virtual point P is a point located closest to the first edge in the second edge IE2. Next, the virtual line NL is defined. The virtual line NL is a straight line that passes through the virtual point P and is parallel to the design pattern of the second edge portion IE2. d _MAX is a distance between the virtual line NL and the virtual point P _MAX . The virtual point P _MAX is a point that is farthest from the virtual line NL in the reference portion REF in the first edge portion IE. d _min is the distance between the virtual line NL and the virtual point P _min . The virtual point P _min is a point that is closest to the virtual line NL in the first edge portion IE other than the reference portion REF.

  As described above, if the distance for moving the reference portion is determined in step S106, the distance between the first edge and the second edge in the wiring trench IT1 formed in the step shown in FIG. The reference portion of the first edge and the other portions of the first edge are substantially the same.

  Step S106 of the present embodiment may include a step of correcting the design data by moving the peripheral portion to the second edge side. The peripheral portion is a portion of the first edge portion of the first wiring that is adjacent to the reference portion and located on the reference portion side. The distance and the length of the peripheral portion for moving the peripheral portion in step S106 are determined so that the first edge portion in the wiring trench IT1 formed in the step shown in FIG. 3B is substantially flat.

The meaning that the first edge portion of the wiring trench IT1 becomes “substantially flat” will be described with reference to FIG. FIG. 7 is a plan view showing the vicinity of the reference portion of the wiring trench IT1 formed in the step shown in FIG. A pattern drawn with diagonal lines in FIG. 7 indicates the wiring trench IT1 formed in the step shown in FIG. Reference numerals IP1 and IP2 denote a first wiring and a second wiring, respectively. Reference numerals IE1 and IE2 denote a first edge and a second edge, respectively. The first edge portion IE1 is actually not completely flat in the pattern of the wiring trench IT1 formed in the process shown in FIG. In the pattern of the wiring trench IT1, the first edge portion IE1 has a shape recessed in the reference portion REF on the side opposite to the second edge portion IE2. The fact that the first edge portion IE1 is “substantially flat” means that 0 ≦ MAX [θ] ≦ 20 [degrees]. MAX [θ] means the maximum value of θ. θ is defined as follows. That is, first, the virtual line NL is defined. The virtual line NL is a straight line parallel to the design pattern of the first edge portion IE1. Next, a virtual tangent line TL is defined. A virtual tangent line TL is tangent at a virtual point _{P t} on the first edge IE1. θ is an angle formed by the virtual line NL and the virtual tangent line TL. The value of θ varies depending on the position of the virtual point P _t.

  As described above, when the distance and the length of the peripheral portion are determined in step S106, the first edge portion in the wiring trench IT1 formed in the step shown in FIG. 3B becomes substantially flat. .

  FIG. 8 is a block diagram showing a configuration of a pattern correction apparatus used in the pattern correction method of FIG.

  This pattern correction apparatus includes, as function units, an input unit INU, a design data generation unit DGU, a design data acquisition unit DOU, a wiring data extraction unit IEU, a wiring data correction unit IAU, and an optical proximity effect correction unit OAU. It is equipped with. The input unit INU is provided for the user of the pattern correction apparatus to make various inputs to the pattern correction apparatus. The design data generation unit DGU generates design data as described later. The design data acquisition unit DOU performs the process shown in step S102 of FIG. The wiring data extraction unit IEU performs the process shown in step S104 of FIG. The wiring data correction unit IAU performs the process shown in step S106 of FIG. The optical proximity effect correction unit OAU performs the process shown in step S108 of FIG.

  This pattern correction apparatus includes a design data storage unit DST, an extraction condition storage unit EST, a reference storage unit RST, and an optical proximity effect correction storage unit OST as storage units. The design data storage unit DST stores design data output from the design data acquisition unit DOU. The design data storage unit DST further stores extracted design data output by the wiring data extraction unit IEU. The design data storage unit DST further stores correction extraction design data output from the wiring data correction unit IAU. The design data storage unit DST further stores optical proximity effect correction design data output from the optical proximity effect correction unit OAU. In addition to the above, the design data storage unit DST stores design data, extraction design data, correction extraction design data, and optical proximity effect correction design data in association with each other. Details of the extraction condition storage unit EST, the reference storage unit RST, and the optical proximity effect correction storage unit OST will be described later.

  The design data generation unit DGU generates design data in accordance with an instruction input to the input unit INU. The design data indicates a design pattern in plan view of the wiring trench IT1 in each wiring layer WI1. The design data may include first wiring data indicating the arrangement and shape of the first wiring and second wiring data indicating the arrangement and shape of the second wiring. The second wiring is located in the same layer as the first wiring, and is located around the first wiring in plan view. The design data generation unit DGU outputs the design data to the design data acquisition unit DOU or the design data storage unit DST.

  The design data acquisition unit DOU acquires design data in accordance with an instruction input to the input unit INU (step S102). When the design data generation unit DGU outputs the design data to the design data acquisition unit DOU, the design data acquisition unit DOU acquires the design data. On the other hand, when the design data generation unit DGU outputs the design data to the design data storage unit DST, the design data acquisition unit DOU acquires the design data from the design data storage unit DST. The design data acquisition unit DOU outputs the design data acquired by the design data acquisition unit DOU to the design data storage unit DST. The design data storage unit DST stores design data. Then, the design data storage unit DST outputs a design data output signal indicating that the design data has been output to the wiring data extraction unit IEU.

  The wiring data extraction unit IEU reads design data from the design data storage unit DST after receiving a design data output signal in accordance with an instruction input to the input unit INU. At this time, the wiring data extraction unit IEU also reads the extraction condition data from the extraction condition storage unit EST. The extraction condition data is data stored in the extraction condition storage unit EST. The extraction condition data is data indicating conditions that the first wiring data and the second wiring data should satisfy. Specifically, the first wiring data and the second wiring data must satisfy the following conditions. In other words, the first wiring indicated by the first wiring data has a first edge portion formed in a straight line. The second wiring indicated by the second wiring data has a second edge. The second edge faces the first edge in parallel. The second edge is shorter than the first edge. Data indicating a wiring pattern satisfying the above conditions is defined as first wiring data and second wiring data. The wiring data extraction unit IEU extracts the first wiring data and the second wiring data from the design data according to the extraction condition data read by the wiring data extraction unit IEU (Step S104). The extracted first wiring data and second wiring data become extracted design data. The wiring data extraction unit IEU outputs the extracted design data to the design data storage unit DST. The design data storage unit DST stores extracted design data. Then, the wiring data extraction unit IEU outputs an extraction design data output signal indicating that the extraction design data has been output to the wiring data correction unit IAU.

  The wiring data correction unit IAU reads the extracted design data from the design data storage unit DST after receiving the extracted design data output signal in accordance with the instruction input to the input unit INU. At this time, the wiring data correction unit IAU also reads the reference data from the reference storage unit RST. The reference data is data stored in the reference storage unit RST. The reference data corresponds to a reference value related to various parameters of the first wiring and the second wiring (for example, the distance between the first edge and the second edge, the length of the second edge) and the reference value. The preliminary correction distance δ (the details of the preliminary correction distance δ will be described later) is included. The wiring data correction unit IAU measures various parameters of the first wiring and the second wiring with respect to the extracted design data. Then, the wiring data correction unit IAU searches the reference data for reference values corresponding to these measured values. After this search, the wiring data correction unit IAU corrects the extracted design data (step S106). Specifically, the wiring data correction unit IAU corrects the extracted design data by moving the reference portion of the first wiring to the second edge side. A reference | standard part is a part which opposes a 2nd edge part among the 1st edge parts of a 1st wiring. At this time, the reference portion is moved toward the second edge side by the preliminary correction distance δ corresponding to the searched reference value. The corrected extracted design data becomes corrected extracted design data. Then, the wiring data correction unit IAU outputs the correction extraction design data to the design data storage unit DST. The design data storage unit DST stores correction extraction design data. Further, the wiring data correction unit IAU outputs a correction design data output signal indicating that the correction extraction design data has been generated to the optical proximity effect correction unit OAU.

  The preliminary correction distance δ included in the reference data stored in the reference storage unit RST is determined as follows. That is, the correction extraction design data is subjected to optical proximity effect correction in step S108 (details will be described later). The preliminary correction distance δ is the distance between the first edge and the second edge in the wiring trench IT1 formed in FIG. 3B when the mask MK1 based on the design data subjected to the optical proximity effect correction is used. The interval between them can be determined to be substantially the same between the reference portion of the first edge and the other portions of the first edge. The meaning that the interval between the first edge and the second edge in the wiring groove IT1 becomes “substantially the same” in the reference portion of the first edge and the other portions of the first edge is shown in FIG. 6 as described above. The preliminary correction distance δ is equal to the distance between the first edge and the second edge in the wiring groove IT1 formed in the step of FIG. It can be calculated by conducting an experiment in advance under various conditions of the preliminary correction distance δ whether the other parts are substantially the same. Based on this experimental result, the reference storage unit RST determines the preliminary correction distance δ, the width W1 of the first wiring, the width W2 of the second wiring, the length L2 of the second edge, and the first edge, You may memorize | store in relation to the distance S between 2nd edge parts.

  In step S106, the extracted design data may be corrected by moving the peripheral portion of the first wiring to the second wiring side. The peripheral portion is a portion of the first edge portion of the first wiring that is adjacent to the reference portion and located on the reference portion side. At this time, the peripheral portion is moved toward the second edge side by the preliminary correction distance δ ′. In this case, the reference data includes reference values regarding various parameters of the first wiring and the second wiring (for example, the distance between the first edge and the second edge, the length of the second edge), and the reference The preliminary correction distance δ ′ corresponding to the value may be included. The preliminary correction distance δ ′ and the length of the peripheral portion are determined as follows. That is, the correction extraction design data is subjected to optical proximity effect correction in step S108 (details will be described later). The preliminary correction distance δ ′ and the length of the peripheral portion are the first edge portion in the wiring trench IT1 formed in FIG. 3B when the mask MK1 based on the design data subjected to the optical proximity effect correction is used. Can be determined to be substantially flat. The meaning that the first edge portion in the wiring trench IT1 becomes “substantially flat” is as described above with reference to FIG.

  The meaning of moving the preliminary correction distance δ ′ to the second edge side will be described. As described with reference to FIGS. 6 and 7, the first edge portion in the wiring trench IT is not completely flat, and has a shape that is recessed on the side opposite to the second edge side in the reference portion. If the reference part is moved to the second edge side in step S106 by the preliminary correction distance δ, this dent in the reference part can be suppressed. On the other hand, this dent may occur not only in the reference portion but also in the peripheral portion. In this case, when only the reference portion is moved in step S106, the first edge portion may include a stepped shape in which the dent suddenly returns from the inside to the outside of the peripheral portion. In order to prevent this situation, the peripheral portion can be moved to the second correction portion δ ′ toward the second edge. Thereby, the 1st edge part can take the shape which a dent returns gently toward the outer side from the inner side of a peripheral part. As a result, it is possible to prevent the first edge portion from including the stepped shape described above.

  The preliminary correction distance δ ′ and the length of the peripheral portion are determined based on whether the first edge in the wiring groove IT1 formed in the step of FIG. 3B is substantially flat. It can be calculated by conducting an experiment in advance under the condition of the length. Based on the experimental results, the reference storage unit RST determines the length of the peripheral portion and the preliminary correction distance δ ′, the width W1 of the first wiring, the width W2 of the second wiring, and the length L2 of the second edge. And the distance S between the first edge and the second edge may be stored in association with each other.

  The optical proximity effect correcting unit OAU reads the design data and the correction extraction design data from the design data storage unit DST after receiving the corrected design data output signal according to the instruction input to the input unit INU. At this time, the optical proximity effect correction unit OAU also reads out the optical proximity effect correction data from the optical proximity effect correction storage unit OST. The optical proximity effect correction data is data stored in the optical proximity effect correction storage unit OST. The optical proximity effect correction data is data indicating rules for correcting the optical proximity effect of the mask pattern so that the resist pattern RP1 formed in the step shown in FIG. 3A becomes a desired pattern.

  After receiving the corrected design data output signal, the optical proximity correction unit OAU creates corrected design data in which a portion corresponding to the extracted design data in the design data is replaced with the corrected extracted data. Then, the optical proximity effect correction unit OST corrects the optical proximity effect on the corrected design data (step S108).

  The correction design data corrected for the optical proximity effect as described above becomes optical proximity effect correction design data. After the optical proximity effect correction, the optical proximity effect correction unit OAU outputs the optical proximity effect correction design data to the design data storage unit DST. The design data storage unit DST stores optical proximity effect correction design data.

  A mask having a pattern based on the optical proximity effect correction design data obtained by the above steps is manufactured. The mask manufactured in this way is used for the mask MK1 in the process shown in FIG. In this case, since the mask MK1 is manufactured through step S106, the width of the reference portion of the first wiring can be prevented from being shorter than the width of the other portion of the first wiring.

  Next, a specific example of the pattern correction method in this embodiment will be described. First, a specific example of the extracted design data in step S104 will be described with reference to FIGS. 9 (a) and 9 (b).

  FIG. 9A is a diagram illustrating a first example of the arrangement and shape of the first wiring IP1 and the second wiring IP2 in the extracted design data. In the first example, the T-shaped second wiring IP2 is abutted against the first wiring IP1. The first wiring IP1 includes a first edge portion IE1 formed linearly. The second wiring IP2 includes a second edge portion IE2. The second edge portion IE2 faces the first edge portion IE1 in parallel and is shorter than the first edge portion IE1. Further, the second wiring IP2 includes an edge portion IE21 and an edge portion IE22 that are orthogonal to the second edge portion IE2. The second wiring IP2 may include a second sub wiring IPS2. The second sub wiring IPS2 includes an edge portion IES1 and an edge portion IES2. The edge part IES1 and the edge part IES2 are linearly formed in a direction perpendicular to the second edge part IE2. The first edge portion IE1 includes a reference portion REF, a peripheral portion PER1, and a peripheral portion PER2. The reference portion REF is a portion of the first edge portion IE1 that faces the second edge portion IE2. The peripheral portion PER1 is a portion of the first edge portion IE1 that is adjacent to the reference portion REF and located on the edge portion IE21 side of the reference portion REF. The peripheral portion PER2 is a portion of the first edge portion IE1 that is adjacent to the reference portion REF and located on the edge portion IE22 side of the reference portion REF. In addition to the above, the width of the first wiring IP1 is W1. The width of the second wiring IP2 is W2. The distance between the first wiring IP1 and the second wiring IP2 is S. The length of the second edge portion IE2 is L2. The width of the second sub-wiring IPS2 is WS2, which is shorter than the length L2 of the second edge portion IE2. The distance in the second edge portion IE2 direction between the edge portion IE21 and the edge portion IES1 is ΔL1. Further, the distance in the second edge portion IE2 direction between the edge portion IE22 and the edge portion IES2 is ΔL2. The length of the peripheral part PER1 is ΔW1. The length of the peripheral part PER2 is ΔW2.

  FIG. 9B is a diagram showing a second example of the arrangement and shape of the first wiring IP1 and the second wiring IP2 in the extracted design data. In the second example, the L-shaped second wiring IP2 is abutted against the first wiring IP1. The second example shows the same arrangement and shape of the first wiring IP1 and the second wiring IP2 as in the first example except that ΔL2 = 0. That is, in the second example, the edge portion IE22 and the edge portion IES2 are formed on the same straight line. In the second example shown in FIG. 9B, the case of ΔL1> 0 and ΔL2 = 0 is shown, but the case of ΔL1 = 0 and ΔL2> 0 is naturally included in the present embodiment.

  The first example shown in FIG. 9A and the second example shown in FIG. 9B are merely examples of the present embodiment, and the arrangement and shape of the first wiring IP1 and the arrangement of the second wiring IP2 The shape is not limited to this. For example, the present embodiment includes a case where ΔL1 = ΔL2 = 0. That is, in this case, the edge portion IE21 and the edge portion IES1 are formed on the same straight line, and the edge portion IE22 and the edge portion IES2 are formed on the same straight line.

  Step S104 includes the width W1 of the first wiring IP1, the width W2 of the second wiring IP2, the length L1 of the first edge (not shown in FIGS. 9A and 9B), and the length of the second edge. L1, the first wiring IP1 and the second wiring IP2 are extracted using the distance S between the first edge portion IE1 and the second edge portion IE2 as a search parameter. The relationship between the first wiring IP1 and the second wiring IP2 is determined by the magnitude relationship between L1 and L2.

  At this time, the distances ΔL1 and ΔL2 may also be used as search parameters. When ΔL1> 0 and ΔL2> 0 (first example shown in FIG. 9A), the first wiring IP1 and the second wiring IP2 are assumed to have the second wiring IP2 belonging to the T-shaped wiring category. Can be extracted. When ΔL1 = 0 and ΔL2> 0 or ΔL1> 0 and ΔL2 = 0 (second example shown in FIG. 9B), the first wiring IP1 and the second wiring IP2 have an L-shaped second wiring IP2. It can be extracted as belonging to the type wiring category.

  Further, the width WS2 of the second sub wiring IPS2 may be used as a search parameter. When WS2 is used as a search parameter, when ΔL1 = ΔL2 = 0, the first wiring IP1 and the second wiring IP2 can be extracted as the second wiring IP2 belonging to the bar-shaped wiring category. That is, when ΔL1 = ΔL2 = 0, the edge portion IE21 and the edge portion IES2 are formed on the same straight line, and the edge portion IE22 and the edge portion IES22 are formed on the same straight line. For this reason, the width W2 of the second wiring IP2 does not effectively act as a parameter for distinguishing the second wiring IP2 and the second sub wiring IPS2. Also, the distances ΔL1 and ΔL2 do not act effectively as search parameters unless the width W2 of the second wiring IP2 is recognized. However, if the width WS2 of the second sub-wiring IPS2 is used as a search parameter, the length L2 of the second edge and the first distance at a predetermined distance from the second edge IE2 in the opposite direction to the first edge IE1. When the width WS2 of the two sub wirings IPS2 is equal, the first wiring IP1 and the second wiring IP2 can be extracted as the second wiring IP2 belonging to the category of the bar-shaped wiring.

  Thus, when the second wiring IP2 is categorized into a T-shaped wiring, an L-shaped wiring, and a rod-shaped wiring, in step S108, wiring data correction that is optimal for each category can be performed. As a result, it is possible to improve the pattern accuracy of the formed wiring trench IT1 in plan view.

  Next, a specific example of the correction extraction design data in step S106 will be described with reference to FIGS.

  FIG. 10A shows a first example of the arrangement and shape of the first wiring IP1 and the second wiring IP2 in the correction extraction design data. In the first example shown in FIG. 10A, the extracted design data of the first example shown in FIG. 9A is corrected through step S106. In this first example, the extracted design data shown in FIG. 9A is corrected by moving the reference portion REF to the second edge portion IE2 side by the preliminary correction distance δ. The preliminary correction distance δ is such that the distance between the first edge IE1 and the second edge IE2 in the wiring groove IT1 formed in the step shown in FIG. 3B is the reference portion REF of the first edge IE1. And other portions of the first edge portion IE1 may be determined to be substantially the same. The interval between the first edge portion IE1 and the second edge portion IE2 in the wiring groove IT1 becomes “substantially the same” in the reference portion REF of the first edge portion IE1 and the other portions of the first edge portion IE1. Is as described above with reference to FIG.

  In the first example shown in FIG. 10A, only the reference portion REF is moved by the preliminary correction distance δ, but the peripheral portion PER1 is moved to the second edge portion IE2 side in the preliminary correction distance δ1 ′ (in FIG. 10A). The peripheral portion PER2 may be moved to the second edge portion IE2 side, and the preliminary correction distance δ2 ′ (not shown in FIG. 10A) may be moved. The preliminary correction distance δ1 ′ and the length ΔW1 of the peripheral portion PER1 and the preliminary correction distance δ2 ′ and the length ΔW2 of the peripheral portion PER2 are substantially flat at the first edge portion IE1 in the wiring groove IT1 formed in FIG. Can be determined. The meaning that the first edge portion IE1 in the wiring trench IT1 becomes “substantially flat” is as described above with reference to FIG.

  FIG. 10B shows a second example of the arrangement and shape of the first wiring IP1 and the second wiring IP2 in the correction extraction design data. In the second example shown in FIG. 10B, the extracted design data of the second example shown in FIG. 9B is corrected through step S106. The second example shows the same arrangement and shape of the first wiring IP1 and the second wiring IP2 as in the first example except that ΔL2 = 0. Further, the preliminary correction distance δ shown in FIG. 10B includes the width W1 of the first wiring IP1, the length L1 of the first edge portion IE1 (not shown in FIG. 8B), The width W2 of the second wiring IP2, the length L2 of the second edge IE2, the distance S between the first edge IE1 and the second edge IE2, and the width WS2 of the second subwiring IPS2 are as shown in FIG. Even if it is equal to the above, it may be different from the preliminary correction distance δ shown in FIG. In this case, in step S104, the second wiring IP2 in FIGS. 9A and 10A is a T-shaped wiring, and the second wiring IP1 in FIGS. 9B and 10B is an L-shaped wiring. When categorized, step S106 can provide an optimal preliminary correction distance δ for each category. Further, when such categorization is performed, in step S106, it is possible to give appropriate values for each category for the preliminary correction distances δ1 ′ and δ2 ′ and the lengths ΔW1 and ΔW2.

  The first example shown in FIG. 10A and the second example shown in FIG. 10B are merely examples of the present embodiment, and the arrangement and shape of the first wiring IP1 and the wiring of the second wiring IP2 The shape is not limited to this. For example, the present embodiment includes a case where ΔL1 = ΔL2 = 0 (when the second wiring IP2 belongs to the category of rod-shaped wiring).

  Next, a specific example of a method for determining the preliminary correction distance δ of the reference unit REF will be described with reference to FIG. FIG. 11 is a diagram illustrating the reference data stored in the reference storage unit RST in a table format. As shown in FIG. 11, the preliminary correction distance δ of the reference portion REF includes the width W1 of the first wiring IP1, the width W2 of the second wiring IP2, the length L2 of the second wiring IP2, and the first edge portion. You may determine by the relationship with distance S between IE1 and 2nd edge part IE2. For example, in the pattern 1 in FIG. 11, the width W1 of the first wiring IP1 is 66 nm, the width W2 of the second wiring IP2 is 132 nm or less, and the length L2 of the second wiring IP2 is less than 660 nm. When the distance S between the edge portion IE1 and the second edge portion IE2 is 77 nm, the preliminary correction distance δ may be set to 2.5 nm. The table in FIG. 11 may include a pattern other than the pattern 1. In the table in FIG. 11, the relationships between the distances ΔL1 and ΔL2, the width WS2 of the second sub wiring IPS2, and the preliminary correction distance δ may be defined. If the values of ΔL1, ΔL2, and WS2 are also included, the second wiring IP2 can be categorized into a T-shaped wiring, an L-shaped wiring, and a rod-shaped wiring. As a result, the optimum preliminary correction distance δ can be given to each category. Further, the table in FIG. 11 may define the relationship between the various parameters described above, the preliminary correction distances δ1 ′ and δ2 ′, and the lengths ΔW1 and ΔW2.

  The above preliminary correction distance δ can be calculated by measuring the machining conversion difference. A specific example of the measurement of the processing conversion difference will be described with reference to FIGS.

  FIG. 12 is a diagram illustrating a specific example of the processing conversion difference in the Line and Space (L & S) pattern. FIG. 12A is a diagram illustrating an L & S pattern in which wirings having a width W are formed with an interval S therebetween. FIG. 12B is formed by the processes of FIG. 2B, FIG. 3A and FIG. 3B using the mask MK1 obtained by correcting the optical proximity effect of the design pattern shown in FIG. It is a graph which shows what kind of processing conversion difference wiring trench IT1 has. The processing conversion difference indicated by a negative value in FIG. 12B indicates that the width of the wiring trench IT1 formed in FIG. 3B is different from the width of the resist pattern RP1 formed in FIG. Shows how thin it is. In FIGS. 12A and 12B, W1 = 66 [nm]. As shown in FIG. 12B, the machining conversion difference is 13 nm at the fine pitch (S = 66 [nm]) (6. half of the difference shown at “X” in FIG. 12A). On the other hand, it is 20 nm or more at a sparse pitch (S = saturated at about 600 nm or more).

  FIG. 13 is a diagram illustrating a specific example of the processing conversion difference in the T-shaped butting pattern. FIG. 13A shows a T-shaped butting pattern. In FIG. 13A, a first wiring IP1 and a second wiring IP2 are formed. The arrangement and shape of the first wiring IP1 and the second wiring IP2 shown in FIG. 13A are the same as the arrangement and shape of the first wiring IP1 and the second wiring IP2 shown in FIG. . In FIG. 13A, the width of the first wiring is W1. The length of the second edge portion IE2 is L2, and the distance between the first edge portion IE1 and the second edge portion IE2 is S. In the pattern shown in FIG. 13A, a second wiring IP2 ′ is formed in addition to the second wiring IP2. The second wiring IP2 ′ has the same shape as the second wiring IP2. Further, the second wiring IP2 ′ is in a position symmetrical with the second wiring IP2 with the center in the longitudinal direction of the first wiring IP1 as the target axis. FIG. 13B is formed by the processes of FIGS. 2B, 3A, and 3B using the mask MK1 obtained by correcting the optical proximity effect of the design pattern shown in FIG. 13A. It is a graph which shows what kind of processing conversion difference wiring trench IT1 has. The processing conversion difference indicated by a negative value in FIG. 13B indicates that the width of the wiring trench IT1 formed in FIG. 3B is different from the width of the resist pattern RP1 formed in FIG. Shows how thin it is. In FIGS. 13A and 13B, W1 = 66 [nm] and S = 66 [nm]. As shown in FIG. 11B, the processing conversion difference is indicated by a value at a fine pitch in FIG. 12B (approximately 13 nm (“x” in FIG. 13A) when L2 = 1000 [nm]. In other words, L2 = 660 [nm] is a value at a sparse pitch in FIG. 10B (about 21 nm (“×” in FIG. 13A). In the displayed part, it is about 10.5 nm, which is half of that)). When the value of L2 is decreased, the absolute value of the processing conversion difference is further increased.

  The preliminary correction distance δ can be determined by measuring the processing conversion difference as described above. In particular, the preliminary correction distance δ may be increased as the length of the second edge portion IE2 becomes shorter from the relationship between L2 and the processing conversion difference in FIG.

  Next, a specific example of the optical proximity effect correction in step S108 will be described with reference to FIG. FIG. 14 is a diagram showing a specific example of the arrangement and shape of the first wiring IP1 and the second wiring IP2 in the optical proximity effect correction design data obtained by correcting the correction extraction design data shown in FIG. is there. The first wiring IP1, the second wiring IP2, and the second sub wiring IPS2 in FIG. 14 correspond to the first wiring IP1, the second wiring IP2, and the second sub wiring IPS2 in FIGS. 9A and 10A, respectively. To do.

  Next, a specific example of the effect of the pattern correction method according to this embodiment will be described with reference to FIGS. FIG. 15A is a diagram for explaining the effect when the wiring data correction in step S106 in the present embodiment is performed. FIG. 15B is a diagram for explaining a comparison with the effect shown in FIG. In FIGS. 15A and 15B, the hatched pattern in the portion surrounded by the broken line on the left side shows the resist pattern RP1 formed in the step shown in FIG. On the other hand, in FIG. 15 (a) and FIG. 15 (b), the pattern drawn with diagonal lines in the portion surrounded by the broken line on the right side shows the wiring trench IT1 formed in the step shown in FIG. 3 (b). . In FIG. 15A, the pattern formed in FIGS. 15A and 15B is corrected for the wiring data in step S106 for the mask MK1 in FIG. 15A, whereas in FIG. The only difference is that the wiring data is not corrected.

  Comparing FIG. 15A and FIG. 15B, in FIG. 15A, the width of the first wiring IP1 at the reference portion REF is equal to the resist pattern RP1 (inside the broken line on the left side of FIG. 15A) and the wiring. In any of the grooves IT1 (inside the broken line on the right side of FIG. 15A), there is almost no difference from the width in the other part of the first wiring IP1. In contrast, in FIG. 15B, the width of the first wiring IP1 at the reference portion REF is within the resist pattern RP1 (inside the broken line on the left side of FIG. 15B) and the wiring groove IT1 (inside the broken line on the right side of FIG. In both cases, the width is narrower than the width of the other portion of the first wiring IP1. From this comparison, it can be said that the wiring data correction in step S106 can prevent the width of the reference portion REF of the first wiring IP1 from being shorter than the width of the other portion of the first wiring IP1.

(Second Embodiment)
The flowchart and the block diagram showing the configuration of the pattern correction apparatus in the second embodiment are the same as those in FIGS. This embodiment will be described with reference to FIGS.

  In the present embodiment, step S104 includes a step of extracting third wiring data. The third wiring data is data indicating the arrangement and shape of the third wiring. The third wiring includes a third edge. The third edge portion is opposed to the first edge portion in parallel with the first edge via the second wire in the vicinity of the first wire and the second wire. The third edge extends outward from the second edge when viewed from the first edge. Further, in the present embodiment, step S106 includes a step of measuring the distance between the first edge and the third edge. And in this embodiment, the distance which moves a reference | standard part in process S106 is determined according to the distance between a 1st edge part and a 3rd edge part. Except for the above points, the present embodiment is the same as the first embodiment.

  The design data generation unit DGU generates design data as in the first embodiment. And the design data acquisition part DOU acquires design data similarly to 1st Embodiment (process S102). The design data acquisition unit DOU outputs the design data acquired by the design data acquisition unit DOU to the design data storage unit DST. The design data storage unit DST stores design data. Then, the design data storage unit DST outputs a design data output signal indicating that the design data has been output to the wiring data extraction unit IEU.

  The wiring data extraction unit IEU reads design data from the design data storage unit DST after receiving a design data output signal in accordance with an instruction input to the input unit INU. At this time, the wiring data extraction unit IEU also reads the extraction condition data from the extraction condition storage unit EST. The extraction condition data is data stored in the extraction condition storage unit EST. The extraction condition data is data indicating conditions that the first wiring data, the second wiring data, and the third wiring data should satisfy. The conditions to be satisfied by the first wiring data and the second wiring data are the same as those in the first embodiment. On the other hand, the third wiring data needs to satisfy the following conditions. In other words, the third wiring indicated by the third wiring data has the third edge. The third edge faces the first edge in parallel with the first wiring in the vicinity of the first wiring and the second wiring. The third edge extends outward from the second edge when viewed from the first edge. Data indicating a wiring pattern satisfying the above conditions is defined as third wiring data. The wiring data extraction unit IEU extracts the first wiring data, the second wiring data, and the third wiring data from the design data according to the extraction condition data read by the wiring data extraction unit IEU (Step S104). The extracted first wiring data, second wiring data, and third wiring data are extracted design data. The wiring data extraction unit IEU outputs the extracted design data to the design data storage unit DST. The design data storage unit DST stores extracted design data. Then, the wiring data extraction unit IEU outputs an extraction design data output signal indicating that the extraction design data has been output to the wiring data correction unit IAU.

  The wiring data correction unit IAU reads the extracted design data from the design data storage unit DST after receiving the extracted design data output signal in accordance with the instruction input to the input unit INU. At this time, the wiring data correction unit IAU also reads the reference data from the reference storage unit RST. The reference data is data stored in the reference storage unit RST. The reference data includes various parameters of the first wiring, the second wiring, and the third wiring (for example, the distance between the first edge and the second edge, the distance between the first edge and the third edge). , The length of the second edge) and a preliminary correction distance δ corresponding to the reference value (details of the preliminary correction distance δ will be described later). The wiring data correction unit IAU measures various parameters of the first wiring, the second wiring, and the third wiring with respect to the extracted design data. Then, the wiring data correction unit IAU searches the reference data for reference values corresponding to these measured values. After this search, the wiring data correction unit IAU corrects the extracted design data (step S106). Specifically, the wiring data correction unit IAU corrects the extracted design data by moving the reference portion of the first wiring to the second edge side. A reference | standard part is a part which opposes a 2nd edge part among the 1st edge parts of 1st wiring. At this time, the reference portion is moved toward the second edge side by the preliminary correction distance δ corresponding to the searched reference value. The corrected extracted design data becomes corrected extracted design data. Then, the wiring data correction unit IAU outputs the correction extraction design data to the design data storage unit DST. The design data storage unit DST stores correction extraction design data. Further, the wiring data correction unit IAU outputs a correction design data output signal indicating that the correction extraction design data has been generated to the optical proximity effect correction unit OAU.

  The preliminary correction distance δ included in the reference data stored in the reference storage unit RST is determined as follows. That is, the correction extraction design data is subjected to optical proximity effect correction in step S108. The preliminary correction distance δ is the distance between the first edge and the second edge in the wiring trench IT1 formed in FIG. 3B when the mask MK1 based on the design data subjected to the optical proximity effect correction is used. The interval between them can be determined to be substantially the same between the reference portion of the first edge and the other portions of the first edge. The meaning that the interval between the first edge and the second edge in the wiring groove IT1 becomes “substantially the same” in the reference portion of the first edge and the other portions of the first edge is shown in FIG. 6 as described above. The preliminary correction distance δ is equal to the distance between the first edge and the second edge in the wiring groove IT1 formed in the step of FIG. It can be calculated by conducting an experiment in advance under various conditions of the preliminary correction distance δ whether the other parts are substantially the same. Based on this experimental result, the reference storage unit RST determines the preliminary correction distance δ, the width W1 of the first wiring, the width W2 of the second wiring, the length L2 of the second edge, and the first edge, The distance S between the second edge and the distance SS between the first edge and the third edge may be stored in association with each other.

  In the present embodiment, the preliminary correction distance δ may be decreased as the distance SS between the first edge and the third edge becomes shorter. This is based on the knowledge obtained from FIG. According to FIG. 12B, the processing conversion difference decreases as the inter-wiring distance decreases, that is, as the wiring density increases. Therefore, the preliminary correction distance δ is reduced based on the fact that the density of the first wiring, the second wiring, and the third wiring increases as the distance SS between the first edge and the third edge decreases. Also good.

  In the present embodiment, as in the first embodiment, the extracted design data may be corrected in step S106 by moving the peripheral portion of the first wiring to the second wiring side. The peripheral portion is a portion of the first edge portion of the first wiring that is adjacent to the reference portion and located on the reference portion side. At this time, the peripheral portion is moved toward the second edge side by the preliminary correction distance δ ′. In this case, the reference data includes various parameters of the first wiring and the second wiring (for example, the distance between the first edge and the second edge, the distance between the first edge and the third edge). , The length of the second edge) and a preliminary correction distance δ ′ corresponding to this reference value. The preliminary correction distance δ ′ and the length of the peripheral portion are determined as follows. That is, the correction extraction design data is subjected to optical proximity effect correction in step S108. The preliminary correction distance δ ′ and the length of the peripheral portion are the first edge portion in the wiring trench IT1 formed in FIG. 3B when the mask MK1 based on the design data subjected to the optical proximity effect correction is used. Can be determined to be substantially flat. The meaning that the first edge portion in the wiring trench IT1 becomes “substantially flat” is as described above with reference to FIG.

  The optical proximity effect correction unit OAU corrects the optical proximity effect on the correction design data as in the first embodiment (step S108).

  A mask having a pattern based on the optical proximity effect correction design data obtained by the above steps is manufactured. The mask manufactured in this way is used for the mask MK1 in the process shown in FIG. In this case, since the mask MK1 is manufactured through step S106 that takes into account the processing conversion difference due to the third wiring, it is possible to form a wiring pattern with higher accuracy than in the first embodiment.

  Next, a specific example of the pattern correction method in this embodiment will be described. First, a specific example of the extracted design data in step S104 will be described with reference to FIG.

  FIG. 16 is a diagram illustrating an example of the arrangement and shape of the first wiring IP1, the second wiring IP2, and the third wiring IP3 in the extracted design data. In this example, the T-shaped second wiring IP2 is abutted against the first wiring IP1. The arrangement and shape of the first wiring IP1, the second wiring IP2, and the second sub wiring IPS2 are the same as the arrangement and shape of the first wiring IP1, the second wiring IP2, and the second sub wiring IPS2 shown in FIG. The same. In the example shown in FIG. 16, the third wiring IP3 is provided. The third wiring IP3 includes a third edge portion IE3. The third edge portion IE3 faces the first edge portion IE1 in parallel in the vicinity of the first wiring IP1 and the second wiring IP2 via the second wiring IP2. The third edge portion IE3 extends outward from the second edge portion IE2 when viewed from the first edge portion IE1. On the other hand, the second wiring IP2 includes a fourth edge portion IE4. The fourth edge portion IE4 is an edge portion that faces the second edge portion IE2 in parallel with the second wiring IP2. The distance between the third edge portion IE3 and the fourth edge portion IE4 is D. The distance between the first edge portion IE1 and the third edge portion IE3 is SS.

  The example shown in FIG. 16 is merely an example of the present embodiment, and the arrangement and shape of the first wiring IP1, the arrangement and shape of the second wiring IP2, and the arrangement and shape of the third wiring are not limited thereto. For example, in this embodiment, as shown in FIG. 9B, an example in which the L-shaped second wiring IP2 hits the first wiring IP1 (ΔL1 = 0 and ΔL2> 0 or ΔL1> 0 and ΔL2 = 0). The present embodiment further includes an example (ΔL1 = ΔL2 = 0) in which the rod-like second wiring IP2 hits the first wiring IP1.

  Next, a specific example of a method for determining the preliminary correction distance δ of the reference unit REF will be described with reference to FIG. FIG. 17 is a diagram illustrating the reference data stored in the reference storage unit RST in a table format. As shown in FIG. 17, the preliminary correction distance δ for moving the reference portion REF includes the width W1 of the first wiring IP1, the width W2 of the second wiring IP2, the length L2 of the second wiring IP2, and the first edge. The distance S between the portion IE1 and the second edge portion IE2 and the distance D between the third edge portion IE3 and the fourth edge portion IE4 may be determined. The preliminary correction distance δ may be determined not by the distance D between the third edge portion IE3 and the fourth edge portion IE4 but by the relationship with the distance SS between the first edge portion IE1 and the third edge portion IE3. The distance D is used in the table shown in FIG. In the example shown in FIG. 16, D can be defined by D = SS− (S + W2). Therefore, setting the preliminary correction distance δ in relation to D means that the preliminary correction distance δ in relation to SS. Is synonymous with As shown in the table in FIG. 15, the preliminary correction distance δ may be changed according to the distance D between the third edge portion IE3 and the fourth edge portion IE4. When the distance D is large, that is, when the wiring density is small, the preliminary correction distance δ is increased according to the tendency shown in FIG. 12B (pattern 1 in FIG. 17). On the other hand, when the distance D is small, that is, when the wiring density is large, the preliminary correction distance δ is reduced according to the tendency shown in FIG. 12B (pattern 2 in FIG. 17). When the second wiring IP2 is a rod-shaped wiring (ΔL1 = ΔL2 = 0), the distance D between the third edge portion IE3 and the fourth edge portion IE4 cannot be defined. Therefore, in this case, the preliminary correction distance δ does not use the relationship with the distance D but uses the relationship with the distance SS between the first edge portion IE1 and the fourth edge portion IE4. Further, the table in FIG. 17 may define the relationship between the various parameters described above and the preliminary correction distance δ ′.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

SM1 Semiconductor device TR1 Transistor SB1 Semiconductor substrate EI1 Element isolation film SD1 Source / drain region ES1 Etching stopper film ES2 Etching stopper film SC1 Silicide layer GI1 Gate insulating film GE1 Gate electrode SW1 Side wall IL1 Interlayer insulating film IL2 Interlayer insulating film CP1 Contact plug VP1 Via plug IC1 Wiring WI1 Wiring layer HM1 Hard mask AR1 Antireflection film RS1 Resist film MK1 Mask LT1 Optical RP1 Resist pattern IT1 Wiring groove BM1 Barrier metal film ML1 Metal film INU Input unit DGU Design data generation unit DOU Design data acquisition unit IEU Wiring data extraction Part IAU Wiring data correction part OAU Optical proximity effect correction part DST Design data storage part EST Extraction condition storage part RST Reference storage part OST Optical proximity effect compensation Storage section IP1 First wiring IP2 Second wiring IP2 ′ Second wiring IP3 Third wiring IPS2 Second subwiring IE1 First edge IE2 Second edge IE3 Third edge IE4 Fourth edge IE21 Edge IE22 Edge IES1 edge IES2 edge REF reference part PER1 peripheral part PER2 peripheral part

Claims (18)

Forming an insulating film on the substrate;
Forming a resist film on the insulating film;
Forming a resist pattern by exposing the resist film through a mask formed with a pattern;
Forming a wiring groove in the insulating film by etching using the resist film on which the resist pattern is formed as a mask;
Embedding a conductive film in the wiring trench;
A mask pattern correction method used in a method for manufacturing a semiconductor device comprising:
Obtaining design data indicating a design pattern in plan view of the wiring groove;
From the design data,
First wiring data indicating the arrangement and shape of the first wiring having a first edge formed in a straight line;
Second wiring data indicating the arrangement and shape of a second wiring that is parallel to the first edge and has a second edge shorter than the first edge;
Extracting the
A step of correcting the design data by moving a reference portion facing the second edge of the first edge of the first wiring toward the second edge;
A pattern correction method comprising: The pattern correction method according to claim 1,
A step of correcting an optical proximity effect on the design data corrected in the step of correcting the first wiring data;
The distance by which the reference portion is moved in the step of correcting the design data is the distance between the first edge and the second edge in the wiring groove formed in the step of forming the wiring groove. Is a pattern correction method in which the reference portion of the first edge and the other portions of the first edge are determined to be substantially the same. The pattern correction method according to claim 2,
In the step of correcting the design data, a peripheral portion adjacent to the reference portion and located on the reference portion side of the first edge portion of the first wiring is set on the second edge portion side. A step of correcting the design data by moving,
The distance for moving the peripheral portion in the step of correcting the design data and the length of the peripheral portion are such that the first edge portion in the wiring groove formed in the step of forming the wiring groove is substantially flat. A pattern correction method determined to be. The pattern correction method according to claim 1,
The pattern correction method, wherein the step of correcting the design data increases a distance for moving the reference portion as the length of the second edge portion becomes shorter. The pattern correction method according to claim 1,
The step of extracting the first wiring data and the second wiring data is opposed to the first edge in parallel with the first edge in the vicinity of the first wiring and the second wiring; and Extracting the third wiring data indicating the arrangement and shape of the third wiring including the third edge extending outward from the second edge when viewed from the first edge;
The step of correcting the design data includes measuring a distance between the first edge and the third edge;
The pattern correction method in which the distance for moving the reference portion in the step of correcting the design data is determined according to the distance between the first edge and the third edge. The pattern correction method according to claim 5,
The pattern correction method, wherein the distance by which the reference portion is moved in the step of correcting the design data decreases as the distance between the first edge and the third edge decreases. Forming an insulating film on the substrate;
Forming a resist film on the insulating film;
Forming a resist pattern by exposing the resist film through a mask formed with a pattern;
Forming a wiring groove in the insulating film by etching using the resist film on which the resist pattern is formed as a mask;
Embedding a conductive film in the wiring trench;
A method for manufacturing the mask used in a method for manufacturing a semiconductor device comprising:
Obtaining design data indicating a design pattern in plan view of the wiring groove;
From the design data,
First wiring data indicating the arrangement and shape of the first wiring having a first edge formed in a straight line;
Second wiring data indicating the arrangement and shape of a second wiring that is parallel to the first edge and has a second edge shorter than the first edge;
Extracting the
A step of correcting the design data by moving a reference portion facing the second edge of the first edge of the first wiring toward the second edge;
A method for manufacturing a mask comprising: It is a manufacturing method of the mask according to claim 7,
A step of correcting an optical proximity effect on the design data corrected in the step of correcting the first wiring data;
The distance by which the reference portion is moved in the step of correcting the design data is the distance between the first edge and the second edge in the wiring groove formed in the step of forming the wiring groove. However, the manufacturing method of the mask determined so that it may become substantially the same in the said reference | standard part of the said 1st edge part, and the other part of the said 1st edge part. It is a manufacturing method of the mask according to claim 8, Comprising:
In the step of correcting the design data, a peripheral portion adjacent to the reference portion and located on the reference portion side of the first edge portion of the first wiring is set on the second edge portion side. A step of correcting the design data by moving,
The distance for moving the peripheral portion in the step of correcting the design data and the length of the peripheral portion are such that the first edge portion in the wiring groove formed in the step of forming the wiring groove is substantially flat. A method for manufacturing a mask that has been determined to be. It is a manufacturing method of the mask according to claim 7,
The step of correcting the design data is a mask manufacturing method in which the distance to which the reference portion is moved is increased as the length of the second edge portion becomes shorter. It is a manufacturing method of the mask according to claim 7,
The step of extracting the first wiring data and the second wiring data is opposed to the first edge in parallel with the first edge in the vicinity of the first wiring and the second wiring; and Extracting the third wiring data indicating the arrangement and shape of the third wiring including the third edge extending outward from the second edge when viewed from the first edge;
The step of correcting the design data includes measuring a distance between the first edge and the third edge;
The distance for moving the reference portion in the step of correcting the design data is a mask manufacturing method in which the distance between the first edge and the third edge is determined according to the distance. It is a manufacturing method of the mask according to claim 11, Comprising:
The method of manufacturing a mask, wherein the distance by which the reference portion is moved in the step of correcting the design data decreases as the distance between the first edge portion and the third edge portion decreases. Forming an insulating film on the substrate;
Forming a resist film on the insulating film;
Forming a resist pattern by exposing the resist film through a mask formed with a pattern;
Forming a wiring groove in the insulating film by etching using the resist film on which the resist pattern is formed as a mask;
Embedding a conductive film in the wiring trench;
With
The pattern formed on the mask is
Obtaining design data indicating a design pattern in plan view of the wiring groove;
From the design data,
First wiring data indicating the arrangement and shape of the first wiring having a first edge formed in a straight line;
Second wiring data indicating the arrangement and shape of a second wiring that is parallel to the first edge and has a second edge shorter than the first edge;
Extracting the
A step of correcting the design data by moving a reference portion facing the second edge of the first edge of the first wiring toward the second edge;
A method of manufacturing a semiconductor device formed through the process. A method for a semiconductor device according to claim 13, comprising:
A step of correcting an optical proximity effect on the design data corrected in the step of correcting the first wiring data;
The distance by which the reference portion is moved in the step of correcting the design data is the distance between the first edge and the second edge in the wiring groove formed in the step of forming the wiring groove. Is determined so that the reference portion of the first edge portion and the other portions of the first edge portion are substantially the same. 15. A method of manufacturing a semiconductor device according to claim 14,
In the step of correcting the design data, a peripheral portion adjacent to the reference portion and located on the reference portion side of the first edge portion of the first wiring is set on the second edge portion side. A step of correcting the design data by moving,
The distance for moving the peripheral portion in the step of correcting the design data and the length of the peripheral portion are such that the first edge portion in the wiring groove formed in the step of forming the wiring groove is substantially flat. A method of manufacturing a semiconductor device determined to be A method of manufacturing a semiconductor device according to claim 13,
The step of correcting the design data is a method of manufacturing a semiconductor device, wherein the distance by which the reference portion is moved is increased as the length of the second edge portion becomes shorter. A method of manufacturing a semiconductor device according to claim 13,
The step of extracting the first wiring data and the second wiring data is opposed to the first edge in parallel with the first edge in the vicinity of the first wiring and the second wiring; and Extracting the third wiring data indicating the arrangement and shape of the third wiring including the third edge extending outward from the second edge when viewed from the first edge;
The step of correcting the design data includes measuring a distance between the first edge and the third edge;
The method of manufacturing a semiconductor device, wherein a distance for moving the reference portion in the step of correcting the design data is determined according to the distance between the first edge portion and the third edge portion. A method of manufacturing a semiconductor device according to claim 17,
The method for manufacturing a semiconductor device, wherein the distance for moving the reference portion in the step of correcting the design data decreases as the distance between the first edge and the third edge decreases.

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