JP2012190842A - Manufacturing method of semiconductor device - Google Patents

Abstract

The present invention provides a technique capable of predicting a finished shape of a pattern after wafer processing with high accuracy.
The amount of each reaction product is expressed by the plasma emission intensity, and these are normalized. Then, the standardized plasma emission intensity of each reaction product is converted into predicted value correction data, and optimal predicted value correction data corresponding to the aperture ratio is selected from these predicted value correction data. By adding the predicted value correction data to the predicted value data obtained from the monitoring signal, the finished shape of the pattern is predicted.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device manufacturing technique, and more particularly to a technique effective when applied to a wafer processing process using a dry etching technique.

  In recent years, the process window has been reduced with the miniaturization of circuit patterns, and high-precision process control is required. In order to realize this requirement, an increase in the frequency of workmanship inspection after the wafer processing is unavoidable, and there is a problem that the productivity of semiconductor products is reduced and the cost is increased. Therefore, establishment of VM (Virtual Metrology) technology, which is a technology for predicting the result after wafer processing, is expected.

  For example, in JP 2009-152269 A (Patent Document 1), the amount of deposits incident on the processing side wall represented by the product of the reaction product flux and the solid angle is determined according to the wafer aperture ratio and the solid angle of the local pattern. A control unit for controlling the shape simulator to be controlled, calculating the correction value of the etching process by comparing the database obtained by the shape simulator and the actual value detected from the etching state during dry etching, and instructing the correction value to the etching chamber And a technique for correcting the parameters of the etching process in real time.

  Japanese Patent Laid-Open No. 2007-250902 (Patent Document 2) discloses a method of measuring electrical data while etching a predetermined number of model creation wafers, and determining a CD (Critical Dimension) shift amount of each model creation wafer. Actual measurement, moving average value of each CD shift amount is obtained, a correlation equation between operation data and moving average CD shift amount is obtained by using a multivariate analysis method, and the operation when other wafers are etched. A method for predicting a CD shift amount by applying data to a correlation equation is disclosed.

  Japanese Patent Laid-Open No. 2006-83433 (Patent Document 3) discloses an etching end point time corresponding to a harmonic component by using a sensor that measures a harmonic component of plasma reactance and a predetermined linear function. A plasma etching apparatus including a calculating means is disclosed, and it is described that a predetermined linear function is selected from a plurality of linear functions according to a pattern aperture ratio of a thin film to be plasma etched. .

  Japanese Patent Laid-Open No. 2005-12218 (Patent Document 4) discloses an etching process in combination with in-situ monitoring (for example, spectroscopy, interference measurement, scattering measurement, reflectance measurement, etc.) performed during the etching process. On the other hand, a method for monitoring an etching process by using measurement information (for example, critical dimension, layer thickness, etc.) provided by Exsau Chu is disclosed.

  Japanese Patent Laid-Open No. 2005-183756 (Patent Document 5) discloses an opening of a pressure control valve for controlling the pressure in a reaction chamber to a set pressure and a bias voltage generated when high-frequency power is applied in a plasma processing apparatus. A technique for constantly monitoring with an equipment monitoring system and confirming a plasma state in a reaction chamber is disclosed.

JP 2009-152269 A JP 2007-250902 A JP 2006-83433 A JP 2005-12218 A JP 2005-183756 A

  For example, in a dry etching system equipped with an APC (Advanced Process Control) system, if VM technology is not applied, the inspection of the previous lot is completed, and after waiting for feedback of information such as the finished dimensions, the next The lot is processed. Therefore, there is a waiting time until the inspection of the previous lot is completed. On the other hand, when the VM technology is applied, a predicted value of the finished dimensions of all the wafers in one lot can be obtained in real time. Therefore, compared with the case where the VM technology is not applied, TAT (Turn Around Time) can be shortened.

  Therefore, the present inventors have reduced the number of performance inspections after wafer processing by applying a VM technology that predicts the performance of a wafer from a monitoring signal of a dry etching apparatus. However, with the VM technology using only the monitoring signal, it is difficult to control the dimensions on the nanometer (nm) scale. Therefore, in the microfabrication process that requires nanometer scale accuracy, the number of workmanship inspections after wafer processing is reduced. I can't.

  Also, in a dry etching process for forming a multilayer wiring, processing is usually performed under one etching condition regardless of the product type or wiring layer if the standard of the processing shape (for example, dimensions) of the wiring pattern is the same. ing. However, even if the processing pattern standard of the wiring pattern is the same, if the pattern aperture ratio or the pattern density is different, the VM technology using only the monitoring signal has a lower accuracy of predicting the finished shape after wafer processing. Problems arise. In particular, the difference in pattern aperture ratio affects the etching process (processing pressure, etching gas species, reaction product flux, flow rate, etc.), and as the wiring pattern becomes finer and the wafer diameter increases, the influence is increased. Has become prominent.

  An object of the present invention is to provide a technique capable of predicting the finished shape of a pattern after wafer processing with high accuracy.

  It is another object of the present invention to provide a technique capable of improving product productivity and reducing costs by reducing the number of pattern inspections after wafer processing.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in this application, an embodiment of a representative one will be briefly described as follows.

  This embodiment is a method for manufacturing a semiconductor device, which includes a step of processing a film to be etched formed on a main surface of a substrate by dry etching using a resist pattern as a mask to form a pattern of the film to be etched. The amount of each reaction product generated by dry etching is represented by the plasma emission intensity, and after normalizing these, the plasma emission intensity of each normalized reaction product is converted into predicted value correction data, By selecting the optimal predicted value correction data corresponding to the aperture ratio from these predicted value correction data, and introducing this optimal predicted value correction data into the predicted value data obtained from the monitoring signal, the pattern performance is achieved. The shape is predicted.

  Among the inventions disclosed in the present application, effects obtained by one embodiment of a representative one will be briefly described as follows.

  It is possible to provide a technique capable of predicting a finished shape of a pattern after wafer processing with high accuracy. Also, by reducing the number of pattern inspections after wafer processing, product productivity can be improved and costs can be reduced.

It is the schematic explaining the structure of each calculating part with which the dry etching apparatus by one embodiment of this invention is equipped. (A) and (b) are schematic plan views of a resist pattern formed on an etching target film when the aperture ratio is small (the aperture ratio is about 5%), and when the aperture ratio is large (the aperture ratio is about It is a schematic plan view of a resist pattern formed on a film to be etched (55%). (A) And (b) is a schematic diagram explaining the mode of generation of the reaction product by etching when the aperture ratio is small and the mode of generation of the reaction product by etching when the aperture ratio is large. It is process drawing explaining the procedure of the normalization of the plasma light emission data in the light emission data calculation process part by one embodiment of this invention. The SiO ₂ film according to an embodiment of the present invention is a graph showing an example of the relationship between the plasma emission intensity obtained when dry etching the emission wavelength (wavelength region 200 to 800 nm). The SiO ₂ film according to an embodiment of the present invention is a graph showing changes with time of plasma emission intensity obtained when the dry etching. The SiO ₂ film according to an embodiment of the present invention is a diagram summarizing the mean value of the mean and normalized plasma emission intensity of the plasma emission intensity of each reaction product obtained upon dry etching. Mean value data (I ₁ , I ₂ , I ₃ , I ₄ ) and aperture ratio data of plasma emission intensity of each normalized reaction product (CO, SiF, CF, CN) according to an embodiment of the present invention It is a graph explaining the relationship. Relationship between average value data (I ₃ , I ₄ ) of plasma emission intensity of each normalized reaction product (CF, CN) used when aperture ratio is small according to an embodiment of the present invention and aperture ratio data FIG. Relationship between the average value data (I ₁ , I ₂ ) of plasma emission intensity of each normalized reaction product (CO, SiF) used when the aperture ratio is large according to an embodiment of the present invention and the aperture ratio data FIG. (A) and (b) are graphs showing the state of fluctuation of the predicted value obtained from only the monitoring signal of the width of the wiring groove and the actual value of the width of the wiring groove as the number of processed wafers increases, and the wiring groove, respectively. It is a graph which shows the relationship between the predicted value calculated | required only from the monitoring signal of width | variety, and the measured value of the width | variety of a wiring groove | channel. (A) and (b) are graphs showing the fluctuation of the predicted value obtained from the equation (1) of the wiring groove width and the actual measurement value of the wiring groove width as the number of wafers processed increases, and wiring It is a graph which shows the relationship between the predicted value calculated | required from Formula (1) of the width | variety of a groove | channel, and the measured value of the width | variety of a wiring groove | channel. (A) and (b) are graphs showing the state of fluctuation of the predicted value obtained from only the monitoring signal of the wiring groove depth and the measured value of the wiring groove depth as the number of wafers processed increases, and It is a graph which shows the relationship between the predicted value calculated | required only from the monitoring signal of the depth of a wiring groove | channel, and the measured value of the depth of a wiring groove | channel. (A) And (b) is a graph which shows the mode of the fluctuation | variation of the predicted value calculated | required from Formula (2) of the depth of a wiring groove | channel accompanying the increase in the number of wafer processing, respectively, and the measured value of the wiring groove depth, It is a graph which shows the relationship between the predicted value calculated | required from Formula (2) of the depth of a wiring groove | channel, and the measured value of the depth of a wiring groove | channel. (A) and (b) are graphs showing the variation of the predicted value obtained from the equation (9) of the width of the wiring groove and the actual value of the width of the wiring groove as the number of processed wafers increases, and wiring It is a graph which shows the relationship between the predicted value calculated | required from Formula (9) of the width | variety of a groove | channel, and the measured value of the width | variety of a wiring groove | channel. (A) And (b) is a graph which shows the mode of the fluctuation | variation of the predicted value calculated | required from Formula (10) of the depth of a wiring groove | channel accompanying the increase in the number of wafer processes, respectively, and the measured value of a wiring groove depth, It is a graph which shows the relationship between the predicted value calculated | required from Formula (10) of the depth of a wiring groove | channel, and the measured value of the depth of a wiring groove | channel. It is principal part sectional drawing of the semiconductor device in the manufacturing process explaining the manufacturing method of the semiconductor device by one embodiment of this invention. FIG. 18 is an essential part cross-sectional view of the same portion as that of FIG. 17 of the semiconductor device during a manufacturing step following that of FIG. 17; FIG. 19 is an essential part cross-sectional view of the same portion as that in FIG. 17 of the semiconductor device during a manufacturing step following that of FIG. 18; FIG. 20 is an essential part cross-sectional view of the same portion as that of FIG. 17 of the semiconductor device during a manufacturing step following that of FIG. 19; It is process drawing which shows an example of the flow of the etching process by one embodiment of this invention. FIG. 21 is an essential part cross-sectional view of the same portion as that of FIG. 17 of the semiconductor device during a manufacturing step following that of FIG. 20; FIG. 23 is an essential part cross-sectional view of the same portion as that of FIG. 17 of the semiconductor device during a manufacturing step following that of FIG. 22; FIG. 24 is an essential part cross-sectional view of the same portion as that of FIG. 17 of the semiconductor device during a manufacturing step following that of FIG. 23; FIG. 25 is an essential part cross-sectional view of the same portion as that of FIG. 17 of the semiconductor device during a manufacturing step following that of FIG. 24; FIG. 26 is an essential part cross-sectional view of the same portion as that of FIG. 17 of the semiconductor device during a manufacturing step following that of FIG. 25; FIG. 27 is an essential part cross-sectional view of the same portion as that of FIG. 17 of the semiconductor device during a manufacturing step following that of FIG. 26;

  In the following embodiments, when necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other, and one is the other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number. Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  Further, in the drawings used in the following embodiments, hatching may be added to make the drawings easy to see even if they are plan views. In the following embodiments, the term “wafer” is mainly a Si (Silicon) single crystal wafer. However, not only that, but also an SOI (Silicon On Insulator) wafer and an integrated circuit are formed thereon. Insulating film substrate or the like. The shape includes not only a circle or a substantially circle but also a square, a rectangle and the like.

  In all the drawings for explaining the following embodiments, components having the same function are denoted by the same reference numerals in principle, and repeated description thereof is omitted. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment)
A method for predicting the performance of a pattern after wafer processing using the VM technique according to this embodiment will be described below. In the present embodiment, description will be given by taking as an example the prediction of the performance of a wiring pattern. Specifically, when a damascene wiring is formed, a finished shape of a wiring groove formed in the insulating film is predicted by a dry etching method.

  FIG. 1 is a schematic diagram illustrating the configuration of each calculation unit provided in the dry etching apparatus according to the present embodiment.

  The dry etching apparatus 1 includes a monitoring signal storage unit 2 and a light emission intensity detection unit 3, and further includes a statistical processing unit 4, a light emission data calculation processing unit 5, and an aperture ratio data calculation processing unit 6. A model formula calculation processing unit 7 is provided. The processing units 4, 5, 6, and 7 provided outside may be provided inside the dry etching apparatus 1.

The dry etching apparatus 1 is a single wafer etching apparatus. Inside the chamber 8 provided in the dry etching apparatus 1, a lower electrode 9 and an upper electrode 10 are arranged in parallel at a predetermined distance, and a wafer 11 is arranged on the lower electrode 9. A plasma 12 is created between the lower electrode 9 and the upper electrode 10, and ions or radicals generated in the plasma 12 are used to form an etching target film formed on the wafer 11 (in this embodiment, an insulating film made of SiO _2. The film) is etched.

  In the monitoring signal storage unit 2, for example, a set value (hereinafter referred to as an etching process) for controlling a plasma state during an etching process such as a lower electrode temperature (temp), a lower electrode potential difference (Vpp), and an upper matching capacitor position (C1). The monitoring signal).

  The emission intensity detection unit 3 acquires emission intensity data of plasma generated during an etching process in a predetermined wavelength region (for example, 200 to 800 nm).

  The statistical processing unit 4 has a correlation with the finished shape of the wiring pattern (width and depth of the wiring groove) after the wafer treatment in the monitoring signal at the time of the etching process, and is necessary for the prediction formula of the finished shape of the wiring pattern. Extract multiple monitoring signals.

  The emission data calculation processing unit 5 obtains time-series data of plasma emission intensity at each emission wavelength of each reaction product from the plasma emission intensity data obtained by the emission intensity detection unit 3, and further calculates average value data. Ask. Then, after normalizing the average value data, the average value data of the plasma emission intensity of each normalized reaction product is converted into predicted value correction data that can be introduced into the prediction formula.

In the aperture ratio data calculation processing unit 6, the optimum predicted value correction data (f) according to the aperture ratio obtained from the wafer information from the predicted value correction data of each reaction product obtained in the light emission data calculation processing unit 5. ₂ (Ix), g ₂ (Ix)).

In the model formula calculation processing unit 7, the optimum predicted value correction data selected according to the aperture ratio in the aperture ratio data calculation processing unit 6 is used as the predicted value data of the finished shape of the wiring pattern obtained using only the monitoring signal. A predicted value of the finished shape of the wiring pattern is obtained by a prediction formula (formula (1) and formula (2)) to which (f ₂ (Ix), g ₂ (Ix)) is added. A plurality of monitoring signals extracted by the statistical processing unit 4 are used to calculate the predicted value data of the finished shape of the wiring pattern obtained using only the monitoring signal.

Wiring groove width = f (temp, Vpp, C1) + (Δmask dimension) + f ₂ (Ix) Equation (1)
The depth of the wiring groove = g (Vpp, temp) + g 2 (Ix) Equation (2)
Next, a predictive formula for the finished shape of the wiring pattern obtained by adding the optimum predicted value correction data selected according to the aperture ratio to the predicted value data of the finished shape of the wiring pattern obtained using only the monitoring signal (formula ( 1) and formula (2)) will be described in detail.

  First, the predicted value data of the finished shape of the wiring pattern obtained using only the monitoring signal will be described.

  Experiments and statistics using an experimental design using monitoring signals extracted by the statistical processing unit 4, such as the lower electrode temperature (temp), the lower electrode potential difference (Vpp), and the position of the upper matching capacitor (C1). Analysis is performed to obtain predicted value data of a finished shape of the wiring pattern (width and depth of the wiring groove) after the wafer processing. In the present embodiment, multiple regression analysis is used for statistical analysis.

  The width of the wiring groove is predicted value data (f (temp) obtained from statistical analysis of the lower electrode temperature (temp), the lower electrode potential difference (Vpp), and the position (C1) of the upper matching capacitor in the monitoring signal of the dry etching apparatus. , Vpp, C1)) and mask dimension data (Δ mask dimension). The mask dimension data is, for example, an error between a resist pattern dimension and a mask dimension (design dimension).

  Further, the depth of the wiring trench is predicted by predicted value data (g (Vpp, temp)) obtained from statistical analysis of the lower electrode potential difference (Vpp) and the lower electrode temperature (temp) in the monitoring signal of the dry etching apparatus. It is possible.

  Next, the prediction formulas (formula (1) and formula (2)) for the finished shape of the wiring pattern to which the optimum predicted value correction data selected according to the aperture ratio is added will be described in detail.

  Here, the aperture ratio is an amount determined by the ratio or area ratio of the etched portion of the entire surface to be processed. For example, when etching an insulating film, if 80% of the total surface area of the insulating film is covered with a resist pattern and 20% is exposed, the aperture ratio is 20%.

  2A and 2B show a schematic diagram when the aperture ratio is small (the aperture ratio is about 5%) and a schematic diagram when the aperture ratio is large (the aperture ratio is about 55%), respectively. In FIG. 2, reference numeral 14 denotes a resist pattern formed on the etching target film, and reference numeral 15 denotes an opening from which the etching target film is exposed.

  When the aperture ratio is relatively large, the amount of reaction products generated by etching increases. When the aperture ratio is relatively small, the amount of reaction products generated by etching decreases. In general, when the aperture ratio is relatively large, the etching rate tends to be slow, and when the aperture ratio is relatively small, the etching rate tends to be fast. Accordingly, the plasma emission intensity or the etching rate changes as the aperture ratio changes variously.

For example, when a SiO ₂ film is used as the insulating film, if a CF-based gas and an inert gas Ar are used, the etching of the SiO ₂ film proceeds by the reaction of formula (3).

SiO + CF → SiF + CO Formula (3)
Therefore, etching produces, for example, CO, SiF, CF, CN, etc. as reaction products, and these amounts depend on the aperture ratio.

FIGS. 3A and 3B show the generation of reaction products by etching when the aperture ratio is relatively small and the generation of reaction products by etching when the aperture ratio is relatively large, respectively. The schematic diagram to explain is shown. In the opening 15 of the resist pattern 14 formed on the SiO ₂ film 13, SiO ₂ film 13 is etched by the etching gas species (CF *). This etching produces reaction products such as CO and SiF. When the aperture ratio is relatively large, the amount of CO and SiF is large, and when the aperture ratio is relatively small, the amount of CO and SiF and the like is small. .

  That is, the amount of reaction product generated by etching is proportional to the product of the etching amount per unit time (etching rate) and the aperture ratio, as shown in Equation (4).

(Amount of reaction product) ∝ (etching rate) × (opening ratio) Equation (4)
In the present embodiment, the amount of each reaction product is expressed by the plasma emission intensity and normalized. Then, the normalized plasma emission intensity data of each reaction product is converted into predicted value correction data that can be added to the prediction formula. Among them, the optimum prediction value correction data corresponding to the aperture ratio is selected, and this optimum prediction value correction data is added to the prediction value data of the finished shape of the wiring pattern obtained using only the monitoring signal ( Formulas (1) and (2)) are constructed, and the finished shape of the wiring pattern is predicted using the prediction formulas (Formula (1) and Formula (2)).

  The plasma emission intensity of each reaction product that is the basis of the predicted value correction data is subjected to data processing by the light emission data calculation processing unit 5, and the optimal predicted value correction data is determined by the aperture ratio data calculation processing unit 6 according to the aperture ratio. The finished shape of the selected wiring pattern is calculated by using the prediction formulas (formula (1) and formula (2)) in which the optimal prediction value correction data is introduced in the model formula calculation processing unit 7.

Next, standardization of the plasma emission intensity of each reaction product in the emission data calculation processing unit 5 will be described in detail with reference to FIGS. FIG. 4 is a process diagram for explaining the procedure for normalizing the plasma emission data in the emission data calculation processing unit 5, and FIG. 5 shows the plasma emission intensity and emission wavelength (wavelength region 200) obtained when the SiO ₂ film is dry-etched. FIG. 6 is a graph showing the change over time in plasma emission intensity obtained when dry etching the SiO ₂ film, and FIG. 7 is dry etching the SiO ₂ film. It is the figure which put together the average value of the plasma luminescence intensity of each reaction product obtained at the time, and the average value of the normalized plasma luminescence intensity.

  (Step P1 in FIG. 4) The light emission data calculation processing unit 5 monitors the plasma light emission intensity in the wavelength region of 200 to 800 nm acquired by the light emission intensity detection unit 3 until the wafer processing is completed at intervals of ± 1 nm, for example. .

  (Step P2 in FIG. 4) Time-series data of plasma emission intensity at each emission wavelength of each reaction product (CO, SiF, CF, CN) is obtained. As shown in FIG. 5, in the wavelength region of 200 to 800 nm, for example, CO emits plasma emission intensity at an emission wavelength of about 483 nm, and Ar obtains plasma emission intensity at an emission wavelength of about 750 nm.

(Step P3 in FIG. 4) The average value data (I _CO , I _SiF , I _CF , I _CN ) of the plasma emission intensity at each emission wavelength of each reaction product (CO, SiF, CF, CN) is obtained. As shown in FIG. 6, the time series data, for example, after performing smoothing such as moving average, does not include the time during which plasma emission intensity is not stable for several seconds at the start and end of plasma discharge, Ask for data.

(Step P4 in FIG. 4) The average value data (I _CO , I _SiF , I _CF , I _CN ) of the plasma emission intensity at the respective emission wavelengths of each reaction product (CO, SiF, CF, CN) is obtained from Ar. Normalization is performed using the average value data (I _Ar ) of the plasma emission intensity at the emission wavelength. For example, the average value data (I ₁ , I ₂ , I ₃ , I ₄ ) of the plasma emission intensity at each emission wavelength of each normalized reaction product (CO, SiF, CF, CN) is expressed by the formula (5) to It can be expressed as equation (8).

I ₁ = I _CO / I _Ar formula (5)
I ₂ = I _SiF / I _Ar formula (6)
I ₃ = I _CF / I _Ar formula (7)
I ₄ = I _CN / I _Ar formula (8)
FIG. 7 shows average data (I _CO , I _SiF , I _CF , I _CN ) of plasma emission intensity at each emission wavelength of each reaction product (CO, SiF, CF, _CN ) and each reaction product normalized. The average value data (I ₁ , I ₂ , I ₃ , I ₄ ) of the plasma emission intensity at each emission wavelength of the product (CO, SiF, CF, CN) is summarized.

(Step P5 in FIG. 4) The result of the wiring pattern obtained by using only the monitoring signal, the average value data of the plasma emission intensity at each emission wavelength of each normalized reaction product (CO, SiF, CF, CN) as can be corrected by adding the predicted value data of the shape, the predicted value correction data _{(f 2 (Ix): x} = 1~4 and _{g 2 (Ix): x =} 1~4) to convert.

Next, a method for selecting optimum predicted value correction data in the aperture ratio data calculation processing unit 6 will be described with reference to FIGS. FIG. 8 shows average value data (I ₁ , I ₂ , I ₃ , I ₄ ) (plasma emission data) and aperture ratio data of plasma emission intensity of each normalized reaction product (CO, SiF, CF, CN). FIG. 9 is a graph illustrating the relationship between the plasma emission intensity average values (I ₃ , I ₄ ) (plasma) of each normalized reaction product (CF, CN) used when the aperture ratio is small FIG. 10 is a graph for explaining the relationship between the emission data) and the aperture ratio data. FIG. 10 is a graph showing average data (I, plasma emission intensity of each reaction product (CO, SiF) normalized when the aperture ratio is large). ₁ , I ₂ ) and the aperture ratio data.

As shown in FIG. 8, the average value data (I ₁ , I ₂ , I ₃ , I ₄ ) of the plasma emission intensity of each normalized reaction product (CO, SiF, CF, CN) and the aperture ratio data There is a correlation between them.

When the aperture ratio is relatively small, the ratio of the exposed area of the etching target film (SiO ₂ film) is small and the ratio of the resist pattern is large. Therefore, the average value data (I ₃ ) of the plasma emission intensity of the reaction product (CF) of the etching gas species or the average value data (I ₄ ) of the plasma emission intensity of the reaction product (CN) of the etching gas species is large. Become. Therefore, as shown in FIG. 9, from the average value data (I ₁ , I ₂ , I ₃ , I ₄ ) of the plasma emission intensity of each normalized reaction product (CO, SiF, CF, CN), the average value is obtained. Data (I ₃ ) or average value data (I ₄ ) is selected. Then, these values are converted to obtain predicted value correction data, and optimum predicted value correction data is introduced as a correction value into the predicted value data of the finished shape of the wiring pattern obtained using only the monitoring signal.

On the other hand, when the aperture ratio is relatively large, the ratio of the exposed area of the etching target film (SiO ₂ film) is large and the ratio of the resist pattern is small. Therefore, the average value data of the emission intensity of the average value data of the plasma emission intensity of the reaction product of SiO ₂ constituting the film to be etched (CO) _{(I 1)} or SiO ₂ in the reaction product (SiF) _{(I 2} ) Becomes larger. Therefore, as shown in FIG. 10, from the average value data (I ₁ , I ₂ , I ₃ , I ₄ ) of the plasma emission intensity of each normalized reaction product (CO, SiF, CF, CN), the average value is obtained. Data (I ₁ ) or average value data (I ₂ ) is selected. Then, these values are converted to obtain predicted value correction data, and optimum predicted value correction data is introduced as a correction value into the predicted value data of the finished shape of the wiring pattern obtained using only the monitoring signal.

  As described above, by selecting the optimum predicted value correction data to be introduced into the prediction formula (formula (1) and formula (2)) according to the aperture ratio, the work pattern shape of the wiring pattern can be predicted with high accuracy. Can do.

  Next, the prediction result of the finished shape of the wiring groove calculated in the model formula calculation processing unit 7 will be described with reference to FIGS.

In the formula (1) for predicting the width of the wiring groove, the predicted value is corrected to predicted value data (f (temp, Vpp, C1) + (Δ mask size)) of the finished shape of the wiring pattern obtained using only the monitoring signal. Add data f ₂ (Ix). f ₂ (Ix) is an optimum value selected from the aperture ratio among the predicted value correction data f ₂ (I ₁ ), f ₂ (I ₂ ), f ₂ (I ₃ ), and f ₂ (I ₄ ). Predictive value correction data is introduced. Similarly, in the formula (2) for predicting the depth of the wiring groove, the predicted value correction data g ₂ (Ix) is used as the predicted value data (g (Vpp, temp)) of the work pattern shape obtained using only the monitoring signal. G ₂ (Ix) includes predicted value correction data g ₂ (I ₁ ), g ₂ (I ₂ ), g ₂ (I ₃ ), and g ₂ (I ₄ ) from the aperture ratio. The optimum predicted value correction data to be selected is introduced.

For example, when processing a wafer having an aperture ratio of 5%, predicted value correction data f ₂ (I ₁ ), f ₂ (I ₂ ), f ₂ (I ₃ ), Of f ₂ (I ₄ ), predicted value correction data f ₂ (I ₃ ) or f ₂ (I ₄ ) is added, and predicted value correction data g ₂ (I ₁ ), g ₂ (I ₂ ), g ₂ ( I _3), of g 2 _{(I 4),} added to the predicted value correction data _g 2 _{(I 3)} or _g 2 _{(I 4).}

Further, when processing a wafer having an aperture ratio of 55%, predicted value correction data f ₂ (I ₁ ), f ₂ (I ₂ ), f ₂ (I ₃ ), obtained by the light emission data calculation processing unit 5, f _{2 (I 4)} of the predicted value correction data _f 2 _{(I 1)} or _{f 2 (I} 2) was added, the predicted value correction data _{g 2 (I 1), g} 2 (I 2), g 2 ( Predicted value correction data g ₂ (I ₁ ) or g ₂ (I ₂ ) is added out of I ₃ ) and g ₂ (I ₄ ).

  FIG. 11A is a graph showing the state of fluctuation of the predicted value obtained from only the monitoring signal of the width of the wiring groove and the actual value of the width of the wiring groove as the number of processed wafers increases, and FIG. FIG. 10 is a graph showing a relationship between a predicted value obtained only from a wiring groove width monitoring signal and an actual measured value of the wiring groove width; FIG. 12A is a graph showing the variation of the predicted value obtained from the equation (1) of the wiring groove width and the actual value of the wiring groove width as the number of wafers processed increases. b) is a graph showing the relationship between the predicted value obtained from the wiring groove width formula (1) and the actual measured value of the wiring groove width;

  As shown in FIG. 11 and FIG. 12, the predicted value of the width of the wiring groove obtained from the formula (1) in which the predicted value correction data is introduced is larger than the predicted value of the width of the wiring groove obtained from only the monitoring signal. It can be seen that the prediction accuracy is high.

  FIG. 13A is a graph showing the state of fluctuation of the predicted value obtained from only the monitoring signal of the wiring groove depth and the measured value of the wiring groove depth as the number of processed wafers increases, and FIG. ) Is a graph showing the relationship between the predicted value obtained only from the monitoring signal of the wiring groove depth and the measured value of the wiring groove depth. FIG. 14A is a graph showing how the predicted value obtained from the equation (2) of the wiring groove depth and the measured value of the wiring groove depth fluctuate as the number of wafers processed increases. FIG. 14B is a graph showing the relationship between the predicted value obtained from the equation (2) of the wiring groove depth and the measured value of the wiring groove depth.

  As shown in FIG. 13 and FIG. 14, the predicted value of the wiring groove depth obtained from the formula (2) in which the predicted value correction data is introduced, rather than the predicted value of the wiring groove depth obtained from only the monitoring signal. It can be seen that the prediction accuracy is higher.

  In the present embodiment, since multiple regression analysis is used for statistical analysis, if there is a correlation between independent variables (explanatory variables), a multicollinearity state occurs and the predicted value becomes unstable. In the present embodiment, since plasma emission data has a strong correlation, when a plurality of prediction value correction data is introduced into the prediction equations (Equation (1) and Equation (2)), the accuracy of the prediction value decreases.

FIG. 15 shows a predicted value of the width of the wiring trench obtained by using the formula (9) in which, for example, two predicted value correction data f ₃ (Ix, Iy) are introduced, and FIG. 16 shows, for example, two predicted value corrections The predicted value of the depth of the wiring groove obtained by using equation (10) in which data g ₃ (Ix, Iy) is introduced is shown. FIG. 15A is a graph showing the variation of the predicted value obtained from the equation (9) of the wiring groove width and the actual measurement value of the wiring groove width as the number of wafers processed increases, and FIG. These are graph figures which show the relationship between the predicted value calculated | required from Formula (9) of the width | variety of a wiring groove | channel, and the measured value of the width | variety of a wiring groove | channel. FIG. 16A is a graph showing how the predicted value obtained from the equation (10) of the wiring groove depth and the measured value of the wiring groove depth fluctuate as the number of wafers processed increases. FIG. 16B is a graph showing the relationship between the predicted value obtained from the wiring groove depth equation (10) and the actual measured value of the wiring groove depth.

Wiring groove width = f (temp, Vpp, C1) + (Δ mask dimension) + f ₂ (Ix, Iy) Equation (9)
Wiring groove depth = g (Vpp, temp) + g ₂ (Ix, Iy) Equation (10)
As shown in FIGS. 15 and 16, when two pieces of predicted value correction data are used, the width and depth of the wiring trench are larger than when one piece of predicted value correction data is used (the above-described FIGS. 12 and 14). The accuracy of the predicted value is low. Therefore, it is desirable to use one selected predicted value correction data in a prediction formula using multiple regression analysis for statistical analysis.

  As described above, according to the present embodiment, the optimum predicted value correction data corresponding to the aperture ratio is selected from the predicted value correction data obtained from the plasma emission data of each reaction product, and this is monitored. By using prediction formulas (Equation (1) and Equation (2)) in addition to the predicted value data of the finished shape of the wiring pattern obtained using only the signal, the finished shape of the wiring pattern obtained using only the monitoring signal It is possible to predict with higher accuracy than the prediction of, for example, nanometer-scale accuracy. Thereby, the inspection frequency after wafer processing can be reduced, and productivity can be improved and costs can be reduced.

  Next, the manufacturing method of the semiconductor device according to the present embodiment will be described in the order of steps with reference to FIGS. Various semiconductor elements such as a field effect transistor, a resistance element, and a capacitor element are formed in the semiconductor device. In this embodiment, a CMIS (Complementary Metal Insulator Oxide Semiconductor) device is exemplified. FIGS. 17 to 20 and FIGS. 22 to 27 are cross-sectional views of main parts of the semiconductor device, and FIG. 21 is a process diagram showing an example of the flow of the etching process. In the following description, a MISFET (Metal Insulator Semiconductor Field Effect Transistor) representing a field effect transistor is abbreviated as MIS, a p-channel type MISFET is abbreviated as pMIS, and an n-channel type MISFET is abbreviated as nMIS.

  First, as shown in FIG. 17, for example, a semiconductor substrate (semiconductor plate having a substantially circular plane called a wafer) 21 made of single crystal silicon is prepared. Next, an isolation portion 22 made of an insulating film is formed in the element isolation region on the main surface of the semiconductor substrate 21. Subsequently, an impurity exhibiting p-type conductivity is ion-implanted into the semiconductor substrate 21 in a region where the nMIS is formed (nMIS formation region) to form a p-type well 23. Similarly, a region where the pMIS is formed ( An n-type well 24 is formed by ion-implanting an impurity having n-type conductivity into the semiconductor substrate 21 in the pMIS formation region.

  Next, a gate insulating film 25 is formed on the main surface of the semiconductor substrate 21 (the respective surfaces of the p-type well 23 and the n-type well 24). Subsequently, an nMIS gate electrode 26n is formed on the gate insulating film 25 in the nMIS formation region, and similarly, a pMIS gate electrode 26p is formed on the gate insulating film 25 in the pMIS formation region.

  Next, sidewalls 27 are formed on the respective sidewalls of the nMIS gate electrode 26n and the pMIS gate electrode 26p. Subsequently, an impurity having n-type conductivity is ion-implanted into the p-type well 23 on both sides of the nMIS gate electrode 26n, and the n-type semiconductor region 28 functioning as the source / drain of the nMIS is formed in the gate electrode 26n and the sidewall 27. In a self-aligned manner. Similarly, an impurity exhibiting p-type conductivity is ion-implanted into the n-type well 24 on both sides of the gate electrode 26p of the pMIS, and the p-type semiconductor region 29 functioning as the source / drain of the pMIS is formed into the gate electrode 26p and the sidewall 27. In a self-aligned manner.

  Next, as shown in FIG. 18, after forming the insulating film 30 on the main surface of the semiconductor substrate 21, the insulating film 30 is processed by dry etching using the resist pattern as a mask to form connection holes 31. The connection hole 31 is formed in a necessary portion such as on the n-type semiconductor region 28 or the p-type semiconductor region 29. Subsequently, a plug 32 having, for example, a tungsten (W) film as a main conductor is formed in the connection hole 31.

  Next, a stopper insulating film 33 and a wiring forming insulating film 34 are sequentially formed on the main surface of the semiconductor substrate 21. The stopper insulating film 33 is a film that serves as an etching stopper when a groove is formed in the insulating film 34, and a material having an etching selectivity with respect to the insulating film 34 is used. The stopper insulating film 33 can be a silicon nitride film formed by, for example, plasma CVD (Chemical Vapor Deposition), and the insulating film 34 can be a silicon oxide film formed by, for example, plasma CVD. The stopper insulating film 33 and the insulating film 34 are formed with a first layer wiring M1 described below.

  Next, the first layer wiring M1 is formed by a single damascene method.

  First, as shown in FIG. 19, a resist pattern RP is formed on the insulating film 34. Here, in the resist pattern RP formed in a predetermined region, the resist pattern dimension is measured, and an error (Δmask dimension) between the resist pattern dimension and the mask dimension (design dimension) is obtained.

  Next, as shown in FIG. 20, the insulating film 34 and the stopper insulating film 33 are sequentially dry-etched using the resist pattern RP as a mask to form concave wiring grooves in predetermined regions of the stopper insulating film 33 and the insulating film 34. 35 is formed.

Here, as shown in FIG. 21, the monitoring signal and the plasma emission data are obtained in real time during the etching process. Further, respective predicted value correction data obtained from the plasma emission intensity of each reaction product is obtained, and optimum predicted value correction data corresponding to the aperture ratio is obtained from these. In formula (1) for predicting the finished shape of the wiring groove 35, an error (Δ mask dimension) between the predicted value data (f (temp, Vpp, C1)) obtained from the monitoring signal and the mask dimension is optimal. By inputting the predicted value correction data (f ₂ (Ix)), the predicted value of the width of the wiring trench 35 can be obtained in real time. Similarly, the predicted value data (g (Vpp, temp)) obtained from the monitoring signal and the optimal predicted value correction data (g ₂ (Ix)) are expressed in Equation (2) for predicting the finished shape of the wiring groove 35. Can be obtained in real time.

  The obtained predicted value of the width and depth of the wiring trench 35 are fed back (FB) to the dry etching apparatus, and the set value of the etching process is corrected in real time, while the stopper insulating film 33 of each wafer and The insulating film 34 is etched. When the predicted value of the width of the wiring groove 35 and the predicted value of the depth are deviated from the standard value, the width and depth of the wiring groove 35 can be quickly returned to the standard value by adjusting the etching process conditions. Therefore, an increase in processing defects of the wiring groove 35 can be suppressed.

  Next, as shown in FIG. 22, the register pattern RP is removed. Here, as shown in FIG. 21 described above, the finished dimensions of the width and depth of the wiring groove 35 may be measured.

  Next, as shown in FIG. 23, a barrier metal film 36 is formed on the main surface of the semiconductor substrate 21. The barrier metal film 36 is, for example, a titanium nitride (TiN) film, a tantalum (Ta) film, or a tantalum nitride (TaN) film. Subsequently, a Cu seed layer (not shown) is formed on the barrier metal film 36 by CVD or sputtering, and a Cu plating film 37 is further formed on the seed layer by electrolytic plating. The inside of the wiring groove 35 is buried with the Cu plating film 37.

  Next, as shown in FIG. 24, the Cu plating film 37, the seed layer, and the barrier metal film 36 in a region other than the inside of the wiring groove 35 are removed by a CMP method, and the first layer having the Cu film as a main conductor is removed. An eye wiring M1 is formed. In this embodiment, the Cu film, which is the main conductor constituting the first-layer wiring M1, is formed by the electrolytic plating method, but may be formed by the CVD method, the sputtering method, the sputter reflow method, or the like. .

  Next, a second layer wiring is formed by a dual damascene method.

  First, as shown in FIG. 25, a cap insulating film 38, an interlayer insulating film 39, and a stopper insulating film 40 for wiring formation are sequentially formed on the main surface of the semiconductor substrate 21. A connection hole is formed in the cap insulating film 38 and the interlayer insulating film 39 as described later. The cap insulating film 38 is made of a material having an etching selectivity with respect to the interlayer insulating film 39, and can be a silicon nitride film formed by, for example, a plasma CVD method. Further, the cap insulating film 38 has a function as a protective film for preventing diffusion of Cu constituting the first layer wiring M1. The interlayer insulating film 39 can be a TEOS (Tetra Ethyl Ortho Silicate) film formed by, for example, a plasma CVD method. The stopper insulating film 40 is made of an insulating material having an etching selectivity with respect to the interlayer insulating film 39 and a wiring forming insulating film deposited on the stopper insulating film 40 later, and is formed by, for example, a plasma CVD method. A silicon nitride film can be formed.

  Next, the stopper insulating film 40 is processed by dry etching using a resist pattern for hole formation as a mask. Here, similarly to the dry etching process when forming the wiring trench 35 described above, a predicted value of the pattern finished shape is obtained and fed back to the dry etching apparatus to correct the set value of the etching process in real time. However, the stopper insulating film 40 of each wafer is processed.

  Subsequently, an insulating film 41 for wiring formation is formed on the stopper insulating film 40. The insulating film 41 can be a TEOS film, for example.

  Next, the insulating film 41 is processed by dry etching using a resist pattern for wiring trench formation as a mask. At this time, the stopper insulating film 40 functions as an etching stopper. Here, similarly to the dry etching process when forming the wiring trench 35 described above, a predicted value of the pattern finished shape is obtained and fed back to the dry etching apparatus to correct the set value of the etching process in real time. However, the insulating film 41 of each wafer is processed.

  Subsequently, the interlayer insulating film 39 is processed by dry etching using the stopper insulating film 40 and the wiring groove forming resist pattern as a mask. At this time, the cap insulating film 38 functions as an etching stopper. Subsequently, by removing the exposed cap insulating film 38 by dry etching, a connection hole 42 is formed in the cap insulating film 38 and the interlayer insulating film 39, and a wiring groove 43 is formed in the stopper insulating film 40 and the insulating film 41. The

  Next, as shown in FIG. 26, the second-layer wiring M <b> 2 is formed inside the connection hole 42 and the wiring groove 43. The second layer wiring M2 is made of a barrier metal layer and a Cu film as a main conductor, and a connecting member for connecting the wiring M2 and the first layer wiring M1 as a lower layer wiring is a second layer wiring. It is formed integrally with M2. First, a barrier metal film is formed on the main surface of the semiconductor substrate 21 including the insides of the connection holes 42 and the wiring grooves 43. The barrier metal film is, for example, a titanium nitride (TiN) film, a tantalum (Ta) film, or a tantalum nitride (TaN) film. Subsequently, a Cu seed layer is formed on the barrier metal film by a CVD method or a sputtering method, and a Cu plating film is further formed on the seed layer by an electrolytic plating method. The inside of the connection hole 42 and the wiring groove 43 is embedded with a Cu plating film. Subsequently, the Cu plating film, the seed layer, and the barrier metal film in regions other than the connection hole 42 and the wiring groove 43 are removed by CMP to form a second-layer wiring M2.

  Thereafter, as shown in FIG. 27, for example, an upper layer wiring is formed by the same method as the above-described second layer wiring M2. FIG. 27 illustrates a semiconductor device in which wirings M3, M4, M5, and M6 of the third to sixth layers are formed.

  In the semiconductor device according to the present embodiment, for example, a relatively thin Cu wiring having a minimum line width of 70 nm or less is adopted as the first-layer wiring M1 to the fourth-layer wiring M4. For the wiring M5 and the sixth-layer wiring M6, for example, a relatively thick Cu wiring having a minimum line width of 100 nm or more is employed. In addition, the thickness, aperture ratio, pattern density, and the like of the insulating film in which the wiring trench is formed vary depending on each wiring layer. However, since a prediction formula in which predicted value correction data is added to the wiring groove pattern of each wiring layer can be established, the predicted value of the finished shape of the wiring groove pattern of each wiring layer can be obtained with high accuracy.

  Next, a silicon nitride film 44 is formed on the sixth-layer wiring M 6, and a silicon oxide film 45 is formed on the silicon nitride film 44. The silicon nitride film 44 and the silicon oxide film 45 function as a passivation film that prevents moisture and impurities from entering from the outside and suppresses the transmission of α rays.

  Next, the silicon nitride film 44 and the silicon oxide film 45 are processed by etching using the resist pattern as a mask to expose a part of the sixth-layer wiring M6 (bonding pad portion). Subsequently, a bump base electrode 46 made of a laminated film such as a gold (Au) film and a nickel (Ni) film is formed on the exposed sixth layer wiring M6, and gold (Au) or gold is formed on the bump base electrode 46. By forming the bump electrode 47 made of solder or the like, the semiconductor device according to the present embodiment is almost completed. The bump electrode 47 serves as an external connection electrode. Thereafter, the wafer is cut into individual semiconductor chips and mounted on a package substrate or the like, but the description thereof is omitted.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

For example, in the above-described embodiment, the case where the present invention is applied to the etching process of the SiO ₂ film has been described, but the film to be etched is not limited to this. For example, it can be applied to a Si film or an Al film.

  In the case of the Si film, the etching of the Si film proceeds by the reaction of the formula (11).

Si + Cl → SiCl Formula (11)
Accordingly, for example, SiCl is generated as a reaction product by etching, and therefore, predicted value correction data can be obtained using the plasma light emission data and the aperture ratio data of SiCl. Thereby, the pattern shape after wafer processing can be predicted with high accuracy.

  In the case of an Al film, the etching of the Al film proceeds by the reaction of the formula (12).

Al + Cl → AlCl Formula (12)
Therefore, for example, AlCl is generated as a reaction product by etching, so that predicted value correction data can be obtained by using plasma emission data and aperture ratio data of AlCl. Thereby, the pattern shape after wafer processing can be predicted with high accuracy.

  The present invention can be applied to an etching process using a dry etching apparatus for manufacturing a semiconductor device.

DESCRIPTION OF SYMBOLS 1 Dry etching apparatus 2 Monitoring signal memory | storage part 3 Light emission intensity detection part 4 Statistical processing part 5 Light emission data arithmetic processing part 6 Aperture ratio data arithmetic processing part 7 Model type arithmetic processing part 8 Chamber 9 Lower electrode 10 Upper electrode 11 Wafer 12 Plasma 13 SiO ₂ film 14 Resist pattern 15 Opening 21 Semiconductor substrate 22 Separating part 23 P-type well 24 N-type well 25 Gate insulating film 26n, 26p Gate electrode 27 Side wall 28 N-type semiconductor region 29 P-type semiconductor region 30 Insulating film 31 Connection Hole 32 Plug 33 Stopper insulating film 34 Insulating film 35 Wiring groove 36 Barrier metal film 37 Copper (Cu) plating film 38 Cap insulating film 39 Interlayer insulating film 40 Stopper insulating film 41 Insulating film 42 Connection hole 43 Wiring groove 44 Silicon nitride film 45 Silicon oxide film 46 Bump foundation electrode 47 Bump electricity Pole M1-M6 Wiring RP Resist pattern

Claims (6)

A method for manufacturing a semiconductor device comprising the following steps:
(A) forming an etching target film on the main surface of the substrate;
(B) forming a resist pattern on the film to be etched;
(C) In a dry etching apparatus, a step of processing the etching target film using the resist pattern as a mask to form a pattern made of the etching target film;
Here, in the step (c),
Prediction formula including predicted value data obtained from the monitoring signal and optimum predicted value correction data selected according to the aperture ratio from the respective predicted value correction data obtained from the plasma emission intensity of each reaction product Thus, the finished shape of the pattern is predicted, and the set value of the etching process is corrected in real time.   2. The method of manufacturing a semiconductor device according to claim 1, wherein when the aperture ratio is relatively small, the predicted value correction obtained from the plasma emission intensity of the reaction product of the etching gas species is used as the optimal predicted value correction data. A method for manufacturing a semiconductor device, characterized by using data.   2. The method of manufacturing a semiconductor device according to claim 1, wherein when the aperture ratio is relatively large, the optimum predicted value correction data includes the predicted value obtained from the plasma emission intensity of the reaction product of the film to be etched. A method of manufacturing a semiconductor device, wherein correction data is used. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the optimum predicted value correction data is obtained by a process including the following steps:
(C1) monitoring plasma emission intensity data in a predetermined emission wavelength range;
(C2) obtaining plasma emission intensity of each reaction product from the emission intensity data of the plasma;
(C3) a step of obtaining average value data of plasma emission intensity of each reaction product;
(C4) normalizing the average value data;
(C5) converting the normalized average value data into the predicted value correction data;
(C6) A step of selecting the optimum predicted value correction data according to the aperture ratio from the predicted value correction data.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the prediction formula includes an error between a dimension of the resist pattern and a dimension of a mask used when forming the resist pattern in the step (b). A method of manufacturing a semiconductor device. 2. The method of manufacturing a semiconductor device according to claim 1, wherein when the film to be etched is a SiO ₂ film, the plasma emission intensity of CO, SiF, CF, and CN is obtained,
When the aperture ratio is relatively small, the predicted value correction data obtained from the plasma emission intensity of CF or CN is used as the optimal predicted value correction data,
When the aperture ratio is relatively large, the predicted value correction data obtained from the plasma emission intensity of CO or SiF is used as the optimum predicted value correction data.

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