JP2014146654A - Laminated electronic component - Google Patents

Laminated electronic component Download PDF

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JP2014146654A
JP2014146654A JP2013013360A JP2013013360A JP2014146654A JP 2014146654 A JP2014146654 A JP 2014146654A JP 2013013360 A JP2013013360 A JP 2013013360A JP 2013013360 A JP2013013360 A JP 2013013360A JP 2014146654 A JP2014146654 A JP 2014146654A
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conductor layer
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JP6117557B2 (en
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Masahiro Nishigaki
政浩 西垣
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Kyocera Corp
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Abstract

PROBLEM TO BE SOLVED: To provide a laminated electronic component capable of suppressing the occurrence of delamination even when an inner conductor layer is multilayered.SOLUTION: A laminated electronic component includes: a laminated part 9 where a ceramic insulator layer 5 and an inner conductor layer 7 are alternately laminated to form a multilayer; and ceramic cover layers 11 provided on both end faces in the lamination direction of the laminated part 9, respectively. In the inner conductor layer 7 in contact with the cover layer 11 among the inner conductor layers 7, a metal oxide phase 13 constituting the inner conductor layer 7 is formed so as to penetrate through the inner conductor layer 7 in the thickness direction.

Description

本発明は、各種電子回路を構成する際に使用される積層型電子部品に関する。   The present invention relates to a multilayer electronic component used when configuring various electronic circuits.

従来より、複数の絶縁体層と複数の内部導体層とを積み重ねた後、一体的に焼成して作製された積層型電子部品が知られている(例えば、特許文献1を参照)。このような積層型電子部品において、形状が略等しくかつ重なり合う内部導体層を数枚積層した場合、特に、積層方向の最上層および最下層に位置する内部導体層とその主面に積層されたカバー層との間でデラミネーションが発生しやすいという問題がある。その原因は、内部導体層とカバー層とが例えば金属とセラミックスというように材質が全く異なるため接着し難いことや、内部導体層とセラミック絶縁体層との熱膨張係数が大きく異なるため、温度変化において内部導体層と絶縁体層との収縮量の差による歪みが大きくなるからである。   2. Description of the Related Art Conventionally, there has been known a multilayer electronic component manufactured by stacking a plurality of insulator layers and a plurality of internal conductor layers and then firing them integrally (for example, see Patent Document 1). In such a multilayer electronic component, when several internal conductor layers having substantially the same shape and overlapping are laminated, in particular, the inner conductor layers located at the uppermost layer and the lowermost layer in the lamination direction and the cover laminated on the main surface thereof There is a problem that delamination is likely to occur between the layers. The reason is that the inner conductor layer and the cover layer are difficult to adhere because the materials are completely different, for example, metal and ceramics, and the thermal expansion coefficients of the inner conductor layer and the ceramic insulator layer are greatly different. This is because distortion due to the difference in shrinkage between the inner conductor layer and the insulator layer increases.

特開2011−129841号公報JP 2011-129841 A

従って、本発明の目的は、内部導体層を多層化してもデラミネーションの発生を抑制できる積層型電子部品を提供することにある。   Accordingly, an object of the present invention is to provide a multilayer electronic component that can suppress the occurrence of delamination even if the inner conductor layer is made multilayer.

本発明の積層型電子部品は、セラミック絶縁体層と内部導体層とが交互に多層に積層された積層部と、該積層部の積層方向の両端面にそれぞれ設けられたセラミック製のカバー層とを有する積層型電子部品において、前記内部導体層のうち前記カバー層に接している内部導体層には、該内部導体層を構成する金属の酸化物相が前記内部導体層を厚み方向に貫通するように形成されていることを特徴とする。   The multilayer electronic component of the present invention includes a laminated portion in which ceramic insulator layers and internal conductor layers are alternately laminated, and a ceramic cover layer provided on each end surface of the laminated portion in the lamination direction. In the multilayer electronic component having the inner conductive layer, the inner conductor layer in contact with the cover layer among the inner conductor layers has a metal oxide phase constituting the inner conductor layer penetrating the inner conductor layer in the thickness direction. It is formed as follows.

本発明によれば、内部導体層を多数積層しても、デラミネーションの発生しない積層型電子部品を得ることができる。   According to the present invention, it is possible to obtain a multilayer electronic component in which delamination does not occur even when a large number of internal conductor layers are stacked.

図1は、本発明の積層型電子部品の一実施形態を示す概略断面図である。FIG. 1 is a schematic cross-sectional view showing an embodiment of a multilayer electronic component of the present invention. 図1におけるカバー層付近(A部)を拡大した概略断面図である。It is the schematic sectional drawing which expanded the cover layer vicinity (A part) in FIG.

図1は、本発明の積層型電子部品の一実施形態を示す概略断面図である。図2は、図1におけるカバー層付近(A部)を拡大した概略断面図である。   FIG. 1 is a schematic cross-sectional view showing an embodiment of a multilayer electronic component of the present invention. 2 is an enlarged schematic cross-sectional view of the vicinity of the cover layer (part A) in FIG.

本発明の積層型電子部品の一例として、以下のように積層型のコンデンサを例にして説明する。なお、本発明はコンデンサに限らず、アクチュエータ、フィルタ、インダクタなど、セラミック絶縁体層と内部導体層とが多層に積層された電子部品に幅広く適用できることは言うまでもない。   As an example of the multilayer electronic component of the present invention, a multilayer capacitor will be described below as an example. Needless to say, the present invention is not limited to capacitors and can be widely applied to electronic parts in which ceramic insulator layers and internal conductor layers are laminated in multiple layers, such as actuators, filters, and inductors.

本実施形態の積層型電子部品は、電子部品本体1の対向する両端部に外部電極3を有し
ている。電子部品本体1は、セラミック絶縁体層5と内部導体層7とが交互に多層に積層された積層部9と、積層部9の積層方向の両方の端面9aにそれぞれ設けられたセラミック製のカバー層11とを有している。
The multilayer electronic component of the present embodiment has external electrodes 3 at opposite ends of the electronic component body 1. The electronic component body 1 includes a laminated portion 9 in which ceramic insulator layers 5 and internal conductor layers 7 are alternately laminated, and a ceramic cover provided on both end faces 9a of the laminated portion 9 in the laminating direction. Layer 11.

ここで、内部導体層7のうち、カバー層11に接している内部導体層7には、この内部導体層7を構成する金属の酸化物相13がその内部導体層7を厚み方向に貫通するように形成されている。   Here, in the inner conductor layer 7 in contact with the cover layer 11 among the inner conductor layers 7, the metal oxide phase 13 constituting the inner conductor layer 7 penetrates the inner conductor layer 7 in the thickness direction. It is formed as follows.

通常、セラミック絶縁体層5と内部導体層7とが多層に積層された積層部9の端面9aにセラミック製のカバー層11を有するような積層型電子部品においては、内部導体層7とカバー層11との材質が大きく異なることから元々接着し難いものとなっている。また、内部導体層7とセラミック絶縁体層5とは上記のように異なる材質であることから熱膨張係数も大きく異なっている。   Usually, in a multilayer electronic component having a ceramic cover layer 11 on an end surface 9a of a laminated portion 9 in which ceramic insulator layers 5 and internal conductor layers 7 are laminated in multiple layers, the internal conductor layers 7 and the cover layers Since the material is significantly different from 11, it is difficult to bond. Further, since the inner conductor layer 7 and the ceramic insulator layer 5 are made of different materials as described above, their thermal expansion coefficients are also greatly different.

このような構成の積層型電子部品が、例えば、ハンダのリフロー工程など温度変化の大きい環境に置かれると、セラミック絶縁体層5と内部導体層7との界面にデラミネーションが発生するという問題がある。このデラミネーションは上記した理由から、とりわけ積層部9の端面9aとカバー層11との界面に発生しやすくなっている。   When the multilayer electronic component having such a configuration is placed in an environment with a large temperature change such as a solder reflow process, delamination occurs at the interface between the ceramic insulator layer 5 and the internal conductor layer 7. is there. This delamination is particularly likely to occur at the interface between the end surface 9a of the laminated portion 9 and the cover layer 11 for the reasons described above.

本実施形態の積層型電子部品は、積層部9を構成している内部導体層7のうち、カバー層11に接している内部導体層7中には、金属の酸化物相13が内部導体層7を厚み方向に貫通するように形成されていることから内部導体層7とカバー層11とが部分的ではあるが同じ酸化物同士で強固に接着されている。これにより内部導体層7とカバー層11との間のデラミネーションを抑制することができる。   In the multilayer electronic component of the present embodiment, among the internal conductor layers 7 constituting the multilayer portion 9, the metal oxide phase 13 is present in the internal conductor layer 7 in contact with the cover layer 11. 7, the inner conductor layer 7 and the cover layer 11 are partially but firmly bonded with the same oxide. Thereby, delamination between the inner conductor layer 7 and the cover layer 11 can be suppressed.

この場合、金属の酸化物相13が内部導体層7を厚み方向に貫通した状態であることからカバー層11と積層部9のセラミック絶縁層5とが金属の酸化物相13を介して接続された状態でもあるため、内部導体層7とカバー層11との間の接着性をより強固にでき、デラミネーションの防止に寄与するものとなっている。   In this case, since the metal oxide phase 13 penetrates the inner conductor layer 7 in the thickness direction, the cover layer 11 and the ceramic insulating layer 5 of the laminated portion 9 are connected via the metal oxide phase 13. Therefore, the adhesiveness between the inner conductor layer 7 and the cover layer 11 can be further strengthened, contributing to prevention of delamination.

また、この実施形態の積層型電子部品において、金属の酸化物相13を有している内部導体層7がカバー層11側から複数層にわたって設けられている場合には、カバー層11に近い方の内部導体層7の熱膨張係数がセラミックス製のカバー層11の熱膨張係数により近づくため、積層部9とカバー層11との界面における応力をさらに低減でき、歪み量を小さくすることができる。これにより積層部9とカバー層11との界面でのデラミネーションの発生をさらに抑制することができる。   In the multilayer electronic component of this embodiment, when the inner conductor layer 7 having the metal oxide phase 13 is provided over a plurality of layers from the cover layer 11 side, the one closer to the cover layer 11 Since the thermal expansion coefficient of the inner conductor layer 7 is closer to the thermal expansion coefficient of the ceramic cover layer 11, the stress at the interface between the laminated portion 9 and the cover layer 11 can be further reduced, and the amount of strain can be reduced. Thereby, generation | occurrence | production of the delamination in the interface of the laminated part 9 and the cover layer 11 can further be suppressed.

金属の酸化物相13を有する内部導体層7の層数は積層部9の端面9a側に1層設ければ効果を奏するものとなるが、金属の酸化物相13を有する内部導体層7の層数が多くなるとデラミネーションの発生を抑えることができるものの、例えば、コンデンサなどの場合には静電容量の低下が大きくなる。このため金属の酸化物相13を有する内部導体層7の層数は積層部9における端面9a側から10層以下であることが望ましい。   The number of layers of the inner conductor layer 7 having the metal oxide phase 13 is effective if one layer is provided on the end face 9a side of the laminated portion 9, but the inner conductor layer 7 having the metal oxide phase 13 is effective. Although the occurrence of delamination can be suppressed when the number of layers increases, for example, in the case of a capacitor or the like, the capacitance decreases greatly. For this reason, the number of layers of the inner conductor layer 7 having the metal oxide phase 13 is desirably 10 layers or less from the end face 9 a side in the laminated portion 9.

本実施形態の積層型電子部品を構成する内部導体層7の主成分金属の熱膨張係数は12×10−6〜20×10−6/℃であることが望ましく、このような熱膨張係数を有する金属材料としては、ニッケル(12.8×10−6/℃)、銅(16.8×10−6/℃)、パラジウム(11.8×10−6/℃)および銀(18.9×10−6/℃)から選ばれる1種もしくはこれらの合金を適用することが好ましい。 The thermal expansion coefficient of the main component metal of the inner conductor layer 7 constituting the multilayer electronic component of the present embodiment is desirably 12 × 10 −6 to 20 × 10 −6 / ° C., and such a thermal expansion coefficient is As a metal material to have, nickel (12.8 × 10 −6 / ° C.), copper (16.8 × 10 −6 / ° C.), palladium (11.8 × 10 −6 / ° C.) and silver (18.9) It is preferable to apply one kind selected from × 10 −6 / ° C. or an alloy thereof.

セラミック絶縁体層5およびカバー層11の材料としては、コンデンサ、アクチュエー
タ、インダクタ、フィルタなどに適用されるセラミック材料が好ましく、例えば、チタン酸バリウム、チタンジルコン酸鉛、フェライト、マグネシア,カルシア,五酸化ニオブおよび二酸化チタン等から選ばれる少なくとも2種の金属酸化物により構成される複合酸化物などが好ましい。これらの材料の熱膨張係数としては9×10−6〜11×10−6/℃であるのが良い。
As a material of the ceramic insulator layer 5 and the cover layer 11, ceramic materials applied to capacitors, actuators, inductors, filters, etc. are preferable. For example, barium titanate, lead zirconate titanate, ferrite, magnesia, calcia, pentoxide A composite oxide composed of at least two metal oxides selected from niobium and titanium dioxide is preferred. The thermal expansion coefficient of these materials is preferably 9 × 10 −6 to 11 × 10 −6 / ° C.

また、本実施形態の積層型電子部品では、内部導体層7の平均厚みは積層方向の中央部よりもカバー層11側に近いほど薄くなっていることが望ましい。つまり、金属の酸化物相13を有している内部導体層7の平均厚みが積層方向の中央部に位置する内部導体層7の平均厚みよりも薄くなっていることが望ましい。カバー層11側の内部導体層7の平均厚みが薄くなっていると、内部導体層7の1層あたりの剛性を低下させることができるため、内部導体層7とカバー層11との界面9aに歪みが発生したときにも内部導体層7がカバー層11やセラミック絶縁層5の変形に追従しやすく、これによりデラミネーションの発生をさらに抑えることが可能となる。   In the multilayer electronic component of the present embodiment, it is desirable that the average thickness of the internal conductor layer 7 is thinner as it is closer to the cover layer 11 side than the central portion in the stacking direction. That is, it is desirable that the average thickness of the inner conductor layer 7 having the metal oxide phase 13 is thinner than the average thickness of the inner conductor layer 7 located at the center in the stacking direction. If the average thickness of the inner conductor layer 7 on the cover layer 11 side is thin, the rigidity per layer of the inner conductor layer 7 can be reduced, so that the interface 9a between the inner conductor layer 7 and the cover layer 11 can be reduced. Even when distortion occurs, the internal conductor layer 7 can easily follow the deformation of the cover layer 11 and the ceramic insulating layer 5, thereby further suppressing the occurrence of delamination.

上述した積層型電子部品としては、セラミック絶縁体層5の平均厚みが1〜30μm、内部導体層7の平均厚みが0.5〜20μm、積層部9における内部導体層7の積層数が100層以上、カバー層の厚みが積層部9の積層方向の厚みを1としたときに0.02以上あるような薄層、高積層の積層型電子部品に好適なものとなる。   As the above-described multilayer electronic component, the average thickness of the ceramic insulator layer 5 is 1 to 30 μm, the average thickness of the internal conductor layer 7 is 0.5 to 20 μm, and the number of the internal conductor layers 7 in the multilayer portion 9 is 100 layers. As described above, the thickness of the cover layer is preferably 0.02 or more when the thickness in the stacking direction of the stacked portion 9 is 1, which is suitable for a multilayer electronic component having a high layer and a thin layer.

次に、本実施形態の積層型電子部品を製造する方法についてコンデンサを例にして説明する。まず、セラミック絶縁体層5の材料として、誘電体粉末を準備し、これに有機ビヒクルを加えてセラミックスラリを調製し、次いで、ドクターブレード法またはダイコータ法などのシート成形法を用いてセラミックグリーンシートを作製する。   Next, a method for manufacturing the multilayer electronic component of the present embodiment will be described using a capacitor as an example. First, a dielectric powder is prepared as a material for the ceramic insulator layer 5, an organic vehicle is added thereto to prepare a ceramic slurry, and then a ceramic green sheet using a sheet forming method such as a doctor blade method or a die coater method. Is made.

次に、ニッケル粉末を主成分とする導体ペーストを調製する。この場合、ニッケル粉末としては、ニッケル粉末中に平均粒径が0.1μm以下の微粒のニッケル粉末を含んでいるものを用いることが望ましい。   Next, a conductor paste mainly composed of nickel powder is prepared. In this case, as the nickel powder, it is desirable to use nickel powder containing fine nickel powder having an average particle diameter of 0.1 μm or less.

次に、導体ペーストを用いてセラミックグリーンシートの主面上に矩形状の内部導体パターンの形成されたパターンシートを形成する。このとき焼成後に積層部9となる積層体の端面側に重ねるパターンシートの導体パターンは、積層体の中央部に配置させるパターンシートよりも印刷用スクリーンの製版線幅(メッシュ材の太さ)を厚くしたものを用いる。端面側に重ねるパターンシートの導体パターンを形成する製版線幅は中央部に位置するパターンシートの導体パターンを形成する製版線幅の1.2倍以上であることが望ましい。この場合、製版の線の厚みは両方とも同じであるのがよい。つまり、端面側に重ねるパターンシートの導体パターンの印刷用スクリーンの製版は、開口率が中央部に位置するパターンシートの導体パターンの印刷用スクリーンの製版よりも低いものを用いるのがよい。   Next, a pattern sheet on which a rectangular internal conductor pattern is formed is formed on the main surface of the ceramic green sheet using a conductor paste. At this time, the conductive pattern of the pattern sheet that is stacked on the end face side of the laminate that becomes the laminate portion 9 after firing has a plate making line width (the thickness of the mesh material) of the printing screen rather than the pattern sheet that is arranged in the center portion of the laminate. Use a thicker one. The plate-making line width for forming the conductor pattern of the pattern sheet to be superimposed on the end face side is desirably 1.2 times or more the plate-making line width for forming the conductor pattern of the pattern sheet located at the center. In this case, both the thicknesses of the plate making lines should be the same. That is, it is preferable to use a plate for printing the conductive pattern of the pattern sheet to be overlapped on the end face side with an aperture ratio lower than that of the screen for printing the conductive pattern of the pattern sheet located at the center.

こうして、端面側に重ねるパターンシートの導体パターンは積層体の中央部に位置するパターンシートの導体パターンよりも凹凸を有し部分的に薄い領域を有するものとなり、この薄い導体パターンの部分が焼成時に厚みの厚い部分よりも酸化される領域の割合が多くなり、内部導体層7の面内に部分的に内部導体層7を構成する金属の酸化物相13を形成することができる。   In this way, the conductor pattern of the pattern sheet stacked on the end face side is uneven and has a partly thinner area than the conductor pattern of the pattern sheet located at the center of the laminate, and this thin conductor pattern portion is The ratio of the oxidized region is larger than that of the thicker portion, and the metal oxide phase 13 that partially constitutes the inner conductor layer 7 can be formed in the plane of the inner conductor layer 7.

従来のコンデンサにおいても印刷用のスクリーンとしては、同様のスクリーンが用いられてきたが、この場合、製造工程において内部導体層7の表面に極めて薄く金属の酸化物膜が形成される程度であり、内部導体層7を貫通するような金属の酸化物相13が形成されるようなものではない。   In the conventional capacitor, the same screen has been used as a printing screen, but in this case, an extremely thin metal oxide film is formed on the surface of the internal conductor layer 7 in the manufacturing process. The metal oxide phase 13 that penetrates the inner conductor layer 7 is not formed.

次に、パターンシートを複数層重ねてコア積層体を形成する。この場合、コア積層体は積層方向の中央部に製版線幅の狭い(開口率が高い)スクリーンを用いて導体パターンを形成したパターンシートを置き、コア積層体の上下の端面側には製版線幅の広い(開口率が低い)スクリーンを用いて導体パターンを形成したパターンシートを配置させるようにする。   Next, a core laminated body is formed by stacking a plurality of pattern sheets. In this case, the core laminate is provided with a pattern sheet in which a conductor pattern is formed using a screen with a narrow plate making line width (high aperture ratio) at the center in the laminating direction, and the plate making wire is placed on the upper and lower end faces of the core laminate. A pattern sheet on which a conductor pattern is formed is placed using a wide screen (low aperture ratio).

次に、このコア積層体の上下面に導体パターンを形成していないセラミックグリーンシートを所定の枚数だけ重ね、加圧加熱処理を行って電子部品本体1となる積層体を複数個有する母体積層体を形成する。次に、この母体積層体を切断することにより積層体にする。次に、作製した積層体を所定の条件にて焼成することにより電子部品本体1を作製する。   Next, a mother laminate having a plurality of laminates to be the electronic component main body 1 by stacking a predetermined number of ceramic green sheets on which the conductor pattern is not formed on the upper and lower surfaces of the core laminate, and performing pressure heating treatment. Form. Next, the base laminate is cut to obtain a laminate. Next, the electronic component main body 1 is manufactured by baking the manufactured laminated body on predetermined conditions.

次に焼成により得られた電子部品本体1の内部導体層7が露出した端面を含む端部に外部電極3を形成して積層型電子部品を完成させる。   Next, the external electrode 3 is formed on the end portion including the end face where the internal conductor layer 7 of the electronic component main body 1 obtained by firing is exposed, thereby completing the multilayer electronic component.

こうして得られた積層型電子部品では、内部導体層7のうち、少なくともカバー層11に接している内部導体層7は、この内部導体層7を構成する金属の酸化物相13が内部導体層7を厚み方向に貫通するように形成されているものとなる。   In the multilayer electronic component thus obtained, of the internal conductor layers 7, at least the internal conductor layer 7 in contact with the cover layer 11 has a metal oxide phase 13 that constitutes the internal conductor layer 7. Is formed so as to penetrate through in the thickness direction.

以上はコンデンサを例に説明したが、アクチュエータ、インダクタおよびフィルタの場合もそれぞれに適用されるセラミック絶縁体層5用の材料および内部導体層7用の材料に応じて本発明の積層型電子部品を作製することができる。   Although the capacitor has been described above as an example, the multilayer electronic component of the present invention can be used according to the material for the ceramic insulator layer 5 and the material for the internal conductor layer 7 applied to the actuator, the inductor, and the filter, respectively. Can be produced.

以下、具体的に積層型のコンデンサを作製して本発明の効果を確認した。まず、セラミック絶縁体層用の材料として以下の誘電体粉末を調製した。誘電体粉末の原料粉末として、チタン酸バリウム粉末、MgO粉末、Y粉末およびMnCO粉末を準備した。これらの各種粉末を、チタン酸バリウム粉末量を100モルとしたときに、MgO粉末を0.5モル、Y粉末を1モル、MnCO粉末を0.5モル添加し、さらに、チタン酸バリウム粉末100質量部に対して、ガラス粉末(SiO=55,BaO=20,CaO=15,LiO=10(モル%))を1質量部添加して誘電体粉末を調製した。次いで、この誘電体粉末を直径5mmのジルコニアボールを用いて、溶媒としてトルエンとアルコールとからなる混合溶媒を添加し湿式混合した。 Hereinafter, a multilayer capacitor was specifically manufactured to confirm the effect of the present invention. First, the following dielectric powder was prepared as a material for the ceramic insulator layer. Barium titanate powder, MgO powder, Y 2 O 3 powder and MnCO 3 powder were prepared as raw material powders for the dielectric powder. These various powders, when the barium titanate powder amount is 100 mol, 0.5 mol of MgO powder, Y 2 O 3 powder 1 mol, and 0.5 mol addition of MnCO 3 powder, further, titanium A dielectric powder was prepared by adding 1 part by mass of glass powder (SiO 2 = 55, BaO = 20, CaO = 15, Li 2 O = 10 (mol%)) to 100 parts by mass of barium acid powder. Next, this dielectric powder was wet mixed using a zirconia ball having a diameter of 5 mm and a mixed solvent composed of toluene and alcohol as a solvent.

次に、湿式混合した粉末を、ポリビニルブチラール樹脂を溶解させたトルエンおよびアルコールの混合溶媒中に投入し、直径5mmのジルコニアボールを用いて湿式混合してセラミックスラリを調製し、ドクターブレード法により厚みが2.5μmのセラミックグリーンシートを作製した。   Next, the wet-mixed powder is put into a mixed solvent of toluene and alcohol in which polyvinyl butyral resin is dissolved, wet-mixed using a zirconia ball having a diameter of 5 mm, and a ceramic slurry is prepared. Produced a ceramic green sheet having a thickness of 2.5 μm.

次に、このセラミックグリーンシートの上面に矩形状の導体パターンを形成してパターンシートを形成した。導体パターンを形成するための導体ペーストは、Ni粉末45質量%に対して、共材としてチタン酸バリウム粉末を20重量%と、エチルセルロース5質量%およびオクチルアルコール95質量%からなる有機ビヒクル30質量%を3本ロールで混練したものを用いた。Ni粉末は粒度分布において累積%表示したときに10〜90%の範囲にある粒径が0.05〜0.2μmであるものを用いた。   Next, a rectangular conductor pattern was formed on the upper surface of the ceramic green sheet to form a pattern sheet. The conductor paste for forming the conductor pattern is 20% by weight of barium titanate powder as a co-material with respect to 45% by weight of Ni powder, 30% by weight of an organic vehicle consisting of 5% by weight of ethyl cellulose and 95% by weight of octyl alcohol. Was kneaded with three rolls. Ni powder having a particle size in the range of 10 to 90% in the range of 10 to 90% in terms of cumulative percentage in the particle size distribution was used.

このとき積層体の端面側に重ねるパターンシートの導体パターンは製版線幅が約30μmのスクリーンを用い、一方、積層体の中央部に配置させるパターンシートの導体パターンは製版線幅が約20μmのスクリーンを用いた。製版線幅が約30μmのスクリーンの
開口率は約40%、製版線幅が約20μmのスクリーンの開口率は約60%であった。
At this time, the conductor pattern of the pattern sheet to be overlapped on the end face side of the laminate uses a screen having a plate making line width of about 30 μm, while the conductor pattern of the pattern sheet disposed at the center of the laminate has a screen having a plate making line width of about 20 μm. Was used. The aperture ratio of a screen having a plate-making line width of about 30 μm was about 40%, and that of a screen having a plate-making line width of about 20 μm was about 60%.

次に、作製したパターンシートのうち製版線幅が約20μmのスクリーンを用いて形成した導体パターンを有するパターンシートを複数層重ね、次いで、この積層体の上下面に製版線幅が約30μmのスクリーンを用いて導体パターンを形成したパターンシートを積層してコア積層体を形成し、さらにこの上下面にそれぞれ導体パターンを形成していないセラミックグリーンシートを重ね、加圧加熱処理を行って電子部品本体となる積層体を複数個有する母体積層体を形成した。この後、この母体積層体を、所定の寸法に切断して積層体を形成した。積層体における内部導体層の積層数は147層とした。   Next, a plurality of pattern sheets having a conductor pattern formed using a screen having a plate making line width of about 20 μm among the prepared pattern sheets are stacked, and then a screen having a plate making line width of about 30 μm is formed on the upper and lower surfaces of this laminate. A core laminated body is formed by laminating pattern sheets formed with conductor patterns using a ceramic, and further, ceramic green sheets not formed with conductor patterns are stacked on the upper and lower surfaces, respectively, and subjected to pressure heating treatment to form an electronic component body. A base laminate having a plurality of laminates was formed. Then, this base material laminated body was cut | disconnected to the predetermined dimension, and the laminated body was formed. The number of laminated inner conductor layers in the laminate was 147.

次に、作製した積層体を大気中にて脱脂した後、水素−窒素の混合ガス雰囲気にて酸素分圧が10−8Paの条件にて1140℃で2時間の焼成を行い、電子部品本体を作製した。作製した電子部品本体のサイズは1005型に相当するものであり、そのサイズはおおよそ、0.95mm×0.48mm×0.48mmであった。また、セラミック絶縁体層の平均厚みは2μm、積層部の中央に位置する内部導体層の1層の平均厚みは1μmであった。カバー層側の内部導体層の平均厚みは0.9μmであった。カバー層の平均厚みは20μmであった。なお、作製した電子部品本体から得られる静電容量の設計値(セラミック絶縁体層を挟んで内部導体層が上下で重なっている有効面積の領域に空隙が無い状態で発現する静電容量)は1.15μFと見積もった。 Next, the prepared laminate is degreased in the air, and then fired at 1140 ° C. for 2 hours in a hydrogen-nitrogen mixed gas atmosphere at an oxygen partial pressure of 10 −8 Pa. Was made. The size of the manufactured electronic component main body corresponds to 1005 type, and the size was approximately 0.95 mm × 0.48 mm × 0.48 mm. The average thickness of the ceramic insulator layer was 2 μm, and the average thickness of one layer of the inner conductor layer located at the center of the laminated portion was 1 μm. The average thickness of the inner conductor layer on the cover layer side was 0.9 μm. The average thickness of the cover layer was 20 μm. In addition, the design value of the capacitance obtained from the manufactured electronic component body (capacitance expressed in a state where there is no void in the area of the effective area where the internal conductor layers overlap each other with the ceramic insulator layer sandwiched therebetween) is Estimated to be 1.15 μF.

次に、作製した電子部品本体に窒素雰囲気中(酸素分圧:10−6Pa)、900〜1000℃で5時間の熱処理を行った。 Next, the produced electronic component main body was heat-treated at 900 to 1000 ° C. for 5 hours in a nitrogen atmosphere (oxygen partial pressure: 10 −6 Pa).

次に、作製した電子部品本体にバレル研磨処理を行い、電子部品本体の端面に内部導体層を十分に露出させた。   Next, barrel polishing treatment was performed on the manufactured electronic component main body to sufficiently expose the inner conductor layer on the end surface of the electronic component main body.

次に、バレル研磨した電子部品本体の端部に銅ペーストを塗布し、約800℃、酸素分圧を1Pa、最高温度の保持時間を0.2時間とする条件で加熱して外部電極を形成した。   Next, a copper paste is applied to the end of the barrel-polished electronic component body and heated under conditions of about 800 ° C., oxygen partial pressure of 1 Pa, and maximum temperature holding time of 0.2 hours to form external electrodes. did.

次に、この外部電極の表面に、順に、電解めっき法によりNiメッキ膜およびSnメッキ膜を形成して積層型のコンデンサを作製した。   Next, an Ni plating film and an Sn plating film were sequentially formed on the surface of the external electrode by electrolytic plating to produce a multilayer capacitor.

次に、作製した積層型のコンデンサについて以下の評価を行った。   Next, the following evaluation was performed on the manufactured multilayer capacitor.

コンデンサの積層部の内部導体層に形成された内部導体層を構成する金属の酸化物相はコンデンサを断面研磨して金属顕微鏡および走査型電子顕微鏡による観察によって確認した。このとき金属の酸化物相中の酸素の有無は走査型電子顕微鏡に付設された波長分散型分析器を用いて同定した。金属の酸化物相は走査型電子顕微鏡観察の写真において黒色化した部分であった。   The oxide phase of the metal composing the inner conductor layer formed on the inner conductor layer of the laminated portion of the capacitor was confirmed by observing with a metal microscope and a scanning electron microscope after the capacitor was polished in cross section. At this time, the presence or absence of oxygen in the metal oxide phase was identified using a wavelength dispersion analyzer attached to a scanning electron microscope. The metal oxide phase was a blackened portion in a photograph taken with a scanning electron microscope.

金属の酸化物相の割合は断面研磨したコンデンサを走査型電子顕微鏡観察により写真に撮り、写真上に写し出された内部導体層に平行な直線を引き、金属の酸化物相が存在する部分の長さの割合を算出した。写真の範囲において、金属の酸化物相を総和した長さを内部導体層の長さで除して求めた。ここでは内部導体層を貫通したものを金属の酸化物相として判定した。なお、製版線幅が約30μmのスクリーンを用いて形成した導体パターンから得られた内部導体層には金属の酸化物相が長さの比で15〜20%形成されていたが、製版線幅が約20μmのスクリーンを用いて形成した導体パターンから得られた内部導体層には金属の酸化物相に相当するものは認められなかった。   The ratio of the metal oxide phase is determined by taking a photograph of a cross-polished capacitor with a scanning electron microscope, drawing a straight line parallel to the internal conductor layer on the photo, and measuring the length of the portion where the metal oxide phase exists. The ratio was calculated. In the range of the photograph, the total length of the metal oxide phases was divided by the length of the inner conductor layer. Here, what penetrated the inner conductor layer was determined as a metal oxide phase. In addition, although the metal oxide phase was formed 15 to 20% in length ratio in the internal conductor layer obtained from the conductor pattern formed using the screen whose plate-making line width was about 30 micrometers, plate-making line width However, in the inner conductor layer obtained from the conductor pattern formed using a screen of about 20 μm, no metal oxide phase was found.

静電容量は温度25℃、周波数1.0kHz、測定電圧を1Vrmsとして測定し、その平均値を求めた。試料数は30個とした。   The capacitance was measured at a temperature of 25 ° C., a frequency of 1.0 kHz, and a measurement voltage of 1 Vrms, and the average value was obtained. The number of samples was 30.

デラミネーションは、焼成後、耐熱衝撃試験後の2つの条件にて行った。耐熱衝撃試験はハンダ槽を350℃に加熱したハンダ槽にコンデンサを約1秒間沈める方法を用いた。デラミネーション発生率は試料数300個から求めた。   Delamination was performed under two conditions after firing and after a thermal shock test. The thermal shock test used a method in which a capacitor was submerged in a solder bath heated to 350 ° C. for about 1 second. The delamination occurrence rate was obtained from 300 samples.

また、積層部の内部導体層となる導体パターンの全層を製版線幅が約20μmまたは30μmのスクリーンを用いてそれぞれ形成したものから上記と同様の製法によりコンデンサを作製した。これを比較例の試料(試料1、5)として同様に評価した。   In addition, a capacitor was manufactured by the same manufacturing method as described above from all the layers of the conductor pattern serving as the inner conductor layer of the laminated portion formed using a screen having a plate-making line width of about 20 μm or 30 μm. This was similarly evaluated as a sample of a comparative example (samples 1 and 5).

Figure 2014146654
Figure 2014146654

表1の結果から明らかなように、内部導体層のうちカバー層に接している内部導体層がこの内部導体層を構成する金属の酸化物相を有している試料(試料No.2〜4)は内部導体層に金属の酸化物相を有しない試料(試料No.1)に比較してデラミネーションの発生率が低かった。   As is clear from the results in Table 1, the samples in which the inner conductor layer in contact with the cover layer among the inner conductor layers has an oxide phase of the metal constituting the inner conductor layer (sample Nos. 2 to 4). ) Had a lower delamination rate than the sample (sample No. 1) having no metal oxide phase in the inner conductor layer.

金属の酸化物相を有している内部導体層をカバー層側から10層にわたって設けた試料はデラミネーションの発生率がさらに低かった。   The sample in which the inner conductor layer having a metal oxide phase was provided over 10 layers from the cover layer side had an even lower rate of delamination.

これらの試料はいずれも金属の酸化物相は内部導体層を厚み方向に貫通した状態となっていた。   In all of these samples, the metal oxide phase penetrated the inner conductor layer in the thickness direction.

なお、積層部の全層に製版線幅が約30μmのスクリーンを用いて形成した試料(試料No.5)には、デラミネーションは見られなかったが静電容量が大きく低下していた。   In addition, although the delamination was not seen in the sample (sample No. 5) formed using a screen having a plate-making line width of about 30 μm in all layers of the laminated portion, the capacitance was greatly reduced.

1・・・電子部品本体
3・・・外部電極
5・・・セラミック絶縁体層
7・・・内部導体層
9・・・積層部
9a・・端面
11・・カバー層
13・・金属の酸化物相
DESCRIPTION OF SYMBOLS 1 ... Electronic component main body 3 ... External electrode 5 ... Ceramic insulator layer 7 ... Internal conductor layer 9 ... Laminate part 9a .. End surface 11 .... Cover layer 13 .... Metal oxide phase

Claims (4)

セラミック絶縁体層と内部導体層とが交互に多層に積層された積層部と、該積層部の積層方向の両端面にそれぞれ設けられたセラミック製のカバー層とを有する積層型電子部品において、前記内部導体層のうち前記カバー層に接している前記内部導体層には、該内部導体層を構成する金属の酸化物相が前記内部導体層を厚み方向に貫通するように形成されていることを特徴とする積層型電子部品。   In a multilayer electronic component having a laminated part in which ceramic insulator layers and internal conductor layers are alternately laminated in multiple layers, and a ceramic cover layer provided on each end face in the lamination direction of the laminated part, Among the internal conductor layers, the internal conductor layer that is in contact with the cover layer is formed so that the metal oxide phase constituting the internal conductor layer penetrates the internal conductor layer in the thickness direction. Characteristic multilayer electronic component. 前記金属の酸化物相を有している前記内部導体層は前記カバー層側から複数層にわたって設けられていることを特徴とする請求項1に記載の積層型電子部品。   2. The multilayer electronic component according to claim 1, wherein the inner conductor layer having the metal oxide phase is provided over a plurality of layers from the cover layer side. 前記内部導体層の平均厚みは積層方向の中央部よりもカバー層側に近いほど薄いことを特徴とする請求項1または2に記載の積層型電子部品。   3. The multilayer electronic component according to claim 1, wherein an average thickness of the inner conductor layer is thinner as it is closer to the cover layer side than a central portion in the stacking direction. 前記金属の酸化物相を有している前記内部導体層の平均厚みは積層方向の中央部に位置する内部導体層の平均厚みよりも薄くなっていることを特徴とする請求項1乃至3のうちいずれかに記載の積層型電子部品。   The average thickness of the inner conductor layer having the metal oxide phase is thinner than the average thickness of the inner conductor layer located at the center in the stacking direction. A laminated electronic component according to any one of the above.
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