JP2014143435A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device that is able to suppress degradation in semiconductor characteristics, due to stress concentration on a corner part of a recessed part, resulting from solder heat hysteresis, in a semiconductor chip having the recessed part, which is formed from a non-penetration V-shaped groove, in a semiconductor substrate.SOLUTION: The surface of an n-type wafer 1 has a p-type diffusion layer 31 of a grid pattern. The back of the n-type wafer 1 has a grid pattern of the same pitch as the grid pattern on the surface. A V-shaped groove 21b is provided. The V-shaped groove 21b has a bottom face, parallel to the back, from which the p-type diffusion layer 31 is exposed, and tapering side faces 9d extending from the bottom face. The back surrounded by the tapering side faces 9d has a p-type semiconductor layer. A p-type separation layer 4b that conductively connects the p-type diffusion layer 31 of the surface and the p-type semiconductor layer of the back is provided along the side faces 9d. In the V-shaped groove 21b, a portion near the intersection of a corner of each side face and the bottom face has a chamfered face.

Description

The present invention, IC, MOS, insulated gate bipolar transistor (hereinafter, abbreviated as IGBT) relates to semiconductor equipment such as, in particular, relates to an improvement of a bidirectional device or a reverse blocking IGB T having a bidirectional breakdown voltage characteristics .

  As a semiconductor device, a reverse blocking IGBT will be described below. Conventional IGBTs (Insulated Gate Bipolar Transistors) have no problem in the inverter circuit and chopper circuit, which are the main applications, as long as the forward breakdown voltage can be secured. The end face was made exposed on the side face of the chip cutting portion without considering reliability. Recently, however, some DC (direct current) / AC conversion circuits, such as AC (alternating current) / AC conversion circuits, current type DC / AC conversion circuits, and new three-level circuits, which are direct link type conversion circuits such as matrix converters, etc. Therefore, it has been studied to use a switching element having a reverse breakdown voltage to reduce the size, weight, efficiency, speed response, and cost of a circuit.

  In reverse blocking IGBTs, in order to ensure reverse blocking voltage capability, when a semiconductor substrate (hereinafter sometimes referred to as a wafer) that has undergone a manufacturing process is cut into a square shape to form a semiconductor chip, the reverse in each chip The breakdown voltage pn junction is bent and extended to the surface side of the semiconductor chip so as not to be exposed by cutting, and the junction termination is protected by an insulating film on the surface to ensure reliability. In order to extend the reverse breakdown voltage pn junction to the front surface side, it is a diffusion layer of the same conductivity type (for example, p type) as the p-type collector layer on the back surface side of the semiconductor chip, and one end is connected to the back surface p-type collector layer. And the other end requires a p-type diffusion layer extending to the surface. This diffusion layer is formed along the side surface of the chip. Here, the diffusion layer formed on the side surface of the chip is referred to as a separation layer.

  FIG. 2 is a cross-sectional view of a principal part of a semiconductor substrate (hereinafter also referred to as a wafer) showing one of manufacturing methods for forming a separation layer in a conventional reverse blocking IGBT in the order of steps. A method for forming the separation layer by coating diffusion will be described. First, a dopant mask oxide film 2 having a film thickness of about 2.5 μm is formed on the wafer 1 by a thermal oxidation method (FIG. 2A). Next, an opening 3 for diffusing boron, which is a p-type impurity source, is formed in the oxide film by patterning and etching using a photolithography technique (FIG. 2B). Next, a boron source 5 is applied to the opening 3 and then heat treatment is performed at a high temperature for a long time in a diffusion furnace to form a p-type diffusion layer having a depth of about several hundred μm (FIG. 2C). )). This p-type diffusion layer becomes the separation layer 4. Then, after forming the surface side MOS structure 10 as shown in FIG. 3 which is a completed drawing of the reverse blocking IGBT, the surface side MOS structure 10 is ground from the back side to reach the vicinity of the tip of the separation layer 4 (see FIG. 2C). The broken line is the backside grinding depth). A back surface structure composed of the p-type collector layer 6 and the collector electrode 7 is formed on this ground surface (FIG. 3). When the wafer is cut by a scribe line located at the center line of the surface pattern of the separation layer 4, a reverse blocking IGBT chip shown in a sectional view in the vicinity of the cutting end 8 in FIG.

  FIG. 4 is a cross-sectional view of a principal part of a wafer showing another manufacturing method for forming a separation layer 4 in a conventional reverse blocking IGBT in the order of steps. 4 shows a separation layer 4a having a function similar to that of the aforementioned separation layer 4 by forming a diffusion layer along a substantially vertical side surface of a trench (groove) 11 dug vertically from the surface of the wafer 1. FIG. FIG.

  First, an etching mask for trench formation is formed with a thick oxide film 2 of several μm (FIG. 4A). Next, a trench 11 having a depth of about several hundred μm is formed by dry etching (FIG. 4B). Next, impurities (boron) are introduced into the side surface of the trench 11 by vapor phase diffusion to form the p-type isolation layer 4a (FIG. 4C). The trench is filled with a reinforcing material such as an insulating film and polysilicon, and a front side MOS gate structure 10, a back side p-type collector layer 6 and a collector electrode 7 necessary for back side polishing and IGBT are formed. Next, when the IGBT chip is cut out from the wafer 1 by dicing along the scribe line located in the center of the trench 11 or between two trenches (not shown), the sectional view in the vicinity of the cut end 8 in FIG. The reverse blocking IGBT shown can be made (Patent Documents 1, 2, and 3).

  In the method of forming the reverse blocking IGBT separation layer shown in FIG. 2 by coating diffusion, boron source (boron liquid diffusion source) is applied from the surface to thermally diffuse boron, and a diffusion depth of about several hundred μm. In order to form the p-type separation layer, high-temperature and long-time thermal diffusion treatment is required. As a result, the manufacturing cost is likely to increase due to the occurrence of quartz jigs such as quartz boards, quartz tubes, and quartz nozzles that constitute the diffusion furnace, contamination from heaters, and strength reduction due to devitrification of the quartz jigs. Becomes higher. Further, in the formation of the separation layer by this coating diffusion method, a high-quality and thick oxide film must be used so that the mask oxide film can withstand long-time boron diffusion and boron does not penetrate through the oxide film. . A thermal oxidation method is known as a method for obtaining a high-quality silicon oxide film having high mask durability.

  As described above, in order to make the durability of the mask oxide film effective even when forming the p-type isolation layer by diffusion of boron at a high temperature for a long time (for example, 1300 ° C., 200 hours), the film thickness is about A thermal oxide film of 2.5 μm is required. In order to form a thermal oxide film having a thickness of 2.5 μm, for example, an oxidation time required at an oxidation temperature of 1150 ° C. requires about 200 hours in dry (dry oxygen atmosphere) oxidation in which a good quality oxide film can be obtained. And Furthermore, during these oxidation treatments, a large amount of oxygen is introduced into the wafer, so that crystal defects such as oxygen precipitates and oxidation-induced stacking faults occur, resulting in deterioration of device characteristics due to the oxygen donor phenomenon. And adverse effects of reduced reliability.

  In addition, even after diffusion after boron source application, interstitial oxygen is introduced into the wafer because diffusion treatment is usually performed at a high temperature for a long time in an oxidizing atmosphere. As a result, even in this diffusion step, crystal defects such as oxygen precipitates, an oxygen donor phenomenon, an oxidation induced stacking fault (OSF) and slip dislocations are generated. It is known that the pn junction formed in the vicinity of these crystal defects has a high leakage current, and the breakdown voltage and reliability of the thermal oxide film formed in the vicinity of the crystal defects of the wafer are greatly deteriorated. In addition, oxygen taken into the wafer during the diffusion may become a donor, which may cause a negative effect that the breakdown voltage decreases. Further, in the method of forming the separation layer by coating diffusion shown in FIG. 2, boron diffusion proceeds substantially isotropically up and down and left and right from the opening of the mask oxide film into the silicon bulk. As a result, when boron diffusion of 200 μm is performed in the depth direction, boron diffuses and expands by 160 μm at the same time in the lateral direction, which is an obstacle to the problem of chip size reduction.

In the method of forming the isolation layer using the trench shown in FIG. 4, the trench is formed by dry etching, and boron is introduced into the side wall of the formed trench to form the p-type isolation layer. Thereafter, the trench is filled with a reinforcing material such as an insulating film or polysilicon. The p-type isolation layer shown in FIG. 4 formed in this way can use a trench having a high aspect ratio and a narrow width. Therefore, the p-type isolation layer is more advantageous in reducing the device pitch than the p-type isolation layer by thermal diffusion shown in FIG. It is. However, the time required for etching with a depth of about 200 μm requires a processing time of about 100 minutes per wafer when a typical dry etching apparatus is used. Bring about evil. When a deep trench is formed by dry etching, when a silicon oxide film (SiO ₂ ) is used as a mask, the selection ratio is 50 or less, so a thick silicon oxide film of about several μm is required. As a result, there is a new problem that the cost increases and the yield rate decreases due to the introduction of process-induced crystal defects such as oxidation-induced stacking faults and oxygen precipitates. Furthermore, in the separation layer forming process using a high aspect ratio trench by dry etching, as shown in FIG. There is a problem that causes harmful effects such as.

Usually, when introducing a dopant such as phosphorus or boron into the sidewall of the trench 11, the sidewall of the trench 11 is vertical, so that the dopant is introduced into the sidewall of the trench 11 by ion implantation with the wafer inclined. To do. However, introduction of dopants into the sidewalls of trenches with a high aspect ratio can lead to a decrease in effective dose, resulting in an increase in implantation time, a decrease in effective projection range, a loss in dose due to a screen oxide film, and a decrease in implantation uniformity. Cause harmful effects. In order to cope with this problem, as a method for introducing impurities into the trench 11 having a high aspect ratio, a gasified dopant zero such as PH ₃ (phosphine) or B ₂ H ₆ (diborane) is used instead of ion implantation. A vapor phase diffusion method in which the wafer is exposed to the atmosphere may be used, but the dose controllability is inferior to that of the ion implantation method. Further, in order to increase the wafer strength in the trench 11 having a high aspect ratio, a step of filling with an insulating film or polysilicon is required. However, a gap called a void is easily formed in the narrow trench, and reliability is improved. The problem may occur.

  A manufacturing method that solves the above problems has been proposed. FIG. 17 is a partial plan view of a semiconductor substrate related to an etching process for forming a separation layer in such a manufacturing method. Specifically, the partial plan view of FIG. 17 shows nine chips among reverse blocking type IGBT chips partitioned by through V-groove etching consisting of a lattice-like plane pattern on the wafer 1 having the (100) plane 23. Show. In FIG. 17, since the through V-shaped groove 21a is formed by wet anisotropic etching, the side surface of the reverse blocking IGBT is an azimuth plane represented by a {111} plane. 7A and 7B are cross-sectional views (for one chip) of the reverse blocking IGBT separated from the wafer 1 by the through V-shaped groove 21a shown in FIG. Indicates that there are omissions in the drawing). (A) And (b) is sectional drawing which shows that the wafer 1 surface which starts a penetration V groove | channel etching is a reverse direction, respectively. Like this reverse blocking type IGBT chip, along the tapered surface (side surfaces 9a, 9b) of the V-shaped through-groove 21a having a V-shaped cross section formed by etching in a lattice-like plane pattern on the main surface of the wafer 1, By performing ion implantation and annealing (activation), the separation layer 4b is formed on the side surface 9a of the chip region. Anisotropic etching using an alkaline etchant is employed for the above-mentioned through V-groove etching that forms the tapered surfaces that form the four side surfaces 9a and 9b of the reverse blocking IGBT chip (Patent Documents 4 and 5). 6).

  Furthermore, the reverse blocking type IGBT having the tapered side surface 9b shown in FIG. 7B is closer to the emitter side (upper side of the drawing of FIG. 7) than the FIG. 7A having the reverse inclined surface. The surface can be widely used. This increases the area that can be used for the n-type emitter region 15 and the p-type base region 16 formed in the surface layer on the emitter side, so that the current density can be increased, and the chip area can be increased for the same current rating. This is an advantage that can be reduced. Further, in the reverse blocking IGBT shown in FIGS. 7A and 7B, the separation layer 4b can be formed by ion implantation in an extremely short processing time as compared with the above-described high-temperature long-time diffusion. The problem of crystal defects and oxygen-induced defects in the method of forming the separation layer 4 by the above, and further the problem of damage of the diffusion furnace can be solved at once. Furthermore, since the aspect ratio of the V-shaped groove is lower than that of the manufacturing method using the vertical trench described above, there are no voids and residues which are problematic when filling the vertical trench with an insulating film. The dopant can be easily introduced.

JP-A-2-22869 JP 2001-185727 A JP 2002-76017 A JP 2006-156926 A JP 2004-336008 A JP 2006-303410 A

  As described in Patent Documents 4 to 6, as described above, in the manufacturing method of the reverse blocking IGBT having the separation layer formed along the tapered surface of the through V-shaped groove formed by alkali anisotropic etching, as described above. It is possible to avoid long-term diffusion with various adverse effects. However, since the depth of the impurity distribution in the separation layer formed by ion implantation is extremely shallow, the crystal defects formed with the ion implantation remain without being sufficiently recovered even by the activation treatment (annealing). Since the defect is close to the pn junction, the leakage current at the time of reverse bias tends to increase, and the reverse breakdown voltage cannot be maintained. In addition, when laser annealing treatment is adopted as a crystal defect recovery treatment method, the laser irradiation is performed for a short time (several tens of nanoseconds to several microseconds) and the focal position of the laser irradiation is separated from the wafer surface and the side surface. It has been found that there is a case where the focal point shifts due to the difference between the layers, and in particular, the activation of the separation layer on the side surface tends to be insufficient and the crystal defects cannot be sufficiently recovered. Furthermore, when laser annealing is performed, the laser irradiation area is narrow, so for sufficient activation, the laser irradiation is scanned and the narrow irradiation area is arranged in a plane to cover the entire ion implantation layer. Irradiation is necessary. At this time, irradiation marks are formed along the scan, which may adversely affect the breakdown voltage characteristics.

  Still further, as shown in FIG. 8, the reverse blocking IGBT using the tapered surface formed by the V-shaped groove formed by alkali anisotropic etching is shallow without penetrating the wafer when the V-shaped groove is formed. There is also a manufacturing method in which a p-type diffusion layer formed from the opposite surface of the opposite position is exposed on the bottom surface of the groove (the wavy double broken line in FIG. 8 indicates that there is an omitted portion in the drawing). Even with such a non-penetrating type V-shaped groove, a reverse blocking IGBT can be obtained by forming a separation layer made of a p-type diffusion layer on the tapered surface. This structure also alleviates the problems associated with high-temperature and long-time diffusion as described above. Further, in the process flow of the reverse blocking IGBT having the above-mentioned through V-shaped groove (FIG. 7), the wafer separated by the through V-shaped groove needs to be bonded by the supporting substrate in order to hold the chip integrally. This non-penetrating type V-shaped groove has an advantage that a supporting substrate for the wafer becomes unnecessary.

  However, regarding the manufacturing process of the above-mentioned non-penetrating type V-shaped groove (hereinafter abbreviated as non-penetrating V-shaped groove), at the four corners of the groove portion where the lattice plane pattern of the other main surface (back surface) intersects, As shown in the perspective view of FIG. 15 showing the vicinity of one corner, a portion where the angular corner portion A formed in the groove and the thin emitter-side silicon surface B which is the bottom surface of the groove intersect at a predetermined angle is formed. Is done. As shown in the cross-sectional view of FIG. 16B, the reverse-blocking IGBT chip having a recess made of a groove at the end as described above is mounted on the mounting substrate. When the concave portion is joined to the mounting substrate 20 with the solder 21, it becomes the lower side. Due to the thermal history applied to the chip 30b during the soldering operation, the concave portion at the end of the chip 30b has a difference in thermal expansion coefficient between the different materials of the chip 30b and the solder 21 of the reverse blocking IGBT. Stress is generated, and the stress is concentrated particularly near the intersection of A and B. It has been found that due to the stress strain due to this stress concentration, the end of the chip 30b may crack and the semiconductor characteristics may be destroyed. Furthermore, even when the chip 30b is not cracked, the passivation film covering the outermost surface of the chip 30b may be peeled off, and the reliability characteristics may be deteriorated. FIG. 16A is a cross-sectional view showing a state in which a normal IGBT 30a is joined to the mounting substrate 20 with solder 21, and is shown for comparison.

The present invention has been made in view of the above-described points, and an object of the present invention is to provide a semiconductor chip having a recess by a non-through V-shaped groove formed by anisotropic etching on a semiconductor substrate. the stress concentration on the corner portion of the recessed portion due to thermal history is to provide a semiconductor equipment which can prevent the semiconductor characteristics are deteriorated.

In order to achieve the object of the present invention, the present invention comprises a second conductive type diffusion layer having a lattice-like planar pattern on one main surface of a first conductive type semiconductor substrate, A bottom surface on which the second conductivity type diffusion layer is exposed, and a tapered side surface rising from the bottom surface, the second surface being parallel to the other main surface, A second conductive type semiconductor layer on the other principal surface surrounded by the tapered side surface, along the side surface, a second conductive separation layer of conductively connecting with the second conductive type semiconductor layer of the second conductivity type diffusion layer and the other principal surface, said V-shaped groove, and the bottom surface and the side edge surface a semiconductor device which four corners of the corner portions intersecting portion and the side edge faces intersect has a chamfered shape That. The chamfered shape is preferably a curved surface. The chamfered shape is more preferably a curved surface having a radius of curvature R = 50 μm or more. It is particularly preferable that the semiconductor device is a reverse blocking insulated gate bipolar transistor.

According to the present invention, a semiconductor chip having a recess due to a non-through V-shaped groove formed by anisotropic etching on a semiconductor substrate has a semiconductor characteristic due to stress concentration at the corner of the recess due to a thermal history of soldering. it is possible to provide a semiconductor equipment which can suppress the deterioration.

It is principal part sectional drawing of the semiconductor substrate which shows the separation layer formation method concerning Example 1 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the separation layer formation method by the conventional application | coating diffusion. It is sectional drawing of the edge part vicinity of the reverse blocking IGBT which has the separation layer formed by the conventional application | coating diffusion. It is principal part sectional drawing of the semiconductor substrate which shows the isolation layer formation method using the conventional vertical trench. It is sectional drawing of the edge part vicinity of the reverse blocking IGBT which has the isolation layer using the conventional vertical trench. It is principal part sectional drawing of the semiconductor substrate which shows the problem at the time of forming the isolation layer using the conventional vertical trench. It is principal part sectional drawing of the reverse blocking IGBT which has the isolation layer formed by the conventional penetration V-shaped groove. It is principal part sectional drawing of the reverse blocking IGBT which has the isolation layer formed by the conventional non-penetrating V-shaped groove. It is an impurity concentration profile figure of the separated layer and collector layer which were calculated | required by SR measurement in the case of using the low temperature annealing concerning this invention. FIG. 6 is an impurity concentration profile diagram of a separation layer and a collector layer obtained by SR measurement when flash lamp annealing according to the present invention is used. It is the impurity concentration profile figure of the separated layer and collector layer which were calculated | required by SR measurement at the time of using the laser annealing concerning this invention. It is a current-voltage waveform diagram of the reverse direction for comparing the magnitude of the reverse leakage current of the reverse blocking IGBT due to the difference in the annealing method of the separation layer according to the present invention. It is principal part sectional drawing which shows the manufacturing process process of the non-penetrating V-shaped groove | channel and isolation | separation layer concerning Example 5 of this invention. It is principal part sectional drawing which shows the manufacturing process process of the non-penetrating V-shaped groove | channel and isolation | separation layer concerning Example 6 of this invention. It is a principal part perspective view of the semiconductor substrate which shows the vicinity of one corner of the non-penetration V-shaped groove part which a grid | lattice-like plane pattern cross | intersects. It is principal part sectional drawing which shows mounting the chip | tip of the reverse blocking IGBT which has a recessed part which consists of a non-penetrating V-shaped groove | channel on the mounting board | substrate. It is a partial top view of the semiconductor substrate which shows having formed the penetration V character slot which consists of a lattice-like plane pattern. It is principal part sectional drawing of the semiconductor substrate which has the non-penetrating V-shaped groove | channel (a) without the conventional chamfering, and the non-penetrating V-shaped groove | channel (b) which performed the chamfering concerning Example 1 of this invention. It is sectional drawing of the reverse prevention IGBT chip | tip which has the non-penetrating V-shaped groove | channel which gave the chamfer concerning this invention.

A semiconductor instrumentation such an embodiment the location of the present invention, in particular as a semiconductor device, taking the reverse blocking IGBT, with reference to the accompanying drawings. The present invention is not limited to the description of the examples described below unless it exceeds the gist. In the following description, n-type is used as the first conductivity type, and p-type is used as the second conductivity type. When the semiconductor device is an IGBT, one main surface is the emitter side or surface of the IGBT and the other main surface is the collector side or back surface of the IGBT.

  Hereinafter, a preferred embodiment according to the present invention will be described in detail for a reverse blocking IGBT having a withstand voltage of 600V. In the reverse blocking IGBT, a p-type diffusion layer having a depth of about 120 μm is formed in a lattice-like planar pattern on one main surface (surface) of the FZ-n type silicon semiconductor substrate 1 having a (100) plane as a main surface. Each of the rectangular regions surrounded by the lattice includes a semiconductor element region. The semiconductor element region has a MOS gate structure and a breakdown voltage structure that constitute the surface side of the reverse blocking IGBT. The other main surface (back surface) facing the p-type diffusion layer has a non-penetrating V-shaped groove formed by alkali anisotropic etching. The non-penetrating V-shaped groove has a bottom surface parallel to the other main surface, and the bottom of the p-type diffusion layer formed on the one main surface is exposed on the bottom surface. The non-penetrating V-shaped groove is formed in a lattice-like plane pattern on the other main surface of the wafer, and is opposed to the lattice-like plane pattern of the p-type diffusion layer on the one main surface of the wafer. Therefore, when the substrate is diced and cut at the center of the lattice-like planar pattern, for example, it can be taken out from the wafer as a reverse blocking IGBT chip. The non-penetrating V-shaped groove has a bottom surface with a depth of about 80 μm and a tapered side surface rising from the bottom surface to the other main surface (back surface). The other main surface surrounded by the tapered side surface is provided with a p-type collector layer (second conductivity type semiconductor layer), and the p-type of the one main surface is formed along the side surface. A p-type isolation layer is provided for conductively connecting the diffusion layer and the p-type collector layer on the other main surface. In the present invention, when the reverse blocking IGBT is viewed from the other main surface in the vertical direction, the vicinity of the intersection between the corner portion where the tapered side surface intersects and the bottom surface of the V-shaped groove is chamfered. It is a feature.

  The first embodiment according to the present invention will be described in detail below with a focus on characteristic portions. A p-type diffusion layer having a depth of about 120 μm and a width of about 200 μm is formed on one main surface side of the n-type wafer in a lattice-like plane pattern (first step). If the depth is about 120 μm, the disadvantages due to the high temperature thermal diffusion of 1300 ° C. and 200 hours necessary for the thermal diffusion of several hundreds of μm as described above are considerably alleviated, even if the thermal diffusion is high temperature. There is no problem.

  A p-type base region is formed on the (100) plane of the wafer surrounded by the p-type diffusion layer, an n-type emitter region is formed on the surface of the p-type base region, and the p-type sandwiched between the n-type emitter region and the surface region of the n-type wafer. A MOS gate structure consisting of a gate electrode and the like provided on the surface of the mold base region via a gate insulating film and the gate electrode are covered with an interlayer insulating film, and then an emitter electrode mainly composed of aluminum is formed by a well-known manufacturing method To do. Thereafter, the other main surface of the wafer is polished to a wafer thickness of 180 μm. When a wafer having a thickness of 180 μm is used from the beginning of the wafer process, the step of reducing the wafer thickness by grinding the back surface is unnecessary.

  A non-penetrating V-shaped groove having a depth of 80 μm is formed on the other main surface of the wafer having a thickness of 180 μm with a lattice-shaped planar pattern having the same pitch as the lattice-shaped planar pattern of the p-type diffusion layer on the one main surface. This non-penetrating V-shaped groove having a depth of 80 μm uses the thermal oxide film formed on the other main surface as a mask and the (100) surface of the wafer exposed at the opening is made of TMAH (tetramethylammonium hydroxide). It can be obtained by etching with a 5% solution at 80 ° C. for 2 hours and 40 minutes. As a result, a non-penetrating V-shaped groove having a trapezoidal cross section is formed on the other main surface side of the wafer, which is wide on the back surface side and narrows as it becomes deeper (second step). Inside this non-penetrating V-shaped groove, a side wall composed of {111} planes which are the four side surfaces of the semiconductor chip is formed. When the opening width of this non-penetrating V-shaped groove is 150 μm, the depth to the bottom surface is 80 μm, and the width of the non-penetrating V-shaped groove bottom surface is a (100) surface of 36 μm. The bottom of the p-type diffusion layer formed from the emitter side on one main surface side is exposed on the bottom surface formed of the (100) surface of the formed non-penetrating V-shaped groove.

  Regarding the etching solution for forming the non-penetrating V-shaped groove, in addition to the above-mentioned TMAH aqueous solution, an etching solution made of a mixed solution of potassium hydroxide 21: isopropyl alcohol 8: water 71 is used and kept at a constant temperature from about 50 ° C. to 70 ° C. However, a non-penetrating V-shaped groove similar to that described above can also be formed. Further, as another etching solution, an aqueous solution containing hydrazine, ethylenediamine, or the like can be used.

  In the above-described etching solution, the etching rate for the (100) plane is about 100 times faster than the etching rate for the (111) plane. The (side wall) stops as a V-shaped groove composed of a {111} plane equivalent to the (111) plane. Further, if the difference in etching rate between the (100) plane and the (111) plane of this etching solution is utilized, it becomes practically possible to control the depth of the V-shaped groove by the opening width of the etching mask. In the wafer, since the angle formed by the (100) plane and the (111) plane is 54.7 °, for example, in Example 1, the opening width is 150 μm, and the depth of the V-shaped groove is stopped at about 80 μm. FIG. 18A shows a cross-sectional view of the wafer 1 in which the non-penetrating V-shaped groove 21b having such an inclined surface 9c and a bottom surface from which the bottom of the p-type diffusion layer 31 formed from the opposite surface is exposed is shown.

  Further, the anisotropic anisotropic etching has been described as an etching method for forming the non-penetrating V-shaped groove, but as another method for forming the non-penetrating V-shaped groove, the tip shape is V-shaped or reverse. A trapezoidal dicing blade can also be used (second step). In this case, if a non-penetrating V-shaped groove is formed with a dicing blade and then isotropic dry etching is performed, the surface distortion caused by the blade can be removed, and at the same time, the four corners of the corner portion can be chamfered.

After the formation of the non-penetrating V-shaped groove 21b having the inclined surface 9c shown in the cross-sectional view of FIG. 18 (a), the inclined surface 9d shown in FIG. 18 (b) according to the present invention is rounded. A manufacturing process for producing the non-penetrating V-shaped groove 21b is shown in FIG. First, a resist mask 32 having a thickness of about 0.5 μm to 5 μm is formed on the other main surface (collector surface) of the wafer 1 on which the non-penetrating V-shaped groove 21b is formed (FIG. 1A). Laser irradiation indicated by an arrow is applied toward the bottom surface of the non-penetrating V-shaped groove 21b (FIG. 1B). A YAG2ω laser (wavelength of 532 nm, half width of 100 ns) is used as the laser device, and the other main surface (collector surface) is irradiated from the vertical direction at an energy density of 4 J / cm ² . Since the collector surface above the side surface 9c shown in FIG. 1A is masked by the resist mask 32, the laser irradiation light does not strike. As the resist mask 32, the resist mask 32 that has been etched by TMAH for forming the non-penetrating V-shaped groove 21b can be used as it is. When an oxide film is used as an etching mask, a resist mask is formed again. By this laser irradiation, a side surface 9d having a corner portion chamfered to a radius of curvature R = 50 μm shown in FIG. 18B can be formed (FIGS. 1B, 1C) (third). Process). Although the side surface is also irradiated with laser, the side surface is inclined, so that the irradiation energy density per unit area is small and the influence of chamfering is small. On the other hand, in the lower part of the side surface near the bottom surface, the surface is melted by a large irradiation energy and is chamfered so as to be effectively rounded. Although a resist mask is described here as a mask for laser irradiation, a metal hard mask may be used.

Subsequently, as shown in FIG. 1C, boron is ion-implanted into the side surface using the resist mask 32. Ion implantation conditions of boron and a dosage of ^{1 × 10 15 atoms / cm 2} / 45keV. At this time, the semiconductor substrate may be tilted and implanted into the side wall as in the case of ion implantation into a normal vertical trench having a vertical side wall, but in the case of FIG. 1C, the non-penetrating V-shaped groove 21b side is provided. Since the inclination angle of the side surface 9d is approximately 125 °, the wafer can be implanted so as to be perpendicularly incident on the semiconductor substrate surface without being inclined. As a result, a boron ion implantation layer connected to the p-type diffusion layer 31 formed in the first step at one end 4b is formed on the side surface 9d of the non-penetrating V-shaped groove 21b. Subsequently, laser irradiation (YAG 2ω laser (wavelength 532 nm, half width 100 ns)) is performed at an irradiation energy density (4 J / cm ² ) The ion implantation layer on the side surface 9 d is activated by this laser annealing, and a p-type diffusion layer is formed. A separation layer 4b made of is formed.

Next, as shown in the cross-sectional view of the reverse blocking IGBT according to the first embodiment of FIG. 19, the inside of the non-penetrating V-shaped groove 21b is masked again with a resist (not shown), and non-penetrating V-shaped groove is formed by boron ion implantation. A boron ion implantation layer connected to the separation layer 4b is formed on a plane surrounded by the line. Again, laser irradiation (YAG2ω laser (wavelength 532 nm, half width 100 ns) is performed at an irradiation energy density (4 J / cm ² ) The ion implantation layer is activated by this laser annealing, and a p-type collector layer comprising a p-type diffusion layer 6 is formed (the waveform double broken line in FIG. 19 shows that there is an omission in the drawing).

  The p-type diffusion layer isolation layer 4b formed on the side surface 9d of the non-penetrating V-shaped groove 21b is a p-type diffusion formed from one surface of the semiconductor substrate at the bottom surface of the non-penetrating V-shaped groove 21b. Since it is connected to the layer 31 at one end and connected to the p-type collector layer 6 formed on the collector surface on the other side, the p-type region of the same conductivity type is a semiconductor. One main surface of the substrate is connected to the other main surface. As a result, the separation layer 4b moves the end surface of the collector pn junction 32 to one main surface (front surface) side of the wafer. The end surface of the collector pn junction 32 exposed on the surface is protected by the insulating film 19 on one main surface (surface) (FIG. 19).

Finally, when the collector electrode 7 made of Ti, Ni, Au or the like is deposited on the p-type collector layer 6 on the other main surface, the reverse blocking IGBT according to the present invention can be obtained (FIG. 19).
In the reverse blocking IGBT having the non-penetrating V-shaped groove according to the first embodiment of the present invention described above, the non-penetrating V-shaped groove is likely to occur when receiving a thermal history due to solder bonding during assembly. Since stress concentration is alleviated, chip cracking due to stress concentration at the four corners where the substrate is thin, deterioration of semiconductor characteristics, and the like can be suppressed.

Example 2 according to the present invention will be described below with a focus on features.
The non-penetrating V-shaped groove 21b is formed in the same manner as described in the first embodiment, and after chamfering the lower side surface 9c of the non-penetrating V-shaped groove 21b by laser irradiation, ion implantation and activation are performed. I do. As an activation method, unlike the laser annealing of the first embodiment, the low temperature annealing (hereinafter, annealing is used for activation) is performed in the second embodiment. Ion implantation is performed with boron at a dose of 1 × 10 ¹⁴ (cm ⁻² ) / 50 keV, and furnace annealing at a low temperature is performed at 380 ° C. for 1 hour. This temperature is determined so as to avoid 450 ° C. in consideration of deterioration of characteristics due to oxygen donor conversion in the vicinity of 450 ° C.

  FIG. 9A is an impurity concentration profile diagram of the p-type isolation layer obtained by SR measurement on the side surface 9d of the non-penetrating V-shaped groove 21b at that time. Although the activation rate of the boron ion implantation layer is as low as about 1%, an IGBT having reverse breakdown voltage characteristics can be formed.

  In the reverse blocking type IGBT having the non-penetrating V-shaped groove according to the second embodiment of the present invention described above, the non-penetrating V-shaped groove is likely to occur when receiving a thermal history due to solder bonding during assembly. Since stress concentration is alleviated, chip cracking due to stress concentration at the four corners where the substrate is thin, deterioration of semiconductor characteristics, and the like can be suppressed.

A third embodiment according to the present invention will be described below with a focus on features. The non-penetrating V-shaped groove 21b is formed in the same manner as described in the first embodiment, and after chamfering the lower side surface 9c of the non-penetrating V-shaped groove 21b by laser irradiation, the non-penetrating V-shaped groove 21b is formed. An ion implantation layer for forming a separation layer is formed by ion implantation of boron into the side surface 9d (FIG. 1). The third embodiment is different from the first and second embodiments described above in that flash lamp annealing is performed in order to activate the ion implantation layer to form the separation layer 4b. Ion implantation is performed with boron at a dose of 1 × 10 ¹⁴ (cm ⁻² ) / 50 keV, and flash lamp annealing is performed by heating the wafer to 300 ° C., which is hardly affected by oxygen donor formation, and raising the temperature in advance. In this state, irradiation was performed at an energy density of 30 J / cm ² . FIG. 10A is an impurity concentration profile diagram of the p-type isolation layer obtained by SR measurement on the side surface of the non-penetrating V-shaped groove at that time. The activation rate of the boron layer is about 40%, and an element having reverse breakdown voltage characteristics can be formed.

  In the reverse blocking IGBT having the non-penetrating V-shaped groove according to the third embodiment of the present invention described above, the non-penetrating V-shaped groove is likely to occur when receiving a thermal history due to soldering during assembly. Since stress concentration is alleviated, chip cracking due to stress concentration at the four corners where the substrate is thin, deterioration of semiconductor characteristics, and the like can be suppressed.

Example 4 according to the present invention will be described below with a focus on features. In Example 4, the ion implantation layer for forming the separation layer on the side surface and the ion implantation layer for forming the back surface p-type collector layer on the side surface in Examples 2 and 3 are formed at the same time, and then the ion implantation layer for forming the separation layer. And the back surface p-type collector layer forming ion-implanted layer are simultaneously performed by low-temperature furnace annealing. For both the separation layer on the side surface of the non-penetrating V-shaped groove and the back surface p-type collector layer, the ion implantation was performed with boron at a dose of 1 × 10 ¹⁴ (cm ⁻² ) / 50 keV. . The furnace annealing conditions at low temperature were 380 ° C. and 1 hour. FIG. 9B is an impurity concentration profile diagram obtained by SR measurement of the back surface p-type collector layer at that time. Although the activation rate of the boron layer is as low as about 1.3%, an element having reverse breakdown voltage characteristics can be formed. The concentration distribution of the back surface p-type collector layer becomes deeper than the side surface of the non-penetrating V-shaped groove (diffusion depth increases). The side surface is ion-implanted into the inclined surface. This is because the amount of dopant injected into the side surface is reduced by the amount of the etching (FIG. 9 to FIG. 11 also have a larger diffusion depth on the back collector layer for the same reason).

Further, simultaneous activation by flash lamp annealing may be performed instead of the low temperature furnace annealing. As activation conditions in this case, ion implantation was performed with boron at a dose of 1 × 10 ¹⁴ (cm ⁻² ) / 50 keV, and then flash lamp annealing was performed with an energy of 30 J / cm ² . FIG. 10B is an impurity concentration profile diagram obtained by SR measurement of the back surface p-type collector layer at that time. The activation rate of the boron ion implanted layer is about 40%, but an element having reverse breakdown voltage characteristics can be formed.

  According to the fourth embodiment described above, the side surface of the non-penetrating V-shaped groove and the back surface p-type collector layer do not need to be performed in separate steps, and stress generation at the lower corner is suppressed as described above. Therefore, it is possible to obtain an element that is not easily affected by chip cracking or chipping due to stress concentration.

Example 5 according to the present invention will be described below with a focus on features. In the present invention, after the non-penetrating V-shaped groove is formed by etching (in this case, alkali anisotropic etching), the chamfering process by laser irradiation is not performed in this process stage, and the side of the non-penetrating V-shaped groove is first performed. Boron ions are implanted into the surface. Thereafter, the ion-implanted layer formed on the side surface of the non-penetrating V-shaped groove is activated by laser irradiation to form a separation layer, and at the same time, chamfering is performed at the lower corner of the non-penetrating V-shaped groove. Ion implantation was performed with boron at a dose of 1 × 10 ¹⁴ (cm ⁻² ) / 50 keV, laser annealing conditions were YAG 2ω laser (wavelength 532 nm, half width 100 ns), and irradiation energy density 4 J / cm ² . FIG. 11A is an impurity concentration profile diagram obtained by SR measurement of the p-type separation layer formed on the side surface of the non-penetrating V-shaped groove at that time. The activation rate of the p-type isolation layer is about 50%, and an element having reverse breakdown voltage characteristics can be formed. Further, by this laser irradiation, a non-penetrating V-shaped groove having a chamfered corner lower portion of about R = 50 μm can be formed.

  FIG. 13: is sectional drawing which shows the process ((a)-(d)) of the characteristic part of the invention concerning Example 5 in order. (A) is sectional drawing which shows the process of forming the non-penetration V-shaped groove | channel 21b from the main surface on the opposite side to a p-type diffused layer by the alkali anisotropic etching similar to the above using the resist 32 as a mask. FIG. 6B is a cross-sectional view showing a boron ion implantation step into the side surface 9c of the non-penetrating V-shaped groove 21b using the same resist 32; (C) is sectional drawing which shows the laser irradiation process which performs simultaneously the formation of the p-type isolation | separation layer 4b by activation of the boron ion implantation layer formed in the said side surface 9c, and the chamfering of the lower side surface 9c lower part. (D) is sectional drawing which shows that the resist 32 is removed and the p-type isolation layer 4b and the p-type diffusion layer 31 are connected. As a result, the p-type diffusion layer is connected from one main surface of the wafer 1 to the other main surface, and the end of the collector pn junction 32 formed on the other main surface side extends to the one main surface (front surface) side. Can exist. Thereafter, a boron ion-implanted layer is formed on the other main surface surrounded by the side surface 21b, connected to the other end of the p-type isolation layer 4b, and activated to form a p-type collector layer.

A sixth embodiment according to the present invention will be described below with a focus on characteristic portions. In addition to the fifth embodiment, the present invention is a manufacturing method in which the separation layer on the side surface of the non-penetrating V-shaped groove and the back surface p-type collector layer can be simultaneously activated by laser irradiation. Both the side surface of the non-penetrating V-shaped groove and the back surface p-type collector layer are ion-implanted with boron at a dose of 1 × 10 ¹⁴ (cm ⁻² ) / 50 keV and laser annealing conditions. Is a YAG2ω laser (wavelength 532 nm, full width at half maximum 100 ns) at an irradiation energy density of 4 J / cm ² . FIG. 11B is an impurity concentration profile diagram obtained by SR measurement of the back surface p-type collector layer at that time. The activation rate of the boron ion implanted layer is about 60%, and an element having reverse breakdown voltage characteristics can be formed. Both the separation layer on the side surface of the non-penetrating V-shaped groove and the back surface p-type collector layer are activated, and at the same time, this laser irradiation causes a non-penetrating V having a chamfered corner lower portion of about R = 50 μm. A gutter can be formed.

  FIG. 12 is a reverse current-voltage waveform diagram for comparing the magnitude of the reverse leakage current of the reverse blocking IGBT due to the difference in the annealing method of the separation layer. (A) is a current-voltage waveform diagram in the reverse direction of the reverse-blocking IGBT by low-temperature furnace annealing produced in Examples 2 and 4. FIG. (B) is the current-voltage waveform diagram of the reverse direction of reverse blocking type IGBT by flash lamp annealing produced in Example 3, 4. FIG. (C) is the current-voltage waveform diagram of the reverse direction of the reverse blocking IGBT by laser annealing produced in Examples 5 and 6. FIG. All of (a), (b), and (c) are within the standard of the predetermined reverse leakage current, and are non-defective products, but when using flash annealing from low temperature furnace annealing and laser annealing from flash lamp Indicates that the leakage current is lower. The reason is that laser annealing can form a chamfered non-penetrating V-shaped groove corner portion, and at the same time, anneals the separation layer on the side surface of the non-penetrating V-shaped groove and the back surface p-type collector layer to form a crystal. This is because defects can be recovered.

  FIG. 14: is sectional drawing which shows process (a) of the invention part concerning Example 6 in order (b). 13 shows that the number of steps is two steps smaller than the four-step process of the invention portion according to Example 5 shown in the cross-sectional view of FIG. In the sixth embodiment, the YAG2ω laser has been described. However, an excimer laser (XeF, XeCl) or a laser device that activates at the same time that the inclined surface 9d of the non-through V-shaped groove 21b having a chamfered shape is formed can be used. An all-solid-state laser (YAG3ω) and a semiconductor laser may be used. A combination of an excimer laser and a semiconductor laser, or a combination of an all-solid-state laser is not a problem.

  By using laser irradiation to form the chamfered shape of the corner portion of the non-penetrating V-shaped groove and to activate the ion implantation region, it is possible to form an ion implantation layer with a high activation rate and to form a corner with a thin substrate thickness at the four corners It is possible to provide a method for manufacturing a reverse blocking IGBT with less cracking due to stress concentration and good semiconductor characteristics.

Further, in Examples 1 to 6 described above, laser irradiation is used as the method of the chamfering process, but the chamfering process can also be performed by isotropic dry etching. As the isotropic dry etching, well-known dry etching using XeF ₄ , CF ₄ or the like can be used.

DESCRIPTION OF SYMBOLS 1 Wafer 2 Oxide film 3 Opening 4 p-type diffusion layer 4a, 4b Separation layer 6 p-type collector layer 7 Collector electrode 10 M0S gate structure 15 n-type emitter region 16 p-type base region 17 Gate electrode 18 Emitter electrode 19 Insulating film 20 Mounting board 21a Through V-shaped groove 12b Non-through V-shaped groove 22 Solder 23 (100) surface 30b Reverse blocking IGBT
31 p-type diffusion layer 32 resist mask

Claims (4)

One main surface of the first conductivity type semiconductor substrate is provided with a second conductivity type diffusion layer having a lattice-like plane pattern, and the other main surface is provided with a lattice-like plane pattern having the same pitch as the lattice-like plane pattern. And having a V-shaped groove formed of a bottom surface that is parallel to the other main surface and from which the second conductivity type diffusion layer is exposed and a tapered side surface that rises from the bottom surface. a second conductive semiconductor layer on the other main surface surrounded by the side edge surface, along the side edge surface, wherein the other main surface and the second conductive type diffusion layer of the one main surface a second conductive separation layer of conductively connecting a second conductive type semiconductor layer, 4 the V-grooves, intersections and the sides faces of the bottom and the sides surfaces of the corner portions intersecting A semiconductor device characterized in that a corner has a chamfered shape. The semiconductor device according to claim 1, wherein the chamfered shape is a curved surface. 3. The semiconductor device according to claim 2, wherein the curved surface of the chamfered shape has a radius of curvature R = 50 [mu] m or more. 2. The semiconductor device according to claim 1, wherein the semiconductor device is a reverse blocking insulated gate bipolar transistor.