JP2013239600A - Semiconductor device manufacturing method and semiconductor manufacturing apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device having high withstanding voltage, a small device pitch and a small chip size, and high reliability; and provide a semiconductor manufacturing apparatus.SOLUTION: A semiconductor device manufacturing method comprises: forming grooves 32 along dicing lines only in a central part 31a of a semiconductor wafer 31; attaching, in dicing of the semiconductor wafer 31, a dicing tape 34 on a surface of the semiconductor wafer 31 where the grooves 32 are formed so as to generate hollow parts 35 by the grooves 32 between the semiconductor wafer 31 and the dicing tape 34; and by a control part controlling a vertical position of a blade 33 such that a tip of a blade 33 reaches the dicing tape 34 when a thick outer periphery of the semiconductor wafer 31 without the groove 32 is cut, and on the other hand, controlling the vertical position of the blade 33 such that the tip of the blade 33 does not reach the dicing tape 34 when a thin part in the central part 31a of the semiconductor wafer 31 where the grooves 32 are formed is cut.

Description

  The present invention relates to a semiconductor device manufacturing method and a semiconductor manufacturing apparatus.

  In the reverse blocking semiconductor device, a reverse blocking capability equivalent to the forward blocking capability is required. In order to ensure this reverse blocking capability, it is necessary to extend the pn junction that maintains the reverse breakdown voltage from the back surface of the semiconductor chip to the front surface. A diffusion layer for forming a pn junction extending from the back surface to the front surface is a separation layer. Conventionally, as a method for forming a reverse blocking IGBT separation layer, there is a first method for forming a separation layer by coating diffusion.

FIGS. 7A to 7D are cross-sectional views illustrating a state during the manufacture of the conventional reverse blocking IGBT. FIGS. 7A to 7D show a state in the process of manufacturing a conventional reverse blocking IGBT in the order of steps. In the first method, first, thermal oxidation is performed to form an oxide film 2 having a thickness of about 2.5 μm on the front surface of the n ⁻ -type semiconductor wafer 1 as a dopant mask (FIG. 7-1). . Next, the oxide film 2 is patterned and etched to form an opening 3 having a width of about 100 μm for forming a separation layer (FIG. 7-2).

  Next, a boron source 4 is applied to the opening 3 and heat treatment is performed for a long time at a high temperature in a diffusion furnace to form a p-type diffusion layer having a depth of about several hundred μm in the surface region of the semiconductor wafer 1 (FIG. 7-3). This p-type diffusion layer becomes the separation layer 5. Thereafter, although not particularly illustrated, after the surface structure is formed, the back surface of the semiconductor wafer 1 is ground to the extent that it reaches the separation layer 5 to thin the semiconductor wafer 1, and the ground surface 6 is constituted by a p collector region and a collector electrode. The back surface structure to be formed is formed. And the semiconductor wafer 1 is cut | disconnected by the dicing line located in the center part of the separation layer 5, and an IGBT chip | tip is obtained (FIGS. 7-4). 7-4, 7 is a p collector region, 8 is a p well region, 9 is a gate insulating film, 10 is a p breakdown voltage region, 11 is a dicing surface, and 12 is a field oxide film. The emitter region, gate electrode, interlayer insulating film, emitter electrode, field plate and collector electrode are not shown.

  As another method of forming the isolation layer of the reverse blocking IGBT, there is a second method of forming the isolation layer by forming a diffusion layer on the sidewall of the trench. In the second method, first, an etching mask is formed on the front surface of the semiconductor wafer with an oxide film having a thickness of several μm. Then, dry etching is performed to form a trench having a depth of about several hundred μm in the semiconductor wafer. Next, a vapor phase diffusion process is performed to introduce impurities into the sidewalls of the trench, thereby forming an isolation layer on the sidewall of the trench. Next, the trench is filled with a reinforcing material to form a back structure such as a p collector region and a collector electrode, and then diced along a dicing line to obtain an IGBT chip from the semiconductor wafer. In this way, the reverse blocking IGBT is completed. The second method is disclosed in, for example, the following Patent Documents 1 to 3.

  In the following Patent Document 1, a trench reaching the back side pn junction from the front surface of the device is formed so as to surround the active region, and a diffusion layer serving as a separation layer is formed on the side wall of the trench, thereby forming the back side pn It has been proposed to extend the junction to the front surface of the device. In the following Patent Documents 2 and 3, as in the following Patent Document 1, it is proposed to secure reverse blocking capability by forming a diffusion layer on the side wall of the trench reaching the back surface pn junction from the front surface of the device. .

  As another method for forming the reverse blocking IGBT separation layer, there is a third method in which a V-shaped groove is formed by wet anisotropic wet etching and a p separation layer is formed on the sidewall of the groove. This third method is disclosed, for example, in Patent Documents 4 to 6 below.

  In the following Patent Document 4, the surface of a thin semiconductor wafer on which a surface structure constituting a semiconductor chip is formed is attached to a support substrate with a double-sided adhesive tape, and a trench that becomes a dicing line from the back surface of the thin semiconductor wafer is formed by wet anisotropic etching. It has been proposed to form a separation layer that protrudes from the crystal face and maintains the reverse breakdown voltage on the side surface of the trench where the crystal face is exposed by ion implantation and low-temperature annealing or laser annealing simultaneously with the p collector region that is the back diffusion layer. ing.

  In the following Patent Document 5, a thin semiconductor wafer on which a front surface structure and a back surface structure constituting a semiconductor chip are formed is attached to a support substrate with a double-sided adhesive tape, and a trench serving as a dicing line is crystallized by wet anisotropic etching on the thin semiconductor wafer. Ion implantation and low-temperature annealing or laser so that a separation layer that maintains a reverse breakdown voltage is formed on the side surface of the trench where the crystal plane is exposed and extends to the surface side in contact with the p collector region that is the back diffusion layer. It has been proposed to form by annealing.

  In the following Patent Document 6, a groove serving as a second side wall is formed on an n semiconductor substrate by cutting with an inverted trapezoidal dicing blade. The bottom of the groove is in contact with the p diffusion layer formed on the first main surface (front surface) of the n semiconductor substrate so that the p diffusion layer is not cut. It has been proposed to form a p isolation layer connected to the p collector layer and the p diffusion layer on the second sidewall.

  Further, as a semiconductor wafer dicing apparatus, a dicing apparatus for cutting a certain amount of a plate-like object in a thickness direction thereof, a stage for fixing the plate-like object, and a surface of the plate-like object fixed on the stage A surface displacement recognizing means for measuring the displacement state of the height position at each point of the surface, and a plane of the plate-like object while controlling vertical movement on the surface of the plate-like object based on displacement information from the surface displacement recognizing means. An apparatus including a rotating blade mechanism that performs cutting in a direction has been proposed (for example, see Patent Document 7 below).

  As another dicing method of a semiconductor wafer, a dicing method in which a wafer having a circuit pattern to be a plurality of semiconductor elements formed on the front surface and an adhesive sheet attached to the back surface is diced with a blade to obtain individual pieces of the semiconductor elements. In the above, when the blade dices the peripheral portion of the semiconductor element that becomes a piece, the blade edge of the blade is cut to a position that reaches the adhesive sheet, and the blade does not become a piece of the semiconductor element. When dicing the peripheral edge of a wafer, a method of cutting so that the blade edge of the blade does not reach the back surface of the wafer has been proposed (for example, see Patent Document 8 below).

JP-A-2-02869 JP 2001-185727 A JP 2002-076017 A JP 2006-303410 A JP 2006-156926 A International Publication No. 2009/139417 JP-A 64-040307 JP 2007-019478 A

  However, in the first method described above, in order to form the separation layer 5 having a diffusion depth of about several hundred μm, a diffusion process is required at a high temperature for a long time (for example, 1300 ° C. for 200 hours). For this reason, quartz jigs such as quartz boards, quartz tubes (quartz tubes) and quartz nozzles constituting the diffusion furnace are deteriorated, contaminated by the heater, and the strength of the quartz jig is reduced due to devitrification. There is a problem. In order to form a high-quality and thick oxide film 2 that can withstand diffusion treatment at high temperature for a long time (eg, 1300 ° C., 200 hours) by a dry (dry oxygen atmosphere) oxidation method, the film thickness is set to about 2.5 μm. For example, it is necessary to perform thermal oxidation at 1150 ° C. for about 200 hours. Even wet oxidation or pyrogenic oxidation, which is slightly inferior to the dry oxidation method, requires about 15 hours of treatment. Thus, since it is necessary to perform the thermal oxidation process for a long time, there exists a problem that a throughput falls.

  In addition, since a large amount of oxygen is introduced into the semiconductor wafer during a long-time thermal oxidation treatment, oxygen precipitates are generated, crystal defects such as oxidation induced stacking faults (OSF) and slip dislocations occur. Introduced or oxygen donors are generated. For these reasons, there is a problem that the leakage current at the pn junction increases and the withstand voltage and reliability of the insulating film formed on the semiconductor wafer are significantly reduced. Usually, the same problem occurs in the diffusion treatment performed in an oxidizing atmosphere. Furthermore, since the angle formed by the active region side between the separation layer 5 and the p collector region 7 is steep at the back surface edge portion of the semiconductor chip, there is a possibility that the breakdown voltage is reduced due to electric field concentration.

In addition, in the second method described above, when a high aspect ratio trench is formed by dry etching, a residue of a resist or a chemical solution may be generated in the trench, resulting in a decrease in yield or reliability. There is a problem of doing. In addition, when introducing an impurity into a trench having a high aspect ratio, an ion implantation method is not appropriate due to a decrease in effective dose or a decrease in implantation uniformity. Therefore, PH ₃ (phosphine) or B ₂ H ₆ ( A vapor phase diffusion method is used in which a semiconductor wafer is exposed to a dopant atmosphere in which diborane or the like is gasified. However, the vapor phase diffusion method is inferior to the ion implantation method in terms of precise controllability of the dose. Further, in the vapor phase diffusion method, the dose of the dopant that can be introduced is often limited by the solubility limit.

  Furthermore, when the aspect ratio of the trench is high, a gap called a void may be formed in the trench when the trench is filled with an insulating film, resulting in a problem that reliability is lowered. Further, in order to avoid deterioration of device characteristics due to exposure of the surface of the semiconductor wafer to the plasma atmosphere for a long time when forming the trench, it is necessary to form the trench before forming the gate structure. In that case, it is necessary to fill the trench with a semiconductor film, an insulating film, or the like in order to avoid generation of a resist or chemical residue in the trench in various processes after the trench is formed. Therefore, there is a problem that the manufacturing cost increases.

  In the third method described above, when a V-shaped groove is formed from the front surface on which the gate structure of the semiconductor wafer is formed, the gate structure requires a predetermined area. The device pitch is increased by the opening width of the shape. Furthermore, since the separation layer and the p collector region are contacted at a steep angle at the back surface edge portion of the semiconductor chip, there is a possibility that the breakdown voltage is reduced due to electric field concentration. These problems can be avoided by forming a V-shaped groove from the back surface of the semiconductor wafer. In addition, by forming the V-shaped groove from the back surface of the semiconductor wafer, the diffusion processing time can be significantly shortened compared to the first method.

FIG. 4 is an explanatory diagram showing an example of the relationship between the breakdown voltage class and the thickness of the semiconductor chip. FIG. 4 shows an example of the thickness of the semiconductor chip for each withstand voltage class when the reverse blocking IGBT is manufactured. As shown in FIG. 4, the higher the breakdown voltage class, the thicker the semiconductor chip. Therefore, when the depth of the p breakdown voltage region formed on the front surface of the semiconductor chip is constant, the p breakdown voltage region and the p The p ⁺ isolation layer for connecting the collector region becomes thicker as the thickness of the semiconductor chip increases. Therefore, in the method of forming the p ⁺ isolation layer on the side wall of the V-shaped groove formed from the back surface of the semiconductor wafer, the effect of shortening the processing time is particularly significant as the thickness of the semiconductor chip is increased.

  However, the groove extends from the region where the device is formed at the center of the semiconductor wafer (hereinafter referred to as the device formation region) to the end of the semiconductor wafer across the region where the device is not formed, which surrounds the device formation region. There is a possibility that the strength of the semiconductor wafer may be lowered and easily cracked depending on the position and shape of the groove, for example, when the groove is formed or when the cross-sectional shape of the groove is a complete V shape without a bottom surface. Therefore, in order to ensure the strength of the semiconductor wafer, it is desirable to form a trapezoidal groove only in the device formation region at the center of the semiconductor wafer. This state is shown in FIG. FIG. 5 is an explanatory view showing a state in which grooves are formed on the back surface of the semiconductor wafer. The trapezoidal groove 22 is shown in the right sectional view of FIG. 5, and the formation position of the groove 22 is shown in the left plan view of FIG. A hatched portion surrounded by the outermost groove 22 is a device formation region of the semiconductor wafer 21a.

  FIG. 6 is an explanatory view schematically showing the positional relationship between a blade and a semiconductor wafer during conventional dicing. FIG. 6A shows the state of the semiconductor wafer 21a formed with the groove 22 shown in FIG. 5 during full cut dicing, and FIG. 6B shows the state of the normal flat semiconductor wafer 21b during full cut dicing. Indicates the state. The full cut dicing is to cut the semiconductor wafer so as to cut into the dicing tape 24 attached to the back surface of the semiconductor wafer. Both the semiconductor wafers 21 a and 21 b have a dicing tape 24 attached to the back surface, and are placed on the stage 26 via the dicing tape 24.

  Normally, as shown in FIG. 6A, the dicing tape 24 cannot be attached to the semiconductor wafer 21a in which the groove 22 is formed along the side wall of the groove 22. The hollow part 25 by the groove | channel 22 arises in between. Since the groove 22 coincides with the dicing line, unlike the full cut dicing of the normal flat semiconductor wafer 21b, in the full cut dicing of the semiconductor wafer 21a in which the groove 22 is formed, the blade 23 is formed between the semiconductor wafer 21a and the dicing tape 24. It will pass through the hollow part 25 produced in between.

  Thus, as a result of the inventors' diligent research on the dicing of the semiconductor wafer 21a in which the grooves 22 are formed, the following problem has been newly found. Even if the groove 22 is formed on the back surface of the semiconductor wafer 21a, full-cut dicing is possible, but a large amount of debris during dicing is present in the vicinity of the groove 22 even though cleaning is performed after dicing. It was confirmed that it was adhered. The reason for this is that the circulation of the water that is supplied to the cutting location during dicing and discharges the cutting waste to the outside is stagnant in the hollow portion 25, and the washing water does not circulate sufficiently in the hollow portion 25 even during the cleaning after dicing. It is estimated that. Further, organic components mainly composed of a silicon (Si) component and carbon (C) were detected as components of deposits near the groove 22. For this reason, it is presumed that the main deposits in the vicinity of the groove 22 are cutting scraps of the semiconductor wafer itself and scraps of the dicing tape 24 scraped by the blade 23 during full cut dicing.

  Therefore, half dicing (not shown) for cutting only a thin portion where the groove 22 is formed in the central portion of the semiconductor wafer 21a is performed so that the blade 23 is not cut into the dicing tape 24. It was confirmed that the cutting waste was reduced. In the assembly process of modules and the like, the entire back surface of the chip is soldered. Therefore, foreign matters other than the back surface electrode present on the back surface of the chip, which is a joint surface with the solder, may cause the reliability to deteriorate. Therefore, it is preferable to keep the back surface of the semiconductor chip as clean as possible without deposits. In this respect, it is effective to reduce deposits near the grooves 22 by half-cut dicing. However, as shown in FIG. 5, since the groove 22 is formed only in the device forming region in the central portion of the semiconductor wafer 21a, the outer peripheral portion of the semiconductor wafer 21a in which the groove 22 is not formed is not completely cut by half-cut dicing. . For this reason, in order to prevent the chips from interfering with each other when the semiconductor chips are peeled from the dicing tape 24, it is not possible to perform the wafer expanding process that extends the dicing tape 24 and widens the distance between the chips. There is a problem that peeling work is difficult.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device manufacturing method and a semiconductor manufacturing apparatus capable of manufacturing a highly reliable semiconductor device in order to eliminate the above-described problems caused by the prior art. Another object of the present invention is to provide a semiconductor device manufacturing method and a semiconductor manufacturing apparatus capable of manufacturing a semiconductor device having a small device pitch and chip size. Furthermore, an object of the present invention is to provide a semiconductor device manufacturing method and a semiconductor manufacturing apparatus capable of manufacturing a semiconductor device having a high breakdown voltage.

  In order to solve the above-described problems and achieve the object of the present invention, a semiconductor device manufacturing method according to the present invention includes a semiconductor device manufacturing method in which a semiconductor wafer having grooves formed in a device forming region is cut into chips. A step of attaching a tape to the surface of the semiconductor wafer on which the groove is formed, a step of placing the semiconductor wafer on a stage via the tape, and a region other than the device formation region A first cutting step of cutting the semiconductor wafer with the blade in a state where the blade edge of the blade has reached the tape in the region; and in the device formation region, the blade edge of the blade is separated from the tape by the blade. And a second cutting step of cutting the semiconductor wafer along the groove.

  In the semiconductor device manufacturing method according to the present invention, in the above-described invention, after the first cutting step, the blade is raised to the position of the blade at the time of the second cutting step, and the second cutting step is performed. It is characterized by that.

  Further, in the above-described invention, the method of manufacturing a semiconductor device according to the present invention includes the step of following the inclination of the side wall of the groove until reaching the position of the blade at the time of the second cutting step after the first cutting step. The blade is raised.

  According to the semiconductor device manufacturing method of the present invention, in the above-described invention, in the first cutting step, a thick outer peripheral portion without a groove of the semiconductor wafer is completely cut, and in the second cutting step, the semiconductor A thin portion where the groove is formed at the center of the wafer is completely cut.

  In the method for manufacturing a semiconductor device according to the present invention, in the above-described invention, in the attaching step, the tape is attached so that a hollow portion is formed by the groove between the semiconductor wafer and the tape. Features.

  According to the method for manufacturing a semiconductor device according to the present invention, in the above-described invention, before the attaching step, the back surface of the first conductivity type semiconductor wafer is connected to the pn junction on the front surface side of the semiconductor wafer. A groove forming step for forming the groove reaching, a second conductivity type collector region on the back surface of the semiconductor wafer, and a second conductivity type separation layer extending from the collector region to the pn junction on the side wall of the groove And a step of forming a collector electrode for covering the second conductivity type separation layer.

  In order to solve the above-described problems and achieve the object of the present invention, a semiconductor manufacturing apparatus according to the present invention is a semiconductor manufacturing apparatus that cuts a semiconductor wafer having grooves formed in a device formation region into chips. A stage for holding the semiconductor wafer via a tape attached to the surface on which the groove is formed, a blade for cutting the semiconductor wafer held on the stage along the groove, and the semiconductor wafer When cutting an area other than the device forming area of the blade, when controlling the vertical position of the blade so that the blade edge of the blade reaches the tape, and cutting the device forming area along the groove And control means for controlling the position of the blade in the vertical direction so that the blade edge of the blade is separated from the tape.

  Further, in the semiconductor manufacturing apparatus according to the present invention, in the above-described invention, the control means moves the blade from the thick outer peripheral portion without the groove of the semiconductor wafer to the thin portion where the groove is formed at the central portion of the semiconductor wafer. And the blade is raised after the outer peripheral portion of the semiconductor wafer is completely cut by the blade.

  In the semiconductor manufacturing apparatus according to the present invention, in the above-described invention, the control means raises the blade along the inclination of the side wall of the groove after the outer peripheral portion of the semiconductor wafer is completely cut. It is characterized by.

  The semiconductor manufacturing apparatus according to the present invention is characterized in that, in the above-described invention, the tape is attached so that a hollow portion is formed by the groove between the semiconductor wafer and the tape.

  According to the above-described invention, full cut dicing is performed in the outer peripheral portion where the groove of the semiconductor wafer is not formed, and half cut dicing is performed in the central portion where the groove of the semiconductor wafer is formed, so that the semiconductor which is a device formation region The dicing tape is not scraped off by the blade during dicing at the center of the wafer. For this reason, it is possible to reduce silicon grinding scraps and dicing tape scraps remaining in the vicinity of the grooves of the semiconductor wafer after dicing.

  According to the above-described invention, the V-shaped groove is formed so as to reach the pn junction of the front surface from the back surface of the semiconductor wafer, and the second conductivity type separation layer is formed on the side wall of the groove. There is no need to perform a long-time diffusion treatment to form a two-conductivity type separation layer or to form a high aspect ratio trench. In addition, according to the embodiment, the lateral diffusion of the dopant is reduced by forming the V-shaped groove from the back surface of the semiconductor wafer and forming the second conductivity type separation layer on the side wall of the groove. Therefore, the device pitch and chip size can be reduced. Further, according to the embodiment, by forming the V-shaped groove from the back surface of the semiconductor wafer, the angle formed by the active region side between the second conductivity type separation layer and the collector region at the back surface edge portion of the semiconductor chip is increased. Since it does not become steep, it is possible to avoid a decrease in breakdown voltage due to electric field concentration.

  According to the semiconductor device manufacturing method and the semiconductor manufacturing apparatus according to the present invention, it is possible to manufacture a highly reliable semiconductor device at low cost. Further, according to the semiconductor device manufacturing method and the semiconductor manufacturing apparatus according to the present invention, the device pitch and the chip size can be reduced. Furthermore, according to the semiconductor device manufacturing method and the semiconductor manufacturing apparatus according to the present invention, it is possible to manufacture a semiconductor device having a high breakdown voltage.

It is sectional drawing explaining the manufacturing method of the semiconductor device concerning embodiment of this invention. It is explanatory drawing which shows typically the positional relationship of the semiconductor wafer at the time of dicing in the cutting line A-A 'of FIG. It is an example of the semiconductor device which can be manufactured by applying the manufacturing method of the semiconductor device concerning embodiment of this invention. It is explanatory drawing which shows an example of the relationship between a pressure | voltage resistant class and the thickness of a semiconductor chip. It is explanatory drawing which shows the state in which the groove | channel was formed in the back surface of a semiconductor wafer. It is explanatory drawing which shows typically the positional relationship of the braid | blade and semiconductor wafer at the time of the conventional dicing. It is sectional drawing which shows the state in the middle of manufacture of the conventional reverse blocking IGBT. It is sectional drawing which shows the state in the middle of manufacture of the conventional reverse blocking IGBT. It is sectional drawing which shows the state in the middle of manufacture of the conventional reverse blocking IGBT. It is sectional drawing which shows the state in the middle of manufacture of the conventional reverse blocking IGBT.

  Exemplary embodiments of a semiconductor device manufacturing method and a semiconductor manufacturing apparatus according to the present invention will be explained below in detail with reference to the accompanying drawings. In the present specification and the accompanying drawings, it means that electrons or holes are majority carriers in layers and regions with n or p, respectively. Further, + and − attached to n and p mean that the impurity concentration is higher and lower than that of the layer or region where it is not attached. Note that, in the following description of the embodiments and the accompanying drawings, the same reference numerals are given to the same components, and duplicate descriptions are omitted.

(Embodiment)
FIG. 1 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 2 is an explanatory view schematically showing the positional relationship of the cross section of the semiconductor wafer during dicing along the line AA ′ in FIG. First, a semiconductor wafer 31 to be diced by applying a semiconductor device manufacturing method according to an embodiment of the present invention will be described. As shown in FIGS. 1 and 2, the semiconductor wafer 31 is provided with a groove 32 in a region (device formation region) where a device of the central portion 31 a is formed so as not to reach the other main surface from one main surface. ing. Due to the groove 32, the central portion 31a of the semiconductor wafer 31 is partially thinned. The device formation region is a portion indicated by a thick frame surrounded by the outermost peripheral groove 32 in the groove 32, and is an effective area for forming a semiconductor device with a high yield.

  The groove 32 is provided so as not to reach the end of the semiconductor wafer 31. That is, the groove 32 is not provided in the outer peripheral portion 31b of the semiconductor wafer 31 surrounding the device formation region. For this reason, the outer peripheral portion 31 b of the semiconductor wafer 31 is thicker than the portion of the central portion 31 a of the semiconductor wafer 31 where the groove 32 is provided. Moreover, the groove | channel 32 is provided in the grid | lattice form, for example along the dicing line. FIG. 1 shows a cross-sectional structure along a line (arrow 41) that cuts the groove 32 in the X direction.

  Each region in the device formation region divided into a plurality by the grooves 32 is a region that becomes a semiconductor chip after dicing. Although not shown, the cross-sectional structure in which the region to be the semiconductor chip is cut by a line parallel to the X direction has a configuration in which each region to be the semiconductor chip protrudes in a convex shape with respect to the deepest portion of the groove 32 in the Y direction. It has become. The same applies to the cross-sectional structure when a region to be a semiconductor chip is cut along a line parallel to the Y direction. Moreover, the groove | channel 32 may be trapezoid shape as shown in a substantially rectangular shape, V shape, and FIG. 2, for example. FIG. 2 shows a cross-sectional structure taken along line A-A ′ perpendicular to the arrow 41 in the X direction and crossing a region to be a convex semiconductor chip. A device structure formed in a region to be a semiconductor chip will be described later.

  The side wall of the groove 32 may be substantially perpendicular to the main surface of the semiconductor wafer 31 or may be inclined with respect to the main surface of the semiconductor wafer 31. When the side wall of the groove 32 is substantially perpendicular to the main surface of the semiconductor wafer 31, the groove 32 is formed by, for example, anisotropic wet etching. When the side wall of the groove 32 is inclined with respect to the main surface of the semiconductor wafer 31, the opening width is closer to the opening side (back surface side) than the bottom surface side (front surface side), for example, by isotropic wet etching. ) Forms a wide groove 32. 1 and 2 show a state in which the side wall of the groove 32 is inclined with respect to the main surface of the semiconductor wafer 31.

  Next, a semiconductor manufacturing apparatus according to an embodiment of the present invention will be described. A semiconductor manufacturing apparatus according to an embodiment of the present invention includes a stage 36 for holding a semiconductor wafer 31, a blade 33 for dicing the semiconductor wafer 31, a control unit (not shown) for controlling the position of the blade 33 (or stage 36), It is comprised with the memory | storage part (not shown) which memorize | stores the information which a control part refers. A semiconductor wafer 31 is placed on the stage 36 via a dicing tape 34. The dicing tape 34 is affixed to the surface of the semiconductor wafer 31 where the grooves 32 are formed so that a hollow portion 35 is formed by the grooves 32 between the semiconductor wafer 31 and the dicing tape 34.

  The blade 33 (or stage 36) is movable in two directions (X direction and Y direction) parallel to the main surface of the semiconductor wafer 31 and orthogonal to each other, and in a direction orthogonal to the main surface of the semiconductor wafer 31 (Z direction). It is supported. When the semiconductor wafer 31 is diced, the position of the blade 33 (or stage 36) in the horizontal direction (XY direction) and the vertical direction (Z direction) is controlled by the control unit, and the semiconductor wafer 31 is cut one by one along the dicing line. (In FIG. 1, a rough arrow 41 indicates a direction in which the semiconductor wafer 31 is cut along one dicing line parallel to the X direction).

  The distance in the X direction from the end of the semiconductor wafer 31 to the end of the groove 32 on the dicing line (the distance in the Y direction when the semiconductor wafer 31 is cut along the dicing line parallel to the Y direction) is dicing. Different for each line. Such information regarding the groove 32 is stored in, for example, a storage unit. The information about the groove 32 is, for example, the XY coordinates of both ends of the groove 32 with respect to the center of the semiconductor wafer 31 or the X direction (Y direction) from the end of the semiconductor wafer 31 to the end of the groove 32 on the dicing line. ), The inclination angle of the side wall of the groove 32, and the like.

  Information about the groove 32 is stored in advance in the storage unit, for example. The control unit controls the position of the blade 33 in the XY direction and the vertical direction based on the information regarding the groove 32 stored in the storage unit. Specifically, the control unit has a plurality of dicing lines extending in parallel to the X direction and arranged in a stripe shape in the Y direction (or a plurality of dicing lines extending in parallel to the Y direction and arranged in a stripe shape in the X direction. Each time one line is cut, the blade 33 is moved in the Y direction (or X direction) to cut another dicing line parallel to the cut dicing line.

  Further, the control unit controls the position of the blade 33 in the Z direction so that the blade tip of the blade 33 reaches the dicing tape 34 in the region other than the device formation region, that is, the outer peripheral portion 31 b of the semiconductor wafer 31 by the blade 33. The control unit controls the position of the blade 33 in the Z direction so that the blade tip of the blade 33 does not reach the dicing tape 34 as shown in FIG. 2 in the device formation region, that is, the central portion 31 a of the semiconductor wafer 31 by the blade 33. . That is, the control unit controls the position of the blade 33 in the Z direction according to the thickness of the semiconductor wafer 31. In FIG. 1, the locus of the lowermost edge of the blade 33 when cutting the semiconductor wafer 31 as indicated by an arrow 41 is indicated by a fine dotted arrow 42.

  A method for controlling the position of the blade 33 in the Z direction by the control unit will be described more specifically. First, the controller controls the blade 33 so that the lowermost end of the blade 33 reaches the dicing tape 34 before the blade 33 cuts one outer peripheral portion 31b (starting side of the arrow 42) of the semiconductor wafer 31. Determine the position in the Z direction. And a control part maintains the position of the Z direction of the braid | blade 33, while the one outer peripheral part 31b of the semiconductor wafer 31 is cut | disconnected. That is, the cutting of the outer peripheral portion 31b of the semiconductor wafer 31 is full cut dicing.

  Next, the control unit raises the blade 33 substantially vertically after one outer peripheral portion 31b of the semiconductor wafer 31 is completely cut. At this time, the controller controls the position of the blade 33 in the Z direction so that the thin portion is completely cut by the groove 32 of the central portion 31 a of the semiconductor wafer 31 and the lowermost end of the blade 33 does not reach the dicing tape 34. To decide. The control unit then moves the blade 33 in the Z direction until the leading edge side of the blade 33 that cuts the central portion 31a of the semiconductor wafer 31 reaches the other outer peripheral portion 31b of the semiconductor wafer 31 (the end point side of the arrow 42). Maintain position. That is, the cutting of the central portion 31a of the semiconductor wafer 31 is half-cut dicing.

  Thereafter, the control unit makes the blade 33 substantially vertical so that the lowermost end of the blade 33 reaches the dicing tape 34 when the moving direction side of the blade 33 reaches the other outer peripheral portion 31 b of the semiconductor wafer 31. Lower. Then, the control unit maintains the position of the blade 33 in the Z direction until the other outer peripheral portion 31b of the semiconductor wafer 31 is completely cut. Thereby, the cutting of the semiconductor wafer 31 is completed with one dicing line. The control of the blade 33 by such a control unit is performed for each dicing line.

  The blade 33 is disk-shaped and has a predetermined diameter. For this reason, when the outer peripheral portion 31b of the semiconductor wafer 31 is completely cut, the cutting edge of the blade 33 reaches the outermost device forming region, and a part of the outermost device forming region is formed by full-cut dicing. Disconnected. However, it has been confirmed by the inventor of the present invention that the chipping state of the semiconductor chip after cutting can be used as a product both at the time of full cut dicing and half cut dicing. Therefore, even if a part of the device formation region is fully cut and diced in a state where the blade 33 is located at a position several tens of micrometers lower than the preferred height of the blade 33, the chipping state of the semiconductor chip is not greatly affected. It is guessed.

  The controller raises (lowers) the blade 33 stepwise or continuously after the blade 33 completely cuts a portion of the one (other) outer peripheral portion 31 b of the semiconductor wafer 31 that is in contact with the dicing tape 34. You may let them. When the position of the blade 33 in the Z direction is changed step by step, the locus of the lower end portion of the blade tip of the blade 33 is stepped. When the position of the blade 33 in the Z direction is continuously changed, the locus of the lower end portion of the blade 33 is inclined with respect to the main surface of the semiconductor wafer 31. Thus, by raising (lowering) the blade 33 stepwise or continuously, the position of the blade 33 in the Z direction can be changed while cutting the semiconductor wafer 31.

  For example, when the side wall of the groove 32 is inclined with respect to the main surface of the semiconductor wafer 31, the blade 33 is raised (lowered) stepwise or continuously along the groove 32, thereby The position of the blade 33 in the Z direction can be changed stepwise or continuously along the inclination. Therefore, the blade 33 can be raised (lowered) without scraping the dicing tape 34 before the blade 33 reaches the thinnest portion of the groove 32 of the central portion 31 a of the semiconductor wafer 31, and the semiconductor wafer 31. In the outer peripheral portion 31b, the inclined portion 31c of the side wall of the groove 32 whose thickness gradually decreases toward the central portion 31a can be completely cut.

  Further, instead of controlling the position of the blade 33 in the Z direction, the position of the stage 36 in the Z direction may be controlled. In this case, the control unit controls the position of the stage 36 in the Z direction so that the positions of the blade 33 and the semiconductor wafer 31 are maintained in the same manner as the control for the blade 33.

Next, an example of a semiconductor device that can be manufactured by applying the manufacturing method of the semiconductor device according to the embodiment of the present invention will be described. FIG. 3 is an example of a semiconductor device that can be manufactured by applying the semiconductor device manufacturing method according to the embodiment of the present invention. 3, the same components as those in FIG. 1 are denoted by the same reference numerals. As shown in FIG. 3, on the front surface of the semiconductor wafer 31 to be the n ⁻ drift region, in the active region where current flows when it is turned on, it is made of MOS (metal-oxide film-semiconductor) such as an emitter region and a gate electrode. An insulating gate) structure (not shown), an emitter electrode (not shown), a p-well region 51, and a gate insulating film 52 are provided.

A p ⁺ breakdown voltage region 53, a field oxide film 54, and a field plate (not shown) are provided on the front surface of the semiconductor wafer 31 so as to surround the active region. A groove 32 is provided on the back surface of the semiconductor wafer 31. A p ⁺ collector region 55 is provided on the entire back surface of the semiconductor wafer 31. The side walls of the groove 32, p ⁺ isolation layer 56 which connects the p ⁺ voltage region 53 and p ⁺ collector region 55 are provided. A collector electrode (not shown) covers the p ⁺ collector region 55 and the p ⁺ isolation layer 56. The semiconductor wafer 31 is diced along the grooves 32 formed in the dicing region, and becomes a reverse blocking IGBT chip.

Next, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described by taking as an example the case where the blade 33 is controlled by the control unit. First, as shown in FIG. 3, a p-well region 51, a gate insulating film 52, a p ⁺ breakdown voltage region 53, and a field oxidation are formed on the front surface of an n-type semiconductor wafer 31 serving as an n ⁻ drift region by a known method. A front surface structure including the film 54 is formed. The p ⁺ breakdown voltage region 53 is formed so as to include a region (dicing region) to be cut in a subsequent dicing process.

Further, a groove 32 that penetrates the n ⁻ drift region and reaches the p ⁺ breakdown voltage region 53 is formed on the back surface of the semiconductor wafer 31 by a known method. Then, a p ⁺ isolation layer 56 is formed on the back surface structure including the p ⁺ collector region 55 on the back surface of the semiconductor wafer 31 and on the side wall of the groove 32 by a known method. The p ⁺ collector region 55 and the p ⁺ isolation layer 56 may be formed simultaneously. At this stage, the wafer process is finished. Therefore, although not shown, an emitter region, a gate electrode, an interlayer insulating film, an emitter electrode, a field plate, a collector electrode, and the like are also formed.

  Next, as shown in FIG. 1, a dicing tape 34 is attached to the back surface of the semiconductor wafer 31 where the grooves 32 are formed so that a hollow portion 35 is formed by the grooves 32. In FIG. 1, since the cross section by the line 41, ie, the cross section of the groove | channel 32, is shown, the hollow part 35 is continuing in the X direction. As shown in FIG. 2, the region (the convex portion) to be a semiconductor chip is attached to a dicing tape. The dicing tape 34 may or may not be of a UV curing type that can be peeled off by curing by irradiation with UV light. The dicing tape 34 is fixed to a frame (not shown) having an inner diameter larger than the diameter of the semiconductor wafer 31. Next, the semiconductor wafer 31 is placed on the stage 36 with the dicing tape 34 side down (stage 36 side).

  Next, the control unit reads the position information of the blade 33 stored in the storage unit, and controls the position in the XY direction and the position in the Z direction of the blade 33 based on the position information. As a result, the outer peripheral portion 31 b of the semiconductor wafer 31 is fully cut and diced so that the cutting edge of the blade 33 reaches the dicing tape 34. On the other hand, the central portion 31 a of the semiconductor wafer 31 is half-cut diced so that the cutting edge of the blade 33 does not reach the dicing tape 34.

  Specifically, when the blade 33 is controlled by the control unit, the blade 33 is moved as follows to cut the semiconductor wafer 31. First, the position of the blade 33 in the X and Y directions is such that the cutting edge on the traveling direction side of the blade 33 is on one end side of the semiconductor wafer 31 and the cutting edge of the blade 33 is parallel to a predetermined dicing line. It is determined. Next, the position of the blade 33 in the Z direction is determined so that the lowermost end of the blade 33 reaches the dicing tape 34. At this time, the depth of the dicing tape 34 cut by the blade 33 can be variously changed according to the diameter and thickness of the semiconductor wafer 31.

  Next, by moving the blade 33 along a predetermined dicing line, one outer peripheral portion 31b of the semiconductor wafer 31 is completely cut from one end portion of the semiconductor wafer 31 (full cut dicing). Next, the blade 33 is raised to a position where only the thin portion where the groove 32 of the central portion 31a of the semiconductor wafer 31 is formed can be completely cut. That is, the position of the blade 33 in the Z direction is determined so that the lowest end of the blade tip of the blade 33 is separated from the dicing tape 34 and is exposed in the hollow portion 35 by the groove 32. At this time, the blade 33 may be raised substantially vertically, or may be raised stepwise or continuously while dicing the semiconductor wafer 31.

  Next, by moving the blade 33 along a predetermined dicing line, the central portion 31a of the semiconductor wafer 31 is completely cut (half-cut dicing). Next, when the cutting edge on the traveling direction side of the blade 33 reaches the other outer peripheral portion 31 b of the semiconductor wafer 31, the blade 33 is lowered to a position where the lowermost end of the cutting edge of the blade 33 reaches the dicing tape 34. At this time, the blade 33 may be lowered substantially vertically, or the semiconductor wafer 31 may be lowered stepwise or continuously while dicing.

  Next, by moving the blade 33 along a predetermined dicing line, the other outer peripheral portion 31 b of the semiconductor wafer 31 is completely cut to the other end portion of the semiconductor wafer 31 (full cut dicing). Thereby, the semiconductor wafer 31 is cut along one predetermined dicing line. After such control of the blade 33 is repeatedly performed one by one along the dicing line parallel to the X direction, and further one by one along the dicing line parallel to the Y direction, the control of the semiconductor wafer 31 is performed. The device formation area is cut into individual chips. Thereby, for example, a semiconductor chip such as a reverse blocking IGBT as shown in FIG. 3 is obtained.

  As described above, according to the embodiment, full cut dicing is performed at the outer peripheral portion where the groove of the semiconductor wafer is not formed, and half cut dicing is performed at the central portion where the groove of the semiconductor wafer is formed, The dicing tape is not scraped off by the blade during dicing of the central portion of the semiconductor wafer, which is a device formation region. For this reason, it is possible to reduce silicon grinding scraps and dicing tape scraps remaining in the vicinity of the grooves of the semiconductor wafer after dicing. Therefore, a highly reliable semiconductor device can be manufactured.

According to the embodiment, a V-shaped (or trapezoidal) groove is formed so as to reach the p ⁺ breakdown voltage region from the back surface of the semiconductor wafer, and a p ⁺ isolation layer is formed on the side wall of the groove. It is not necessary to perform a long-time diffusion process for forming the p ⁺ isolation layer or to form a trench with a high aspect ratio. Therefore, a highly reliable semiconductor device can be manufactured at low cost. In addition, since the dicing tape is pasted so that a hollow portion by the groove is formed on the surface of the semiconductor wafer where the groove is formed, the dicing tape for pasting the dicing tape even if the central portion is a partially thin semiconductor wafer. No special method is required.

According to the embodiment, the device pitch can be narrowed by forming the V-shaped groove from the back surface of the semiconductor wafer. Further, when the p ⁺ isolation layer is formed on the side wall of the trench, the lateral diffusion of the dopant can be reduced, so that the device pitch and the chip size can be reduced. Further, according to the embodiment, by forming a V-shaped groove from the back surface of the semiconductor wafer, the angle formed by the active region side of the p ⁺ isolation layer and the p ⁺ collector region at the back surface edge portion of the semiconductor chip is increased. Since it is not steep, it is possible to avoid a breakdown voltage drop due to electric field concentration. Therefore, a semiconductor device having a high breakdown voltage can be manufactured.

  As described above, the present invention is not limited to the above-described embodiment, and various modifications can be made. For example, the cross-sectional shape of the groove described in the embodiment is an example, and the present invention is not limited to that shape. In the embodiment, the first conductivity type is p-type. However, the present invention is similarly established even if the first conductivity type is n-type. The present invention is not limited to reverse blocking IGBTs, but can be applied to other reverse blocking devices, bidirectional devices, or semiconductor devices such as MOSFETs, bipolar transistors, or MOS thyristors with separation layer formation. It is also effective when applied.

  Note that the control of the blade (or stage) by the control unit described in the present embodiment can be realized by executing a program prepared in advance on a computer such as a personal computer or a workstation. This program is recorded on a computer-readable recording medium such as a hard disk, a flexible disk, a CD-ROM, an MO, and a DVD, and is executed by being read from the recording medium by the computer. The program may be a transmission medium that can be distributed via a network such as the Internet.

  As described above, the method for manufacturing a semiconductor device and the semiconductor manufacturing apparatus according to the present invention are useful for a power semiconductor device used for a power conversion device and the like, and are particularly suitable for a bidirectional device or a reverse blocking device. Yes.

31 Semiconductor wafer 31a Central portion of semiconductor wafer 31b Peripheral portion of semiconductor wafer 31c Inclined portion of groove side wall 32 Groove 33 Blade 34 Dicing tape 35 Hollow portion

Claims (10)

A method for manufacturing a semiconductor device by cutting a semiconductor wafer having grooves formed in a device formation region into chips,
An attaching step of attaching a tape to the surface of the semiconductor wafer on which the groove is formed;
A placing step of placing the semiconductor wafer on a stage via the tape;
In a region other than the device formation region, a first cutting step of cutting the semiconductor wafer with the blade in a state where the blade edge reaches the tape;
A second cutting step of cutting the semiconductor wafer along the groove by the blade in a state where the blade edge of the blade is separated from the tape in the device forming region;
A method for manufacturing a semiconductor device, comprising:   2. The method of manufacturing a semiconductor device according to claim 1, wherein after the first cutting step, the second cutting step is performed by raising the blade to a position of the blade at the time of the second cutting step.   3. The semiconductor according to claim 1, wherein after the first cutting step, the blade is raised along the inclination of the side wall of the groove until the position of the blade at the time of the second cutting step is reached. Device manufacturing method. In the first cutting step, a thick outer peripheral portion without a groove of the semiconductor wafer is completely cut,
4. The method of manufacturing a semiconductor device according to claim 1, wherein, in the second cutting step, the thin portion where the groove is formed in the central portion of the semiconductor wafer is completely cut. .   5. The semiconductor device according to claim 1, wherein, in the attaching step, the tape is attached so that a hollow portion is formed by the groove between the semiconductor wafer and the tape. Manufacturing method. Before the pasting step,
A groove forming step of forming the groove reaching the pn junction on the front surface side of the semiconductor wafer on the back surface of the semiconductor wafer of the first conductivity type;
Forming a second conductivity type collector region on the back surface of the semiconductor wafer, and forming a second conductivity type separation layer extending from the collector region to the pn junction on the sidewall of the groove;
An electrode forming step of forming a collector electrode covering the second conductive type separation layer;
The method for manufacturing a semiconductor device according to claim 1, further comprising: A semiconductor manufacturing apparatus for cutting a semiconductor wafer having grooves formed in a device formation region into chips,
A stage for holding the semiconductor wafer via a tape attached to the surface on which the groove is formed;
A blade for cutting the semiconductor wafer held on the stage along the groove;
When cutting an area other than the device formation area of the semiconductor wafer, the vertical position of the blade is controlled so that the blade edge of the blade reaches the tape, and the device formation area is cut along the groove. Control means for controlling the vertical position of the blade so that the blade edge of the blade is separated from the tape,
A semiconductor manufacturing apparatus comprising:   The control means moves the blade from a thick outer periphery without a groove of the semiconductor wafer to a thin portion where the groove is formed at the center of the semiconductor wafer, and the outer periphery of the semiconductor wafer is completely removed by the blade. The semiconductor manufacturing apparatus according to claim 7, wherein the blade is lifted after being cut.   9. The semiconductor manufacturing apparatus according to claim 8, wherein the control means raises the blade along the inclination of the side wall of the groove after the outer peripheral portion of the semiconductor wafer is completely cut.   The semiconductor manufacturing apparatus according to claim 7, wherein the tape is attached so that a hollow portion is formed by the groove between the semiconductor wafer and the tape.

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