JP2014143378A - Semiconductor device having esd protection element - Google Patents

Semiconductor device having esd protection element Download PDF

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JP2014143378A
JP2014143378A JP2013012388A JP2013012388A JP2014143378A JP 2014143378 A JP2014143378 A JP 2014143378A JP 2013012388 A JP2013012388 A JP 2013012388A JP 2013012388 A JP2013012388 A JP 2013012388A JP 2014143378 A JP2014143378 A JP 2014143378A
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diffusion layer
type diffusion
esd protection
protection element
semiconductor device
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Tetsuo Someya
哲勇 染谷
Hirotane Hirose
嘉胤 廣瀬
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Seiko Instruments Inc
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Seiko Instruments Inc
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Priority to JP2013012388A priority Critical patent/JP2014143378A/en
Priority to PCT/JP2013/085191 priority patent/WO2014115484A1/en
Priority to TW103101158A priority patent/TW201448158A/en
Publication of JP2014143378A publication Critical patent/JP2014143378A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/0814—Diodes only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/8611—Planar PN junction diodes

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having an ESD protection element having a reverse connection protection mechanism.SOLUTION: The semiconductor device has an ESD protection element provided with an N-type diffusion layer 14 functioning as cathodes of Zener diodes 21 and 22 and formed on the surface of a semiconductor substrate 11, a P-type diffusion layer 15a functioning as an anode of the Zener diode 21 and formed on the surface of the N-type diffusion layer 14 in a portion at which an input pad 31 and an input terminal of the ESD protection device 10 are connected, and a P-type diffusion layer 15b functioning as an anode of the Zener diode 22 and formed on the surface of the N-type diffusion layer 14 in a portion at which a ground pad and a ground terminal of the ESD protection device 10 are connected.

Description

本発明は、半導体装置に関する、特に、半導体装置に搭載されるＥＳＤ（静電気放電）保護素子に関する。   The present invention relates to a semiconductor device, and more particularly to an ESD (electrostatic discharge) protection element mounted on a semiconductor device.

従来のＥＳＤ保護素子について説明する。図６は、従来のＥＳＤ保護素子を示す断面図及び等価回路図である。   A conventional ESD protection element will be described. FIG. 6 is a sectional view and an equivalent circuit diagram showing a conventional ESD protection element.

入力パッドに印加されたサージ電圧は、入力パッドに連なるカソード電極１０６へ伝わり、ＥＳＤサージ電流が入力パッドから接地パッドにアノード電極１０７を介して流れる。この時、ＥＳＤ保護素子のツェナーダイオード１０８（ツェナー領域１０３、カソード１０４、及び、アノード１０５からなる）及びツェナーダイオード１０９（ツェナー領域１０３、カソード１０４、及び、基板１０１、ピックアップ領域１０２からなる）は、ブレイクダウン動作により、このＥＳＤサージ電流をダイオードの逆方向に流す。これにより、ＥＳＤサージ電流は内部回路に流れないので、内部回路がＥＳＤサージ電流から保護されることになる（例えば、特許文献１参照）。   The surge voltage applied to the input pad is transmitted to the cathode electrode 106 connected to the input pad, and an ESD surge current flows from the input pad to the ground pad via the anode electrode 107. At this time, the Zener diode 108 (comprising the Zener region 103, the cathode 104, and the anode 105) and the Zener diode 109 (comprising the Zener region 103, the cathode 104, the substrate 101, and the pickup region 102) of the ESD protection element are: This ESD surge current flows in the reverse direction of the diode by the breakdown operation. Thereby, since the ESD surge current does not flow to the internal circuit, the internal circuit is protected from the ESD surge current (see, for example, Patent Document 1).

特開平１０−１８９７６１号公報JP-A-10-189761

しかし、特許文献１によって開示された技術では、電源電圧が接地パッドに誤って印加される逆接続の状態においては、ダイオードが順方向となり接地パッドから入力パッドへと電流が流れてしまう。そのため、半導体装置は、誤動作したり破壊されたりしてしまう可能性が高い。そこで、製品によってはこうした事態を避けるために、半導体装置に搭載されるＥＳＤ保護素子には、逆接続保護機能が要求されるようになる。本発明は、上記課題に鑑みてなされ、逆接続保護機能を有するＥＳＤ保護素子を備えた半導体装置を提供するものである。   However, in the technique disclosed in Patent Document 1, in the reverse connection state where the power supply voltage is improperly applied to the ground pad, the diode becomes forward and current flows from the ground pad to the input pad. Therefore, there is a high possibility that the semiconductor device will malfunction or be destroyed. Therefore, depending on the product, in order to avoid such a situation, an ESD protection element mounted on a semiconductor device is required to have a reverse connection protection function. This invention is made in view of the said subject, and provides the semiconductor device provided with the ESD protection element which has a reverse connection protection function.

本発明は、上記課題を解決するため、ＥＳＤ保護素子を有する半導体装置であって、半導体基板と、第一〜第二ツェナーダイオードのカソードとして機能し、前記半導体基板の表面に形成されるＮ型拡散層と、前記第一ツェナーダイオードのアノードとして機能し、入力パッドとＥＳＤ保護素子の入力端子との接続部分において、前記Ｎ型拡散層の表面に形成される第一Ｐ型拡散層と、前記第二ツェナーダイオードのアノードとして機能し、接地パッドとＥＳＤ保護素子の接地端子との接続部分において、前記Ｎ型拡散層の表面に形成される第二Ｐ型拡散層と、前記第一Ｐ型拡散層の上にコンタクトが設けられる領域において、前記第一Ｐ型拡散層の表面に形成される第一高濃度Ｐ型拡散層と、前記第二Ｐ型拡散層の上にコンタクトが設けられる領域において、前記第二Ｐ型拡散層の表面に形成される第二高濃度Ｐ型拡散層と、を備えることを特徴とするＥＳＤ保護素子を有す半導体装置提供する。   In order to solve the above problems, the present invention provides a semiconductor device having an ESD protection element, which functions as a semiconductor substrate and cathodes of first to second Zener diodes, and is formed on the surface of the semiconductor substrate. A first P-type diffusion layer that functions as an anode of the diffusion layer and the first Zener diode, and is formed on the surface of the N-type diffusion layer at a connection portion between the input pad and the input terminal of the ESD protection element; A second P-type diffusion layer which functions as an anode of the second Zener diode and is formed on the surface of the N-type diffusion layer at a connection portion between the ground pad and the ground terminal of the ESD protection element; and the first P-type diffusion In a region where a contact is provided on the layer, a contact is provided on the first high-concentration P-type diffusion layer formed on the surface of the first P-type diffusion layer and on the second P-type diffusion layer. In that area, to provide a semiconductor device having a ESD protection device characterized by comprising: a second high-concentration P-type diffusion layer formed on the surface of the second P-type diffusion layer.

本発明では、電源電圧が接地パッドに誤って印加される逆接続の状態において、ＥＳＤ保護素子の第一ツェナーダイオードは、逆バイアスとなるので、オフしている。そのため、接地パッドに印加された電源電圧は、入力パッドに印加されないので、半導体装置は、誤動作したり破壊されたりしない。   In the present invention, in the reverse connection state where the power supply voltage is improperly applied to the ground pad, the first Zener diode of the ESD protection element is turned off because it is reverse biased. Therefore, the power supply voltage applied to the ground pad is not applied to the input pad, so that the semiconductor device does not malfunction or be destroyed.

ＥＳＤ保護素子を示す断面図及び等価回路図である。It is sectional drawing and an equivalent circuit schematic which show an ESD protection element. ＥＳＤ保護素子を示す平面図である。It is a top view which shows an ESD protection element. ＥＳＤ保護素子を示す平面図である。It is a top view which shows an ESD protection element. ＥＳＤ保護素子を示す平面図である。It is a top view which shows an ESD protection element. ＥＳＤ保護素子を示す平面図である。It is a top view which shows an ESD protection element. 従来のＥＳＤ保護素子を示す断面図及び回路図である。It is sectional drawing and a circuit diagram which show the conventional ESD protection element.

以下、本発明の実施形態について、図面を参照して説明する。図中のＰあるいはＮは半導体領域の導電型を表し、付属する＋、±、−は不純物濃度の相対的な大小関係を示し、Ｐ−、Ｐ±、Ｐ＋の順で濃度は高くなる。Ｎ型に関しても同様である。   Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the figure, P or N represents the conductivity type of the semiconductor region, and the attached +, ±, and − indicate the relative magnitude relationship of the impurity concentration, and the concentration increases in the order of P−, P ±, and P +. The same applies to the N type.

まず、半導体装置におけるＥＳＤ（静電気放電）保護素子の構成について説明する。図１は、ＥＳＤ保護素子を示す断面図及び等価回路図である。図２は、ＥＳＤ保護素子を示す平面図である。   First, the configuration of an ESD (electrostatic discharge) protection element in a semiconductor device will be described. FIG. 1 is a cross-sectional view and an equivalent circuit diagram showing an ESD protection element. FIG. 2 is a plan view showing the ESD protection element.

図１の（Ａ）に示すように、ＥＳＤ保護素子１０が形成されない領域において、Ｐ型半導体基板１１の表面に、Ｐ型ウェル１２が形成されている。ＥＳＤ保護素子１０が形成される領域において、Ｐ型半導体基板１１の表面に、Ｎ型ウェル１３が形成されている。Ｎ型ウェル１３の表面には、Ｎ型拡散層１４が形成されている。そして、入力パッド３１とＥＳＤ保護素子１０の入力端子との接続部分には、Ｎ型拡散層１４の表面に、第一のＰ型拡散層１５ａが形成されている。さらに、接地パッドとＥＳＤ保護素子１０の接地端子との接続部分において、Ｎ型拡散層１４の表面に、第二のＰ型拡散層１５ｂが形成されている。   As shown in FIG. 1A, a P-type well 12 is formed on the surface of a P-type semiconductor substrate 11 in a region where the ESD protection element 10 is not formed. In the region where the ESD protection element 10 is formed, an N-type well 13 is formed on the surface of the P-type semiconductor substrate 11. An N-type diffusion layer 14 is formed on the surface of the N-type well 13. A first P-type diffusion layer 15 a is formed on the surface of the N-type diffusion layer 14 at a connection portion between the input pad 31 and the input terminal of the ESD protection element 10. Further, a second P-type diffusion layer 15 b is formed on the surface of the N-type diffusion layer 14 at a connection portion between the ground pad and the ground terminal of the ESD protection element 10.

Ｐ型ウェル１２及びＰ型拡散層１５ａ〜１５ｂの上にコンタクトをとるための高濃度Ｐ型拡散層１７ａ〜１７ｃが設けられない領域において、Ｐ型半導体基板１１の表面には、ＬＯＣＯＳ法（Local Oxidation of Silicon：シリコンを部分的に酸化する方法）による比較的膜厚の厚いＬＯＣＯＳ酸化膜１６が形成されている。Ｐ型ウェル１２の上にコンタクトが設けられる領域において、Ｐ型ウェル１２の表面に、高濃度Ｐ型拡散層１７ｃが形成される。Ｐ型拡散層１５ａの上にコンタクトが設けられる領域において、Ｐ型拡散層１５ａの表面に、第一の高濃度Ｐ型拡散層１７ａが形成される。Ｐ型拡散層１５ｂの上にコンタクトが設けられる領域において、Ｐ型拡散層１５ｂの表面に、第二の高濃度Ｐ型拡散層１７ｂが形成される。   In a region where the high-concentration P-type diffusion layers 17a to 17c for making contacts are not provided on the P-type well 12 and the P-type diffusion layers 15a to 15b, the surface of the P-type semiconductor substrate 11 is subjected to a LOCOS method (Local A relatively thick LOCOS oxide film 16 is formed by Oxidation of Silicon: a method of partially oxidizing silicon. In the region where the contact is provided on the P-type well 12, a high concentration P-type diffusion layer 17 c is formed on the surface of the P-type well 12. In the region where the contact is provided on the P-type diffusion layer 15a, the first high-concentration P-type diffusion layer 17a is formed on the surface of the P-type diffusion layer 15a. In the region where the contact is provided on the P-type diffusion layer 15b, the second high-concentration P-type diffusion layer 17b is formed on the surface of the P-type diffusion layer 15b.

Ｎ型拡散層１４は、ツェナーダイオード２１〜２２のカソードとして機能する。Ｐ型拡散層１５ａは、ツェナーダイオード２１のアノードとして機能する。Ｐ型拡散層１５ｂは、ツェナーダイオード２２のアノードとして機能する。ツェナーダイオード２１及びツェナーダイオード２２がＥＳＤ保護素子１０を構成している。   The N-type diffusion layer 14 functions as the cathode of the Zener diodes 21 to 22. The P-type diffusion layer 15 a functions as the anode of the Zener diode 21. The P-type diffusion layer 15 b functions as the anode of the Zener diode 22. The Zener diode 21 and the Zener diode 22 constitute the ESD protection element 10.

Ｎ型拡散層１４の不純物濃度は、Ｎ型ウェル１３の不純物濃度よりも濃い。Ｐ型拡散層１５ａ〜１５ｂの不純物濃度は、Ｐ型ウェル１２の不純物濃度よりも濃く、高濃度Ｐ型拡散層１７ａ〜１７ｃの不純物濃度よりも薄い。Ｎ型拡散層１４及びＰ型拡散層１５ａ〜１５ｂの不純物濃度は、ツェナーダイオード２１〜２２の耐圧によって適宜設計される。また、高濃度Ｐ型拡散層１７ａ〜１７ｃの不純物濃度は、高濃度Ｐ型拡散層１７ａ〜１７ｃとその上のコンタクトとの接触抵抗の値が小さくなるよう適宜設計される。   The impurity concentration of the N-type diffusion layer 14 is higher than the impurity concentration of the N-type well 13. The impurity concentration of the P-type diffusion layers 15a to 15b is higher than the impurity concentration of the P-type well 12, and lower than the impurity concentration of the high-concentration P-type diffusion layers 17a to 17c. The impurity concentrations of the N-type diffusion layer 14 and the P-type diffusion layers 15a to 15b are appropriately designed according to the breakdown voltage of the Zener diodes 21 to 22. Further, the impurity concentration of the high-concentration P-type diffusion layers 17a to 17c is appropriately designed so that the value of contact resistance between the high-concentration P-type diffusion layers 17a to 17c and the contact thereon is small.

また、図２に示すように、Ｐ型拡散層１５ａ及び高濃度Ｐ型拡散層１７ａの平面形状は、本実施形態においては、対称性の高い正方形である。これらのＰ型拡散層１５ａ及び高濃度Ｐ型拡散層１７ａを中心として、図２の平面図で上下左右対称に、ＬＯＣＯＳ酸化膜１６及び高濃度Ｐ型拡散層１７ｂ〜１７ｃを形成する。   Further, as shown in FIG. 2, the planar shapes of the P-type diffusion layer 15a and the high-concentration P-type diffusion layer 17a are squares with high symmetry in the present embodiment. With the P-type diffusion layer 15a and the high-concentration P-type diffusion layer 17a as the center, the LOCOS oxide film 16 and the high-concentration P-type diffusion layers 17b to 17c are formed symmetrically vertically and horizontally in the plan view of FIG.

次に、ＥＳＤ保護素子１０の回路について説明する。
図１の（Ｂ）に示すように、入力パッド３１は、ツェナーダイオード２１のアノード及び半導体装置の内部回路に接続される。ツェナーダイオード２１のカソードは、ツェナーダイオード２２のカソードに接続される。ツェナーダイオード２２のアノードは、接地パッドに接続される。 Next, a circuit of the ESD protection element 10 will be described.
As shown in FIG. 1B, the input pad 31 is connected to the anode of the Zener diode 21 and the internal circuit of the semiconductor device. The cathode of the Zener diode 21 is connected to the cathode of the Zener diode 22. The anode of the Zener diode 22 is connected to the ground pad.

次に、ＥＳＤ保護素子１０の動作について説明する。
通常の動作においてはＥＳＤ保護素子１０のツェナーダイオード２２は、逆バイアスとなるので、オフしている。よって、ＥＳＤ保護素子１０は、入力パッド３１に印加される電圧に影響しない。 Next, the operation of the ESD protection element 10 will be described.
In normal operation, the Zener diode 22 of the ESD protection element 10 is turned off because it is reverse-biased. Therefore, the ESD protection element 10 does not affect the voltage applied to the input pad 31.

次に、電源電圧が接地パッドに誤って印加される逆接続の状態においては、ＥＳＤ保護素子１０は逆接続保護動作を行う。即ち、ＥＳＤ保護素子１０のツェナーダイオード２１は、逆バイアスとなるので、オフしたままである。よって、接地パッドに印加された電源電圧は、入力パッド３１に印加されない。   Next, in a reverse connection state where the power supply voltage is improperly applied to the ground pad, the ESD protection element 10 performs a reverse connection protection operation. That is, the Zener diode 21 of the ESD protection element 10 is reverse-biased and thus remains off. Therefore, the power supply voltage applied to the ground pad is not applied to the input pad 31.

続いて、ＥＳＤ保護素子１０のＥＳＤ保護動作について説明する。
入力パッド３１へ印加されたサージ電圧により、ＥＳＤサージ電流が入力パッド３１から接地パッドに流れる。この時、ＥＳＤ保護素子１０のツェナーダイオード２１は、このＥＳＤサージ電流を順方向に流している。また、ＥＳＤ保護素子１０のツェナーダイオード２２は、ブレイクダウン動作により、このＥＳＤサージ電流を逆方向に流している。これにより、ＥＳＤサージ電流が内部回路に流れないので、内部回路がＥＳＤサージ電流から保護される。 Next, the ESD protection operation of the ESD protection element 10 will be described.
Due to the surge voltage applied to the input pad 31, an ESD surge current flows from the input pad 31 to the ground pad. At this time, the Zener diode 21 of the ESD protection element 10 passes this ESD surge current in the forward direction. Further, the Zener diode 22 of the ESD protection element 10 allows this ESD surge current to flow in the reverse direction by the breakdown operation. Thereby, since the ESD surge current does not flow to the internal circuit, the internal circuit is protected from the ESD surge current.

なお、Ｐ型拡散層１５ａ及び高濃度Ｐ型拡散層１７ａの平面形状は、正方形であるが、電界集中防止のため、角をカットされた八角形としても良い。この時、これらのＰ型拡散層１５ａ及び高濃度Ｐ型拡散層１７ａを中心として、平面図で上下左右対称に、ＬＯＣＯＳ酸化膜１６及び高濃度Ｐ型拡散層１７ｂ〜１７ｃを形成する。   The planar shapes of the P-type diffusion layer 15a and the high-concentration P-type diffusion layer 17a are squares, but may be octagons with corners cut to prevent electric field concentration. At this time, the LOCOS oxide film 16 and the high-concentration P-type diffusion layers 17b to 17c are formed symmetrically in the plan view with the P-type diffusion layer 15a and the high-concentration P-type diffusion layer 17a as the center.

また、ＬＯＣＯＳ法が使用されているが、ＳＴＩ法（Shallow Trench Isolation：浅い溝を使った分離方法）を使用しても良い。
また、図３に示すように、Ｐ型拡散層１５ａ及び高濃度Ｐ型拡散層１７ａの平面形状は、長方形としても良い。 Further, although the LOCOS method is used, an STI method (Shallow Trench Isolation) may be used.
Further, as shown in FIG. 3, the planar shapes of the P-type diffusion layer 15a and the high-concentration P-type diffusion layer 17a may be rectangular.

また、図４に示すように、Ｐ型拡散層１５ａ及び高濃度Ｐ型拡散層１７ａの平面形状は、電界の集中を避けられるように円形としても良い。
また、図５に示すように、Ｐ型拡散層１５ａ及び高濃度Ｐ型拡散層１７ａの平面形状は、長方形類似の形状でも良く、この長方形の短手方向の部分は、丸くなっている。
また、Ｎ型ウェル１３は、無くても良い。この時、ＥＳＤ保護素子１０が形成される領域において、Ｐ型半導体基板１１の表面に、直接、Ｎ型拡散層１４が形成される。 As shown in FIG. 4, the planar shapes of the P-type diffusion layer 15a and the high-concentration P-type diffusion layer 17a may be circular so as to avoid the concentration of the electric field.
As shown in FIG. 5, the planar shape of the P-type diffusion layer 15a and the high-concentration P-type diffusion layer 17a may be a rectangle-like shape, and the rectangular portion in the short direction is rounded.
Further, the N-type well 13 may be omitted. At this time, the N-type diffusion layer 14 is formed directly on the surface of the P-type semiconductor substrate 11 in the region where the ESD protection element 10 is formed.

１０ ＥＳＤ保護素子
１１ Ｐ型半導体基板
１２ Ｐ型ウェル
１３ Ｎ型ウェル
１４ Ｎ型拡散層（ツェナーダイオード２１〜２２のカソード）
１５ａ Ｐ型拡散層（ツェナーダイオード２１のアノード）
１５ｂ Ｐ型拡散層（ツェナーダイオード２２のアノード）
１６ ＬＯＣＯＳ酸化膜
１７ａ〜１７ｃ 高濃度Ｐ型拡散層
１８ Ｎ型拡散層
２１ ツェナーダイオード
２２ ツェナーダイオード
３１ 入力パッド 10 ESD protection element 11 P-type semiconductor substrate 12 P-type well 13 N-type well 14 N-type diffusion layer (cathode of Zener diodes 21 to 22)
15a P-type diffusion layer (anode of Zener diode 21)
15b P-type diffusion layer (anode of Zener diode 22)
16 LOCOS oxide films 17a to 17c High-concentration P-type diffusion layer 18 N-type diffusion layer 21 Zener diode 22 Zener diode 31 Input pad

Claims (8)

Ｐ型の半導体基板と、
第一のツェナーダイオードおよび第二のツェナーダイオードのカソードとして機能し、前記半導体基板の表面から内部にかけて形成されたＮ型拡散層と、
前記第一のツェナーダイオードのアノードとして機能し、入力パッドとＥＳＤ保護素子の入力端子との接続部分において、前記Ｎ型拡散層の表面に形成された第一のＰ型拡散層と、
前記第二のツェナーダイオードのアノードとして機能し、接地パッドとＥＳＤ保護素子の接地端子との接続部分において、前記Ｎ型拡散層の表面に形成された第二のＰ型拡散層と、
前記第一のＰ型拡散層の上にコンタクトが設けられる領域において、前記第一のＰ型拡散層の表面に形成された第一の高濃度Ｐ型拡散層と、
前記第二のＰ型拡散層の上にコンタクトが設けられる領域において、前記第二のＰ型拡散層の表面に形成された第二の高濃度Ｐ型拡散層と、
を備えたことを特徴とするＥＳＤ保護素子を有する半導体装置。 A P-type semiconductor substrate;
An N-type diffusion layer functioning as a cathode of the first Zener diode and the second Zener diode and formed from the surface of the semiconductor substrate to the inside;
A first P-type diffusion layer that functions as an anode of the first Zener diode and is formed on a surface of the N-type diffusion layer at a connection portion between the input pad and the input terminal of the ESD protection element;
A second P-type diffusion layer that functions as an anode of the second Zener diode and is formed on the surface of the N-type diffusion layer at a connection portion between the ground pad and the ground terminal of the ESD protection element;
In a region where a contact is provided on the first P-type diffusion layer, a first high-concentration P-type diffusion layer formed on the surface of the first P-type diffusion layer;
In a region where a contact is provided on the second P-type diffusion layer, a second high-concentration P-type diffusion layer formed on the surface of the second P-type diffusion layer;
A semiconductor device having an ESD protection element. 前記Ｎ型拡散層の下に、さらに、Ｎ型のウェルを有することを特徴とする請求項１記載のＥＳＤ保護素子を有する半導体装置。   The semiconductor device having an ESD protection element according to claim 1, further comprising an N-type well under the N-type diffusion layer. 前記ＥＳＤ保護素子は周囲には、さらに、Ｐ型ウェルを有し、前記Ｐ型ウェルは第三の高濃度Ｐ型拡散層を介して前記接地パッドに接続されていることを特徴とする請求項１または２に記載のＥＳＤ保護素子を有する半導体装置。   The ESD protection element further includes a P-type well in the periphery, and the P-type well is connected to the ground pad via a third high-concentration P-type diffusion layer. A semiconductor device having the ESD protection element according to 1 or 2. 前記第一のＰ型拡散層の平面形状は、正方形である、
ことを特徴とする請求項１乃至３のいずれか１項に記載のＥＳＤ保護素子を有する半導体装置。 The planar shape of the first P-type diffusion layer is a square.
A semiconductor device having the ESD protection element according to claim 1. 前記第一のＰ型拡散層の平面形状は、長方形である、
ことを特徴とする請求項１乃至３のいずれか１項に記載のＥＳＤ保護素子を有する半導体装置。 The planar shape of the first P-type diffusion layer is a rectangle.
A semiconductor device having the ESD protection element according to claim 1. 前記第一のＰ型拡散層の平面形状は、八角形である、
ことを特徴とする請求項１乃至３のいずれか１項に記載のＥＳＤ保護素子を有する半導体装置。 The planar shape of the first P-type diffusion layer is an octagon.
A semiconductor device having the ESD protection element according to claim 1. 前記第一のＰ型拡散層の平面形状は、円形である、
ことを特徴とする請求項１乃至３のいずれか１項に記載のＥＳＤ保護素子を有する半導体装置。 The planar shape of the first P-type diffusion layer is circular.
A semiconductor device having the ESD protection element according to claim 1. 前記第一のＰ型拡散層の平面形状は、長方形類似の形状であり、長方形の短手方向の部分は、丸くなっている、
ことを特徴とする請求項１乃至３のいずれか１項に記載のＥＳＤ保護素子を有する半導体装置。 The planar shape of the first P-type diffusion layer is a shape similar to a rectangle, and the short-side portion of the rectangle is rounded.
A semiconductor device having the ESD protection element according to claim 1.
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