JP2014140005A - Thin film transistor and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a thin film transistor and a manufacturing method of the same, which can inhibit increase in resistance value in a region of an oxide semiconductor even by a heat treatment in a manufacturing process of a thin film transistor, and which can inhibit decrease in drain current and characteristic variation of the thin film transistor.SOLUTION: A thin film transistor comprises a plurality of layers including at least a gate electrode film 2 and an oxide semiconductor layer (IGZO film 4) which are stacked on a substrate 1, in which a part of the oxide semiconductor layer (4) is formed to be an amorphous channel region, and at least a part of a region of the oxide semiconductor layer (4) other than the channel region is formed to be a low-resistant region (4'), and at least a part of the low-resistant region (4') is crystallized.

Description

  The present invention relates to a method of manufacturing a thin film transistor, and more particularly to a bottom gate or top gate thin film transistor having a channel formed of an amorphous oxide semiconductor and a method of manufacturing the same.

  In recent years, an oxide semiconductor containing indium, gallium, and zinc (InGaZnO (IGZO: registered trademark)) is used as a thin film transistor (hereinafter sometimes referred to as TFT) intended to be used for a display driving element. ))) And TFTs using oxide semiconductors such as zinc oxide (ZnO) in the channel and methods for manufacturing the TFTs are actively researched and applied to various actual devices.

  A TFT using such an oxide semiconductor for a channel has an advantage of higher mobility than a TFT using amorphous silicon (a-Si), which is well-known as a liquid crystal display driving element, for a channel.

  In addition, since oxide semiconductors can be deposited at room temperature using sputtering or the like, TFTs using oxide semiconductors for channels can be used not only for glass substrates but also for resins such as polyethylene naphthalate (PEN) and polyethersulfone (PES). It can also be formed on a substrate.

  On the other hand, self-aligned TFTs that are constructed so that the gate electrode and source / drain electrode regions do not overlap in the vertical direction of the TFTs, improve characteristics such as reducing parasitic capacitance, and improve manufacturing efficiency are attracting attention. Therefore, establishment of a manufacturing technique of a self-aligned TFT using such an oxide semiconductor for a channel is urgently required, and a technique such as Patent Document 1 described below by the applicant of the present application is disclosed in the Patent Office.

  That is, in the method for manufacturing a thin film transistor described in Patent Document 1 below, a gate electrode film, a gate insulating film, and an oxide semiconductor layer are stacked in this order (bottom gate) on a substrate, and predetermined light is emitted from the substrate side. Irradiation reduces the resistance of the oxide semiconductor layer region (source / drain region) that does not overlap with the gate electrode film, whereby a self-aligned TFT can be manufactured.

Japanese Patent Application No. 2012-221703

  However, the above light irradiation process may be performed at the end of all TFT manufacturing processes; otherwise, the oxide semiconductor whose resistance value has once decreased by heat treatment in the manufacturing process after the light irradiation process. The resistance value in the region increases again. As a result, there is a problem that the drain current of the TFT element is reduced and the characteristics are varied.

  The present invention has been made in view of the above circumstances, and in a thin film transistor element using an oxide semiconductor for a channel, an increase in the resistance value of a predetermined region of the oxide semiconductor is suppressed even by heat treatment in the thin film transistor manufacturing process. An object of the present invention is to provide a thin film transistor and a method for manufacturing the same that can suppress a decrease in drain current and variations in characteristics of the thin film transistor element.

The thin film transistor according to the present invention is
In a thin film transistor in which a plurality of layers including at least a gate electrode film and an oxide semiconductor layer are stacked on a substrate,
A part of the oxide semiconductor layer is an amorphous channel region, and at least a part of the oxide semiconductor layer other than the channel region is a low-resistance region. It is characterized in that at least a part thereof is crystallized.

In this case, the regions other than the channel region are preferably a source region and a drain region located on both sides of the channel region.
Further, in a region other than the channel region, one side in the thickness direction may be crystallized and the other side may be amorphous.
Further, the thickness of the region other than the channel region can be made thinner than the thickness of the channel region.
Moreover, it is preferable that the low-resistance region is a region whose resistance has been reduced by irradiation with predetermined light.

Further, it is preferable that the predetermined light is any one of excimer laser light, flash lamp light, and CW laser light.
The oxide semiconductor constituting the oxide semiconductor layer contains at least one element of indium, gallium, zinc, tin, aluminum, silicon, germanium, boron, manganese, titanium, and molybdenum, or indium gallium oxide. It is preferable to contain zinc as a material.

The first thin film transistor manufacturing method of the present invention includes
A gate electrode film, a gate insulating film, and an oxide semiconductor layer are stacked in this order on the substrate,
Thereafter, a region of the oxide semiconductor layer that does not overlap the gate electrode film on the line of sight when irradiated with predetermined light from the substrate side toward the oxide semiconductor layer when viewed from the substrate side. A thin film transistor having a self-aligned bottom gate structure is manufactured by crystallizing at least a part of the film to reduce resistance.
The second thin film transistor manufacturing method of the present invention includes
A plurality of layers including an oxide semiconductor layer, a gate insulating film, and a gate electrode film are stacked in this order on the substrate,
Thereafter, the oxide that does not overlap the gate electrode film on the line of sight when viewed from the gate electrode film side by irradiating predetermined light from the gate electrode film side toward the oxide semiconductor layer A thin film transistor having a self-aligned top gate structure is manufactured by crystallizing at least a part of the region of the semiconductor layer to reduce resistance.

In any one of the thin film transistor manufacturing methods, the predetermined light is preferably one of excimer laser light, flash lamp light, and CW laser light.
Here, the “channel region” refers to a region of the oxide semiconductor layer that faces the gate electrode layer.

  In the above-described method for manufacturing a thin film transistor, the “on line of sight” is generally a parallel line, but does not exclude a case where the line is on a slightly convergent line.

  In addition, the “flash lamp” means that electrodes are sealed at both ends of a quartz glass tube or a high silica glass tube having a straight tube shape, a spiral shape, a U shape, a ring shape, etc. It is a light source in which a rare gas such as xenon or hydrogen gas of ˜10 kPa is enclosed and hydrogen light is emitted only for a short time.

Further, when the predetermined light is the excimer laser light, the energy density per pulse of the excimer laser light is preferably 10 to 1000 mJ / cm ² .
In addition, when the predetermined light is the flash lamp light, it is preferable that an energy density per pulse of the flash lamp light is 0.1 to 500 J / cm ² .

  According to the thin film transistor of the present invention, a plurality of layers including at least a gate electrode film and an oxide semiconductor layer are stacked on a substrate, and a part of the oxide semiconductor layer is an amorphous channel region, A region having a low resistance is included in at least a part of the oxide semiconductor layer other than the channel region, and at least a part of the low resistance region is crystallized.

  In general, the resistance value of the low-resistance region of the oxide semiconductor layer is increased by heat treatment in the process after light irradiation. According to the thin film transistor of the present invention, at least a part of the low-resistance region is formed. By being crystallized, even if there is a heat treatment after this, it is possible to suppress an increase in resistance accompanying a temperature increase at that time. For this reason, the stable suppression effect about the fall of drain current or characteristic variation can be acquired.

  Further, according to the method for manufacturing a thin film transistor according to the present invention, any of the above manufacturing methods includes stacking a plurality of layers including a gate electrode film, a gate insulating film, and an oxide semiconductor layer on the substrate, and the oxide semiconductor. The layer is irradiated with predetermined light, and when viewed from above or below, at least part of the region of the oxide semiconductor layer that does not overlap with the gate electrode film on the line of sight is crystallized to reduce resistance. I have to. As a result, a direct action effect due to light energy and a temperature increase effect accompanying light irradiation are imparted to the light irradiation region in the oxide semiconductor layer, so that the oxygen in the oxide semiconductor layer is reduced. Bonds are strongly broken, oxygen atoms are lost, and free electrons increase. By utilizing at least a part of the light irradiation region in the oxide semiconductor layer as a part of the source / drain electrode, for example, the overlap between the gate electrode film and the source / drain electrode can be minimized, and the parasitic capacitance Can be easily reduced. Further, since at least a part of the low resistance region is included and at least a part of the low resistance region is crystallized, even if there is a heat treatment during the subsequent process step, It is possible to suppress an increase in resistance accompanying the temperature increase. For this reason, the stable suppression effect about the fall of drain current or characteristic variation can be acquired.

It is process drawing which shows the manufacturing method of the thin-film transistor of the self-alignment type bottom gate structure based on the 1st Embodiment of this invention. FIG. 10 is a process diagram illustrating a method of manufacturing a thin film transistor having a self-aligned top gate structure according to a second embodiment of the present invention. It is process drawing which shows the manufacturing method of the thin-film transistor of the self-alignment type top gate structure based on the 3rd Embodiment of this invention. It is a graph which shows the XRD spectrum for analyzing crystallinity using the (theta) -2 (theta) method about the sample of the thin-film transistor of the Example which concerns on the 3rd Embodiment of this invention. It is a graph which shows the heating temperature dependence of the sheet resistance in an IGZO film about the sample of the thin-film transistor of the Example which concerns on the 3rd Embodiment of this invention. A thin film transistor sample of an example according to the third embodiment of the present invention was manufactured, using a schematic diagram (a) showing an observation region when measured, and a TEM (Transmission Electron Microscope), It is a figure which shows the electron diffraction photograph (b) which concerns on the crystallinity of an observation area | region.

<First Embodiment>
Hereinafter, a method of manufacturing a thin film transistor according to the first embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows the steps of the manufacturing method according to the first embodiment in order.
First, an aluminum (Al) layer is formed on a glass substrate 1 at room temperature using a sputtering method, and then the aluminum (Al) layer is patterned using a photolithography method and an etching method to form a gate electrode having a short width. A film 2 is formed.

  Next, a gate insulating film 3 made of silicon oxide is formed to a thickness of 200 nm on the gate electrode film 2 (partly on the substrate 1) by plasma CVD.

  Next, an InGaZnO film (hereinafter simply referred to as an IGZO film: oxide semiconductor layer) 4 is formed on the gate insulating film 3 to a thickness of 50 nm. The IGZO film 4 is an oxide semiconductor layer containing indium, gallium, and zinc, and is formed in a room temperature environment using a sputtering method. The IGZO film 4 is amorphous (amorphous). In this case, a sintered body of IGZO is used as the sputtering target. The composition ratio of indium, gallium, zinc, and oxygen in the IGZO target is, for example, 1: 1: 1: 4. Further, the IGZO film 4 is subjected to an appropriate patterning process using a photolithography method and an etching method.

Next, a protective film 5 made of silicon oxide is formed using a plasma CVD method at a substrate temperature of 300 ° C. (FIG. 1A).
The method for forming the protective film 5 is not limited to the plasma CVD method. The film may be formed by using other chemical vapor deposition such as thermal CVD, physical vapor deposition such as sputtering, coating method or the like. Further, the material for forming the protective film 5 is not limited to silicon oxide, and other insulating films such as silicon nitride and aluminum oxide may be used. Furthermore, the protective film 5 is not limited to an inorganic material, and may be an organic material.

Next, in order to improve the drain current and the reliability of the TFT characteristics, a thermal annealing process is performed at 300 ° C. or higher for 1 hour in the air.
Note that the atmosphere of the thermal annealing treatment is not limited to air, and the thermal annealing treatment may be performed in oxygen, nitrogen, ozone, or other atmosphere. Moreover, you may perform a heat-annealing process in the humid atmosphere of the state which raised the humidity significantly.

  Next, as shown in FIG. 1B, excimer laser light (for example, XeCl excimer laser) is irradiated from the substrate 1 side toward the IGZO film 4 to the element structure stacked as described above. Since a part of the excimer laser light is reflected and absorbed by the gate electrode film 2, the excimer laser light is not irradiated to the IGZO film 4 (corresponding to the channel region) located above the gate electrode film 2.

  On the other hand, the region of the IGZO film 4 where the gate electrode film 2 does not exist is irradiated with excimer laser light. The region irradiated with excimer laser is the region where excimer laser is not irradiated because oxygen is lost and free electrons increase due to the direct action effect by light energy and the temperature increase effect accompanying light irradiation. As a result, a region having a low resistance (low resistance IGZO film 4 ′) is obtained (FIG. 1C). Thus, by using at least a part of the low-resistance IGZO film 4 'as the source / drain regions 6a and 6b, it is possible to suppress a decrease in drain current. The low-resistance IGZO region can be used not only as the source / drain regions 6a and 6b but also as a pixel electrode of a liquid crystal element or EL element formed in the same layer as the source or drain regions 6a and 6b.

  Here, the energy density (irradiation intensity) per pulse needs to be an energy density at which oxygen bonds in the oxide semiconductor layer are released, oxygen atoms are lost, and free electrons increase by the irradiation. is there. As a result, the resistance value in this region decreases. The energy density (irradiation intensity) per pulse needs to be an energy density at which at least a part of the oxide semiconductor layer is crystallized by the irradiation. This is because the resistance rise caused by the substrate heating in the subsequent TFT manufacturing process is smaller in the crystal than in the amorphous. As a result, a decrease in drain current and variation in characteristics of the TFT element can be suppressed. On the other hand, the energy density (irradiation intensity) per pulse needs to be a density (intensity) that does not cause shrinkage or warping of the substrate or peeling of the oxide semiconductor layer from the substrate 1 due to the irradiation. is there.

From such a viewpoint, the energy density (irradiation intensity) per pulse of the excimer laser is preferably 10 to 1000 mJ / cm ² , for example. However, the optimum irradiation intensity for crystallization of the oxide semiconductor varies depending on the type and thickness of the oxide semiconductor, the wavelength and pulse width of the excimer laser, and the type and thickness of the substrate, and thus it is preferable to appropriately adjust the irradiation intensity. . In addition, the irradiation intensity at which the oxide semiconductor crystallizes varies depending on the type and thickness of the oxide semiconductor, the wavelength and irradiation intensity of the excimer laser, and the type and thickness of the substrate, so that it is preferable to design appropriately.

  The width per pulse (light emission time) is also preferably set to, for example, 5 to 1000 nsec for the same reason as described for the energy density (irradiation intensity).

  Furthermore, it is preferable that the wavelength of the excimer laser includes a wavelength within a range of 400 nm or less, for the same reason as described for the energy density (irradiation intensity).

  The excimer laser preferably includes a wavelength at which the absorption rate in the IGZO film is increased.

  In addition, the irradiated light can be XeCl excimer as long as it is capable of losing oxygen and increasing free electrons due to the direct action effect of light energy and the temperature increase effect accompanying light irradiation in the irradiated region. It is not limited to a laser, and an excimer laser such as a KrF laser, an ArF laser, a XeF laser, a KrCl laser, or an ArCl laser, a gas laser such as an Ar laser, or a solid laser such as a YAG laser may be used. Further, light other than laser light such as flash lamp light may be used. It is also possible to use continuous light such as a CW laser.

When using flash lamp light, the energy density (irradiation intensity) per pulse of the flash lamp light is preferably 0.1 to 500 J / cm ² , for example.

  Also, the width per pulse (light emission time) is preferably set to, for example, 0.01 to 100 msec for the same reason as described for the energy density (irradiation intensity).

  Further, it is preferable that the wavelength of the flash lamp light includes a wavelength in the range of 200 to 1500 nm, for the same reason as described for the energy density (irradiation intensity).

  The irradiation light needs to be such that it acts on the oxide semiconductor layer but does not damage the substrate 1 or the like as much as possible. From this point of view, it is preferable to select pulsed light such as excimer laser light or flash light that can intermittently apply energy.

  Next, after forming a contact hole in the protective film 5 using a photolithography method and an etching method, the source electrode film 7a and the drain electrode film 7b are formed in a room temperature environment by sputtering Mo. Thereafter, the source electrode film 7a and the drain electrode film 7b are patterned by using a photolithography method and an etching method (FIG. 1D). Note that the maximum process temperature in the photolithography method and the etching method is about 100 ° C. In this patterning, the gate electrode film 2 and the source / drain electrode films 7a and 7b are formed so as to have no overlapping region in the vertical direction. Thereby, there is no room for the gate electrode film 2 and the source region 6a and the drain region 6b of the IGZO film 4 to face each other, so that the generation of parasitic capacitance can be greatly reduced.

  In addition, since the present embodiment is a TFT element having a “bottom gate structure”, the gate electrode film 2 is formed before the oxide semiconductor layer (IGZO film 4). There is no damage to the oxide semiconductor layer during film formation, which is advantageous in terms of characteristic deterioration and characteristic variation as compared with the TFT element having the “top gate structure” according to the second embodiment described below. In addition, it is convenient in manufacturing because it can be used in common with the a-Si line.

  As described above, the self-aligned bottom gate TFT according to this embodiment can be manufactured.

<Second Embodiment>
Hereinafter, a method of manufacturing a thin film transistor according to the second embodiment of the present invention will be described with reference to the drawings. The main difference between the second embodiment and the first embodiment described above is that the order of the layer configuration and the direction of irradiating predetermined light are different. In the second embodiment, the layer corresponding to the layer of the first embodiment is given a reference numeral obtained by adding 10 to the reference numeral of the layer of the first embodiment.

FIG. 2 shows each step of the manufacturing method according to the second embodiment in order.
First, the IGZO film 14 is formed to a thickness of 50 nm on the glass substrate 11. The IGZO film 14 is an oxide semiconductor layer containing indium, gallium, and zinc, and is formed in a room temperature environment by a sputtering method. This IGZO film 14 is amorphous at the time of film formation. In this case, a sintered body of IGZO is used as the sputtering target. The composition ratio of indium, gallium, zinc, and oxygen in the IGZO target is, for example, 1: 1: 1: 4. Further, the IGZO film 14 is subjected to an appropriate patterning process using a photolithography method and an etching method. Next, a gate insulating film 13 made of silicon oxide is formed to a thickness of 200 nm on the IGZO film 14 by plasma CVD. Next, an aluminum (Al) layer is formed in a room temperature environment using a sputtering method, and then the aluminum (Al) layer is patterned using a photolithography method and an etching method to form a gate electrode film 12 having a short width. . Next, a protective film 15 made of silicon oxide is formed at a substrate temperature of 300 ° C. by plasma CVD (FIG. 2A).

The method for forming the protective film 15 is not limited to the plasma CVD method. The film may be formed by using other chemical vapor deposition such as thermal CVD, physical vapor deposition such as sputtering, coating method or the like. Further, the insulating film is not limited to silicon oxide, and may be another insulating film such as silicon nitride or aluminum oxide. Furthermore, the protective film 15 is not limited to an inorganic material, and may be an organic material.
Next, for the purpose of improving the drain current and improving the reliability of the TFT characteristics, a thermal annealing process at 300 ° C. or higher is performed in air for 1 hour.

  Note that the atmosphere in which the thermal annealing treatment is performed is not limited to air, and the thermal annealing treatment may be performed in oxygen, nitrogen, ozone, or other atmosphere. Moreover, you may perform a heat-annealing process in the humid atmosphere of the state which raised the humidity significantly.

  Next, as shown in FIG. 2B, an excimer laser beam (for example, XeCl excimer laser) or a flash lamp is applied to the element structure laminated as described above from the protective film 15 side toward the IGZO film 14. Irradiate light. Since a part of the excimer laser light or the like is reflected and absorbed by the gate electrode film 12, the excimer laser light or the like is not irradiated to the IGZO film 14 (corresponding to the channel region) located below the gate electrode film 12. On the other hand, an excimer laser beam or the like is irradiated on the IGZO film 14 on which the gate electrode film 12 does not exist. The region irradiated with excimer laser light etc. is irradiated with excimer laser because oxygen is lost and free electrons increase due to the direct action effect due to light energy and the temperature increase effect accompanying light irradiation. A region having a low resistance (low-resistance IGZO film 14 ') compared to a region that is not formed (FIG. 2C). By using at least a part of the low-resistance IGZO film 14 'as the source / drain regions 16a and 16b, a decrease in drain current can be suppressed. The low resistance IGZO region can be used not only as the source / drain regions 16a and 16b but also as a pixel electrode in the same layer as the source or drain regions 16a and 16b.

  The irradiation light needs to be such that it acts on the oxide semiconductor layer but does not damage the substrate 11 and the like as much as possible. From this point of view, it is preferable to select pulsed light such as excimer laser or flash light that can intermittently apply energy.

  Next, after forming a contact hole in the protective film 15 using a photolithography method and an etching method, the source electrode film 17a and the drain electrode film 17b are formed in a room temperature environment by sputtering Mo. Thereafter, the source electrode film 17a and the drain electrode film 17b are patterned by using a photolithography method and an etching method (FIG. 1D). Thereafter, the maximum process temperature in the photolithography method and the etching method is about 100 ° C. In this patterning, the gate electrode film 12 and the source / drain electrode films 17a and 17b are formed so that there is no overlapping region in the vertical direction. Thereby, there is no room for the gate electrode film 12 and the source region 16a and the drain region 16b to face each other, so that the generation of parasitic capacitance can be greatly reduced.

The characteristics of the excimer laser light and flash lamp light in the second embodiment (energy density per pulse (irradiation intensity), width per pulse (light emission time), wavelength of light used), the predetermined light Since the change mode, the material for forming each layer, the method for forming the oxide semiconductor layer, and the like are the same as those in the first embodiment, detailed description thereof will be omitted.
As described above, the self-aligned top gate TFT according to this embodiment can be manufactured.

<Third Embodiment>
Hereinafter, a method of manufacturing a thin film transistor according to the third embodiment of the present invention will be described with reference to the drawings. The main difference between the third embodiment and the first embodiment described above is whether or not a protective layer is provided. In the third embodiment, the layer corresponding to the layer of the first embodiment is given a reference numeral obtained by adding 20 to the reference numeral of the layer of the first embodiment.
FIG. 3 shows the steps of manufacturing the thin film transistor according to the third embodiment in order.
First, an aluminum (Al) layer is formed on a glass substrate 21 in a room temperature environment using a sputtering method, and then the aluminum (Al) layer is patterned using a photolithography method and an etching method to form a gate electrode having a short width. A film 22 is formed.

Next, silicon oxide is formed to a thickness of about 200 nm on the gate electrode film 22 (partly on the substrate 21) by sputtering.
Next, an IGZO film 24 is formed on the silicon oxide to a thickness of 48 nm, for example. The IGZO film 24 is an oxide semiconductor layer containing indium, gallium, and zinc and is formed in a room temperature environment by a sputtering method. The IGZO film 24 is amorphous (amorphous). In this case, a sintered body of IGZO is used as the sputtering target. The composition ratio of indium, gallium, zinc, and oxygen in the IGZO target is, for example, 1: 1: 1: 4. Further, the IGZO film 24 is subjected to an appropriate patterning process using a photolithography method and an etching method (FIG. 3A).

Next, in order to improve the drain current and the reliability of the TFT characteristics, a thermal annealing process is performed at 300 ° C. or higher for 1 hour in the air.
Note that the atmosphere of the thermal annealing treatment is not limited to air, and the thermal annealing treatment may be performed in oxygen, nitrogen, ozone, or other atmosphere. Moreover, you may perform a heat-annealing process in the humid atmosphere of the state which raised the humidity significantly.

Next, as shown in FIG. 3B, excimer laser light (for example, XeCl excimer laser light) is irradiated from the substrate 21 side toward the IGZO film to the element structure stacked as described above.
The characteristics of the excimer laser light and flash lamp light in the third embodiment (energy density per pulse (irradiation intensity), width per pulse (light emission time), wavelength of light used), the predetermined light Since the change mode, the material for forming each layer, the method for forming the oxide semiconductor layer, and the like are the same as those in the first embodiment, detailed description thereof will be omitted.
In the thin film transistor according to the third embodiment, the region close to the silicon oxide (SIO ₂ ) as the gate insulating film 22 is usually amorphous, and the surface of the IGZO film 24 in contact with the air layer on the opposite side is many. It is considered as a crystal. This is because, when the IGZO film 24 is irradiated with a laser, the thermal conductivity of silicon oxide (SIO ₂ ) on the opposite side is higher than the thermal conductivity of air on the surface of the IGZO film 24, so the IGZO film This is because the heat generated at 24 conducts faster on the silicon oxide (SIO ₂ ) side than on the surface side. For this reason, the temperature on the surface side in contact with the air layer in the IGZO film 24 is higher than that on the silicon oxide (SIO ₂ ) side, and this surface side is more easily crystallized.
However, conversely, it is possible to crystallize in a region close to silicon oxide (SIO ₂ ) that is a gate insulating film and to be amorphous on the surface of the IGZO film 24 in contact with the air layer on the opposite side.
Furthermore, the thickness of the crystallized region increases as the excimer laser irradiation intensity increases.
Further, in general, the thickness of the IGZO film region 24 ′ having at least a part of the low resistance other than the channel region 24 is thinner than the channel region 24 a.
As described above, the self-aligned top gate TFT according to this embodiment can be manufactured.

  In each of the above-described embodiments, the IGZO film is used as the oxide semiconductor layer. However, the present invention is not limited to this. Instead, indium, gallium, zinc, tin, aluminum, silicon, germanium are used. Alternatively, an oxide semiconductor layer containing at least one element of boron, manganese, titanium, and molybdenum may be used. Further, although the composition ratio of IGZO constituting the IGZO film 4 is In: Ga: Zn: O = 1: 1: 1: 4, this composition ratio is not limited to this.

  In each of the above-described embodiments, the IGZO film as the oxide semiconductor layer is formed using a sputtering method. However, other components such as a pulse laser deposition method, an electron beam deposition method, and a coating film formation method are used. A membrane method may be used.

  In each of the above embodiments, the gate insulating film and the protective film are formed of silicon oxide. However, the present invention is not limited to this, and the light used for reducing the resistance of the oxide semiconductor layer described above ( For example, it is more preferable if the material has a higher transmittance with respect to an excimer laser.

The thin film transistor of the present invention can of course have a layer structure in which other layers (films) are added in addition to the layer structure described above.
Further, if not all of the region other than the channel region in the oxide semiconductor layer is a low-resistance region, further, if not all of the low-resistance region is crystallized. If so, the effects of the present invention can be achieved.

<Measurement results of samples according to examples>
Next, the measurement result of the sample produced by the Example which concerns on the said 3rd Embodiment is demonstrated using FIG. Although the sample according to this example does not include the protective film provided in the first embodiment or the second embodiment, the measurement results similar to the following are obtained even when the protective film is provided. Can be obtained.
First, four samples obtained by forming an IGZO film having a thickness of 50 nm on a glass substrate 21 were subjected to a thermal annealing treatment at 300 ° C. for 1 hour. Next, these four samples were irradiated with XeCl excimer laser light from the substrate side toward the IGZO film. The irradiation pulse width is 50 ns, and the irradiation intensity is 100 mJ / cm ² for the first sample, 150 mJ / cm ² for the ^second sample, 200 mJ / cm ^{2 for} the third sample, and 300 mJ for the fourth sample. / cm ² and then was irradiated for 10 times for the same area.
Next, the crystallinity of each of the samples subjected to the above treatment was analyzed using the XRD (X-ray diffraction) θ-2θ method.

FIG. 4 shows the XRD spectrum. In the first and second samples having irradiation intensity of 100 and 150 mJ / cm ² , no crystal-derived peak is observed, so that it is clear that the sample remains amorphous. On the other hand, the third sample with an irradiation intensity of 200 mJ / cm ² has a sharp peak near 2θ = 30.6 ° and 36.2 ° and X-ray diffraction occurs, so that it is clear that the crystal is changed to a crystal. Furthermore, in the fourth sample with an irradiation intensity of 300 mJ / cm ² , since there are steep peaks near 2θ = 20.4 °, 30.6 °, and 36.2 ° and X-ray diffraction occurs, this also changes to crystals. it is obvious. From this, it is clear that the IGZO film crystallizes at an irradiation intensity of 200 mJ / cm ² or more.

Next, when the sheet resistance was measured by the four-probe measurement method for the first to fourth samples prepared under the same conditions as the above sample, the results were as follows (FIG. 5). In other words, the sheet resistance value was 2.4 × 10 ⁴ Ω before heating in the first sample, which was amorphous with an irradiation intensity of 100 mJ / cm ² , but the sheet resistance was about 100 ° C. Resistance increased to 2.7 × 10 ⁶ Ω at 150 ° C. On the other hand, in the 4 ′ sample crystallized because the irradiation intensity was 300 mJ / cm ² , the sheet resistance was 1.2 × 10 ⁴ Ω even at a heating temperature of 200 ° C. That is, it is clear that the increase in resistance of IGZO due to heating can be suppressed by crystallizing IGZO.

That is, as shown in the above embodiment, the increase in the resistance value of the source / drain region due to heating can be suppressed by crystallizing the source / drain region. For this reason, it is possible to suppress a decrease in drain current and variation in characteristics.
From the above, the preferred irradiation intensity 150 mJ / cm ² or more, it can be said more preferable irradiation intensity is 200 mJ / cm ² or more.

Next, measurement results of a sample produced by the example of the third embodiment using a TEM (Transmission Electron Microscope) will be described with reference to FIG. Specifically, a sample similar to the above-described fourth sample (irradiation pulse width is 50 ns, irradiation intensity is 300 mJ / cm ² ) was prepared as a sample (referred to as a fifth sample).
That is, for the fifth sample, the difference in crystallinity depending on the cross-sectional observation and the observation location of the IGZO film 24 was analyzed using TEM. FIG. 6 shows an observation region position (a) and an observation image (b). In the IGZO film, electron diffraction patterns of a region (A) where Al is not present below and irradiated with excimer laser light and a region (B) where Al is present below and not irradiated with excimer laser light were obtained. As a result, many diffraction spots showing crystallinity were confirmed in the region (A), but no diffraction spots showing crystallinity were confirmed in the region (B).

  In the TFT manufactured in this example, the channel region in which Al as the gate electrode film 22 is present is found to be amorphous. Further, it has been clarified that a part of the low resistance region which is a source / drain region where Al which is the gate electrode film 22 does not exist below is crystallized. Further, when attention is paid to the IGZO region in which Al as the gate electrode film 22 does not exist below, it becomes clear that the gate electrode film 22 is divided into a crystalline region and an amorphous region in the film thickness direction.

As is apparent from FIG. 6, according to the TFT fabricated in this example, the region close to the silicon oxide (SIO ₂ ) that is the gate insulating film is amorphous, but the surface of the IGZO film 24 on the opposite side has a large amount. It became clear that it was a crystal.

  Further, it has been clarified that the thickness of the region to be crystallized increases as the excimer laser irradiation intensity increases. In addition, the thickness of the IGZO film region (channel region) 24a that is not irradiated with the excimer laser is 48 nm while Al as the gate electrode film 22 is present below, whereas the excimer laser does not exist when Al is not present below. The thickness of the irradiated IGZO film region (low resistance IGZO film) 24 ′ partially crystallized was 46 nm. As described above, it is clear that the thickness of the IGZO film region 24 ′ having a low resistance at least partially in the region other than the channel region 24 a of the TFT manufactured in this embodiment is thinner than the thickness of the channel region 24 a. It was.

1, 11, 21 Glass substrate (substrate)
2, 12, 22 Gate electrode film 3, 13, 23 Gate insulating film 4, 14, 24 IGZO film 4 ', 14', 24 'Low resistance IGZO film 4a, 14a, 24a Channel region 5, 15 Protective film 6a, 16a Source region 6b, 16b Drain region 7a, 17a Source electrode film 7b, 17b Drain electrode film

Claims (13)

In a thin film transistor in which a plurality of layers including at least a gate electrode film and an oxide semiconductor layer are stacked on a substrate,
A part of the oxide semiconductor layer is an amorphous channel region, and at least a part of the oxide semiconductor layer other than the channel region is a low-resistance region. A thin film transistor characterized in that at least a part thereof is crystallized.   2. The thin film transistor according to claim 1, wherein the regions other than the channel region are a source region and a drain region located on both sides of the channel region.   3. The thin film transistor according to claim 1, wherein, in a region other than the channel region, one side in the thickness direction of the film is crystallized and the other side is amorphous.   The thin film transistor according to claim 1, wherein a film thickness of a region other than the channel region is thinner than a film thickness of the channel region.   5. The thin film transistor according to claim 1, wherein the low resistance region is formed by light irradiation with predetermined light.   6. The thin film transistor according to claim 5, wherein the predetermined light is one of excimer laser light, flash lamp light, and CW laser light.   The oxide semiconductor constituting the oxide semiconductor layer includes at least one element of indium, gallium, zinc, tin, aluminum, silicon, germanium, boron, manganese, titanium, and molybdenum. The thin film transistor according to any one of 1 to 6.   The thin film transistor according to claim 1, wherein the oxide semiconductor constituting the oxide semiconductor layer contains indium gallium zinc oxide as a material. A gate electrode film, a gate insulating film, and an oxide semiconductor layer are stacked in this order on the substrate,
Thereafter, a region of the oxide semiconductor layer that does not overlap the gate electrode film on the line of sight when irradiated with predetermined light from the substrate side toward the oxide semiconductor layer when viewed from the substrate side. A method of manufacturing a thin film transistor, characterized by crystallizing at least a part of the film to reduce resistance and manufacturing a thin film transistor having a self-aligned bottom gate structure. A plurality of layers including an oxide semiconductor layer, a gate insulating film, and a gate electrode film are stacked in this order on the substrate,
Thereafter, the oxide that does not overlap the gate electrode film on the line of sight when viewed from the gate electrode film side by irradiating predetermined light from the gate electrode film side toward the oxide semiconductor layer A method of manufacturing a thin film transistor, characterized by crystallizing at least a part of a region of a semiconductor layer to reduce resistance and manufacturing a thin film transistor having a self-aligned top gate structure.   11. The method of manufacturing a thin film transistor according to claim 9, wherein the predetermined light is any one of excimer laser light, flash lamp light, and CW laser light. 12. The energy density per pulse of the excimer laser light is 10 to 1000 mJ / cm ² when the predetermined light is the excimer laser light. A method for producing the thin film transistor according to 1. 12. The energy density per pulse of the flash lamp light is 0.1 to 500 J / cm ² when the predetermined light is the flash lamp light. A method for producing the thin film transistor according to 1.