JP2014139860A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an SRAM which achieves both an SNM and a write-in margin even at a low power source voltage.SOLUTION: The SRAM includes: cell power source lines provided corresponding to first and second columns; a power source line supplying a power source voltage; and first and second power source circuits which are provided corresponding to the cell power source lines of the first and second columns, and electrically connect between corresponding memory cell power source lines and the power source lines. Each of the memory cells is constituted by a CMOS latch circuit having first and second P-channel type transistors, first to fourth N-channel type transistors, and first and second storage nodes. The first power source circuit lowers a voltage of a first memory cell power source line in response to a signal selecting the first column during writing, and the second power source circuit lowers a voltage of a second memory cell power source line in response to a signal selecting the second column during writing.

Description

  The present invention relates to a semiconductor integrated circuit device, and more particularly to a technique effective when used for a device having a static RAM (random access memory).

  A static noise margin (hereinafter referred to as SNM) is a characteristic of a memory cell of a static RAM (hereinafter simply referred to as SRAM). The SNM indicates the stability of the data stored in the memory cell. The larger the SNM, the more stable the data holding operation. On the other hand, the SNM is difficult to write when writing reverse data to the held data. As a technique for solving such a problem, there is JP-A-2002-042476. FIG. 17 shows a block diagram of an SRAM that the present inventor previously examined based on the above publication. In the technique of this publication, a voltage supply circuit as shown in FIG. 18 is used at the time of reading, and the signal WEi is set to a low level to turn on the P-channel MOSFET so that the voltage at the same level as the external power supply Vcc is applied to the memory cell. Supply and drive stably. At the time of writing, the signal WEi is set to a high level to turn off the P-channel MOSFET, and the N-channel MOSFET is turned on to reduce the internal power supplied to the memory cell to Vcc−Vth. Thereby, the SNM of the memory cell selected by the word line is lowered, and the write margin can be improved.

JP 2002-042476 A

  In the technique of Patent Document 1, the internal power supply of memory cells that are selected by row decoding and the word line is activated but not selected by column decoding also decreases, and the SNM is not performed. There is a risk of data loss due to the influence of noise or the like. In order to avoid such a risk, in Patent Document 1, a lower limit voltage is set by an external power supply voltage control circuit as shown in FIG. 19, and the SNM of the non-selected memory cell limits a decrease by determining this. It is what you want to do. However, in order to generate the lower limit voltage as described above, it is necessary to provide an intermediate power generation circuit in the memory, which increases the current consumption of the memory circuit, and the SNM of the SNM due to the lower limit voltage. The reduction is limited, and the write margin cannot be improved. In particular, LSI (Large Scale Integrated circuit) tends to lower the power supply voltage due to low power consumption and miniaturization of transistors (MOSFETs) in the LSI, and the difference from the lower limit voltage is small. Become. As the memory circuit, it is necessary to prioritize the SNM, and the technique of the cited document 1 may not be able to improve the write margin.

  An object of the present invention is to provide a semiconductor integrated circuit device including a static RAM that can achieve both SNM and write margin even at a low power supply voltage. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows. The semiconductor integrated circuit device includes a plurality of first memory cells arranged in a first column along a first direction on a main surface of a semiconductor substrate, and a first surface along the first direction on a main surface of the semiconductor substrate. A plurality of second memory cells arranged in two columns, a first bit line commonly connected to the plurality of first memory cells, and a first bit line commonly connected to the plurality of first memory cells. 2 bit lines, a third bit line commonly connected to the plurality of second memory cells, a fourth bit line commonly connected to the plurality of second memory cells, and the plurality of first bits Are connected to the plurality of second memory cells, respectively, and each of the plurality of word lines extends along a second direction, and is commonly connected to the plurality of first memory cells. The first memory cell power line, common to the plurality of second memory cells A connected second memory cell power supply line, a power supply line for supplying a power supply voltage, and a first power supply circuit for electrically connecting the first memory cell power supply line and the power supply line; A first power supply circuit that electrically connects the memory cell power supply line and the power supply line. Each of the plurality of first memory cells includes a first inverter including a first P-channel transistor and a first N-channel transistor, a second P-channel transistor, and a second N-channel transistor. A second inverter whose output is connected to an input of the first inverter, an input of which is connected to an output of the first inverter, the first bit line and the first inverter to chromatic third N-channel transistor for electrically connecting the output, and a fourth N-channel transistor electrically connected between an output of said second bit line and the second inverter, the . The first P-channel transistor and the second P-channel transistor are provided in a first N-well region, and the first N-channel transistor and the third N-channel transistor are in a first P-well region. The second N-channel transistor and the fourth N-channel transistor are provided in a second P-well region, and the first N-well region is provided in the first P-well region and the second P-well region. The first P well region, the N well region, and the second P well region are arranged in the second direction so as to be located between the P well regions, and the semiconductor substrate in the memory cell power supply line First and second connection portions are respectively joined to first and second portions having different surfaces facing each other, and the source of the first P-channel transistor is the first portion. Electrically connected to the memory cell power line via a connection, and the source of the second P-channel transistor is electrically connected to the memory cell power line via the second connection; The gates of the third N-channel transistor and the fourth N-channel transistor are electrically connected to a common first word line of the plurality of word lines, and the common first word Third and fourth connection portions are respectively joined to third and fourth portions of the line opposite to the semiconductor substrate, and a gate of the third N-channel transistor is connected to the third N-channel transistor. It is electrically connected to the common first word line via a connection portion, and the gate of the fourth N-channel transistor is connected to the common first word line via the fourth connection portion. Electrical The distance between the first part and the second part along the first direction is greater than the distance between the third part and the fourth part along the second direction. Is also small. Each of the plurality of second memory cells includes a third inverter including a third P-channel transistor and a fifth N-channel transistor, a fourth P-channel transistor, and a sixth N-channel transistor. A fourth inverter whose output is connected to an input of the third inverter, an input of which is connected to an output of the third inverter, the third bit line and the third inverter A seventh N-channel transistor that electrically connects an output; and an eighth N-channel transistor that electrically connects the fourth bit line and the output of the fourth inverter. The third P-channel transistor and the fourth P-channel transistor are provided in a second N-well region, and the fifth N-channel transistor and the seventh N-channel transistor are provided in a third P-well region. The sixth N-channel transistor and the eighth N-channel transistor are provided in a fourth P-well region, and the second N-well region is provided in the third P-well region and the fourth P-well region. The third P well region, the second N well region, and the fourth P well region are arranged in the second direction so as to be located between the P well regions, and the memory cell power supply line Fifth and sixth connection portions are respectively joined to the fifth and sixth portions having different surfaces facing the semiconductor substrate, and the source of the third P-channel transistor is the And the source of the fourth P-channel transistor is electrically connected to the memory cell power line via the sixth connection part. The gates of the seventh N-channel transistor and the eighth N-channel transistor are electrically connected to a common second word line of the plurality of word lines, and the common second The seventh and eighth connection portions are respectively joined to the seventh and eighth portions of the word line opposite to the surface facing the semiconductor substrate, and the gate of the seventh N-channel transistor is connected to the seventh and eighth portions. And the gate of the eighth N-channel transistor is connected to the common second word line via the eighth connection portion. line The distance between the fifth portion and the sixth portion that are electrically connected and is along the first direction is between the seventh portion and the eighth portion along the second direction. Less than the interval. The first power supply circuit decreases the voltage of the first memory cell power supply line in response to a signal for selecting the first column at the time of writing, and the second power supply circuit reduces the second power supply circuit at the time of writing. The voltage of the second memory cell power supply line is lowered in response to a signal for selecting the column.

  While improving the write operation margin of the memory cell corresponding to the selected complementary bit line, the SNM of the non-selected memory cell connected to the non-selected complementary bit line can be secured.

1 is a block diagram showing an embodiment of a static RAM according to the present invention. FIG. FIG. 2 is a circuit diagram showing an embodiment of the power supply circuit of FIG. 1. 1 is a circuit diagram showing one embodiment of a memory cell according to the present invention. 1 is a layout diagram showing one embodiment of a memory cell according to the present invention. It is a wave form diagram for demonstrating an example of operation | movement of static type RAM which concerns on this invention. It is a block diagram which shows another Example of static type RAM which concerns on this invention. FIG. 7 is a circuit diagram showing an embodiment of a power supply circuit used in the static RAM of FIG. 6. FIG. 7 is a circuit diagram showing another embodiment of a power supply circuit used in the static RAM of FIG. 6. FIG. 7 is a circuit diagram showing still another embodiment of a power supply circuit used in the static RAM of FIG. 6. FIG. 7 is a circuit diagram showing still another embodiment of a power supply circuit used in the static RAM of FIG. 6. FIG. 7 is a circuit diagram showing still another embodiment of a power supply circuit used in the static RAM of FIG. 6. FIG. 7 is a circuit diagram showing still another embodiment of a power supply circuit used in the static RAM of FIG. 6. FIG. 7 is a circuit diagram showing still another embodiment of a power supply circuit used in the static RAM of FIG. 6. FIG. 7 is a layout diagram showing another embodiment of the memory cell according to the present invention. FIG. 7 is a circuit diagram showing an example of a word driver used in the static RAM of FIG. 1 or FIG. 6. 1 is an overall circuit diagram showing an embodiment of a static RAM according to the present invention. It is a block diagram of SRAM which this inventor examined previously based on patent document 1. FIG. 10 is a circuit diagram of an example of a voltage supply circuit disclosed in Patent Document 1. FIG. FIG. 10 is a circuit diagram of another example of the voltage supply circuit disclosed in Patent Document 1.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram showing an embodiment of a static RAM according to the present invention. In the drawing, four memory cells, two corresponding word lines WL0 and WLn, and complementary bit lines / BL0, BL0 and / BLm, BLm are exemplarily shown as representatives. Although not shown, the memory cell forms a latch (flip-flop) circuit by cross-connecting the inputs and outputs of two CMOS inverter circuits composed of a P-channel MOSFET and an N-channel MOSFET to form a memory unit, and this input / output mutual Using the connection portion as a storage node, it is composed of an N-channel MOSFET for address selection provided between the corresponding bit lines / BL and BL. The gate of this address selection MOSFET is connected to the corresponding word line.

  One of the word lines WL0 to Wn is selected by the row decoder. The row decoder includes a word driver as will be described later. The row decoder is supplied with a row (row) address signal among the address signals. Of the plurality of complementary bit lines / BL0, BL0 / BLm, BLm, a pair is connected to a write driver or a sense amplifier via a column selection switch. That is, the column selection switch receives the selection signals YS0 to YSm formed by the column decoder, selects a pair of the plurality of complementary bit lines / BL0, BL0 to / BLm, BLm and Connect to the output terminal and the input terminal of the sense amplifier.

  A read / write control signal R / W is supplied to the control circuit. The control circuit generates a write signal WE or a sense amplifier control signal SAC as a read signal in response to the read / write control signal R / W. The write signal WE is supplied to the write driver and used to activate the write driver. That is, when one of the word lines is selected by the row decoder, a pair of complementary bit lines are selected by the column decoder by the column selection switch, and the write driver is activated, the data input signal is selected by the selected word line and the selected complementary bit. Write to memory cells coupled to the line. The sense amplifier control signal SAC is used to activate the sense amplifier. Similarly to the above, if one of the word lines is selected by the row decoder, a pair of complementary bit lines are selected by the column selection switch by the column decoder, and the sense amplifier is activated, the selected word line and the selected complementary bit line are coupled. The read signal of the memory cell transmitted to the sense amplifier is amplified and read as a data output.

  In this embodiment, in order to secure the SNM of the non-selected memory cell connected to the non-selected complementary bit line while improving the write operation margin of the memory cell corresponding to the selected complementary bit line, Memory cell power supply lines VCC0 to VCCm are provided corresponding to lines / BL0, BL0 to / BLm and BLm, respectively. That is, the memory cell power supply line VCC0 exemplarily shown as a representative is a power supply line of a memory cell connected to the corresponding complementary bits / BL0 and BL0. Similarly, the memory cell power supply line VCCm shown as a representative example is a power supply line of a memory cell connected to the corresponding complementary bit / BLm, BLm. Therefore, power supply circuits 0 to m are provided between the memory cell power supply lines VCC0 to VCCm and the power supply VCC.

  FIG. 2 shows a circuit diagram of an embodiment of the power supply circuit of FIG. In this embodiment, a P-channel MOSFET QP is used as the power supply circuit. The gate of the MOSFET QP is steadily given a circuit ground potential and operates as a resistance element, and transmits the power supply VCC to the internal power supply for each column, that is, the memory cell power supply line. The on-resistance value of the MOSFET QP is such that one of the complementary bit lines / BL or BL is changed from the precharge level such as the power supply voltage VCC to the ground potential of the circuit for the write operation to the memory cell as described below. When the level is changed to a low level, the resistance of the memory cell power supply line is allowed to be temporarily lowered by capacitive coupling with the changed potential of the bit line. By reducing the operating potential to the write memory cell, the SNM is lowered to improve the write margin. On the other hand, since the unselected bit lines / BL and BL are both maintained at a high level like the power supply voltage VCC, the corresponding memory cell power supply line is also maintained at the power supply voltage VCC. Therefore, even in the memory cell in which the word line is selected, the SNM can be maintained high because the power supply voltage is maintained high.

  FIG. 3 is a circuit diagram showing one embodiment of a memory cell according to the present invention. The memory cell comprises a latch (flip-flop) circuit by cross-connecting the input and output of two CMOS inverter circuits from the P-channel MOSFET Q1, the N-channel MOSFET Q2, the P-channel MOSFET Q3, and the N-channel MOSFET Q4 to form a memory unit, Such input / output interconnections are constituted by storage nodes N1 and N2 and N channel MOSFETs Q5 and Q6 for address selection provided between corresponding bit lines / BL and BL. The gates of these address selecting MOSFETs Q5 and Q6 are connected to the corresponding word line WL.

  In the memory cell of this embodiment, the supply of the operating voltage VCC ′ to the memory cells corresponding to the complementary bit lines / BL and BL is provided between the complementary bit lines / BL and BL, and in parallel therewith. Supplied from the extended memory cell power line. That is, the memory cell power supply line is connected to the sources of P-channel MOSFETs Q1 and Q3 constituting the CMOS inverter circuit. The memory cell power line as described above has a parasitic capacitance C1 between one of the complementary bit lines / BL and a parasitic capacitance C2 between the other BL of the complementary bit lines.

  FIG. 4 shows a layout diagram of an embodiment of the memory cell according to the present invention. 4A shows each layout pattern of the source, drain and gate of MOSFET, contact wiring and contact hole, and FIG. 4B shows the operation of bit lines / BL, BL and memory cells. The layout pattern of the memory cell power supply line for supplying the voltage VCC ′, the contact wiring, and the contact hole is shown, and FIG. The layout pattern is shown. A contact hole is indicated by attaching a cross to a square like a CNT, one representative of which is shown in each of (A), (B), and (C).

  In FIG. 4A, P-channel MOSFETs Q1 and Q3 are formed in an N-type well NWEL provided in a hatched central portion. On the other hand, the N-channel MOSFETs Q2, Q4 and Q5 and Q6 are formed on the P-type substrate or the P-type well PWEL other than the portion of the N-type well NWEL. Each of MOSFETs Q1 and Q2 and Q3 and Q4 constituting the CMOS inverter circuit is integrally formed with a gate electrode. In each contact wiring and contact hole, connection destinations are shown as WL, / BL, VCC ′, BL, WL, and VSS. MOSFETs Q1, Q2, and Q5 and MOSFETs Q2, Q4, and Q6 are symmetrically arranged at positions rotated by 180 ° with respect to the middle point of the memory cell. The contact wiring layer is shown by a white pattern surrounding the contact hole, and is not particularly limited, but is composed of the first metal layer M1.

  In FIG. 4B, bit lines / BL and BL correspond to one source and drain of MOSFETs Q5 and Q6 to which the bit lines / BL and BL are connected, and are boundary lines that divide the memory cell region into four equal parts in the horizontal direction in FIG. Among them, 1/4 and 3/4 portions are arranged so as to extend in the vertical direction in the figure, and are not particularly limited, but are formed by the second metal wiring layer M2. The memory cell power supply line is also formed by the second metal layer M2 which is the same as the bit lines / BL and BL, and is formed at the center (2/4) of the boundary line which divides the memory cell region into four equal parts. It is provided to extend in the vertical direction. The memory cell power line (VCC ′) has a protrusion extending in the direction of the adjacent bit line / BL in order to be connected to the source of the P-channel MOSFET Q1 in the upper part, and connected to the source of the P-channel MOSFET Q3 in the lower part. Therefore, a protrusion extending in the direction of the adjacent bit line BL is provided. With such a wiring layout, a parasitic capacitance C1 is formed between the bit line / BL and the memory cell power supply line (VCC ′), and the bit line BL and the memory cell power supply line (VCC ′) A parasitic capacitance C2 is formed between them.

  In FIG. 4C, the word line WL extends in the horizontal direction in the figure at the center of the memory cell region. The word line WL is formed by the third metal layer M3. The memory cell ground line VSS provided in the memory cell region and extending in the vertical direction is composed of a fourth metal layer M4. This ground line VSS is shared with the ground line VSS of the adjacent memory cell. With the memory cell configuration as in this embodiment, it is easy to form a power supply line for each column. Then, coupling capacitors C1 and C2 can be formed between the bit lines / BL and BL and the internal power supply line (memory cell power supply line).

  FIG. 5 is a waveform diagram for explaining an example of the operation of the static RAM according to the present invention. At the time of reading from the static RAM, the address selection MOSFETs Q5 and Q6 of the memory cell are turned on by the selection operation of the word line WL, and the bit line corresponding to the low level node among the storage nodes N1 and N2 of the memory cell. One of / BL and BL decreases. At this time, the bit lines / BL and BL have a relatively large parasitic capacitance by being connected to a large number of memory cells, and the on-resistance values of the address selection MOSFETs Q5 and Q6 are relatively large. The decrease in the read signal of BL is small and its level change is also gradual. Therefore, even if the parasitic capacitances (coupling capacitances) C1 and C2 exist between the bit lines / BL and BL and the memory cell power supply line as described above, the voltage VCC ′ of the memory cell power supply line hardly changes. First, the power supply voltage VCC is maintained. As a result, the static noise margin (SNM) during the read operation can be kept large. A read signal having a small level difference between the bit lines / BL and BL as described above is amplified by a sense amplifier and output as a data output.

  At the time of writing to the static RAM, the address selection MOSFETs Q5 and Q6 of the memory cell are turned on by the selection operation of the word line WL. In response to a write signal from the write driver, one of the bit lines / BL and BL suddenly drops to the ground potential of the circuit. Such a decrease in the full-amplitude write signal is transmitted to the memory cell power supply line via the parasitic capacitance (coupling capacitance) C1 or C2 between the memory cell power supply line and temporarily increases the operating voltage VCC ′ of the memory cell. Decrease. In other words, the operating voltage VCC ′ decreases due to the coupling, but gradually recovers toward the power supply voltage VCC because the power supply voltage VCC is supplied through the resistance element as the power supply circuit. At this time, one of the bit lines / BL or BL is at the low level, and the high level of the storage node N1 or N2 is pulled out to the low level through the MOSFET Q5 or Q6 that is turned on by the selected state of the word line. The stored information in the storage part of the memory cell is inverted.

  For example, when pulling out the high level of the storage node N1 to the low level as described above, the MOSFET Q1 that maintains the high level of the storage node N1 also lowers the storage node N1 even when the power supply voltage VCC 'decreases. At the same time, the high level of the bit line BL is transmitted to the gate (storage node N2) of the MOSFET Q2 through the MOSFET Q6 to turn on the MOSFET Q2. Therefore, the storage node N1 decreases at a high speed due to the above three factors overlapping. A path is also formed to turn on the storage node N2 by turning on the P-channel MOSFET Q3. As a result, the storage node N1 changes from the high level to the low level and the storage node N2 changes from the low level to the high level at high speed, and the write margin can be improved. That is, the write margin can be improved as described above even when the power supply voltage VCC is reduced due to element miniaturization or the like and the drivability of the write driver is reduced.

  At this time, even if the word line WL is in the selected state, the write operation is not performed, that is, in the memory cell connected to the non-selected complementary bit lines / BL and BL that should hold the stored data, Since such a voltage drop due to coupling from the write bit line does not occur, the power supply voltage VCC can be maintained as in the case of the read operation. For this reason, even in the memory cells in which the MOSFETs Q5 and Q6 are turned on with the word line selected, those that should hold the stored data can maintain a large static noise margin (SNM). . As described above, the non-selected column at the time of writing and the bit line at the time of reading have a relatively gentle and small amplitude due to the bit line amplitude by the memory cell, so that the coupling effect is small and the decrease in SNM is small and the operation is stable. .

  FIG. 6 is a block diagram showing another embodiment of the static RAM according to the present invention. In this embodiment, the write signal WE similar to that shown in FIG. 1 is provided for each bit line by combining the bit line selection signals YS0 to YSm formed by the column decoder and the gate circuits G0 and Gm. Used to form write driver activation signals WC0-WCm. That is, when a write operation is instructed, the write driver corresponding to the column address is activated, and data input is written to the memory cells connected to the word line selected by the word driver. On the other hand, when the read operation is instructed, the read column selection switch is turned on corresponding to the column address, and the signals of the selected bit lines / BL and BL are transmitted to the input of the sense amplifier, and the read signal Amplification is performed by the SAC and data is output.

  When write drivers are provided corresponding to the complementary bit lines / BL and BL as described above, the column selection switches are not interposed as in the embodiment of FIG. 1, and the complementary bit lines / BL and BL are connected to the complementary bit lines / BL and BL. Since a write signal corresponding to the data input can be directly transmitted, one of the bit line pairs can be pulled out from the precharge level to the low level at high speed. In this embodiment, the signals WC0 to WCm are used to control the power supply circuits 0 to m connected to the memory cell power supply lines VCC0 to VCCm corresponding to the respective bit lines / BL0, BL0 to / BLm, BLm. Used as a signal. Other configurations are basically the same as those of the embodiment of FIG.

  FIG. 7 shows a circuit diagram of an embodiment of a power supply circuit used in the static RAM of FIG. In this embodiment, a P-channel MOSFET QP2 whose gate is supplied with the signal WC is provided in parallel with a P-channel MOSFET QP1 such as the power supply circuit of FIG. The signal WC is set to a high level corresponding to the selected complementary bit lines / BL, BL. Therefore, for example, the P-channel MOSFET QP2 of the power supply circuit is turned off in correspondence with the selected complementary bit lines / BL0, BL0. Thereby, at the time of writing, the power supply voltage VCC ′ of the selected memory cell is lowered by the coupling with the bit line to which the write signal is transmitted as described above. On the other hand, in the power supply circuit corresponding to the other non-selected complementary bit lines including the selected complementary bit lines / BLm and BLm, the P-channel MOSFETs QP1 and QP2 are both turned on, and the power supply voltage VCC ′ of the non-selected memory cell is turned on. Is kept equal to the power supply voltage VCC.

  In this embodiment, if the on-resistance value of the P-channel MOSFET QP1 is made sufficiently large, the coupling capacitors C1 and C2 are not particularly required. For example, the P-channel MOSFET QP2 of the power supply circuit is turned off corresponding to the selected complementary bit lines / BL0, BL0, and only a very small current is supplied from the high-resistance P-channel MOSFET QP1. Therefore, in this MOSFET QP1, a leakage current in a large number of memory cells connected to the complementary bit lines / BL0 and BL0 and a current corresponding to a change in the output signal of the CMOS inverter circuit flowing in the memory cell to which the inversion writing is performed flow. Accordingly, the operating voltage VCC ′ of the memory cell is lowered even without the above-described capacitive coupling. By reducing the operating voltage VCC ′, the write margin for the memory cell can be increased.

  On the other hand, even if the word line is in the selected state, the write operation is not performed, that is, in the memory cell connected to the non-selected complementary bit line that should hold the stored data, the MOSFETs QP1 and QP2 Since the memory cell power supply line is connected to the power supply voltage VCC with low impedance due to the ON state, the power supply voltage VCC can be more stably maintained. As a result, even in the memory cells in which the word lines are selected and the MOSFETs Q5 and Q6 are in the on state, those that should hold the stored data can maintain a large static noise margin (SNM). . Therefore, the layout of the memory cell of this embodiment is not limited to the embodiment as shown in FIG. 4, for example, the bit lines / BL, BL and the power supply line VCC ′ may be configured by separate wiring layers, The degree of freedom in circuit layout can be increased.

  FIG. 8 shows a circuit diagram of another embodiment of the power supply circuit used in the static RAM of FIG. In this embodiment, the P-channel MOSFET QP1 in FIG. 7 is omitted, and only the P-channel MOSFET QP2 to which the signal WC is supplied to the gate is constituted. In this configuration, for example, the P-channel MOSFET QP2 of the power supply circuit is turned off corresponding to the selected complementary bit lines / BL0, BL0, and the power of all the memory cells corresponding to the complementary bit lines / BL0, BL0 is cut off. It will be in the state. Therefore, in this MOSFET QP1, a leakage current in a large number of memory cells connected to the complementary bit lines / BL0 and BL0 and a current corresponding to a change in the output signal of the CMOS inverter circuit flowing in the memory cell to which the inversion writing is performed flow. Therefore, even if there is no capacitive coupling as described above, the operating voltage VCC ′ of the memory cell is greatly reduced.

  Therefore, even if the voltage drops temporarily below the lower limit operating voltage of the memory cell, the high level and low level from the write driver for the selected memory cell with the word line selected are the MOSFET Q5. And the capacity of the storage nodes N1 and N2 through Q6. On the other hand, in the memory cell in which the word line is not selected, since the MOSFETs Q5 and Q6 are in the off state, even if the power supply voltage VCC ′ is lower than the lower limit operating voltage, the storage nodes N1 and N2 The stored charge is held in the capacitor. Therefore, even if the P-channel MOSFET QP2 is turned off for a short time necessary for the write operation to the memory cell, the non-selected memory cell holds the stored data by the stored charge as in the dynamic memory cell. ing. Then, the P channel MOSFET QP2 can be turned on to supply the power supply voltage VCC to recover the temporarily reduced storage charge.

  In this embodiment, the static memory cells are different from each other in a state where the power sources of all the memory cells corresponding to the complementary bit lines / BL0, BL0 selected as described above are temporarily shut off by the off state of the MOSFET QP2. A storage operation similar to that of the two dynamic memory cells in the charge state is performed, and even if a part of the storage charge of the storage node N1 or N2 is temporarily lost, the inverter circuit is supplied with power by turning on the MOSFET QP2 upon completion of writing Can be restored to its original state. In this embodiment, the pulse width of the write signal WE may be set so that the internal power supply VCC 'of the selected column at the time of the write operation does not reach the level of data erasure of the unselected memory cell. In this embodiment, a non-selected memory cell connected to the non-selected complementary bit line while improving the write operation margin of the memory cell corresponding to the selected complementary bit line while using a power supply circuit having a simple configuration. SNM can be secured.

  FIG. 9 shows a circuit diagram of still another embodiment of the power supply circuit used in the static RAM of FIG. In this embodiment, an N-channel MOSFET QN1 is provided in parallel with the P-channel MOSFET QP2 of FIG. The gates of the P-channel MOSFET QP2 and the N-channel MOSFET QN1 are connected in common and supplied with the write signal WC. In this embodiment, for example, when the P-channel MOSFET QP2 of the power supply circuit is turned off corresponding to the selected complementary bit lines / BL0 and BL0, the N-channel MOSFET QN1 is turned on instead. Therefore, even if a leak current in a large number of memory cells connected to the complementary bit lines / BL0 and BL0 and a current corresponding to a change in the output signal of the CMOS inverter circuit flowing in the memory cell to be inverted write flows, The cell operating voltage VCC ′ decreases only to VCC−Vth. Vth is the threshold voltage of the N-channel MOSFET QN1. This eliminates the concern that even if the pulse width of the write signal WE is increased compared to the embodiment of FIG.

  FIG. 10 is a circuit diagram showing still another embodiment of the power supply circuit used in the static RAM shown in FIG. In this embodiment, the P-channel MOSFET QP1 in FIG. This resistance element R is for replacing with a resistance means other than a MOSFET, for example, a diffusion resistance or a polysilicon resistance, and the operation is the same as in the embodiment of FIG.

  FIG. 11 is a circuit diagram showing still another embodiment of the power supply circuit used in the static RAM of FIG. This embodiment is a modification of the embodiment of FIG. 9, and the lower limit voltage is transmitted to the internal power supply (memory cell power supply line VCC ') for each column by the N-channel MOSFET QN2. That is, in the embodiment of FIG. 9, the power supply voltage VCC-Vth lowered by the threshold voltage Vth of the N-channel MOSFET is supplied to the selected column at the time of writing. Is supplied by an N-channel MOSFET QN2. For this reason, the lower limit voltage <VCC−Vth. If the lower limit voltage is higher than VCC-Vth, a P-channel MOSFET is used, and the write signal WC is inverted by an inverter circuit and supplied to the gate of the P-channel MOSFET that supplies the lower limit voltage. Good. In this case, it is necessary to separately provide a lower limit voltage generation circuit.

  FIG. 12 is a circuit diagram showing still another embodiment of the power supply circuit used in the static RAM shown in FIG. This embodiment is a modification of the embodiment of FIG. 11, and the threshold voltage Vth of the P-channel MOSFET QP3 is used as the lower limit voltage. In this embodiment, a P-channel MOSFET QP3 is provided between the memory cell power supply line and the circuit ground potential VSS. The write signal WC is supplied to the gate of the MOSFET QP3 via the inverter circuit INV1. In this configuration, the write signal WC is set to the high level corresponding to the selected complementary bit lines / BL, BL. Thereby, P-channel MOSFET QP2 is turned off, and P-channel MOSFET QP3 is turned on instead. Due to the on state of the P-channel MOSFET QP3, the memory cell operating voltage VCC 'is lowered to Vth. The memory cells connected to the selected complementary bit lines / BL, BL operate using the threshold voltage Vth of the MOSFET QP3 as the operating voltage.

  As described above, the leakage current in a large number of word line non-selected memory cells connected to the selected complementary bit lines / BL and BL and the data inversion current in the selected word line memory cell are consumed. Since the power supply circuit of the example does not have a current path corresponding thereto, it is substantially the same as the embodiment of FIG. That is, in this embodiment, instead of waiting for the memory cell operating voltage to decrease due to the current as in the embodiment of FIG. 8, the memory cell operating voltage is positively set by turning on the MOSFET QP3 when writing the memory cell. In a state where VCC ′ is lowered to Vth and the write margin is expanded, writing is completed within a short time, and the P-channel MOSFET QP2 is immediately turned on. In this configuration, the writing time can be easily set without being affected by variations in elements.

  FIG. 13 is a circuit diagram showing still another embodiment of the power supply circuit used in the static RAM according to the present invention. In this embodiment, instead of the configuration in which the power supply circuit is provided on the power supply voltage VCC side as in the embodiments of FIGS. 1 and 6, the write operation margin of the memory cell corresponding to the selected complementary bit line is improved. On the other hand, in order to secure the SNM of the non-selected memory cells connected to the non-selected complementary bit lines, the memory cell power supply lines VSS0 to VSSm are set corresponding to the complementary bit lines / BL0, BL0 to / BLm, BLm, respectively. Provide. In other words, the memory cell ground line VSS in the figure is a ground line of the memory cell connected to the corresponding complementary bit / BL0, BL0. A ground supply circuit as shown in FIG. 13 is provided between each of the memory cell ground lines VSS ′ and the circuit ground line VSS.

  In this embodiment, the write signal WCB is set to the low level corresponding to the selected complementary bit lines / BL, BL. As a result, the N-channel MOSFET QQN3 is turned off and the P-channel MOSFET QP4 is turned on. Therefore, the leakage current flowing through a large number of memory cells connected to the selected complementary bit lines / BL, BL and the current flowing for the write operation flow through the P-channel MOSFET QP4, and the ground potential VSS of the memory cell. Increase 'by Vth. That is, since only a low voltage such as VCC-Vth is applied to the memory cell in which the write operation is performed, this is equivalent to the embodiment of FIG. 9 and the write margin can be increased. On the other hand, the ground potential VSS 'of the memory cell corresponding to the non-selected complementary bit lines / BL, BL is in the on state, and the ground potential VSS is transmitted as it is. As a result, the operating voltage of the non-selected memory cell connected to the non-selected complementary bit line becomes VCC, and the SNM can be secured in the same manner as described above.

  The ground supply circuit of this embodiment includes a P-channel MOSFET QP4 and an N-channel MOSFET QN3 arranged in parallel. A write signal WCB inverted by the inverter circuit INV1 as shown in FIG. 12 is supplied to the gates of these MOSFETs QP4 and QN3. The ground supply circuit of this embodiment can be regarded substantially as a power supply circuit as described above. That is, since the memory cell operates with a voltage difference between the power supply voltage VCC and the ground voltage VSS as an operating voltage, the memory cell supplies the voltage VCC ′ obtained by reducing the power supply voltage VCC as in the above-described embodiment, and the circuit. Supplying the voltage VSS ′ obtained by increasing the ground potential VSS is equivalent to the operation of the memory cell.

  As in the embodiment of FIG. 1, in order to raise the ground line to the high level side by capacitive coupling with the bit line, the bit line is precharged to the low level and corresponding to the input data. In this case, one bit line may be discharged to a high level like the power supply voltage VCC.

  FIG. 14 is a layout diagram showing another embodiment of the memory cell according to the present invention. 14A and 14C are the same as FIGS. 4A and 4C, and symbols such as the wiring layers M1 to M4 are omitted. In this embodiment, a device for increasing the capacitance values of the parasitic capacitors C1 and C2 is shown. The parasitic capacitance can be increased even if the wiring width of the power supply line VCC ′ is increased and the distance between the bit lines / BL and BL is shortened. However, the parasitic capacitance between the power supply line VCC ′ and other circuit nodes such as the ground potential of the circuit also increases. Since this parasitic capacitance acts in a direction to prevent potential change due to coupling from the bit line, it cannot be said to be an effective coupling capacitance enhancement measure. In this embodiment, therefore, the power supply line VCC 'is meandered so that the distance between the bit lines / BL and BL is equally reduced without increasing the wiring width. As a result, the parasitic capacitances C1 and C2 can be increased, and the parasitic capacitance between the power supply line VCC ′ and the circuit ground potential can be left as it is, so that the memory cell voltage VCC ′ corresponds to the change in the bit line potential due to the write operation. Can be effectively reduced.

  FIG. 15 shows a circuit diagram of an embodiment of a word driver used in the static RAM of FIG. 1 or FIG. In this embodiment, four word drivers corresponding to four word lines WL0 to WL3 are exemplarily shown as representatives. In this embodiment, when the high level is a logic 1 and a positive logic, a NOR gate circuit is used as a word driver. That is, a word driver corresponding to the word line WL0 will be described as an example. P-channel MOSFETs PA0 and PB0 are connected in series between the power supply voltage VDD and the output terminal (WL0), and the circuit ground potential VSS and the output are output. N-channel MOSFETs NA0 and NB0 are connected in parallel with the terminal (WL0). The gates of the P-channel MOSFET PA0 and the N-channel MOSFET NA0 are connected in common and the input signal PDA [0] is supplied. The gates of the P-channel MOSFET PB0 and the N-channel MOSFET NB0 are connected in common and the input signal PDB [0] is supplied. .

  The power supply voltage VCC is supplied to the source of the P-channel MOSFET PA0, and the drain of the P-channel MOSFET PB0 is connected to the output terminal. The word line WL0 is connected to this output terminal. Further, the ground potential VSS of the circuit is supplied to the sources of the N-channel MOSFETs NA0 and NB0, and the drains of the MOSFETs NA0 and NB0 are commonly connected to the output terminal.

  In this embodiment, although not particularly limited, for simplification of the circuit, the P-channel MOSFET PA0 is also commonly used for a word driver corresponding to the word line WL1. That is, in the word driver corresponding to the word line WL1, the P-channel MOSFETs PA0 and PB1 are connected in series, and the N-channel MOSFETs NA1 and NB1 are connected in parallel between the circuit ground potential VSS and the output terminal (WL1). Connected to. The gates of the P-channel MOSFET PA0 and the N-channel MOSFET NA1 are connected in common and the input signal PDA [0] is supplied. The gates of the P-channel MOSFET PB1 and the N-channel MOSFET NB1 are connected in common and the input signal PDB [1] is supplied. The

  In the remaining two word lines WL2 and WL3, a P-channel MOSFET PA2 whose source is connected to the power supply voltage VCC is used in common for the two word drivers. That is, in the word driver corresponding to the word line WL2, the P-channel MOSFETs PA2 and PB2 are connected in series between the power supply voltage VCC and the output terminal (WL2) as described above, and the circuit ground potential VSS and the output terminal ( WL2) and N-channel MOSFETs NA2 and NB2 are connected in parallel. The gates of the P-channel MOSFET PA2 and the N-channel MOSFET NA2 are connected in common and the input signal PDA [1] is supplied. The gates of the P-channel MOSFET PB2 and the N-channel MOSFET NB2 are connected in common and the input signal PDB [0] is supplied. .

  The P-channel MOSFET PA2 is also used in common for the word driver corresponding to the word line WL3. That is, in the word driver corresponding to the word line WL3, the P-channel MOSFETs PA2 and PB3 are connected in series between the power supply voltage VCC and the output terminal (WL3), and the circuit ground potential VSS and the output terminal (WL3) are connected. N-channel MOSFETs NA3 and NB3 are connected in parallel. The gates of the P-channel MOSFET PA2 and the N-channel MOSFET NA3 are commonly connected to supply the input signal PDA [1], and the gates of the P-channel MOSFET PB3 and the N-channel MOSFET NB3 are commonly connected to supply the input signal PDB [1]. The

  The input signals PDA [0] and [1] are complementary (exclusive) signals when active, and when one is at a high level, the other is at a low level. Similarly, the input signals PDB [0] and [1] are complementary (exclusive) signals when active, and when one is at a high level, the other is at a low level. Although not particularly limited, these input signal input signals PDA and PDB include a clock signal component and a standby signal component as described later in addition to the address signal.

  The input signal PDA is not particularly limited, but is on the upper bit side of the address signal, and the input signal PDB is on the lower bit side. Therefore, when the input signal PDA [0] is low level, the input signal PDA [1] is high level, the input signal PDB [0] is low level, and the input signal PDB [1] is high level, the input signal PDA [0] The P channel MOSFETs PA0 and PB0 are turned on in response to the low level of the input signal PDB [0] and the N channel MOSFETs NA0 and NB0 are turned off, and the word line WL0 is selected at a high level like the power supply voltage VCC. It is said. In the word drivers corresponding to the other word lines WL1 to WL3, at least one of the two P-channel MOSFETs is turned off by the high level of the input signal PDA [1], and at least one of the two N-channel MOSFETs. One of them is turned on, and a low level unselected state such as the ground potential VSS is set.

  In the standby state, the input signals PDA [0], [1] and the input signals PDB [0], [1] are all set to the high level. As a result, all P-channel MOSFETs are turned off, and all N-channel MOSFETs are turned on. In the P-channel MOSFET, when a leak current as described above flows, the potential at the connection point of the series MOSFET rises from VSS to VCC / 2, and the source potential rises in the P-channel MOSFETs PA1 and PA2 on the power supply voltage side. Thus, the leak current can be greatly reduced by the source bias effect that the reverse bias is applied to the substrate.

  As described above, when the word line WL0 is in the selected state, at least one of the P-channel MOSFETs PA0, PB0 or PA0 or PB0 of the corresponding word driver is turned off. In the word driver, the leakage current can be reduced by the source bias effect by vertically stacking P-channel MOSFETs, which is a feature of the NOR type logic gate circuit. In particular, when the input signals PDA [0] [1] and PDB [0] [1] are both in a standby state in which they are at a high level, the two P-channel MOSFETs are both turned off as described above. Leakage current can be greatly reduced. As in this embodiment, even if the P-channel MOSFETs PA0 and PA2 are supplied to two word drivers, the two word lines are not selected at the same time, so that the leakage reduction effect is enhanced while maintaining the driving force. Depending on the decoding logic, the number of shared word drivers can be increased by a power of 2, for example.

  A feature of this embodiment circuit is that a special control signal for reducing the leakage current is not required. When the clock signal component is included in the input signal PDA, that is, when the bit lines are precharged, it is necessary to deselect all the word lines. In all word line non-selected states during this precharge period, the leakage current due to the source bias effect as described above can be reduced. That is, not only the standby state but also the leakage current at the time of memory access can be reduced.

  That is, the power supply voltage of the LSI is lowered due to the low power consumption of the LSI (Large Scale Integrated circuit) and the miniaturization of the transistor (MOSFET) in the LSI. For example, in the 0.13 μm process, an LSI that operates with a power supply voltage of 1.2 V is manufactured. When the power supply voltage of the LSI is lowered, the transistor current is increased by lowering the threshold voltage (Vth) of the transistor in order not to lower the circuit performance (circuit operating speed), for example, 0.13 μm. In the process, a MOSFET having a Vth of about 0.4V is used. In a transistor having a low Vth, when a transistor called a subthreshold current is in an off state, a current flowing between the source and the drain increases. This current continues to flow even when a circuit constituted by the transistor is not operating, and becomes a current consumed when the LSI is energized but not operating (hereinafter referred to as a standby state). In a memory circuit that needs to store data even in the standby state, the power cannot be cut off even in the standby state. Therefore, when the Vth of the transistors constituting the circuit decreases, the subthreshold current increases and the power consumption during standby increases. The word driver can solve this problem.

  FIG. 16 shows an overall circuit diagram of an embodiment of a static RAM according to the present invention. The static RAM is composed of a memory cell array, an address selection circuit, a read circuit and a write circuit provided in its peripheral circuit, and a timing generation circuit for controlling the operation thereof.

  As a memory cell array, one word line WL, two pairs of complementary bit lines BL and / BL, and two memory cells provided at the intersection are representatively shown. Similarly to the above, the memory cell includes a latch circuit in which the inputs and outputs of two CMOS inverter circuits composed of P-channel MOSFETs Q1 and Q3 and N-channel MOSFETs Q2 and Q4 are cross-connected, and a pair of input / output nodes of the latch circuit. A selection switch including N-channel MOSFETs Q5 and Q6 is formed between the bit lines BL and / BL. The gates of these MOSFETs Q5 and Q6 are connected to the word line WL.

  Although not particularly limited, the memory cell array has 128 memory cells arranged on one word line WL. Therefore, the complementary bit lines BL and / BL are composed of 128 pairs. 256 memory cells are arranged on the pair of bit lines BL and / BL. Therefore, the word line WL is composed of 256 lines 0 to 255. Each bit line BL, / BL is provided with a precharge & equalize circuit PC / EQ. As in FIG. 1, the precharge circuit & equalize circuit PC / EQ includes a P-channel MOSFET that applies a precharge voltage such as a power supply voltage to the complementary bit lines BL and / BL, and the complementary bit lines BL and / BL. It is composed of P-channel MOSFETs that short-circuit each other. In this embodiment, a P-channel MOSFET in which a gate and a drain are cross-connected is provided as a pull-up MOSFET between the complementary bit lines BL and / BL and a power supply terminal. This prevents the bit line on the high level side from dropping during reading.

  Although not particularly limited, the 128 pairs of bit lines are connected to 32 pairs of complementary read data lines RD and / RD by a read column switch formed of a P-channel MOSFET. One read data line RD, / RD is connected to any one of four pairs of bit lines BL, / BL. A sense amplifier SA is provided on the read data lines RD, / RD. The sense amplifier SA includes a CMOS latch circuit in which the inputs and outputs of two CMOS inverter circuits each composed of a P-channel MOSFET and an N-channel MOSFET are cross-connected, the source of the N-channel MOSFET of this CMOS latch circuit, and the ground potential of the circuit It is comprised from N channel MOSFET provided in. Corresponding to the 32 pairs of read data lines RD and / RD being provided as described above, 32 sense amplifiers SA are also provided in total.

  The gate of the N-channel MOSFET for activating the sense amplifier SA and the gate circuit for transmitting the amplified signal of the sense amplifier SA are formed by a gate circuit for receiving the timing signal formed by the timing generation circuit and the sense amplifier selection signal sac. The timing control signal φsac thus transmitted is transmitted through the inverter circuit array. This timing control signal φsac is also used as a selection signal for the read column switch. The sense amplifier SA is activated by the selection signal and amplifies the signals on the read data lines RD and / RD.

  The amplified signal of the sense amplifier SA is transmitted to the latch circuit LT constituted by the MOSFETs Q17 to Q22, and the output signal dout is formed by the output circuit OB. Latch circuit LT is formed of a through latch circuit controlled by signal φolc formed based on output latch control signal olc. The output circuit OB includes a gate circuit controlled by a signal φodc formed based on the output driver control signal odc and an output inverter circuit.

  In this embodiment, although not particularly limited, a read operation in which all the 32 sense amplifiers SA are activated to output a read signal consisting of 32 bits, 16 of the 32 sense amplifiers SA are activated and 16 A read operation for outputting a read signal composed of bits or a read operation for activating eight of the 32 sense amplifiers SA and outputting a read signal composed of 8 bits is selectively made possible. The sense amplifier selection signal sac controls the sense amplifier SA and the like in response to the above three kinds of read operations, and the non-reading of the read column switch composed of a P-channel MOSFET by the read switch control signal rswc and the column selection signal sel. Used as a selection signal.

  The 128 pairs of bit lines are connected to 32 pairs of complementary write data lines WD and / WD by a write column switch (WCP) made of an N-channel MOSFET. One write data line WD, / WD is connected to any one of the four pairs of bit lines BL, / BL by the column switch. For the write data lines WD, / WD, an inverter circuit row (WDP1) for transmitting a write signal din to the write data line WD, an inverter circuit (WDP3) for forming an inverted write signal, and an inverted write signal for the write data line A write circuit (write amplifier) including an inverter circuit train (WDP2) for transmitting to / WD is provided. This write circuit is also composed of 32 pieces corresponding to the 32 pairs of complementary write data lines WD, / WD.

  The SRAM of this embodiment is not particularly limited, but a write operation that validates a 32-bit write signal formed by the 32 write amplifiers, and 16 of the 32 write amplifiers are formed by 16 units. Either a write operation for validating a read signal consisting of bits or a write operation for validating a write signal consisting of 8 bits formed by 8 of the 32 write amplifiers can be selectively made possible. The For this reason, the light switch control signal wswc is used. In this embodiment, the column selection signal is combined with the write switch control signal wswc and transmitted to the write column switch composed of an N-channel MOSFET.

  The amplified signal of the sense amplifier SA is transmitted to MOSFETs Q17 to Q22 and a latch circuit including an inverter circuit through a gate circuit, and an output signal dout is formed through the gate circuit and the output inverter circuit. The gate of the N-channel MOSFET for activating the sense amplifier SA and the gate circuit for transmitting the amplified signal of the sense amplifier SA are formed by a gate circuit for receiving the timing signal formed by the timing generation circuit and the sense amplifier selection signal sac. The timing control signal φsac thus transmitted is transmitted through an inverter circuit array constituting a control path. This timing control signal φsac is also used as a non-selection signal for the read column switch.

  The timing generation circuit receives a plurality of control signals such as a clock CLK and a read / write control signal R / W, and corresponds to an operation mode such as a read operation, a write operation, or a standby operation of the SRAM. Various timing signals necessary for the operation are generated.

  One of the 256 word lines WL is selected by the predecoder circuit and the word driver (NOR) as described above. The predecoder circuit receives the timing signal (clock, enable) and address signal add generated by the timing generation circuit, and forms a predecode signal for selecting the word line and a column selection signal. In the operation mode such as the standby operation, all the word lines are set to the non-selected level regardless of the address signal add. The column selection signal formed by the predecoder circuit is used to form the control signals sac, rswc, wswc, etc. corresponding to the 32-bit operation, 16-bit operation, and 8-bit operation by a logic circuit (not shown). .

  The invention made by the inventor has been specifically described based on the embodiments. However, the invention of the present application is not limited to the embodiments, and various modifications can be made without departing from the scope of the invention. Nor. For example, various embodiments can be adopted for the number of word lines and bit lines constituting an SRAM memory cell array mounted in a semiconductor integrated circuit device. The SRAM can be similarly applied to an SRAM as a general-purpose memory in addition to the SRAM embedded in the system LSI. The present invention can be widely used for semiconductor integrated circuit devices including the SRAM as described above.

  The present invention can be widely used for a semiconductor integrated circuit device having a static RAM (Random Access Memory).

QP1 to QP4... P channel MOSFET, QN1 to QN3... N channel MOSFET, INV1... Inverter circuit, R... Resistor, C1, C2 .. parasitic capacitance (coupling capacitance)
NA0 to NA3, N10, N11... N channel MOSFET, PA0, PA2, PB0 to PB3... P channel MOSFET, WL0 to WL3.
WDP1 to WDP3... Write data input path (write amplifier), WCP... Write system control path, LT... Latch circuit, OB. , BL, / BL ... bit lines, RD, / RD ... read data lines, WD, / WD ... write data lines.

Claims (1)

A plurality of first memory cells arranged in a first row along a first direction on a main surface of the semiconductor substrate ;
A plurality of second memory cells arranged in a second row along the first direction on the main surface of the semiconductor substrate;
A first bit line commonly connected to the plurality of first memory cells;
A second bit line commonly connected to the plurality of first memory cells;
A third bit line commonly connected to the plurality of second memory cells;
A fourth bit line commonly connected to the plurality of second memory cells;
A plurality of word lines respectively connected to the plurality of first memory cells and connected to the plurality of second memory cells, each extending along a second direction;
A first memory cell power line commonly connected to the plurality of first memory cells;
A second memory cell power line commonly connected to the plurality of second memory cells;
A power supply line for supplying power supply voltage, and
A first power supply circuit that electrically connects the first memory cell power supply line and the power supply line, and a first power supply circuit that electrically connects the first memory cell power supply line and the power supply line. Power supply circuit, including
Each of the plurality of first memory cells includes:
A first inverter including a first P-channel transistor and a first N-channel transistor;
A second inverter including a second P-channel transistor and a second N-channel transistor, the output of which is connected to the input of the first inverter and the input of which is connected to the output of the first inverter When,
A third N-channel transistor for electrically connecting the first bit line and the output of the first inverter;
A fourth N-channel transistor for electrically connecting the second bit line and the output of the second inverter;
The first P-channel transistor and the second P-channel transistor are provided in a first N well region,
The first N-channel transistor and the third N-channel transistor are provided in a first P well region,
The second N-channel transistor and the fourth N-channel transistor are provided in a second P well region,
The first P well region, the N well region, and the second direction in the second direction so that the first N well region is located between the first P well region and the second P well region. A second P-well region is disposed;
First and second connection portions are respectively joined to first and second portions of the memory cell power line that are opposite to the surface facing the semiconductor substrate, and the source of the first P-channel transistor is the The memory cell power line is electrically connected via a first connection portion, and the source of the second P-channel transistor is electrically connected to the memory cell power line via the second connection portion. And
The gates of the third N-channel transistor and the fourth N-channel transistor are electrically connected to a common first word line of the plurality of word lines,
Third and fourth connection portions are joined to the third and fourth portions of the common first word line, which are different from the surface facing the semiconductor substrate, respectively.
The gate of the third N-channel transistor is electrically connected to the common first word line via the third connection portion, and the gate of the fourth N-channel transistor is Electrically connected to the common first word line through the four connection portions;
An interval between the first portion and the second portion along the first direction is smaller than an interval between the third portion and the fourth portion along the second direction,
Each of the plurality of second memory cells includes:
A third inverter including a third P-channel transistor and a fifth N-channel transistor;
A fourth inverter including a fourth P-channel transistor and a sixth N-channel transistor, the output of which is connected to the input of the third inverter, and the input of which is connected to the output of the third inverter When,
A seventh N-channel transistor for electrically connecting the third bit line and the output of the third inverter;
An eighth N-channel transistor for electrically connecting the fourth bit line and the output of the fourth inverter;
The third P-channel transistor and the fourth P-channel transistor are provided in a second N well region,
The fifth N-channel transistor and the seventh N-channel transistor are provided in a third P well region,
The sixth N-channel transistor and the eighth N-channel transistor are provided in a fourth P-well region,
The third P well region and the second N well in the second direction so that the second N well region is located between the third P well region and the fourth P well region. A region and the fourth P-well region are disposed;
5th and 6th connection parts are joined to the 5th and 6th parts of the memory cell power line different from the surface facing the semiconductor substrate, respectively.
The source of the third P-channel transistor is electrically connected to the memory cell power line via the fifth connection portion, and the source of the fourth P-channel transistor is connected to the sixth connection portion. Electrically connected to the memory cell power line via
The gates of the seventh N-channel transistor and the eighth N-channel transistor are electrically connected to a common second word line of the plurality of word lines,
Seventh and eighth connection portions are bonded to the seventh and eighth portions of the common second word line, which are different from the surface facing the semiconductor substrate, respectively.
A gate of the seventh N-channel transistor is electrically connected to the common second word line via the seventh connection;
A gate of the eighth N-channel transistor is electrically connected to the common second word line via the eighth connection;
An interval between the fifth portion and the sixth portion along the first direction is smaller than an interval between the seventh portion and the eighth portion along the second direction,
The first power supply circuit lowers the voltage of the first memory cell power supply line in response to a signal for selecting the first column during writing,
The second power supply circuit lowers the voltage of the second memory cell power supply line in response to a signal for selecting the second column at the time of writing.
Semiconductor integrated circuit device.

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