JP2014138538A - Power conversion device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a power conversion device having a simple configuration, capable of highly accurately detecting, via an insulating circuit, a current flowing through each of a plurality of semiconductor switching elements provided in a power semiconductor module.SOLUTION: The power conversion device is provided with a power semiconductor module and a control circuit therefor insulated and separated from each other via an insulating circuit. The power semiconductor module is provided with: a sample hold circuit which holds a voltage corresponding to a current detected by a current detection circuit for detecting a current flowing through a semiconductor switching element, for a fixed period of time and transmits the held voltage to the control circuit via the insulating circuit; and a sample signal generation circuit which generates a sample signal for driving the sample hold circuit on the basis of a gate driving signal transmitted from the control circuit via the insulating circuit.

Description

  The present invention relates to a power conversion device in which a power semiconductor module including a plurality of semiconductor switching elements and a control circuit for switching and driving each of the plurality of semiconductor switching elements are insulated and separated.

  BACKGROUND ART A power conversion device that includes a semiconductor switching element such as an IGBT that is driven for switching and constitutes an inverter device, a chopper circuit, or the like is widely used for various applications. FIG. 7 is a schematic configuration diagram of an inverter device (power converter) that drives a three-phase AC motor (load) M. This inverter device associates the power semiconductor module 10 packaged with a plurality (six) semiconductor switching elements (for example, IGBTs) Q1, Q2 to Q6 and the semiconductor switching elements Q1, Q2 to Q6. And a control circuit 20 that is turned on / off.

  The semiconductor switching elements Q1, Q2 to Q6 are connected in series in pairs of two to form three half bridge circuits HB. A plurality (six) of freewheeling diodes D1, D2 to D6 are connected in antiparallel to each of the semiconductor switching elements Q1, Q2 to Q6. These three half-bridge circuits HB are provided in parallel to constitute a drive circuit for the load M.

  Each of the half bridge circuits HB includes a series connection point of the semiconductor switching elements Q1 and Q4, a series connection point of the semiconductor switching elements Q2 and Q5, and a series connection point of the semiconductor switching elements Q3 and Q6 that constitute the half bridge circuit HB. , Three-phase (U-phase, V-phase, W-phase) currents having phases different by 120 ° are supplied to the load M. Accordingly, the three half-bridge circuits HB form a three-phase full-bridge circuit that drives the load M.

  On the other hand, the control circuit 20 includes an arithmetic unit 21 such as a CPU, for example, and generates a control signal for controlling on / off of the semiconductor switching elements Q1, Q2 to Q6 according to the output current of each half bridge circuit HB. The unit 22 is provided. The control circuit 20 also includes gate drive signals Vg1, for driving the semiconductor switching elements Q1, Q2-Q6 on and off in accordance with the control signals generated by the control unit 22 accompanying the control circuit 20. A drive circuit 23 for outputting Vg2 to Vg6 is provided.

  The information on the output current of each of the semiconductor switching elements Q1, Q2 to Q6 required for the control operation by the control unit 22 uses, for example, current detection terminals provided in the semiconductor switching element Q and the freewheeling diode D. Thus, the current flowing through the semiconductor switching element Q and / or the freewheeling diode D is detected (see, for example, Patent Documents 1 and 2).

  Specifically, the current flowing through each of the semiconductor switching elements Q is detected using, for example, current detection circuits 11a, 11b, and 11c connected to current detection terminals (auxiliary emitters) included in each semiconductor switching element Q, for example. The current detected using these current detection circuits 11a, 11b, and 11c becomes a pulse-like discrete sinusoidal current waveform synchronized with the switching operation cycle of the semiconductor switching element Q.

JP 2000-134855 A JP 2003-274667 A

  By the way, in the inverter device (power conversion device) described above, from the viewpoint of safety, for example, the power semiconductor module 10 to which a large current / high voltage is applied and the control circuit 20 may be electrically insulated. Required. For this electrical insulation, for example, as shown in FIG. 7, an insulation circuit 25 (25a, 25b, 25c) is provided between the current detection circuit 11 (11a, 11b, 11c) and the arithmetic unit 21. This is realized by providing an insulating circuit 26 between the control unit 22 and the drive circuit 23. These insulation circuits 25 and 26 are composed of, for example, an insulation amplifier that modulates a voltage signal and applies it to the primary side of the transformer and demodulates a signal output from the secondary side of the transformer to restore the voltage signal.

  Here, the insulation circuit 26 provided on the driving side of the semiconductor switching elements Q1, Q2 to Q6 only transmits an on / off control signal (digital signal) to each of the semiconductor switching elements Q1, Q2 to Q6. On the other hand, the insulation circuit 25 provided in the feedback system needs to transmit the output voltage (analog signal) of the current detection circuit 11 having the discrete sine wave current waveform described above. Therefore, the signal transmission through the insulating circuit 25 has the following problems.

  That is, the output voltage of the current detection circuit 11 corresponds to a current that flows intermittently through the semiconductor switching element Q in synchronization with the switching of the semiconductor switching element Q, and the peak value (voltage) changes. It consists of a pulsed waveform. When the output voltage of the current detection circuit 11 is transmitted through the insulation circuit 25, the output voltage is greatly distorted at the rising edge due to the response characteristic (response delay time) of the insulation circuit 25. I can't deny it.

  Specifically, the switching period of the semiconductor switching element Q is 100 μsec, and the duty ratio command value that defines the ON width of the semiconductor switching element Q of the lower arm in the half bridge circuit HB is 10% (10 μsec) Suppose that In this case, for example, the output voltage of the insulating circuit 25 having a response delay time of 10 μs is substantially triangular. Then, the output voltage of the insulating circuit 25 is reduced to about ½ of the input voltage of the insulating circuit 25 on an average for one cycle. In addition, when the duty ratio command value is further reduced, the error in the input / output voltage of the insulation circuit 25 becomes larger due to the influence of the response delay time of the insulation circuit 25.

  The control circuit is configured to detect equivalently a current flowing through the upper arm semiconductor switching element Q from a freewheeling diode D connected in parallel to the lower arm semiconductor switching element Q constituting the half bridge circuit HB. The same problem occurs when transmitting to the 20 side. Therefore, the signal transmitted through the insulation circuit 25 includes a large error that is significantly different from the output voltage of the current detection circuit 11. Then, in the control circuit 20, there arises a problem that switching control of each of the semiconductor switching elements Q1, Q2 to Q6 cannot be performed with high accuracy according to the current detected as described above.

  The present invention has been made in view of such circumstances, and its purpose is to accurately transmit detection information of a current flowing through a semiconductor switching element in a power semiconductor module to a control circuit via an insulating circuit, thereby An object of the present invention is to provide a power converter having a simple configuration capable of stably and accurately controlling the semiconductor switching element.

  The present invention relates to a pair of semiconductor switching elements (for example, IGBTs) connected in series to form a half-bridge circuit and driven to be turned on / off in relation to each other, and the semiconductor switching elements are anti-parallel to each other. A power semiconductor module having a plurality of freewheeling diodes provided, and a gate drive signal provided to be isolated from the power semiconductor module via an insulation circuit and driving each semiconductor switching element on and off. The present invention relates to a power conversion device including a control circuit to be generated.

  In particular, the power conversion device according to the present invention holds the voltage corresponding to the current detected by the current detection circuit that detects the current flowing through the half-bridge circuit for a certain period in the power semiconductor module in order to achieve the above-described object. A sample-and-hold circuit that transmits the held voltage to the control circuit via the isolation circuit; and further, the sample-and-hold circuit based on the gate drive signal transmitted from the control circuit via the isolation circuit. A sample signal generation circuit for generating a sample signal to be driven is provided.

  Incidentally, the current detection circuit includes, for example, first and second current detectors for detecting a current flowing through the semiconductor switching element and a current flowing through the freewheeling diode, and the first and second currents. And an adder for adding the outputs of the detection circuit. The sample hold circuit is configured to sample the output signal of the current detection circuit in synchronization with the switching period of the semiconductor switching element and hold it until the next sampling timing.

  Preferably, the sample signal generation circuit includes, for example, a pulse width measurement circuit that shapes a waveform of the gate drive signal transmitted from the control circuit via the isolation circuit and detects a pulse width of the gate drive signal, and a waveform A pulse generation circuit that generates the sample signal at a timing when ½ of the pulse width detected by the pulse width measuring unit from the gate drive signal of the previous cycle has elapsed with reference to the rising timing of the shaped gate drive signal And is configured.

  In addition, the power semiconductor module includes, for example, six semiconductor switching elements constituting six pairs of half-bridge circuits corresponding to each phase of a three-phase AC power supply, and six freewheeling diodes. An inverter device is formed. In this case, the control circuit is configured to control the pulse width of the gate drive signal so that the current output from the half-bridge circuit is a sine wave.

Alternatively, the power semiconductor module includes one or two pairs of semiconductor switching elements constituting one or two pairs of half-bridge circuits, and the freewheeling diodes connected in antiparallel to the semiconductor switching elements, respectively. With each
A converter device for controlling a current flowing through the inductance to obtain a predetermined voltage in the output circuit in cooperation with an output circuit connected to an output terminal of the one or two sets of half-bridge circuits via an inductance. It consists of what was formed.

  According to the power conversion device having the above configuration, the output voltage of the current detection circuit that detects a pulse-like discrete sine wave current flowing in the semiconductor switching element is synchronized with the switching operation cycle of the semiconductor switching element. Hold in the sample hold circuit. Then, the voltage held in the sample and hold circuit is transmitted to the control circuit via the insulating circuit. Therefore, the voltage transmitted through the insulating circuit is not distorted due to the response characteristic (response delay time) of the insulating circuit, and the control circuit accurately obtains information on the current flowing through the semiconductor switching element. Can be acquired.

  Further, since the sample signal for driving the sample hold circuit is generated based on the gate drive signal transmitted from the control circuit via the isolation circuit, the current detection circuit of the current detection circuit is synchronized with the operation cycle of the switching element. The output voltage can be simplified and sampled accurately, and this can be held for one operation cycle of the switching element. Therefore, the detection accuracy in the control circuit of the current flowing through the semiconductor switching element can be sufficiently increased, and the control accuracy for the semiconductor switching element can be increased.

  In addition, as described above, since the sample signal is generated based on the gate drive signal transmitted from the control circuit via the isolation circuit, for example, a carrier clock signal used for generation of the gate drive signal is separately supplied from the isolation circuit. No need to communicate through. Therefore, the power semiconductor module side and the control circuit side can be simplified and effectively insulated and separated. Therefore, the power semiconductor module and the control circuit can be easily mounted on a printed circuit board, and restrictions on mounting such as component placement on the printed circuit board can be eased to make the entire power converter compact. An effect such as being able to be achieved is exhibited.

The principal part schematic block diagram of the power converter device which concerns on one Embodiment of this invention. The figure which shows the structural example of the current detection circuit in the power converter device shown in FIG. The figure which shows the structural example of the sample hold circuit in the power converter device shown in FIG. The figure which shows the structural example of the sample signal generation circuit in the power converter device shown in FIG. FIG. 6 is a signal waveform diagram showing sample signal generation and current detection operation. The principal part schematic block diagram of the power converter device which concerns on another embodiment of this invention. The schematic block diagram of the conventional power converter device which insulated and separated the power semiconductor module and its control circuit.

  Hereinafter, a power converter according to an embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 is a schematic configuration diagram of a main part of a power conversion device according to an embodiment of the present invention. This power conversion device (inverter device) is generally an insulating circuit between a power semiconductor module 10 and its control circuit 20. 25 and 26 are used for insulation isolation. The same parts as those in the conventional apparatus shown in FIG. 7 are denoted by the same reference numerals.

  The power converter according to this embodiment is characterized by a sample hold (SH) that holds the output voltage of each of the current detection circuits 11 (11a, 11b, 11c) in synchronization with the switching cycle of the semiconductor switching element Q. ) Circuits 14 (14a, 14b, 14c) are provided, respectively. The output voltage held in each of the sample and hold circuits 14 (14a, 14b, 14c) is transmitted to the control circuit 20 through each of the insulating circuits 25 (25a, 25b, 25c). It is in.

  A sample signal generation circuit 15 for generating a sample signal SH for driving each of the sample hold circuits 14 (14a, 14b, 14c) is output from the drive circuit 23 and the switching elements Q1, Q2-Q6 are turned on. It is characterized in that it is generated based on gate drive signals Vg1, Vg2 to Vg6 for driving off. Specifically, the sample signal generation circuit 15 is provided so as to generate the sample signal SH based on the gate drive signal Vg6 of the lower arm in the half bridge circuit HB, for example, for the semiconductor switching element Q6. The sample signal SH may be generated based on the gate drive signal Vg for the semiconductor switching element Q of the upper arm in the half bridge circuit HB. In this case, the level of the gate drive signal Vg may be converted. is necessary.

  The sample signal generation circuit 15 roughly includes a gate signal detection circuit 15a for detecting the gate drive signal Vg6, and a pulse width of the gate drive signal Vg6 detected by the gate signal detection circuit 15a (ON of the semiconductor switching element Q6). And a pulse width measuring circuit 15b for detecting the width Ton). Further, the sample signal generation circuit 15 obtains a pulse width calculation circuit 15c that calculates a pulse width (Ton / 2) that is ½ of the pulse width detected by the pulse width measurement circuit 15b, and the pulse width calculation circuit 15c calculates the pulse width calculation circuit 15c. A pulse generation circuit 15d for generating the sample signal SH at a timing delayed from the rising edge of the gate drive signal Vg6 by a pulse width.

  The sample signal generation circuit 15 configured in this way is synchronized with a carrier clock signal Fc used by the control circuit 20 to generate the gate drive signals Vg1, Vg2 to Vg6, as will be described later. Plays the role of generating SH. Incidentally, the carrier clock signal Fc is a pulse signal having a duty ratio of 50% that defines the switching frequency fc of the semiconductor switching element Q (Q1, Q2 to Q6).

  Here, the control circuit 20 will be briefly described. The control circuit 20 generates a triangular wave in synchronization with the rising and falling timings of the pulse signal (carrier clock signal Fc), and the triangular wave and the power semiconductor module 10 side. The feedback signal fed back from is compared. The feedback signal is detected by the current detection circuit 11 (11a, 11b, 11c), and the current flowing through the switching element Q (Q1, Q2-Q6) obtained through the insulation circuits 25a, 25b, 25c, respectively. It consists of information.

  For example, the control circuit 20 obtains a period in which the level of the triangular wave exceeds the level of the feedback signal as an on period of each of the semiconductor switching elements Q (Q1, Q2 to Q6), and is defined by the carrier clock signal Fc. The on / off control signal for switching control (on / off control) of each of the semiconductor switching elements Q (Q1, Q2 to Q6) is generated under the switching frequency fc. The on / off control signal is transmitted to the driving circuit 23 through the insulating circuit 26, and the gate driving signals Vg1, Vg2 to Vg6 are generated.

  On the other hand, each of the current detection circuits 11 (11a, 11b, 11c) includes, for example, an inverting amplifier provided with a feedback resistor Rf between the output terminal and the inverting input terminal of the operational amplifier OP as shown in FIG. The current detection circuit 11 inputs the current Is output from the current detection terminal (auxiliary emitter) of the semiconductor switching element Q to the operational amplifier OP and corresponds to the input current Is as an output of the operational amplifier OP. The output voltage Vs is configured to be obtained. The current Is output from the current detection terminal is proportional to the main current Im flowing through the semiconductor switching element Q, and is generally set to about one thousandth of the main current Im. There is no need to explain that now.

  The sample hold circuit 14 (14a, 14b, 14c) includes, for example, an input buffer constituted by an operational amplifier OP1 and an output buffer constituted by an operational amplifier OP2 as shown in FIG. Then, the output voltage of the input buffer (operational amplifier OP1) is sampled through the switch element SW and held in the capacitor C, and the voltage held in the capacitor C is applied to the output buffer (operational amplifier OP2). The

  Specifically, the sample signal generation circuit 15 includes a level converter 15e that performs level conversion and waveform shaping on the gate drive signal Vg6 as shown in FIG. Incidentally, the on / off control signal transmitted from the control circuit 20 through the insulation circuit 26 is a binary voltage signal of [+ 15V / −7V] whose rise and fall are gently set for the purpose of noise reduction. is there. The level converter 15e converts such an on / off control signal into a positive binary signal composed of, for example, [+ 5V / 0V] that is easy to process, and shapes the waveform to shape the gate drive signal Vg6. Play a role in restoring.

  The gate drive signal Vg6 restored in this way is input to the comparator (gate signal detection circuit) 15a and compared with the reference voltage Vref. The comparator 15a enables the up counter (pulse width measuring circuit) 15b over a period from when the rising edge of the gate driving signal Vg6 is detected to when the falling edge of the gate driving signal Vg6 is detected. As a result, the up counter 15b counts (up counts) the high-speed clock CK over the enable period, and measures the pulse width of the gate drive signal Vg6 (on width Ton of the semiconductor switching element Q) as the count value. To do.

  When the comparator 15a detects the falling edge of the gate drive signal Vg6, the comparator 15a triggers a latch circuit (pulse width calculation circuit) 15c via the inverter circuit 15f to latch the count value by the counter 15b. At the same time, the output of the inverter circuit 15f is given to the up counter (pulse width measuring circuit) 15b via the delay circuit 15g, and the counter 15b is reset.

  Here, the latch circuit (pulse width arithmetic circuit) 15c excludes and outputs the minimum bit of the binary n-bit count value by the counter 15b latched as described above, in other words, the latch data (count value). ) Is shifted by 1 bit to the right to obtain a control value (Ton / 2) corresponding to ½ of the pulse width of the gate drive signal Vg6. This control value is preset in the down counter 15h and used for controlling the generation timing of the sample signal SH.

  The down counter 15h is enabled when the comparator 15a detects the rising edge of the gate drive signal Vg6, and counts down the preset control value according to the high-speed clock CK as described above. However, the control value counted down by the down counter 15h is obtained as described above from the pulse width of the gate drive signal Vg6 one switching period before. When the count value of the down counter 15h reaches [0], the down counter 15h energizes the one-shot circuit (pulse generation circuit) 15d with its output. As a result, the one-shot circuit 15d generates the sample signal SH having a predetermined pulse width, and the sample hold circuit 14 (14a, 14b, 14c) is collectively driven by the sample signal SH.

  The presetting of the control value to the down counter 15h is performed prior to the rise of the gate drive signal Vg6 detected next by using the sample signal SH whose timing is adjusted via the delay circuit 15i. The high-speed clock CK has a sufficiently high frequency compared with the input period (switching frequency fc) of the gate drive signal Vg6, which can measure the pulse width of the gate drive signal Vg6 with a predetermined accuracy. It goes without saying that things are used.

  According to the sample hold circuit 14 (14a, 14b, 14c) driven by such a sample signal SH, the output voltage of each of the current detection circuits 11 (11a, 11b, 11c) is as shown in FIG. It is sampled and held in synchronization with the switching period of the semiconductor switching element Q. Specifically, the sample hold circuit 14 samples the output voltage of the current detection circuit 11 at the middle timing (Ton / 2) in each ON period of the semiconductor switching element Q. The sample hold circuit 14 holds the output voltage sampled as described above over a period (one switching cycle) from when the next gate drive signal Vg is detected until a new sample signal SH is generated. As a result, the average value of the output voltage of the current detection circuit 11 that is detected in a pulse manner every ON period of the semiconductor switching element Q and changes in voltage during the ON period of the semiconductor switching element Q is the sample hold circuit 14. It is obtained as an output voltage that changes stepwise.

  That is, the gate drive signal Vg is shown in FIG. 5 by comparing the carrier clock signal Fc composed of the above-described triangular wave and the feedback signal in switching control of each of the semiconductor switching elements Q1, Q2 to Q6. Thus, the signal is generated as a signal whose pulse width is controlled around the peak (mountain) of the carrier clock signal Fc. The comparator 15a detects the rising and falling edges of the gate drive signal Vg and enables the up counter 15b. As a result, the up counter 15b measures the pulse width Ton of the gate drive signal Vg by counting the high-speed clock CK over the rising and falling timings of the gate drive signal Vg.

  The pulse width Ton thus measured is latched in the latch circuit 15c, and a control value that is 1/2 of the pulse width Ton is preset in the down counter 15h. The down counter 15h starts down-counting of the control value at the next input timing of the gate drive signal Vg, and activates the one-shot circuit 15d when the value becomes [0]. The one-shot circuit 15d generates the sample signal SH that drives the sample-and-hold circuit 14. As a result, the sample signal SH is generated in synchronization with the switching period.

  Incidentally, the timing at which the sample hold circuit 14 samples the output voltage of the current detection circuit 11 is based on the pulse width of the gate drive signal Vg when the switching element Q is turned on one cycle before. Therefore, strictly speaking, the sample timing is not obtained on the basis of the time width (Ton) during which the switching element Q is turned on in the current period. For this reason, it cannot be denied that there is a slight difference between the half of the period when the switching element Q is turned on and the sampling timing by the sample and hold circuit 14. Specifically, the sampling timing is shifted by 1/2 of the change of the ON width Ton of the switching element Q.

  However, in the inverter control of the power semiconductor module 10 by the control circuit 20, the pulsed current output from the half-bridge circuit HB in a steady state has a discrete sinusoidal current waveform that smoothly changes. The pulse width of the gate drive signal Vg is gradually changed. Therefore, even if there is an error in the sample signal SH whose timing is controlled as described above due to a shift of one period of the gate drive signal Vg, the error is almost negligible.

  Therefore, the sample-and-hold circuit 14 substantially determines the current flowing through the switching element Q at approximately half the timing during the ON period of the switching element Q, that is, the average value of the current flowing during the ON period of the switching element Q. Sampling is possible. The sample hold circuit 14 holds the sampled output voltage of the current detection circuit 11 (average value of the current flowing during the ON period of the switching element Q) over one cycle of the carrier clock signal Fc. Become.

  Note that if the pulse width of the sample signal SH is shortened to shorten the ON time Δta of the switch element SW in each sample and hold circuit 14, the capacitor C cannot be sufficiently charged, and the current detection circuit 11 The output voltage cannot be reliably held. Conversely, if the pulse width of the sample signal SH is increased to increase the ON time Δta of the switch element SW, an error with respect to the average value of the output voltage of the current detection circuit 11 during the carrier period increases. Therefore, for example, when the carrier cycle is 100 μs, the ON time Δta of the switch element SW is set to about 1 μs, and the capacitance of the capacitor C is set to about 1 nF so that the sampling error does not increase. It is preferable to devise. However, it goes without saying that these values may be set according to specifications such as current detection conditions and allowable detection errors.

  Here, when the insulation circuit 25 (25a, 25b, 25c) having excellent input / output characteristics for accurately transmitting the input voltage is used, it cannot be denied that the response delay time is generally long. For example, it is assumed that the insulating circuit 25 (25a, 25b, 25c) whose rise time from zero voltage (0V) to the maximum voltage is 10 μsec is used. It is assumed that the frequency of the output current of the half-bridge circuit HB is 100 Hz, the amplitude thereof is a sine wave of the maximum allowable current, and this is subjected to switching control with a carrier frequency of 10 kHz.

  Then, switching is performed 25 times until the output current of the half-bridge circuit HB reaches the maximum value from zero (1/4 cycle). Therefore, the amount of voltage change in one carrier cycle is [1/25] of the maximum output voltage range. Therefore, in this case, by simple calculation, the insulating circuit 25 (25a, 25b, 25c) follows the input voltage waveform in 400 nanoseconds to obtain its output voltage. Therefore, the insulation circuit 25 (25a, 25b, 25c) can accurately transmit the output voltage of the current detection circuit 11 (11a, 11b, 11c) with sufficient margin.

  On the other hand, the arithmetic unit 21 calculates the currents flowing through the semiconductor switching element Q and the freewheeling diode D by the arithmetic unit 21b based on the information acquired from the sample and hold circuit 14 through the insulating circuit 25. Then, a signal (feedback signal) necessary for switching control of each of the semiconductor switching elements Q (Q1, Q2 to Q6) is generated according to the calculation result. For example, the PWM modulator 21c is turned on / off by pulse width modulation for driving the semiconductor switching elements Q (Q1, Q2 to Q6) on / off according to the signal (feedback signal) obtained by the arithmetic unit 21b. Each control signal is generated. The on / off control signal generated in this way is transmitted to the drive circuit 23 via the insulating circuit 26 as described above. The gate drive signals Vg1, Vg2 to Vg6 are generated based on the on / off control signal, and the semiconductor switching elements Q (Q1, Q2 to Q6) are driven to be switched at timings related to each other.

  As described above, in the power conversion device according to the present invention, the output voltage of the current detection circuit 11 (11a, 11b, 11c) is synchronized with the switching period of the semiconductor switching element Q in the sample hold circuit 14 (14a, 14b, 14c) is used to hold the sample, and the output voltage of the sample hold circuit 14 (14a, 14b, 14c) is transmitted via the insulating circuit 25 (25a, 25b, 25c). As a result, the information indicated by the output voltage of the current detection circuit 11 (11a, 11b, 11c) is not affected by the response delay time of the insulating circuit 25 (25a, 25b, 25c). Can be accurately transmitted.

  In this power converter, the sample signal for controlling the operation of the sample hold circuit 14 (14a, 14b, 14c) from the gate drive signal Vg transmitted from the control circuit 20 side through the insulating circuit 26. SH is generated. In addition, the pulse width of the gate drive signal Vg is measured, and the sample signal SH is generated at a timing delayed from the rising timing of the gate drive signal Vg by a time ½ of the measured pulse width. Therefore, the sample signal SH can be obtained in synchronism with the carrier clock signal without having to transmit the carrier clock signal from the control circuit 20 side to the power semiconductor module 10 side through an insulating circuit. In addition, the sample signal SH can be obtained at approximately half the timing during the ON period of the switching element Q.

  Therefore, according to the power conversion device having the above configuration, even when the power semiconductor module 10 side and the control circuit 20 side are insulated and separated through the insulation circuit 25 (25a, 25b, 25c), the current The change in the voltage signal detected by the detection circuit 11 (11a, 11b, 11c) and transmitted through the insulating circuit 25 (25a, 25b, 25c) can be reduced. Accordingly, errors themselves caused by the transfer characteristics of the insulating circuits 25 (25a, 25b, 25c) can be reduced, and the semiconductor switching elements Q (Q1) can be reduced according to the output current of the half-bridge circuits HB. , Q2 to Q6) can be switched at appropriate timings. Therefore, it is possible to realize highly accurate switching control.

  Further, as described above, the sample signal SH is generated from the gate drive signal Vg transmitted to the power semiconductor module 10 via the insulation circuit 26, so that an insulation circuit for transmitting the carrier clock signal Fc is not necessary. is there. Therefore, it is possible to simplify the overall circuit configuration by the amount that can reduce the number of signals (information) transmitted through the insulating circuit, that is, the amount that the carrier clock signal Fc need not be transmitted. Further, since the semiconductor module 10 side and the control circuit 20 side can be simplified and effectively insulated and separated, the power semiconductor module 10 and the control circuit 20 can be easily mounted on a printed circuit board. Can be planned. Furthermore, it is possible to relax restrictions on mounting such as component placement on the printed circuit board, thereby achieving an effect that the entire power conversion device can be made compact.

  FIG. 6 shows a schematic configuration of a main part of a power conversion device according to another embodiment of the present invention. In addition to detecting the current flowing through the semiconductor switching elements Q4, Q5, and Q6 constituting the lower arm using the current detection circuits 11a, 11b, and 11c, the power conversion device includes current detection circuits 12a and 12b. , 12c are used to detect the currents flowing in the freewheeling diodes D4, D5, D6 connected in antiparallel to the semiconductor switching elements Q4, Q5, Q6, respectively. The currents flowing through these freewheeling diodes D4, D5, D6 correspond to the currents flowing through the semiconductor switching elements Q1, Q2, Q3 constituting the upper arm. Therefore, the current detection circuits 12a, 12b, and 12c play a role of equivalently detecting the currents flowing through the semiconductor switching elements Q1, Q2, and Q3 from the currents flowing through the freewheeling diodes D4, D5, and D6.

  The currents flowing through the freewheeling diodes D4, D5, D6 (semiconductor switching elements Q1, Q2, Q3) are 180 degrees out of phase with the currents flowing through the semiconductor switching elements Q4, Q5, Q6. In addition, current flows alternately in the upper and lower arms of the half bridge circuit HB every half cycle. Therefore, the current detection circuits 11a, 11b, and 11c and the current detection circuits 12a, 12b, and 12c detect the current alternately every half cycle. Accordingly, the adders 13a, 13b, 13c for adding the output voltages of the current detection circuits 11a, 11b, 11c and the output voltages of the current detection circuits 12a, 12b, 12c In this case, they are combined and output over one period.

  In this embodiment, as described above, the output voltages of the adders 13a, 13b and 13c obtained from the currents flowing through the half-bridge circuits HB over one period are sampled by the sample and hold circuits 14a, 14b and 14c. Hold this. The voltage held in the sample and hold circuits 14a, 14b, and 14c is transmitted to the control circuit 20 side via the insulating circuits 25a, 25b, and 25c.

  Here, the voltage adjustment circuits 16a, 16b and 16c provided in the previous stage of the AD converter 21a receive the voltage signals transmitted from the sample and hold circuits 14a, 14b and 14c through the insulation circuits 25a, 25b and 25c. , And plays the role of adjusting the voltage according to the dynamic range of the AD converter 21a. At the same time, the voltage adjustment circuits 16a, 16b, and 16c also play a role of correcting the voltage signal by gain adjustment and offset adjustment.

  That is, the sense currents Is detected through the current detection terminals of the semiconductor switching element Q and the freewheeling diode D described above ideally flow through the semiconductor switching element Q and the freewheeling diode D, respectively. The current ratio is proportional to the main current, and the current ratio is determined according to the area ratio between the main region and the sense region of the element. However, it cannot be denied that an error occurs in the current ratio due to the device structure and layout of each element. The voltage adjusting circuits 16a, 16b, and 16c correct the voltage signal by the above-described gain adjustment and offset adjustment for such an error, thereby causing the semiconductor switching element Q and the freewheeling diode D to be corrected. Increase the detection accuracy of each flowing current.

  As a result, in the arithmetic unit 21, the half formed by the semiconductor switching element Q and the freewheeling diode D from the current flowing in a pulsed manner through the semiconductor switching element Q and the freewheeling diode D. Current information corresponding to the current output from the bridge circuit HB can be obtained with high accuracy as a feedback signal. A control signal for switching control of the semiconductor switching element Q can be accurately generated.

  The present invention is not limited to the embodiment described above. Here, the power semiconductor module 10 including six semiconductor switching elements Q1, Q2 to Q6 and configuring three sets of half-bridge circuits has been described as an example, but the power semiconductor module 10 including two sets of half-bridge circuits is described as an example. The same applies to the same. Needless to say, the present invention can be similarly applied to the semiconductor module 10 constituting one set of half-bridge circuits.

  Of course, instead of detecting the sense current Is of the freewheeling diode D, it is possible to detect each sense current Is of the pair of switching elements Q constituting the half-bridge circuit. It is of course possible to generate the sample signal SH from the gate drive signals Vg4, Vg5 instead of the gate drive signal Vg6 or from the gate drive signals Vg1, Vg2, Vg3.

  Further, the specific configurations of the insulating circuits 25a, 25b, and 25c can be appropriately adopted as long as they satisfy the specifications of the power conversion device in consideration of the linearity and delay response characteristics of the transfer characteristics. . It is sufficient to realize the sample hold circuits 14a, 14b, and 14c as having characteristics satisfying the specifications of the power converter. Further, it goes without saying that the present invention can be similarly applied to various types of converter devices other than the above-described three-phase AC inverter devices, that is, various types of power converter devices that have been proposed in the past. In addition, the present invention can be variously modified and implemented without departing from the scope of the invention.

DESCRIPTION OF SYMBOLS 10 Semiconductor module 11 (11a, 11b, 11c) Current detection circuit 12 (12a, 12b, 12c) Current detection circuit 13 (13a, 13b, 13c) Adder 14 (14a, 14b, 14c) Sample hold (SH) circuit 15 Sample signal generation circuit 15a Gate signal detection circuit (comparator)
15b Pulse width measurement circuit (up counter)
15c Pulse width arithmetic circuit (latch circuit)
15d Pulse generation circuit (1 shot circuit)
15e level conversion circuit 15h down counter 16 (16a, 16b, 16c) voltage adjustment circuit 20 control circuit 21 arithmetic unit 21a AD converter 21b arithmetic unit 21c PWM modulator 22 control unit 23 drive circuit 25 (25a, 25b, 25c) insulation Circuit 26 Insulation circuit

Claims (7)

A pair or a plurality of pairs of semiconductor switching elements connected in series to form a half-bridge circuit and driven to be turned on / off in relation to each other, and a plurality of freewheeling provided in antiparallel to each of the semiconductor switching elements A power semiconductor module with a diode;
A power conversion device including a control circuit that is provided so as to be isolated from the power semiconductor module via an insulation circuit and generates a gate drive signal for driving each semiconductor switching element on and off,
The power semiconductor module includes a current detection circuit that detects a current flowing through the half-bridge circuit;
A sample and hold circuit that holds a voltage corresponding to the current detected by the current detection circuit for a certain period, and transmits the held voltage to the control circuit via the insulation circuit;
A power conversion apparatus comprising: a sample signal generation circuit that generates a sample signal for driving the sample hold circuit based on the gate drive signal transmitted from the control circuit via the isolation circuit.   The current detection circuit includes first and second current detectors for detecting a current flowing through the semiconductor switching element and a current flowing through the freewheeling diode, and the first and second current detection circuits. The power conversion device according to claim 1, further comprising an adder that adds the outputs.   2. The power conversion device according to claim 1, wherein the sample and hold circuit samples the output signal of the current detection circuit in synchronization with a switching period of the semiconductor switching element and holds it until the next sampling timing.   The sample signal generating circuit includes: a pulse width measuring circuit that shapes a waveform of the gate drive signal transmitted from the control circuit via the isolation circuit and detects a pulse width of the gate drive signal; and the gate that has been waveform shaped And a pulse generation circuit that generates the sample signal at a timing when a half of a pulse width detected from the gate drive signal of the previous cycle by the pulse width measuring unit has elapsed with reference to a rising timing of the drive signal. Item 4. The power conversion device according to Item 1.   The power semiconductor module includes six semiconductor switching elements constituting six pairs of half-bridge circuits corresponding to each phase of a three-phase AC power source, and six freewheeling diodes, and an inverter for a three-phase AC load The power conversion device according to claim 1, wherein the device is formed.   The power converter according to claim 5, wherein the control circuit controls a pulse width of the gate drive signal so that a current output from the half-bridge circuit becomes a sine wave. The power semiconductor module includes one or two pairs of semiconductor switching elements constituting one or two pairs of half-bridge circuits, and the freewheeling diodes connected in antiparallel to the semiconductor switching elements, respectively. Prepared,
A converter device for controlling a current flowing through the inductance to obtain a predetermined voltage in the output circuit in cooperation with an output circuit connected to an output terminal of the one or two sets of half-bridge circuits via an inductance. The power conversion device according to claim 1, which is formed.

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