JP2014138029A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device that reduces influences of variations in manufacturing, and that has a capacitive element with a high relative precision.SOLUTION: A semiconductor device comprises: an interlayer insulating layer provided on a semiconductor substrate; and a capacitor group 1 in which a plurality of capacitors 11 are arranged in an array form in the interlayer insulating layer. The capacitor group 1 comprises a plurality of sub capacitor groups 10. Each of the plurality of sub capacitor groups 10 includes at least one of the plurality of capacitors 11, and is two-dimensionally arranged in a distributed manner in the capacitor group 1. The plurality of sub capacitor groups 10 function as one capacitive element, singularly or plurally.

Description

  The present invention relates to a semiconductor device, and can be suitably used particularly for a semiconductor device having a built-in capacitor.

  With the progress of miniaturization of semiconductor integrated circuits, there is an increasing demand for area reduction in analog circuits. The area of the analog circuit is determined by a passive element such as a capacitive element. Therefore, with the miniaturization of semiconductor integrated circuits, it is necessary to reduce the area of passive elements such as capacitive elements. On the other hand, in order to ensure accuracy as an analog circuit, it is necessary to ensure a certain area for passive elements such as capacitive elements due to restrictions due to variations in the characteristics of elements in manufacturing.

  As a circuit having a passive element such as a capacitive element, for example, a pipeline type A / D converter is known. The pipeline type A / D converter has a plurality of blocks. Each block outputs a digital signal in order from the most significant bit to the least significant bit by one bit as a result of converting the input analog value to a digital value. N-bit conversion goes through (N-1) stage blocks. Here, when a pair of switched capacitors is used on the input side of the operational amplifier constituting each block, if the relative accuracy of the capacitance between the switched capacitors in the preceding block is poor, the accuracy of the A / D conversion in the subsequent block Gets worse. The relative accuracy of the capacitance depends on the size of the capacitive element. Therefore, in order to improve the relative accuracy of the capacitance, it is necessary to increase the area of the capacitive element.

As a circuit having a passive element such as a capacitive element, for example, a successive conversion A / D converter is known. A successive conversion A / D converter basically performs A / D conversion by a binary search method. In capacitive D / A converter circuit for outputting a comparison signal to the comparator 2 ⁰ times the unit structure capacitance C, 2 ^1-fold, 2 ^doubles, ..., 2 ^N-1 times the capacity elements are provided. In order to configure this circuit, it is common to use a capacitor array in which ^2N unit configuration capacitors each having a capacitor C are arranged in an array. In this case, in order to realize a 16-bit capacitive A / D conversion circuit, 2 ¹⁶ = 65536 capacitive elements are required. The capacitance of each capacitive element associated with the data bit needs to be exactly twice that of the next smaller capacitive element. Therefore, in order to improve the accuracy of the capacitance, it is necessary to increase the area of the capacitive element.

  In addition, various circuits are known as circuits having passive elements such as capacitive elements, as exemplified by charge pump boosting.

  As a technique for improving the capacitance accuracy of this capacitive element, a semiconductor device is disclosed in Japanese Patent Application Laid-Open No. 2006-120883 (Patent Document 1: Corresponding US Application Publication US2006087044 (A1)). This semiconductor device includes a semiconductor substrate and at least six first, second, third, fourth, fifth, and sixth strip-shaped metal films formed on the main surface of the semiconductor substrate. Have. The six metal films are arranged side by side so as to be substantially parallel to each other in the order of the first, second, third, fourth, fifth, and sixth in a plane substantially parallel to the main surface. ing. A first capacitor is formed by the first, second, fifth and sixth metal films. A second capacitor is formed by the third and fourth metal films.

  Also, JP 2002-517095 (Patent Document 2: Corresponding US Patent US6016019 (A)) discloses a capacitor array configuration for improving capacitor array matching. The capacitor array layout technique for improving the capacitor array matching includes the following steps. That step provides a capacitor array. Another step is to place the capacitor array in a geometry, the geometry having a center point. Another step is to divide the geometry into a plurality of first sections, wherein each of the plurality of first sections is diagonal from the first section and the center Having a corresponding second section located approximately equidistant from the point to the first section. Another step is storing a predetermined set of capacitors in each of the second sections, each of the plurality of first sections having a value equal to the corresponding second section. Stores a set of capacitors.

  Japanese Unexamined Patent Application Publication No. 2004-208011 (Patent Document 3: Corresponding US Application Publication US2004125005 (A1)) discloses a D / A converter and an A / D converter. The D / A converter includes a capacitor array including a plurality of unit capacitors that distribute charges according to conversion codes. In this D / A converter, each unit capacitor is composed of power-of-two divided capacitors having the same layout shape and connected in parallel. These divided capacitors are arranged in a straight line, and for each unit capacitor, each divided capacitor constituting the unit capacitor is in a mirror inversion arrangement with respect to the center position of the capacitor array.

JP 2006-120883 A Special table 2002-517095 gazette JP 2004-208011 A

As described above, in the pipeline type A / D converter, the relative accuracy between a pair of switched capacitors is an extremely important factor. In the pipeline type A / D conversion converter, the value of the digit is determined in each block for the input level. When the value is “1”, the value is subtracted from the input level, the result is amplified (doubled in the case of 1 bit), and output to the next block. In the next block, the value of the next digit is determined. Thus, the pipeline type A / D conversion converter always requires operational amplification, and the operational amplification uses a switch and a capacitive element. When the accuracy of this operational amplification is poor, the accuracy of A / D conversion in the subsequent block is deteriorated. For example, the first stage of the block is comprised of sample-and-hold circuit and the D / A converter, an error tolerance of long if the output voltage at 10-bit resolution is required to extremely severe value of 1/2 to ¹⁰ . The relative accuracy depends on the area of the capacitive element, and it is necessary to increase the area of the capacitive element in order to improve the accuracy. On the other hand, if two capacitive elements having a larger area are arranged, variations in element characteristics due to manufacturing variations are likely to occur. Therefore, even if the capacitance element is increased in order to increase accuracy, the influence of manufacturing variation is increased, and it is difficult to obtain a capacitance element with high relative accuracy.

Further, as described above, in the capacitive D / A converter circuit in the successive approximation A / D converter, the capacity of the previous stage is increased by a multiple of 2 with the capacitive element having the unit configuration capacity C as a unit. The capacity needs to be exactly twice the capacity of the previous stage. For example, when considering a 16-bit A / D converter as the high-resolution A / D converter, it is necessary to arrange 2 ¹⁶ = 65536 capacitive elements. The number is difficult to realize both in terms of cost and area in order to increase the area of the capacitive element in order to improve the accuracy of the capacitance. In some high-resolution successive approximation A / D converters, trimming or the like is actually performed to reduce errors, but it is impossible to compensate for 16-bit performance. In an actual product, compensation is performed by including a calibration D / A conversion circuit in each capacitor element.

  In Patent Document 1, an attempt is made to improve the variation accuracy using a wiring (linear) MIM (Metal-Insulator-Metal) capacitor. However, this method can increase the relative accuracy in the linear direction, but it is difficult to reduce the systematic variation in the direction orthogonal to the wiring. For this reason, the relative accuracy is reduced by the amount of variation in the direction orthogonal to the wiring. On the other hand, in Patent Documents 2 and 3, the relative accuracy is improved by taking a rotationally symmetric or linearly symmetric arrangement. However, when the variation is not rotationally symmetric or linearly symmetric, the relative accuracy is reduced by the amount of variation that is not rotationally symmetric or linearly symmetric.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  According to one embodiment, a semiconductor device includes a capacitor group in which capacitors are arranged in an array. The capacitor group includes a plurality of sub-capacitor groups, and the plurality of sub-capacitor groups are two-dimensionally included in the array. Distributed.

  According to the embodiment, it is possible to obtain a capacitive element with high relative accuracy by reducing the influence of manufacturing variations.

FIG. 1 is a plan view schematically showing an example of the configuration of the semiconductor device according to the first embodiment. FIG. 2 is a cross-sectional view schematically showing an example of the configuration of the semiconductor device according to the first embodiment. FIG. 3A is a cross-sectional view schematically showing the capacitor connecting method according to the first embodiment. FIG. 3B is a cross-sectional view schematically showing the capacitor connection method according to the first embodiment. FIG. 4A is a cross-sectional view showing an example of a method for manufacturing the semiconductor device according to the first embodiment. FIG. 4B is a cross-sectional view illustrating an example of the method for manufacturing the semiconductor device according to the first embodiment. FIG. 4C is a cross-sectional view showing an example of the method for manufacturing the semiconductor device according to the first embodiment. FIG. 4D is a cross-sectional view illustrating an example of the method for manufacturing the semiconductor device according to the first embodiment. FIG. 4E is a cross-sectional view illustrating an example of the method for manufacturing the semiconductor device according to the first embodiment. FIG. 4F is a cross-sectional view showing an example of the method for manufacturing the semiconductor device according to the first embodiment. FIG. 5A is a functional block diagram showing the configuration of the pipeline type A / D converter according to the second embodiment. FIG. 5B is a functional block diagram showing the configuration of one block in FIG. 5A. FIG. 5C is a functional block diagram showing the configuration of the operational amplifier in FIG. 5B. FIG. 6 is a plan view schematically showing an example of the layout of the capacitor group of the switched capacitor in FIG. 5C. FIG. 7 is a functional block diagram showing a configuration of a semiconductor device to which the A / D converter according to the embodiment is applied. FIG. 8A is a functional block diagram showing a configuration of a successive approximation A / D converter according to the third embodiment. FIG. 8B is a functional block diagram showing a configuration of the digital-analog conversion circuit in FIG. 8A. FIG. 9 is a plan view schematically showing an example of the layout of the capacitor group in FIG. 8B. FIG. 10 is a plan view schematically showing Modification Example 1 of the layout of the capacitor group in FIG. 8B. FIG. 11 is a plan view schematically showing Modification Example 2 of the layout of the capacitor group in FIG. 8B. FIG. 12 is a plan view schematically showing Modification Example 3 of the layout of the capacitor group in FIG. 8B. FIG. 13 is a functional block diagram showing the configuration of the charge pump type booster circuit according to the fourth embodiment.

  Hereinafter, semiconductor devices according to embodiments will be described with reference to the accompanying drawings.

(First embodiment)
FIG. 1 is a plan view schematically showing an example of the configuration of the semiconductor device according to the first embodiment. FIG. 2 is a cross-sectional view schematically showing an example of the configuration of the semiconductor device according to the first embodiment. The semiconductor device 2 according to the present embodiment includes interlayer insulating layers 41 to 50 and a capacitor group 1. The interlayer insulating layers 41 to 50 are provided on the semiconductor substrate 30. In the capacitor group 1, a plurality of capacitors 11 are arranged in an array in the interlayer insulating layers 41-50. The capacitor group 1 includes a plurality of sub-capacitor groups 10. Each of the plurality of sub-capacitor groups 10 includes at least one capacitor 11 of the plurality of capacitors 11. Each of the plurality of sub-capacitor groups 10 is two-dimensionally distributed in the capacitor group 1. The sub-capacitor group 10 can function as a single capacitive element by itself or when a plurality of sub-capacitor groups 10 are gathered. In such a semiconductor device 2, as shown in FIG. 1, a plurality of subcapacitor groups 10 are distributed in the arrayed capacitor group 1, thereby reducing systematic variations that occur during the manufacturing process. it can. Thereby, the relative accuracy between the capacitive elements can be improved.

  Hereinafter, the semiconductor device of the present embodiment will be further described.

  As shown in FIG. 1, the capacitor group 1 includes a plurality of capacitors 11 (including 11-1 to 11-4) arranged in an array (may be a lattice or a matrix). The capacitor 11 is a capacitor for one, and can be said to be the minimum structural unit of the capacitor group 1. Capacitor group 1 includes a plurality of sub-capacitor groups 10 (including 10-1 to 10-2) formed by dividing capacitor group 1. The sub capacitor group 10 includes at least one capacitor 11. In other words, the capacitor 11 can be said to be the smallest structural unit of the sub-capacitor group 10. In other words, each of the plurality of capacitors 11 is included in one of the plurality of sub-capacitor groups 10.

  The plurality of sub-capacitor groups 10 are two-dimensionally distributed in the capacitor group 1. Here, two-dimensionally distributed arrangement means, for example, that a plurality of the same type of sub-capacitor groups 10 having the same number and arrangement of included capacitors 11 are densely arranged in the capacitor group 1. Rather, it means that they are distributed. In the example of FIG. 1, for example, as the subcapacitor group 10 including two capacitors 11, the upper left subcapacitor group 10-1 and the lower right subcapacitor group 10-2 are the capacitor group 1. It is arranged in a distributed manner.

  At this time, it is preferable that the plurality of sub-capacitor groups 10 provided for performing the same type of function are arranged in the capacitor group 1 so as to be point-symmetric or line-symmetric with respect to the center point. In the example of FIG. 1, when the sub-capacitor group 10-1 and the sub-capacitor group 10-2 are used for performing the same type of function, the capacitor group 1 is point-symmetric or line-symmetric with respect to the center point. It is preferable to arrange so as to be. In that case, in the capacitor group 1, the systematic variations of the plurality of sub-capacitor groups 10 are approximately the same. Therefore, systematic variations that occur in the manufacturing process can be relatively reduced compared to when no distributed arrangement is performed. In other words, even if there is a systematic variation, the plurality of sub-capacitor groups 10 can be made the same level. In other words, systematic variations among the plurality of sub-capacitor groups 10 can be offset. As a result, the relative accuracy between the capacitive elements can be improved.

  The two-dimensionally distributed arrangement means that, for example, a plurality of capacitors 11 included in one sub-capacitor group 10 are not arranged densely in the capacitor group 1 but are arranged in a distributed manner. You can say that. In the example of FIG. 1, for example, as the sub-capacitor group 10 including four capacitors 11, the upper left sub-capacitor group 10-1 and the lower right sub-capacitor group 10-2 are connected in parallel by wiring or the like. One subcapacitor group 10 can be considered. The wiring is exemplified by wiring on the upper electrode plate and other wiring layers. In that case, a plurality of capacitors 11-1 to 11-2 and 11-3 to 11-4 included in the single sub-capacitor group 10 are distributed in the capacitor group 1.

  The plurality of capacitors 11 of one sub-capacitor group 10 having one function are preferably arranged in the capacitor group 1 so as to be point-symmetric or line-symmetric with respect to the center point. Further, in the sub-capacitor group 10, it is preferably arranged so as to be point symmetric or line symmetric with respect to the center point. For example, when the capacitors 11-1 to 11-4 are included in one sub-capacitor group 10, the capacitors 11-1 to 11-2 and the capacitors 11-3 to 11-4 are included in the capacitor group 1 and the sub-capacitor group 10. Are arranged so as to be point-symmetric or line-symmetric with respect to the center point. In that case, systematic variations can be approximately the same between capacitors 11 that are distributed (for example, between capacitors 11-1 to 11-2 and capacitors 11-3 to 11-4). Therefore, systematic variations in the sub-capacitor group 10 can be made uniform. In the same manner, systematic variations in other subcapacitor groups 10 can be made uniform. Therefore, compared to the case where no distributed arrangement is performed, systematic variations that occur in the manufacturing process are made uniform, and the influence thereof can be reduced. As a result, the relative accuracy between the capacitive elements can be improved.

Here, the dispersion method is not particularly limited as long as it is possible to reduce the influence of systematic variations occurring in the manufacturing process, but the following methods are conceivable, for example. First, the function to apply the plurality of capacitors 11 of the capacitor group 1 is determined. As a function, for example, a function as a switched capacitor provided on the input side of an operational amplifier of a pipeline type A / D converter, or a unit configuration capacity C provided in a capacitive D / A conversion circuit of a successive conversion type A / D converter. ²ⁿ times the capacity element function. Next, the sub-capacitor group 10 used for the function is arranged, for example, point-symmetrically or line-symmetrically with respect to the center point of the capacitor group 1. For example, when the sub-capacitor group 10 is disposed as a function of the above-described switched capacitor, the plurality of capacitors 11 as the switched capacitors are disposed so as to be point-symmetric or line-symmetric with respect to the center point. For example, 10-1 is one switched capacitor and 10-2 is the other switched capacitor. Further, when arranging the sub-capacitor group 10 as a function of 2 ⁿ times the capacitance element described above, such that a plurality of capacitors 11 as the 2 ⁿ times the capacitance element, a point symmetry or line symmetry with respect to the center point To place. For example, the ^{2 0} times the capacity element together and 10-1 and 10-2. Such an arrangement method can reduce the influence of systematic variation and improve the relative accuracy of the capacitive element.

  When two or more capacitors 11 are included in the same sub-capacitor group 10, the two or more capacitors 11 may be adjacent to each other or separated from each other as long as they are electrically connected in parallel. In the example of FIG. 1, a plurality of capacitors 11 adjacent in a predetermined direction (vertical direction in the drawing) constitute one sub-capacitor group 10. That is, the sub-capacitor group 10 has a vertically long shape. However, the sub-capacitor group 10 is not limited to this example, and the sub-capacitor group 10 may have other shapes as long as the plurality of sub-capacitor groups 10 satisfy the condition of being two-dimensionally distributed in the capacitor group 1. good. For example, there are a horizontally long shape, a triangular shape (example: the capacitor 11 is arranged at the apex of the triangle), a square shape, and a combination thereof. Further, as described above, the subcapacitor groups 10 (vertically long, horizontally long, triangular, square, and combinations thereof) may be connected to each other by wiring to form one subcapacitor group 10 again.

  However, in the above description, the capacitor 11 and the sub-capacitor group 10 do not have to be strictly point-symmetric or line-symmetric, and many parts of the target capacitors 11 (for example, 60% or more) are included. It only needs to be point-symmetric or line-symmetric. Therefore, in this specification, the point symmetry and the line symmetry include such a meaning.

  As described above, in the semiconductor device of the present embodiment, in the capacitor group 1, the plurality of subcapacitor groups 10 in the capacitor group 1 or the plurality of capacitors 11 in the subcapacitor group 10 are two-dimensionally distributed and arranged in the array. ing. As a result, systematic variations that occur during the manufacturing process can be reduced, and as a result, the accuracy of the capacitive element can be improved.

  As shown in FIG. 2, on the semiconductor substrate 30, a contact layer 31 (interlayer insulating layers 41 and 42), a wiring layer 32 (interlayer insulating layers 43 and 44) to a wiring layer 35 (interlayer insulating layers 49 and 50) are formed. Is provided. The capacitor group 1 has a plurality of capacitors 11 arranged in an array in the interlayer insulating layers 41 to 50. The capacitor 11 is preferably a MIM (Metal-Insulator-Metal) type capacitor. Since the capacitor 11 is not an MOS (Metal-Oxide-Semiconductor) type but an MIM type, the parasitic resistance is small and high-speed operation is possible. With this effect, for example, when this is applied to an A / D conversion circuit, a high-speed operation can be realized in the A / D conversion circuit.

The capacitor 11 has a structure embedded in the wiring layer 34 that is one layer below the uppermost layer to the wiring layer 32 that is three layers below. In other words, it has a structure embedded in the interlayer insulating layers 43 to 47. The capacitor 11 is exemplified by a MIM type capacitor 11 having a cylinder shape. The capacitor 11 has a configuration in which an upper electrode 93 connected to an upper electrode plate 94, a dielectric 92, and a lower electrode 91 connected to lower contacts (plugs) 81 and 82 are laminated in this order. doing. The contacts 81 and 82 pass through the contact layer 31 and are connected to a diffusion layer 80 provided in the surface region of the semiconductor substrate 30. The diffusion layer 80 is connected to ground or an active element (eg, MOS transistor). The electrode plate 94 is connected to wirings (including vias) 83 and 75 that penetrate the wiring layer 35. When the capacitor 11 has a cylinder shape, for example, a capacity efficiency of 50 fF / μm ² or more can be obtained. Accordingly, if the capacitance is the same, only an area of 1/100 of the parallel plate type MIM type capacitive element provided between the wirings is occupied. Therefore, area efficiency can be improved. In that case, for example, a capacitor of 10 nF or more can be manufactured as one capacitor 11.

  The semiconductor substrate 30 may further include an electronic circuit unit 15 and a switch unit 14 that connects the capacitor 11 and the electronic circuit unit 15. The switch unit 14 includes a switch MOS transistor Tr. In the switch MOS transistor Tr, one of the source / drain is connected to the capacitor 11 via the contact layer 31 and the contact 71 of the wiring layers 33 to 35 and the wirings 72 to 75. It is preferable to have the switch unit 14 because the connection / disconnection of the capacitor 11 can be easily controlled. The switch MOS transistor Tr connects the other of the source / drain to another electronic element (not shown) of the electronic circuit unit 15 via the contact layer 31 and the contact 61 of the wiring layers 33 to 35 and the wirings 62 to 65. Has been. The connection to the electronic circuit unit 15 on the same semiconductor substrate 30 is preferable because transmission / reception of signals can be performed quickly and easily. The electronic circuit unit 15 controls, for example, a portion of a logic circuit that is not a capacitive element in a pipeline type A / D converter or a successive conversion type A / D converter, a pipeline type A / D converter, or a successive conversion type A / D converter. The control circuit is exemplified.

  Unlike an eDRAM, a capacitor (capacitance element) 11 is directly connected to contacts 81 and 82. Thereby, it is necessary to change the cross-sectional structure (example: contact layer 31 and wiring layers 32 to 35) in another circuit part (example: electronic circuit unit 15) even though the capacitor (capacitance element) is provided. There is no. Accordingly, normal design parameters can be used as they are without change, there is no need for dedicated design, and design costs do not increase with parameter changes.

3A and 3B are cross-sectional views schematically showing a capacitor connecting method according to the present embodiment. As shown in FIG. 3A, the capacitor 11 basically separates the lower electrode 91 for each capacitor 11 as a cylinder capacitive element. That is, the lower electrode 91 is separated at the location D. On the other hand, as shown in FIG. 3B, the lower electrode 91 may be connected between the capacitors 11 configured as the sub-capacitor group 10. That is, at the location D, the lower electrode 91 is connected and not divided. When the lower electrode 91 is connected, the margin between the cylinder capacitive elements (capacitors 11) is relaxed (narrowed). Therefore, the capacity density per area becomes larger than that of the DRAM element, and the capacity density is about 200 fF / μm ² when using a 40 nm or 28 nm generation technology, for example. Further, an etch-back process for dividing the lower electrode 91 is not necessary. Therefore, manufacture as a cylinder capacitive element is simplified and facilitated. Further, one or more contacts between the lower electrode 91 and the diffusion layer 80 of the semiconductor substrate 30 may be provided for each sub-capacitor group 10. In the example shown in the figure, the contact 82 is omitted and one contact 81 is used. In addition, when there are a plurality of contacts, they become the backing wiring, so that the effect of reducing the resistance can be obtained.

  Next, a method for manufacturing a semiconductor device according to the present embodiment will be described. 4A to 4F are cross-sectional views showing an example of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

  As shown in FIG. 4A, other electronic elements (not shown) of the electronic circuit unit 15, the switch MOS transistor Tr of the switch unit 14, and the like are formed so as to cover the semiconductor substrate 30 covered with the insulating film 41. Then, the interlayer insulating layer 42 is formed. Next, in the insulating film 41 and the interlayer insulating layer 42, contacts 81 and 82, contacts 71 and contacts 61 are formed at predetermined locations of the capacitor group 1, the switch unit 14, and the electronic circuit unit 15, respectively. Subsequently, an interlayer insulating layer 43 is formed on the interlayer insulating layer 42. Thereafter, wirings 72 and 62 are formed in the interlayer insulating layer 43 so as to be connected to the contacts 71 and 61 (damascene). Next, interlayer insulating layers 44 and 45 are formed on the interlayer insulating layer 43, respectively. Subsequently, wirings 73 and 63 are formed in the interlayer insulating layers 44 and 45 so as to be connected to the wirings 72 and 62 (dual damascene). Next, interlayer insulating layers 46 and 47 are formed on the interlayer insulating layer 45. Thereafter, wirings 74 and 64 are formed in the interlayer insulating layers 46 and 47 so as to be connected to the wirings 73 and 63 (dual damascene). Thereafter, an interlayer insulating layer 48 a is formed on the interlayer insulating layer 47.

  Next, as shown in FIG. 4B, the interlayer insulating layer 48 a and the interlayer insulating layer 47 are etched halfway according to the pattern of the region where the plurality of capacitors 11 of the capacitor group 1 are formed. As a result, wide and shallow flat recesses are formed in the region where the plurality of capacitors 11 are formed in the interlayer insulating layer 47. Subsequently, the interlayer insulating layers 47, 46, 45, 44, and 43 are etched using a plurality of cylinder patterns for the plurality of capacitors 11. As a result, a plurality of cylinders 90 for the plurality of capacitors 11 are formed.

  Subsequently, as shown in FIG. 4C, a metal film for the lower electrode 91 is formed on the entire surface. Then, the metal film outside the cylinder 90 is etched back. As a result, the metal film remains only on the side wall and bottom surface of the cylinder 90, and the lower electrode 91 is formed in the cylinder 90. Next, as shown in FIG. 4D, a dielectric film for the dielectric 92, a metal film for the upper electrode 93, and a metal film for the upper electrode plate 94 are formed on the entire surface with a predetermined film thickness.

  Subsequently, as shown in FIG. 4E, the metal film for the electrode plate 94, the metal film for the upper electrode 93, and the dielectric film for the dielectric 92 are etched according to the pattern of the plurality of capacitors 11 in the capacitor group 1. As a result, the electrode plate 94, the upper electrode 93, and the dielectric 92 are formed. That is, the MIM type cylinder-shaped capacitor 11 (upper electrode 93, dielectric 92, lower electrode 91) is formed.

  Thereafter, as shown in FIG. 4F, interlayer insulating layers 48 and 49 are formed so as to fill the etched portion of the interlayer insulating layer 47 and cover the entire surface. Subsequently, in the interlayer insulating layers 48 and 49, 83 is formed so as to be connected to the capacitor 11, a wiring 75 is formed so as to be connected to the capacitor 11 and the wiring 74, and a wiring 65 is formed so as to be connected to the wiring 64. (Dual Damascene). Thereafter, an interlayer insulating layer 50 is formed so as to cover the interlayer insulating layer 49.

  The semiconductor device according to the present embodiment is manufactured through the above steps.

In this embodiment, in a capacitor group in which a plurality of capacitors are arranged in an array, a plurality (at least two or more) of sub-capacitor groups among them are dispersedly arranged in a lattice in the array. Systematic variation can be reduced by the grid-like distributed arrangement, and the relative accuracy of the capacitive element can be improved. In this embodiment, in order to reduce the area while ensuring the accuracy of the capacitor, an MIM capacitor cylinder capacitor cell array structure including a plurality of capacitors having an MIM cylinder shape in an array may be used. MIM type capacitor of cylindrical shape, as compared with such wiring between MIM capacitance element (0.5~1fF / μm ²⁾ and parallel plate MIM capacitive element (10fF / μm ^2), a high capacity density (50 fF / [mu] m ² Above). Therefore, when the MIM cylinder capacitor cell array structure is used, the occupation area can be further reduced while improving the accuracy. In that case, for example, a capacitive element of 10 nF or more can be manufactured. Further, the MIM type structure is advantageous in terms of leakage current and operation speed as compared with a MOS capacitor or the like.

(Second Embodiment)
In the present embodiment, a pipeline A / D converter 2a will be described as an example of the semiconductor device 2 according to the first embodiment. FIG. 5A is a functional block diagram showing a configuration of the pipeline type A / D converter according to the present embodiment. The pipeline type A / D converter 2a includes a first stage block 102-1 to an (N-1) th stage block 102- (n-1) and a code conversion circuit 104.

Analog signal IN _A input to the pipelined A / D converter 2a, block of each stage from the first stage blocks 102-1 to the (N-1) th stage blocks 102- (n-1), most It is converted into a digital signal (1 or 0) one bit at a time from the upper bits. These conversion results are all output to the code conversion circuit 104. That their conversion are output from the code converting circuit 104 as a digital signal OUT _D. The N-bit conversion goes through the (N-1) stage block 102. In each stage block, when processing of one signal is completed, processing of the next signal can be performed in the next cycle. Therefore, in each block, the next signal processing can be started without waiting for the output of all bits.

  FIG. 5B is a functional block diagram showing the configuration of one block in FIG. 5A. The block 102 for one stage includes a sample and hold circuit 110, a 1-bit A / D converter (ADC) 112, a 1-bit D / A converter (DAC) 114, and an operational amplifier 116. The sample and hold circuit 110 holds an analog signal from the block 102 in the previous stage. The 1-bit A / D converter 112 determines 1/0 at the bit of the analog signal and outputs it to the code conversion circuit 104 and the 1-bit D / A converter 114 as a 1/0 digital signal. The 1-bit D / A converter 114 converts the digital signal into an analog signal and outputs it to the operational amplifier 116. The operational amplifier 116 amplifies the difference between the analog signal of the sample and hold circuit 110 and the analog signal of the 1-bit D / A converter 114, for example, by a factor of 2, and outputs the amplified signal to the subsequent block 102.

  FIG. 5C is a functional block diagram showing the configuration of the operational amplifier in FIG. 5B. Switched capacitors C 1 and C 2 (capacitor group 122) and a switch 120 constituting a switched capacitor circuit, an operational amplifier 126, and a reset switch 124 are provided.

  The switch 120 inputs the analog signal of the 1-bit D / A converter 114 to the switched capacitor C1, and inputs the analog signal of the sample and hold circuit 110 to the switched capacitor C2. The operational amplifier 126 amplifies the difference between the two analog signals, for example, by a factor of 2, and outputs the amplified signal to the subsequent block 102. In this case, the switched capacitors C1 and C2 need to have the same capacity. Therefore, the relative accuracy between the switched capacitor C1 and the switched capacitor C2 (the relative accuracy of the characteristics of the capacitive element) is an extremely important factor. This is because the error of the block 102 at a certain stage is propagated in an enlarged manner to the subsequent block 102 after the next stage.

  In the present embodiment, the capacitor group 1 described in the first embodiment is applied as the capacitor group 122 for the switched capacitors C1 and C2 in which the relative accuracy is important. FIG. 6 is a plan view schematically showing an example of the layout of the capacitor group of the switched capacitor in FIG. 5C. The capacitor group 122 includes a plurality of capacitors 11 arranged in an array. The capacitor group 122 includes a switched capacitor C1 and a switched capacitor C2 as sub capacitor groups. Each of the switched capacitor C1 and the switched capacitor C2 includes a plurality of capacitors 11. The capacitor 11 is, for example, a MIM type cylinder-shaped capacitor. The capacitor group 122 can be referred to as an MIM cylinder capacitor array when the capacitor 11 is an MIM type cylinder-shaped capacitor.

  In the example of FIG. 5, the sub-capacitor group that constitutes the switched capacitor C1 is composed of jumping columns in the array. Each column includes six adjacent capacitors 11. The switched capacitor C1 has a total of 18 capacitors 11. The plurality of capacitors 11 are connected in parallel to each other via an upper electrode plate (wiring). Similarly, the sub-capacitor group that constitutes the switched capacitor C2 is composed of a skipped column in the array. Each column includes six adjacent capacitors 11. The switched capacitor C2 also has a total of 18 capacitors 11. The plurality of capacitors 11 are connected in parallel to each other via an upper electrode plate (wiring). The flying columns in the array of switched capacitors C1 and the flying columns in the array of switched capacitors C2 are alternately arranged. The switched capacitor C1 and the switched capacitor C2 are arranged symmetrically with respect to the center of the capacitor group 122 or at a point target position. Therefore, the plurality of capacitors 11 included therein are also arranged in line symmetry or point target positions with respect to the center of the capacitor group 122.

  Thus, in the present embodiment, in the switched capacitor C1 and the switched capacitor C2, a plurality of columns of the capacitors 11 are alternately arranged in the array in close proximity. That is, the plurality of capacitors 11 of each switched capacitor can be distributed and used, and a plurality of adjacent array columns can be used as the comparison capacitors (C1 and C2). As a result, process variations due to the layout of the switched capacitors, that is, systematic variations can be minimized. Therefore, the relative accuracy of the capacitance between the switched capacitor C1 and the switched capacitor C2 can be made very high. In addition, random variation can be reduced by using the number of capacitors as the number of megabit class elements in terms of DRAM. As a result, the accuracy of the operational amplifier 116 can be increased. Thereby, the accuracy of the block 102 in each stage is improved, and as a result, the accuracy of the pipeline type A / D converter 2a can be improved.

  Further, in a large area parallel plate capacitor or an inter-wiring MIM capacitor, the relative accuracy depends on the area of the capacitive element. Therefore, in order to ensure relative accuracy, it is necessary to create a pattern having a certain structural area adjacent to each other. As a result, variations in device characteristics due to manufacturing variations were likely to occur. However, according to the present embodiment, the problem can be almost solved by disposing the sub-capacitor group in a two-dimensional manner. Further, according to the present embodiment, by using the MIM type cylinder-shaped capacitor, it is possible to obtain a higher capacitance density than the parallel plate capacitor and the inter-wiring MIM capacitor. Thereby, it is possible to reduce an increase in layout area and an increase in cost due to an improvement in accuracy.

FIG. 7 is a functional block diagram illustrating a configuration of a semiconductor device to which the A / D converter according to the embodiment is applied. The semiconductor device 9 includes a sensor 7, a semiconductor device 2 as an A / D converter, and a logic circuit 8. The sensor 7 is a device that measures an amount (pressure, velocity, acceleration, flow velocity, rotation speed, light, time, temperature, heat, strain (stress), magnetism, etc.) indicating the state of the measurement target. Sensor 7, a measurement result as an analog signal IN _A, and outputs to the semiconductor device 2 of the A / D converter. The semiconductor device 2 (A / D converter) is exemplified by the pipeline type A / D converter 2a of the present embodiment and the successive approximation type A / D converter 2b of the third embodiment to be described later. The semiconductor device 2, converts the analog signal IN _A into a digital signal OUT _D to the logic circuit 8. The logic circuit 8 performs a logical operation based on the digital signal OUT _D and outputs a calculation result. The logical operation may be an operation based on a program stored in an internal storage unit. The logic circuit 8 is exemplified by an MCU (micro-controller unit), an MPU (micro-processing unit), and a CPU (central processing unit). The pipeline type A / D converter 2a, the successive approximation type A / D converter 2b, and the logic circuit 8 may be formed on one semiconductor chip (including a stack of a plurality of semiconductor substrates). Further, the sensor 7, the pipeline type A / D converter 2a, the successive approximation type A / D converter 2b, and the logic circuit 8 are formed on one semiconductor chip (including a laminate of a plurality of semiconductor substrates). May be.

  Since such a semiconductor device 9 uses the pipeline type A / D converter 2a of this embodiment and the successive approximation type A / D converter 2b (described later) of the third embodiment, A / D conversion is performed. Accuracy can be improved. Thereby, an analog signal indicating the measurement result of the sensor 7 can be converted into a digital signal with high accuracy. As a result, the measurement accuracy of the sensor 7 can be increased. In addition, the control based on the measurement result of the sensor can be performed more precisely.

(Third embodiment)
In the present embodiment, a successive approximation A / D converter 2b will be described as an example of the semiconductor device 2 according to the first embodiment. FIG. 8A is a functional block diagram showing a configuration of the successive approximation A / D converter according to the present embodiment. The successive approximation A / D converter 2b basically performs A / D conversion by a binary search method. The successive approximation type A / D converter 2b includes a sample and hold amplifier 132, a digital-analog conversion circuit 134, a comparator (comparator) 133, a control circuit (timing controller 135, control logic circuit 136 (successive comparison register)), and It has.

The control logic circuit 136 outputs a digital signal to be compared in response to a control signal from the timing controller 135. The digital-analog conversion circuit 134 converts the digital signal into an analog signal and outputs the analog signal. Sample-and-hold amplifier 132 is controlled by signals from the timing controller 135, and outputs the analog signal IN _A. The comparator (comparator) 133 compares the analog signal from the digital-analog converter circuit 134 with the analog signal from the sample / hold amplifier 132 and outputs the comparison result to the control logic circuit 136. The control logic circuit 136 stores the comparison result and outputs the next comparison target digital signal based on the comparison result in response to the next control signal from the timing controller 135 (the same applies hereinafter).

FIG. 8B is a functional block diagram showing a configuration of the digital-analog conversion circuit in FIG. 8A. FIG. 8B shows a 16-bit digital-analog conversion circuit as an example. The digital / analog conversion circuit 134 is a capacitive D / A converter (digital / analog conversion circuit). The digital-analog conversion circuit 134 includes an array of capacitors 144 and dummy capacitors 143 (capacitor group 142) and switches 147, 146, and 145. The capacitive element 144 is N capacitive elements 144-0 to 144-15 (C to 32768C = 2 ⁰ C to 2 ¹⁵ C) having weight values. There is one dummy capacitive element 143 (C). The switches 147 are switches 147-0 to 147-15 corresponding to the capacitive elements 144-0 to 144-15. One ends of the capacitive elements 144-0 to 144-15 and 143 are connected to the inverting input terminal of the comparator 140. The other end of the capacitor 144-0～144-15,143 via respective switches 147-0～147-15,146 analog input signal (ANALOG IN), a reference voltage _{(V REF)} and a ground voltage (GROUND) Connected to either. The ground voltage is connected to the non-inverting input terminal of the comparator 140. The reset switch 145 resets the input of the comparator 140.

As described above, the digital-analog conversion circuit 134 can be configured with only a capacitive element and a switch, and is excellent in power saving. In order to convert an analog value into a digital value using this capacitive D / A converter, 2 ⁰ = 1 times, 2 ¹ = 2 times, 2 ² = 4 times, with a capacitive element having a capacitance C as a unit, Each of the capacitance elements increased by a multiple of 2 is required, such as 2 ³ = 8 times. When converting to an N-bit digital value, a maximum capacity of 2 ^N-1 C is required, and a total capacity of 2 ^N C is required. In configuring this capacitive D / A converter, an array in which unit capacitive elements having C capacitance are arranged in a ^2N array is used. For example, it is necessary to arrange 2 ¹⁰ = 1024 capacitors to realize a ¹⁰ -bit D / A converter, and 2 ¹⁶ = 65536 capacitors to realize a 16-bit D / A converter. Ideally, the capacitance of each of the plurality of capacitive elements associated with the data bit needs to be exactly twice the capacitance of the next smaller capacitive element. That is, the relative accuracy between the capacitive elements is important.

  In the present embodiment, the capacitor group 1 described in the first embodiment is applied as the capacitor group 142 for the capacitive elements 144-0 to 144-15 having an important relative accuracy. FIG. 9 is a plan view schematically showing an example of the layout of the capacitor group in FIG. 8B. In FIG. 9, only the capacitive elements 144-0 to 144-2 are representatively shown, but the present invention can be similarly applied to other capacitive elements 144-3 to 144-15. The capacitor group 142 includes a plurality of capacitors 11 arranged in an array. The capacitor group 142 includes capacitive elements 144-0 to 144-2 as sub capacitor groups. Each of the capacitive elements 144-0 to 144-2 includes a plurality of capacitors 11. The capacitor 11 is, for example, a MIM type cylinder-shaped capacitor. The capacitor group 142 can be referred to as an MIM cylinder capacitor array when the capacitor 11 is an MIM type cylinder-shaped capacitor.

In the example of FIG. 9, the sub-capacitor group constituting the capacitive element 144-0 is configured in one row in the array. The column includes six adjacent capacitors 11. Therefore, the capacitive element 144-0 includes the six capacitors 11 as the capacitance C (2 ⁰ C). These six capacitors 11 are connected in parallel to each other via an upper electrode plate (wiring). In addition, the sub-capacitor group constituting the capacitive element 144-1 is composed of two rows in the array. Each column includes six adjacent capacitors 11. Therefore, the capacitive element 144-1 has twelve capacitors 11 as the capacitance 2C (2 ¹ C). The twelve capacitors 11 are connected in parallel to each other through an upper electrode plate (wiring). In addition, the sub-capacitor group constituting the capacitive element 144-2 is composed of four rows in the array. Each column includes six adjacent capacitors 11. Therefore, the capacitive element 144-2 has 24 capacitors 11 as the capacitance 4C (2 ² C). These 24 capacitors 11 are connected in parallel to each other via an upper electrode plate (wiring). One row of the capacitor elements 144-0 is arranged at the center of the array, two rows of the capacitor elements 144-1 are arranged at line (point) symmetrical positions with respect to the center of the array, and four rows of the capacitor elements 144-2 are They are arranged at line (point) symmetrical positions with respect to the center of the array. One row of the capacitor element 144-0 and two rows of the capacitor element 144-1 and the four rows of the capacitor element 144-2 are alternately arranged. Therefore, the plurality of capacitors 11 included therein are also arranged at positions symmetrical with respect to the line (point) with respect to the center of the array.

As described above, in this embodiment mode, each of the capacitor elements 144-0, 144-1, 144-2 (C (2 ⁰ C), 2C (2 ¹ C), 4C (2 ² C)) A plurality of capacitors are distributed and the rows of capacitors 11 are alternately arranged in the array in close proximity. As a result, process variations due to layout, that is, systematic variations can be minimized. Therefore, the capacitance of each sub-capacitor group (capacitance elements 144-0, 144-1 and 144-2) can be doubled very accurately. In addition, random variation can be reduced by using the number of capacitors as the number of megabit class elements in terms of DRAM. As a result, the accuracy of the operational amplifier 116 can be increased. Thereby, the accuracy of the digital-analog converter circuit 134 is improved, and as a result, the accuracy of the successive approximation A / D converter 2b can be improved.

  Further, in a large area parallel plate capacitor or an inter-wiring MIM capacitor, the relative accuracy depends on the area of the capacitive element. Therefore, in order to ensure relative accuracy, it is necessary to create a pattern having a certain structural area adjacent to each other. As a result, variations in device characteristics due to manufacturing variations were likely to occur. However, according to the present embodiment, the problem can be almost solved by disposing the sub-capacitor group in a two-dimensional manner. Further, according to the present embodiment, by using the MIM type cylinder-shaped capacitor, it is possible to obtain a higher capacitance density than the parallel plate capacitor and the inter-wiring MIM capacitor. Thereby, it is possible to reduce an increase in layout area and an increase in cost due to an improvement in accuracy.

(Modification 1)
Next, Modification 1 of the present embodiment will be described. FIG. 10 is a plan view schematically showing Modification Example 1 of the layout of the capacitor group in FIG. 8B. In FIG. 9 described above, the plurality of capacitors 11 are laid out in a rectangular lattice shape (matrix arrangement), but the present embodiment is not limited to this example. For example, as shown in FIG. 10, a plurality of capacitors 11 may be laid out in an oblique grid pattern (staggered arrangement). Also in this case, the same effect as in FIG. 9 can be obtained.

(Modification 2)
Next, a second modification of the present embodiment will be described. FIG. 11 is a plan view schematically showing Modification Example 2 of the layout of the capacitor group in FIG. 8B. In FIG. 10 described above, the layout is such that the plurality of capacitors 11 are connected in parallel by the strip-shaped upper electrode plates in the vertical direction, but the present embodiment is not limited to this example. For example, as shown in FIG. 11, a plurality of capacitors 11 are connected in parallel with diagonal strip-shaped upper electrode plates and upper vias and wiring (shown as solid lines in the figure for simplicity). It may be a layout.

In the example of FIG. 11, the sub-capacitor group configuring the capacitive element 144-0 is configured by one sub-capacitor group belonging to one column in the oblique direction in the array. The capacitor group has a configuration in which six adjacent capacitors 11 are connected in parallel with an upper electrode plate. Therefore, the capacitive element 144-0 includes the six capacitors 11 as the capacitance C (2 ⁰ C). In addition, the sub-capacitor group constituting the capacitive element 144-1 has a configuration in which two sub-capacitor groups belonging to two columns in different directions in the array are connected in parallel using vias and wirings to form one sub-capacitor group. have. The sub-capacitor group for one row has a configuration in which six adjacent capacitors 11 are connected in parallel with an upper electrode plate. Therefore, the capacitive element 144-1 has twelve capacitors 11 as the capacitance 2C (2 ¹ C). In addition, the sub-capacitor group constituting the capacitor element 144-2 has a configuration in which six sub-capacitor groups belonging to six columns in different diagonal directions in the array are connected in parallel using vias and wirings to form one sub-capacitor group. have. The sub-capacitor group for one column is composed of two adjacent capacitors 11 (two sub-capacitor groups), four adjacent capacitors (two sub-capacitor groups) or six adjacent capacitors 11 (two sub-capacitor groups). It has the structure connected in parallel. Therefore, the capacitive element 144-2 has 24 capacitors 11 as the capacitance 4C (2 ² C). One row of the capacitive elements 144-0 is arranged at the center of the array, and two rows of the capacitive elements 144-1 are arranged at positions substantially symmetrical with respect to the center of the array (point), and six rows of the capacitive elements 144-2 are arranged. Are arranged at positions substantially symmetric with respect to the center of the array.

  Also in this case, the same effect as in the case of FIG. 11 can be obtained.

(Modification 3)
Next, a third modification of the present embodiment will be described. FIG. 12 is a plan view schematically showing Modification Example 3 of the layout of the capacitor group in FIG. 8B. In FIG. 11 described above, each capacitive element 144 is divided into a plurality of sub-capacitor groups, but the present embodiment is not limited to this example. For example, as shown in FIG. 12, each capacitive element 144 may be divided into a larger number of sub-capacitor groups and distributed.

In the example of FIG. 12, the sub-capacitor group constituting the capacitive element 144-0 is formed as one sub-capacitor group by connecting three sub-capacitor groups belonging to three different columns in the array in parallel using vias and wirings. It has a configuration. The sub-capacitor group for one row has a configuration in which two adjacent capacitors 11 are connected in parallel by an upper electrode plate. Therefore, the capacitive element 144-0 includes the six capacitors 11 as the capacitance C (2 ⁰ C). The sub-capacitor group constituting the capacitive element 144-1 has a configuration in which six sub-capacitor groups belonging to six different columns in the array are connected in parallel using vias and wirings to form one sub-capacitor group. ing. The sub-capacitor group for one row has a configuration in which two adjacent capacitors 11 are connected in parallel by an upper electrode plate. Therefore, the capacitive element 144-1 has twelve capacitors 11 as the capacitance 2C (2 ¹ C). The sub-capacitor group constituting the capacitive element 144-2 has a configuration in which 11 sub-capacitor groups belonging to nine different columns in the array are connected in parallel using vias and wirings to form one sub-capacitor group. ing. A row of sub-capacitor groups has a configuration in which two adjacent capacitors (10 sub-capacitor groups) or four adjacent capacitors (one sub-capacitor group) 11 are connected in parallel by an upper electrode plate. Therefore, the capacitive element 144-2 has 24 capacitors 11 as the capacitance 4C (2 ² C). Three rows of capacitive elements 144-0 are arranged approximately point-symmetrically at the center of the array, and six rows of capacitive elements 144-1 are arranged at positions substantially symmetrical with respect to the center of the array. The ten rows are arranged at substantially point symmetrical positions with respect to the center of the array.

Also in this case, the same effect as in the case of FIG. 11 can be obtained.
In addition, as shown in FIG. 12, when the sub-capacitor groups are arranged in a distributed manner, the dispersion caused by the layout and size can be almost eliminated by further increasing the degree of dispersion.

In the present embodiment and the modification thereof, the capacitor group constituting C (2 ⁰ C), 2C (2 ¹ C), and 4C (2 ² C) is shown as an example of the layout. The capacitor group can be laid out in the same way. Even in that case, the same effects as those of the above-described embodiment and its modifications can be obtained.

(Fourth embodiment)
In the present embodiment, a charge pump type booster circuit 2c will be described as an example of the semiconductor device 2 according to the first embodiment. FIG. 13 is a functional block diagram showing the configuration of the charge pump type booster circuit according to the present embodiment. The charge pump type booster circuit 2c increases the voltage by combining a capacitive element and a switch (in practice, for example, using a MOS transistor).

  The charge pump booster circuit 2c includes switches 151-1 to 151-4, 152-1 to 152-4, and 153-1 and capacitive elements Cc1, Cc2, and Cout. The capacitive elements Cc1, Cc2, and Cout are connected in parallel to each other. One end of the switch 151-1 is connected to the input, and the other end is connected to one end of the capacitive element Cc1 and one end of the switch 151-2. The other end of the switch 151-2 is connected to one end of the switch 151-3 and one end of the switch 153-1. The other end of the switch 151-3 is connected to one end of the capacitive element Cc2 and one end of the switch 151-4. The other end of the switch 151-4 belongs to the output and one end of the capacitive element Cout. One end of the switch 152-1 is connected to the input, and the other end is connected to the other end of the capacitive element Cc1 and one end of the switch 152-2. The other end of the switch 152-2 is connected to one end of the switch 152-3 and the other end of the switch 153-1. The other end of the switch 152-3 is connected to the other end of the capacitive element Cc2 and one end of the switch 152-4. The other end of the switch 152-4 belongs to the output and the other end of the capacitive element Cout.

In the example of this figure, the switches 151-1 to 151-3, 152-2 to 152-4 are turned on to connect the charge capacitive elements Cc 1 and Cc 2 in parallel, and the charge capacitive elements Cc 1 and Cc 2 with the input voltage Vin. To charge. Thereafter, the switches 152-1, 151-2, 153-1, 152-3, and 151-4 are turned on to switch the charging capacitive elements Cc1 and Cc2 to series connection, and three times the input voltage Vin (Vin + V _CC1 + V _CC2 ) Voltage can be obtained. Furthermore, it is possible to obtain a voltage having an arbitrary magnification of the input voltage Vin by changing the number of capacitive elements Cc to be connected.

In the charge pump type booster circuit, ideally, the capacitor used for charging preferably has a large capacity and a small equivalent series resistance. Further, in the case of a charge pump type booster circuit of three times or more, it is desirable that the capacitances of a plurality of capacitive elements used for charging are exactly equal. This is because, when the accuracy of the capacitance is insufficient, the charge is moved when connected in series at the time of boosting, and the voltage varies. In the example of FIG. 13, there is a possibility that charge transfer occurs between the capacitive element Cc1 and the capacitive element Cc2. In addition, the large capacity here is 0.1 μF or more, and normally, an off-chip (external) capacitive element is usually used. Since the conventional MIM capacitance between wirings can only obtain a capacitance density of about 0.1 fF / μm ² , it is impractical to realize on-chip (an area of 10 ⁹ μm ² = 10 ³ mm ² or more is required). It is.

  In the present embodiment, for example, by using the capacitor group according to the second embodiment as the capacitive element, it is possible to increase the relative accuracy of the capacitance between the multiple capacitive elements used for charging, and to equalize accurately. Can do. Thereby, the movement of the electric field between the capacitive elements can be suppressed to be extremely small, and a highly accurate and efficient on-chip charge pump type booster circuit can be obtained.

  The technologies of the above-described embodiments and modifications can be applied to other embodiments and other modifications as long as no technical contradiction occurs.

    As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

DESCRIPTION OF SYMBOLS 1: Capacitor group 2: Semiconductor device 2a: Pipeline type A / D converter 2b: Successive comparison type A / D converter 2c: Charge pump type booster circuit 7: Sensor 8: Logic circuit 9: Semiconductor device 10: Sub capacitor group 10 -1: Subcapacitor group 10-2: Subcapacitor group 11: Capacitors 11-1 to 11-2, 11-3 to 11-4: Capacitor 14: Switch unit 15: Electronic circuit unit 30: Semiconductor substrate 31: Contact layer 32 to 35: wiring layer 41: insulating film 42 to 50, 48a: interlayer insulating layer 61: contact 62 to 65: wiring 71: contact 72 to 75: wiring 80: diffusion layer 81, 82: contact (plug)
90: Cylinder 91: Lower electrode 92: Dielectric 93: Upper electrode 94: Electrode plate 102: Block 104: Code conversion circuit 110: Sample and hold circuit 112: 1-bit A / D converter 114: Bit DA converter 116: Operation amplification Unit 120: Switch 122: Capacitor group 124: Reset switch 126: Operational amplifier 132: Sample / hold amplifier 133: Comparator
134: Digital-analog conversion circuit 135: Timing controller 136: Control logic circuit 140: Comparator 142: Capacitor group 143: Dummy capacitance element 144: Capacitance element 144-0 to 144-15: Capacitance element 145: Reset switch 147-0 147-15: Switch 151-1 to 151-4: Switch 152-1 to 152-4: Switch

Claims (17)

An interlayer insulating layer provided on a semiconductor substrate;
A capacitor group in which a plurality of capacitors are arranged in an array in the interlayer insulating layer;
The capacitor group includes a plurality of sub-capacitor groups,
Each of the plurality of sub-capacitor groups is
Including at least one of the plurality of capacitors;
The plurality of sub-capacitor groups that are two-dimensionally distributed and arranged in the capacitor group function alone or as a single capacitor element. The semiconductor device according to claim 1,
Each of the plurality of sub-capacitor groups includes two or more capacitors,
The two or more capacitors are two-dimensionally distributed in the capacitor group. Semiconductor device. The semiconductor device according to claim 2,
The two or more capacitors are arranged in a line-symmetrical or point-symmetrical position with respect to the center of the capacitor group. The semiconductor device according to claim 1,
The plurality of subcapacitor groups includes a pair of capacitive elements having a first subcapacitor group and a second subcapacitor group,
The first sub-capacitor group and the second sub-capacitor group have the same capacity. The semiconductor device according to claim 4,
The first sub-capacitor group and the second sub-capacitor group are arranged at positions that are line-symmetric or point-symmetric with respect to the center of the capacitor group. The semiconductor device according to claim 5,
Each of the first sub-capacitor group and the second sub-capacitor group includes two or more capacitors,
The two or more capacitors are arranged in a line-symmetrical or point-symmetrical position with respect to the center of the capacitor group. The semiconductor device according to claim 1,
Wherein the plurality of sub-capacitor group is a semiconductor device including a set of the capacitor capacitance of the first sub-capacitor group through the N-th sub-capacitor group is the unit capacitance × 2 ⁰ to the unit volume × 2 ^N-1, respectively. The semiconductor device according to claim 7,
Each of the first to Nth sub-capacitor groups includes two or more capacitors,
The two or more capacitors are arranged in a line-symmetrical or point-symmetrical position with respect to the center of the capacitor group. The semiconductor device according to claim 1,
Each of the plurality of sub-capacitor groups includes a column having two or more adjacent capacitors in the array. The semiconductor device according to claim 1,
The at least one capacitor has a MIM (metal-insulating film-metal) structure. The semiconductor device according to claim 1,
The at least one capacitor has a cylinder structure. The semiconductor device according to claim 1,
The at least one capacitor has a capacitance of 10 nF or more. The semiconductor device according to claim 1,
The at least one capacitor has a capacitance density of 50 fF / μm ² or more. The semiconductor device according to claim 1,
The capacitor group is formed on the same semiconductor substrate together with at least one of a logic circuit and a sensor circuit. The semiconductor device according to claim 4,
The first sub-capacitor group and the second sub-capacitor group are switched capacitors of an operational amplification unit of a pipeline type A / D converter. The semiconductor device according to claim 7,
The first sub-capacitor group to the N-th sub-capacitor group are capacitive elements of a digital-analog conversion circuit of a successive approximation A / D converter. The semiconductor device according to claim 4,
The first sub-capacitor group and the second sub-capacitor group are boosting capacitive elements of a charge pump type booster circuit. Semiconductor device.

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