JP2014135670A - PLL frequency synthesizer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the generation of phase noise at high frequency signal output.SOLUTION: A fixed frequency oscillator 15 with a center frequency set at 1/2 of a desired frequency is newly provided, and a center frequency of a voltage-controlled oscillator 13 is also set at 1/2 of the desired frequency. Outputs from the voltage-controlled oscillator 13 and the fixed frequency oscillator 15 are multiplied and only a sum frequency component is input into a variable frequency divider 14 that provides a feedback input to a frequency/phase comparator 11. The outputs from the voltage-controlled oscillator 13 and the fixed frequency oscillator 15 are also multiplied and only a high frequency component is output as an output signal from a PLL frequency synthesizer 1.

Description

  The present invention relates to a technology of a PLL (Phase Locked Loop) frequency synthesizer.

  FIG. 5 is a diagram showing a circuit configuration of a conventional PLL frequency synthesizer 1. The conventional PLL frequency synthesizer 1 includes a phase locked loop including a reference oscillator 10, a frequency phase comparator 11, a loop filter 12, a voltage controlled oscillator 13, and a variable frequency divider 14.

  The output signal output from the voltage controlled oscillator 13 is branched and input to the variable frequency divider 14, and after being divided by the variable frequency divider 14, the feedback signal is input to the frequency phase comparator 11.

  The frequency phase comparator 11 receives a reference frequency signal output from the reference oscillator 10 in addition to the hoodback input signal, and a voltage signal having a frequency difference or phase difference between the two input signals is input to the loop filter 12. Is repeatedly output to the voltage controlled oscillator 13.

  Thereafter, the voltage-controlled oscillator 13 outputs a signal having a frequency corresponding to the voltage of the input signal as an output signal from the PLL frequency synthesizer 1. Through these operations, an oscillation frequency signal of several GHz synchronized with the reference frequency in the reference oscillator 10 is repeatedly output.

Toshiyuki Ozawa, “PLL Frequency Synthesizer / Circuit Design Method”, General Electronic Publishing Company, 2000, p.11 Kenji Kawakami, 3 others, “Low phase noise VCO using GaAs devices”, MWE 2005 Micorwave Workshop Digest, p.181

  Here, as is clear from Leeson's model equation of Non-Patent Document 2, the phase noise in the voltage controlled oscillator 13 is multiplied by 2 when the frequency of the output signal output from the PLL frequency synthesizer 1 is doubled. It increases in proportion to the power.

  In the conventional PLL frequency synthesizer 1, a signal having a frequency that is finally output to the outside is generated by one voltage controlled oscillator 13. When the frequency of the output signal becomes higher than several hundred GHz, the voltage controlled oscillator 13 There is a problem that an excessive phase noise generated when generating the signal frequency is included in the output signal.

  The present invention has been made in view of the above circumstances, and an object thereof is to suppress the generation of phase noise when a high-frequency signal is output.

  2. A PLL frequency synthesizer according to claim 1, wherein the center frequency is set to 1 / N (N is a value larger than 1) of the frequency of the output signal output from the PLL frequency synthesizer, and oscillates a signal of a fixed frequency. A voltage controlled oscillator that oscillates a signal whose center frequency is set to 1 / M of the frequency of the output signal (M is a value greater than 1) and whose frequency is changed according to the voltage of the input signal; A multiplier that multiplies the two signals output from the fixed-frequency oscillator and the voltage-controlled oscillator, and outputs only the larger component from the obtained two components, large and small, as the output signal, and outputs from the multiplier A frequency divider that divides the generated signal, a reference oscillator that oscillates a reference signal, and a signal having a voltage corresponding to the frequency difference or phase difference between the two signals output from the divider A frequency phase comparator for outputting the serial voltage controlled oscillator, and summarized in that with.

  The PLL frequency synthesizer according to claim 2 is the PLL frequency synthesizer according to claim 1, wherein the fixed frequency oscillator is a plurality of fixed frequency oscillators having different frequencies, and the fixed frequency oscillator operating according to a desired frequency channel is provided. The gist is that it can be switched.

  The PLL frequency synthesizer according to claim 3 is the PLL frequency synthesizer according to claim 1 or 2, wherein the multiplier multiplies the two signals and outputs only a high frequency component from a high frequency component and a low frequency component. A first multiplier that outputs as a signal, and a second multiplier that multiplies the two signals and outputs only a sum frequency component from a sum frequency component and a difference frequency component, and the frequency divider The gist is to divide the signal output from the second multiplier.

  A PLL frequency synthesizer according to a fourth aspect is the PLL frequency synthesizer according to the third aspect, wherein the signal output from the fixed frequency oscillator is divided by a division factor of 2 to the second multiplier. A first frequency divider that outputs, a second frequency divider that divides the signal output from the voltage controlled oscillator by a factorial division ratio of 2 and outputs the result to the second multiplier; It is a summary to have further.

  The PLL frequency synthesizer according to claim 5 is the PLL frequency synthesizer according to claim 4, wherein the fixed frequency oscillator is a plurality of fixed frequency oscillators having different frequencies, and the first frequency divider includes each fixed frequency oscillator. The gist is a plurality of frequency dividers each having frequency characteristics corresponding to the frequency of the oscillator, and the frequency dividers operating according to a desired frequency channel are switched.

  The PLL frequency synthesizer according to claim 6 is the PLL frequency synthesizer according to any one of claims 1 to 5, wherein each center frequency of the fixed frequency oscillator and the voltage controlled oscillator is 1/2 of the frequency of the output signal. It is set as the gist.

  According to the present invention, it is possible to reduce phase noise when a high frequency signal is output.

It is a figure which shows the circuit structure of the PLL frequency synthesizer which concerns on 1st Embodiment. It is a figure which shows the example of a high-speed operation | movement frequency divider. It is a figure which shows the circuit structure of the PLL frequency synthesizer which concerns on 2nd Embodiment. It is a figure which shows the circuit structure of the PLL frequency synthesizer which concerns on 3rd Embodiment. It is a figure which shows the circuit structure of the conventional PLL frequency synthesizer.

  Hereinafter, an embodiment for carrying out the present invention will be described with reference to the drawings. However, the present invention can be implemented in many different modes and should not be construed as being limited to the description of the present embodiment.

[First Embodiment]
In the first embodiment, a fixed frequency oscillator 15 in which the center frequency is set to be lower than the frequency (desired frequency) of the output signal output from the PLL frequency synthesizer 1 is newly provided, and a phase locked loop is further provided. The center frequency of the voltage controlled oscillator 13 configured is also set in the same manner.

  Then, the outputs from the two oscillators 13 and 15 are multiplied, and only the sum frequency component is input to the conventional variable frequency divider 14 and fed back to the frequency phase comparator 11. By multiplying the output and outputting only the high frequency component as the output signal, the phase noise at the time of outputting the high frequency signal is reduced.

  First, the configuration of the PLL frequency synthesizer 1 according to the present embodiment will be described. FIG. 1 is a diagram illustrating a circuit configuration of the PLL frequency synthesizer according to the first embodiment.

  The PLL frequency synthesizer 1 includes a reference oscillator 10, a frequency phase comparator 11, a loop filter 12, a voltage controlled oscillator 13, a variable frequency divider 14, a fixed frequency oscillator 15, and a first upconversion mixer 16. The first high-speed operation frequency divider 17, the second high-speed operation frequency divider 18, and the second up-conversion mixer 19.

  The reference oscillator 10 is a circuit that oscillates a highly accurate reference frequency signal. For example, a crystal oscillator is used.

  The frequency phase comparator 11 is a circuit that converts a frequency difference or phase difference between two input signals into a voltage and outputs a signal of the voltage. A frequency comparator that converts only the frequency difference into a voltage may be used.

  The loop filter 12 is a circuit that smoothes an input signal. For example, it includes a low-pass filter, a charge pump, and the like.

  The voltage controlled oscillator 13 is a circuit that oscillates a signal whose frequency is changed in accordance with the voltage of the signal applied to the control voltage input terminal. The center frequency is set to ½ of the frequency of the output signal output from the PLL frequency synthesizer 1.

  The fixed frequency oscillator 15 is a circuit that oscillates a signal having a fixed frequency. The center frequency is set to ½ of the frequency of the output signal output from the PLL frequency synthesizer 1, similarly to the voltage controlled oscillator 13.

  The first up-conversion mixer 16 is a circuit that multiplies two input signals and outputs only a high-frequency component from the high-frequency component and the low-frequency component as an output signal from the PLL frequency synthesizer 1.

  Each of the first high-speed operation frequency divider 17 and the second high-speed operation frequency divider 18 is a circuit that divides an input signal by a factorial division ratio of 2.

  The second up-conversion mixer 19 is a circuit that multiplies two input signals and outputs only the sum frequency component from the sum frequency component and the difference frequency component.

  The variable frequency divider 14 is a circuit that can set a frequency dividing ratio from the outside and divides a signal that is input with the set frequency dividing ratio. A frequency divider with a fixed frequency division ratio that is not set from the outside may be used.

  Next, the operation of the PLL frequency synthesizer 1 will be described.

  The signal output from the voltage controlled oscillator 13 is branched on the conducting wire and output to the second high-speed operation frequency divider 18. Since the center frequency of the voltage controlled oscillator 13 is set to ½ of the desired frequency, the frequency of the signal output here is almost ½ of the desired frequency.

Then, the frequency is divided by a factorial of 2 (= 1/2 ^N ) by the second high-speed operation frequency divider 18 and then output to the second up-conversion mixer 19. In this way, by newly adding a frequency dividing process and dividing the frequency to a frequency that can be divided by the variable frequency divider 14, even for a high frequency signal that is difficult to divide by the variable frequency divider 14 using a digital circuit. The frequency is surely divided.

  As such a second high-speed operation frequency divider 18, for example, an injection lock type frequency divider as shown in FIG. 2 is used, so that a frequency higher than that of a frequency divider using a digital circuit such as a flip-flop is obtained. The signal can be divided at high speed.

  On the other hand, in parallel with the above processing, the signal output from the fixed frequency oscillator 15 is output to the first up-conversion mixer 16 and the first high-speed operation frequency divider 17. Since the center frequency of the fixed frequency oscillator 15 is also set to ½ of the desired frequency, the frequency of the signal output here is also almost ½ of the desired frequency.

Then, the first high-speed operation frequency divider 17 divides the frequency into 1 factorial 2 (= 1/2 ^N ), and then outputs it to the second up-conversion mixer 19. By newly adding a frequency dividing process in this way, high frequency signals that are difficult to divide by the variable frequency divider 14 are also reliably divided.

  Thereafter, the two signals output from the first high-speed operation frequency divider 17 and the second high-speed operation frequency divider 18 are multiplied by the second up-conversion mixer 19, and the multiplied sum frequency component and difference frequency are multiplied. Of the components, only the sum frequency component is output to the variable frequency divider 14.

  Then, the variable frequency divider 14 divides the frequency by an externally set division ratio, and then feedback-inputs to the frequency phase comparator 11. The reference frequency signal output from the reference oscillator 10 is compared, and a voltage signal having the frequency difference is repeatedly output to the voltage controlled oscillator 13 via the loop filter 12.

  Since the voltage signal is a repetitive AC signal, it is smoothed by the loop filter 12 and then supplied to the voltage controlled oscillator 13 as a control signal. Thereafter, the voltage controlled oscillator 13 outputs a signal whose frequency is changed according to the voltage of the supplied signal to the first up-conversion mixer 16.

  Finally, the first up-conversion mixer 16 multiplies the two signals output from the voltage controlled oscillator 13 and the fixed frequency oscillator 15, and only the high frequency component of the multiplied high frequency component and low frequency component is the PLL frequency. It is output as an output signal from the synthesizer 1.

  Regarding frequency fluctuations in the voltage controlled oscillator 13 and the fixed frequency oscillator 15, the second up-conversion mixer 19 integrates the frequency-divided signal of the voltage-controlled oscillator 13 and the frequency-divided signal of the fixed frequency oscillator 15. It is fed back to the oscillator 13 and compensated by the voltage controlled oscillator 13.

  As described above, according to the present embodiment, the fixed frequency oscillator 15 having the center frequency set to ½ of the desired frequency is newly provided, the center frequency of the voltage controlled oscillator 13 is also set to ½ of the desired frequency, The two signals output from the voltage controlled oscillator 13 and the fixed frequency oscillator 15 are multiplied, and only a large component (high frequency component, sum frequency component) is input to the variable frequency divider 14 and fed back to the frequency phase comparator 11. At the same time, since it is output as an output signal from the PLL frequency synthesizer 1, phase noise when a high frequency signal is output can be reduced. Hereinafter, this effect will be described in detail.

(Effect 1) In the conventional PLL frequency synthesizer, when the frequency of the output signal from the PLL frequency synthesizer is doubled, for example, the amplitude component of the phase noise component in the voltage controlled oscillator 13 is also doubled. Was raised to the square of 2 or 6 dB.

  On the other hand, according to the PLL frequency synthesizer 1 according to the present embodiment, two voltage controlled oscillators 13 and a fixed frequency oscillator 15 that are independent of each other are used to oscillate at half the desired frequency. , 15 has no correlation, the power of the phase noise of the multiplication signal is simply added, so that the power of the phase noise only doubles, that is, increases by 3 dB. Thereby, compared with the conventional PLL frequency synthesizer which outputs the signal of the same frequency, the electric power of phase noise can be reduced by 3 dB.

(Effect 2) In the conventional PLL frequency synthesizer, even when the cutoff frequency of the transistor constituting the voltage controlled oscillator (the frequency at which the gain of the voltage controlled oscillator is attenuated by 3 dB) is equal to or higher than the desired frequency, the maximum oscillation of the transistor If the frequency (the maximum value of the oscillation frequency) is equal to or lower than the desired frequency, a signal having the desired frequency cannot be obtained from the PLL frequency synthesizer.

  On the other hand, according to the PLL frequency synthesizer 1 according to the present embodiment, each set frequency of the voltage controlled oscillator 13 and the fixed frequency oscillator 15 is set to ½ of the desired frequency. A signal having a desired frequency can be oscillated even when the maximum oscillation frequency of the transistor is about half of the desired frequency.

  That is, as long as the cutoff frequency of the transistors constituting the first up-conversion mixer 16 is equal to or higher than the desired frequency, the maximum oscillation frequency of each transistor constituting the voltage controlled oscillator 13 and the fixed frequency oscillator 15 is 1 / of the desired frequency. Even if it is about 2, a signal of the desired frequency can be output from the phase locked loop.

  Further, in the up-conversion mixer, as a result of multiplying two signals, it is difficult to discriminate if the values of the sum frequency component and the difference frequency component of the obtained signal are close to each other. Since the frequency of the input signal is close, the sum frequency component is about twice that of the signal input to the second up-conversion mixer 19 and the difference frequency component is close to 0. Since the frequency difference between the components becomes large, discrimination is easy and the sum frequency component can be easily extracted.

[Second Embodiment]
In the second embodiment, as shown in FIG. 3, the fixed frequency oscillator 15 of the PLL frequency synthesizer 1 described in the first embodiment has a plurality of Q values that have a high Q value and have different frequencies for each desired frequency channel interval. The fixed-frequency oscillator 15 is changed to an oscillator bank 15 ′.

  Further, a plurality of switch elements S that are connected between the oscillator bank 15 ′ and the first high-speed operation frequency divider 17 by a plurality of conductors corresponding to the plurality of fixed frequency oscillators 15 and can be controlled by ON / OFF signals are provided. Inserted on each conductor. Other configurations are the same as those of the PLL frequency synthesizer 1 described in the first embodiment.

  A high-frequency signal output from a conventional PLL frequency synthesizer is used as a carrier signal for transmitting and receiving high-speed data by wireless communication. However, a wide frequency bandwidth is required for high-speed data communication. For example, a bandwidth of about 20 GHz is required for 20 Gbps data communication. In the case of a frequency of 100 GHz or more, it is not only necessary to increase the Q value of the voltage controlled oscillator, but also because the inductor and the capacitor composed of conducting wires are frequently used, it is extremely sensitive to the wavelength, and only the fixed frequency oscillator is used. It is difficult to oscillate using only it. Furthermore, since the Q value is high, the output frequency range of the voltage controlled oscillator is narrow, and the method of expanding the frequency tuning range by controlling the variable capacitance of the voltage controlled oscillator is a channel of about 20 GHz where multiple users do not interfere. It was extremely difficult to switch the frequency of the output signal at intervals.

  On the other hand, according to the PLL frequency synthesizer 1 according to the present embodiment, the fixed frequency oscillator 15 and the switch element S that are operated according to a desired frequency channel are switched (for example, switched at intervals of 20 GHz), so that a wide frequency channel can be obtained. The output frequency can be switched, and the phase noise is low under conditions where the power consumption is constant, and the power consumption can be reduced under conditions where the phase noise is constant.

  This is because, in applications where the frequency is switched by broadband high-speed communication, the channel interval is extremely wide, and if one frequency variable oscillator such as the voltage-controlled oscillator 13 is used to cover all channels, signal characteristics can be prevented from deteriorating. This is because it is advantageous to use a plurality of fixed frequency oscillators 15 having a high Q value. However, since the frequency of the fixed frequency oscillator 15 also fluctuates, it is necessary to use the voltage controlled oscillator 13 together to compensate for the fluctuation.

[Third Embodiment]
In the third embodiment, as shown in FIG. 4, the fixed frequency oscillator 15 of the PLL frequency synthesizer 1 described in the first embodiment is replaced with a plurality of high Q values and different frequencies for each desired frequency channel interval. The fixed-frequency oscillator 15 is changed to an oscillator bank 15 ′.

  Further, the oscillator bank 15 ′ and the first high-speed operation frequency divider 17 are connected by a plurality of conductive wires corresponding to the plurality of fixed frequency oscillators 15. Further, the plurality of conducting wires are connected to the first up-conversion mixer 16, and a plurality of switch elements S1 that can be controlled by an ON / OFF signal are respectively inserted immediately before the first up-conversion mixer 16.

  Further, the first high-speed operation frequency divider 17 of the PLL frequency synthesizer 1 described in the second embodiment has a plurality of frequency characteristics respectively corresponding to the frequencies of the fixed frequency oscillators 15 constituting the oscillator bank 15 ′. The first high-speed frequency divider 17 is changed to a high-speed frequency divider bank 17 ′.

  Further, the high-speed divider bank 17 ′ and the second up-conversion mixer 19 are connected by a plurality of conductors corresponding to the plurality of first high-speed operation dividers 17, and can be controlled by an ON / OFF signal. A plurality of switch elements S2 are respectively inserted on the respective conductive wires. Other configurations are the same as those of the PLL frequency synthesizer 1 described in the first embodiment.

  When the first high-speed operation frequency divider 17 cannot obtain sufficient characteristics in a wide band, the first high-speed operation frequency divider 17 and the switch element S2 that are operated according to a desired frequency channel are switched (for example, By switching at intervals of 20 GHz, the signal can be divided without deteriorating.

  Through the above-described embodiments, for example, a PLL frequency synthesizer 1 that can generate a signal that has a high frequency of several hundred GHz or more such as 280 GHz, 300 GHz, and 320 GHz and can be switched at a wide channel interval with low phase noise and low power consumption. Can be provided.

  Thereby, it is possible to perform wireless data communication of several tens of Gbps using a frequency of several hundreds GHz or more as a carrier in a multi-frequency channel so that deterioration in quality can be prevented.

  Finally, in each embodiment, the case where each center frequency of the fixed frequency oscillator 15 and the voltage controlled oscillator 13 is set to ½ of the desired frequency has been described as an example. However, each center frequency is set lower than the desired frequency. For example, the same effect can be obtained if it is set to 1 / N (N is a value greater than 1).

  In each of the embodiments, the case where the first high-speed operation frequency divider 17 and the second high-speed operation frequency divider 18 are used has been described as an example. Since the purpose is to surely divide difficult high-frequency signals, the same effects can be obtained without actively using them.

  In each embodiment, the case where two up-conversion mixers 16 and 19 are used has been described as an example, but the function of multiplying two signals output from the voltage controlled oscillator 13 and the fixed frequency oscillator 16 is common. Therefore, they may be realized by one up-conversion mixer. In that case, the output from the one up-conversion mixer is input to the variable frequency divider 14 and also becomes an output signal from the PLL frequency synthesizer.

  Each component circuit of the PLL frequency synthesizer 1 described in each embodiment can be realized by various elements such as a resistor, a capacitor, and a capacitor, and various logic circuits combining them.

DESCRIPTION OF SYMBOLS 1 ... PLL frequency synthesizer 10 ... Reference oscillator 11 ... Frequency phase comparator 12 ... Loop filter 12
13 ... Voltage controlled oscillator 14 ... Variable frequency divider 14
DESCRIPTION OF SYMBOLS 15 ... Fixed frequency oscillator 15 '... Oscillator bank 16 ... 1st up-conversion mixer 17 ... 1st high speed operation frequency divider 17' ... High speed frequency divider bank 18 ... 2nd high speed operation frequency divider 19 ... 2nd Up-conversion mixer

Claims (6)

A fixed frequency oscillator whose center frequency is set to 1 / N (N is a value greater than 1) of the frequency of the output signal output from the PLL frequency synthesizer, and which oscillates a signal of a fixed frequency;
A voltage controlled oscillator that oscillates a signal whose center frequency is set to 1 / M of the frequency of the output signal (M is a value greater than 1) and whose frequency is changed according to the voltage of the input signal;
A multiplier that multiplies two signals output from the fixed frequency oscillator and the voltage controlled oscillator, and outputs only a large component as the output signal from the obtained two components, large and small;
A frequency divider for frequency-dividing the signal output from the multiplier;
A frequency phase comparator that outputs a voltage signal corresponding to a frequency difference or a phase difference between two signals respectively output from a reference oscillator that oscillates a reference signal and the frequency divider, to the voltage controlled oscillator;
A PLL frequency synthesizer characterized by comprising: The fixed frequency oscillator is
2. The PLL frequency synthesizer according to claim 1, wherein a plurality of fixed frequency oscillators having different frequencies are switched to operate according to a desired frequency channel. The multiplier is
A first multiplier that multiplies the two signals and outputs only the high frequency component from the high frequency component and the low frequency component as the output signal;
A second multiplier that multiplies the two signals and outputs only the sum frequency component from the sum frequency component and the difference frequency component;
The frequency divider is
3. The PLL frequency synthesizer according to claim 1, wherein the signal output from the second multiplier is frequency-divided. A first frequency divider that divides the signal output from the fixed frequency oscillator by a factorial ratio of 2 and outputs the divided signal to the second multiplier;
A second frequency divider that divides the signal output from the voltage controlled oscillator by a factorial ratio of 2 and outputs the divided signal to the second multiplier;
The PLL frequency synthesizer according to claim 3, further comprising: The fixed frequency oscillator is a plurality of fixed frequency oscillators having different frequencies,
The first frequency divider is
5. The PLL frequency synthesizer according to claim 4, wherein a plurality of frequency dividers each having a frequency characteristic corresponding to a frequency of each fixed frequency oscillator are switched, and the frequency divider operating according to a desired frequency channel is switched. . Each center frequency of the fixed frequency oscillator and the voltage controlled oscillator is:
The PLL frequency synthesizer according to claim 1, wherein the PLL frequency synthesizer is set to ½ of the frequency of the output signal.

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