JP2014135417A - パターンの形成方法、それを用いた物品の製造方法 - Google Patents

パターンの形成方法、それを用いた物品の製造方法 Download PDF

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Publication number
JP2014135417A
JP2014135417A JP2013003292A JP2013003292A JP2014135417A JP 2014135417 A JP2014135417 A JP 2014135417A JP 2013003292 A JP2013003292 A JP 2013003292A JP 2013003292 A JP2013003292 A JP 2013003292A JP 2014135417 A JP2014135417 A JP 2014135417A
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JP
Japan
Prior art keywords
pattern
resist
forming
layer
space
Prior art date
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Pending
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JP2013003292A
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English (en)
Japanese (ja)
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JP2014135417A5 (enExample
Inventor
Koichiro Tsujita
好一郎 辻田
Yuichi Gyoda
裕一 行田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP2013003292A priority Critical patent/JP2014135417A/ja
Priority to US14/147,679 priority patent/US9406510B2/en
Publication of JP2014135417A publication Critical patent/JP2014135417A/ja
Publication of JP2014135417A5 publication Critical patent/JP2014135417A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
JP2013003292A 2013-01-11 2013-01-11 パターンの形成方法、それを用いた物品の製造方法 Pending JP2014135417A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2013003292A JP2014135417A (ja) 2013-01-11 2013-01-11 パターンの形成方法、それを用いた物品の製造方法
US14/147,679 US9406510B2 (en) 2013-01-11 2014-01-06 Pattern forming method and article manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2013003292A JP2014135417A (ja) 2013-01-11 2013-01-11 パターンの形成方法、それを用いた物品の製造方法

Publications (2)

Publication Number Publication Date
JP2014135417A true JP2014135417A (ja) 2014-07-24
JP2014135417A5 JP2014135417A5 (enExample) 2016-02-25

Family

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JP2013003292A Pending JP2014135417A (ja) 2013-01-11 2013-01-11 パターンの形成方法、それを用いた物品の製造方法

Country Status (2)

Country Link
US (1) US9406510B2 (enExample)
JP (1) JP2014135417A (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016143689A (ja) * 2015-01-30 2016-08-08 東京エレクトロン株式会社 半導体装置の製造方法
KR20170063525A (ko) * 2014-09-22 2017-06-08 인텔 코포레이션 하부에 놓인 격자 상의 비-반사 복사선 리소그래피를 이용한 멀티-패스 패터닝

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6579997B2 (ja) 2016-05-19 2019-09-25 キヤノン株式会社 光学系およびそれを有する撮像装置
EP3255663B1 (en) * 2016-06-07 2021-08-04 IMEC vzw Method for interrupting a line in an interconnect
EP3367428A1 (en) 2017-02-23 2018-08-29 IMEC vzw Method for blocking a trench portion during patterning of trenches in a dielectric material, and corresponding semiconductor structure
JP7009134B2 (ja) 2017-09-25 2022-01-25 キヤノン株式会社 ズームレンズ及びそれを有する撮像装置
JP7183065B2 (ja) 2019-02-08 2022-12-05 キヤノン株式会社 ズームレンズ、光学機器、および、撮像装置

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06196432A (ja) * 1992-10-30 1994-07-15 Kawasaki Steel Corp 半導体装置における多層配線構造の形成方法及び当該形成方法により製造された多層配線構造を有する半導体装置
JP2009016788A (ja) * 2007-06-29 2009-01-22 Hynix Semiconductor Inc 半導体素子の微細パターン形成方法
US20090111056A1 (en) * 2007-08-31 2009-04-30 Applied Materials, Inc. Resolution enhancement techniques combining four beam interference-assisted lithography with other photolithography techniques
JP2010060954A (ja) * 2008-09-05 2010-03-18 Shin-Etsu Chemical Co Ltd ダブルパターン形成方法
JP2012033923A (ja) * 2010-07-29 2012-02-16 Nikon Corp 露光方法及び露光装置、並びにデバイス製造方法
JP2013161987A (ja) * 2012-02-06 2013-08-19 Toshiba Corp パターン形成方法
JP2014096477A (ja) * 2012-11-09 2014-05-22 Ps4 Luxco S A R L マスクパターン作成方法、半導体装置の製造方法およびマスクパターン作成プログラム

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8563229B2 (en) * 2007-07-31 2013-10-22 Micron Technology, Inc. Process of semiconductor fabrication with mask overlay on pitch multiplied features and associated structures
JP5653880B2 (ja) * 2011-10-11 2015-01-14 信越化学工業株式会社 レジスト下層膜形成材料及びパターン形成方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06196432A (ja) * 1992-10-30 1994-07-15 Kawasaki Steel Corp 半導体装置における多層配線構造の形成方法及び当該形成方法により製造された多層配線構造を有する半導体装置
JP2009016788A (ja) * 2007-06-29 2009-01-22 Hynix Semiconductor Inc 半導体素子の微細パターン形成方法
US20090111056A1 (en) * 2007-08-31 2009-04-30 Applied Materials, Inc. Resolution enhancement techniques combining four beam interference-assisted lithography with other photolithography techniques
JP2010060954A (ja) * 2008-09-05 2010-03-18 Shin-Etsu Chemical Co Ltd ダブルパターン形成方法
JP2012033923A (ja) * 2010-07-29 2012-02-16 Nikon Corp 露光方法及び露光装置、並びにデバイス製造方法
JP2013161987A (ja) * 2012-02-06 2013-08-19 Toshiba Corp パターン形成方法
JP2014096477A (ja) * 2012-11-09 2014-05-22 Ps4 Luxco S A R L マスクパターン作成方法、半導体装置の製造方法およびマスクパターン作成プログラム

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20170063525A (ko) * 2014-09-22 2017-06-08 인텔 코포레이션 하부에 놓인 격자 상의 비-반사 복사선 리소그래피를 이용한 멀티-패스 패터닝
JP2017530388A (ja) * 2014-09-22 2017-10-12 インテル・コーポレーション 下層回折格子に対する非反射放射線リソグラフィを使用するマルチパスパターン形成
US10678137B2 (en) 2014-09-22 2020-06-09 Intel Corporation Multi-pass patterning using nonreflecting radiation lithography on an underlying grating
KR102314664B1 (ko) 2014-09-22 2021-10-20 인텔 코포레이션 하부에 놓인 격자 상의 비-반사 복사선 리소그래피를 이용한 멀티-패스 패터닝
JP2016143689A (ja) * 2015-01-30 2016-08-08 東京エレクトロン株式会社 半導体装置の製造方法
US9818612B2 (en) 2015-01-30 2017-11-14 Tokyo Electron Limited Method for manufacturing semiconductor device

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US20140199843A1 (en) 2014-07-17
US9406510B2 (en) 2016-08-02

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