JP2014135388A - Method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the reliability of a semiconductor device.SOLUTION: When a multiple base substrate 17 and a multiple sub substrate 18 are bonded together, the multiple base substrate 17 with an upper surface 17a on which a semiconductor chip 2 and a plurality of conductive members 8 are mounted is opposed to the multiple sub substrate 18 with a lower surface 18b to which a film-like sealing body 10 thicker than the mounting height of the chip is bonded in advance, and heat and load are applied for bonding the substrates through the plurality of conductive members 8. Accordingly, voids included in the sealing body 10 at the time of bonding are reduced and the reliability of the semiconductor device can be improved.

Description

  The present invention relates to a semiconductor device in which another wiring board is arranged on a wiring board on which a semiconductor chip is mounted, and a method for manufacturing the same.

  In a package-on-package (POP) in which a plurality of semiconductor packages are stacked in multiple stages, a first wiring board on which a first semiconductor chip is mounted and a second wiring board on which a second semiconductor chip is mounted are stacked. Such a structure is disclosed in, for example, Japanese Patent Application Laid-Open No. 2009-70965 (Patent Document 1).

  Moreover, a manufacturing method of a chip built-in substrate in which a chip is built between a pair of substrates is disclosed in, for example, Japanese Patent Application Laid-Open No. 2008-288490 (Patent Document 2).

  Also, the semiconductor chip and the post of the conductor are arranged between the insulating film and the semiconductor chip and the post from the thermosetting resin sheet by heating and pressing in a state where the thermosetting resin sheet is further arranged. A method for manufacturing a semiconductor device that forms a sealing layer that seals is disclosed in, for example, Japanese Patent Application Laid-Open No. 2012-15546 (Patent Document 3).

JP 2009-70965 A JP 2008-288490 A JP 2012-15546 A

  For example, in the case of the so-called POP (Package On Package) technology in which a semiconductor package on which another semiconductor chip is mounted is stacked (stacked) on a semiconductor package on which a certain semiconductor chip is mounted as in Patent Document 1 above. There are restrictions on the positions of the external terminals of the semiconductor package disposed on the upper side. That is, the external terminal of the upper semiconductor package is located on the lower surface (mounting surface) of the wiring substrate of the upper semiconductor package so as not to overlap the semiconductor chip mounted on the lower semiconductor package (see Patent Document 1 above). Then, it must be arranged at the peripheral edge of the wiring board.

  Therefore, in order to solve the above problems, the present inventor, as a configuration of the lower-stage semiconductor package, for example, another wiring on a wiring substrate (base substrate) on which a semiconductor chip is mounted as described in Patent Document 2 above. We examined the placement of a substrate (sub-substrate). By adopting such a configuration, for example, as shown in FIG. 2D of Patent Document 2, there are no restrictions on the locations of the external terminals of the upper semiconductor package and the mounting locations of the upper semiconductor package. In addition, it is possible to mount an electronic component having a smaller outer size than the semiconductor chip mounted on the lower semiconductor package.

  However, in Patent Document 2, a sub-substrate (Patent Document 2 described above) is formed on a base substrate (first substrate 10 in Patent Document 2) via a plurality of conductive members (Electrode 21 in Patent Document 2). Then, after arranging the second substrate 20), a resin is supplied between the substrates from the outside of the space between the two substrates (space portion), and the space between the substrates (including each conductive member and the bonding portion between the substrates). ) Is sealed. For this reason, it has been clarified by the inventor's examination that voids are likely to be generated between the substrates (spaces) in the manufacturing method as described in Patent Document 2.

  An object of the embodiment disclosed in the present application is to provide a technique capable of improving the reliability of a semiconductor device.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  A manufacturing method of a semiconductor device according to an embodiment includes a first wiring board having a plurality of first device forming portions, a sealing device having a plurality of second device forming portions and formed on an insulating film on a lower surface. A second wiring board having a material is prepared, and then a semiconductor chip is mounted on each of the plurality of first device forming portions. Further, a plurality of conductive members are respectively formed on the upper surface side lands of the first wiring substrate, and then the second wiring substrate is disposed on the upper surface of the first wiring substrate, and further, the first and second wiring substrates, By applying a load to the second wiring board while applying heat to the stopper, the plurality of conductive members and the plurality of lower surface lands of the second wiring board are electrically connected, and the semiconductor chip and the plurality of conductive members Is sealed with the above-mentioned sealing material.

  According to the one embodiment, the reliability of the semiconductor device can be improved.

2A and 2B are a cross-sectional view and an enlarged partial cross-sectional view illustrating an example of a structure of a semiconductor device according to an embodiment. FIG. 2 is a plan view of a base substrate used in assembling a semiconductor package on the lower side of the semiconductor device shown in FIG. It is sectional drawing along the AA line shown in FIG. FIG. 2 is a plan view showing an example of a structure at the time of die bonding in assembling a semiconductor package on the lower side of the semiconductor device shown in FIG. 1. It is sectional drawing along the AA line shown in FIG. FIG. 2 is a plan view showing an example of a structure when forming an electrode in assembling a semiconductor package on the lower side of the semiconductor device shown in FIG. 1. It is sectional drawing along the AA line shown in FIG. FIG. 2 is a plan view before arrangement of sub-base materials used in assembling a semiconductor package on the lower side of the semiconductor device shown in FIG. 1. It is sectional drawing along the AA line shown in FIG. FIG. 2 is a plan view after arrangement of sub-base materials used in assembling a semiconductor package on the lower side of the semiconductor device shown in FIG. 1. It is sectional drawing along the AA line shown in FIG. FIG. 2 is a plan view showing an example of a structure at the time of ball mounting for assembling a semiconductor package on the lower side of the semiconductor device shown in FIG. 1. It is sectional drawing along the AA shown in FIG. FIG. 2 is a plan view showing an example of a structure at the time of assembling an assembly of a semiconductor package on the lower side of the semiconductor device shown in FIG. 1. It is sectional drawing along the AA line shown in FIG. It is a top view before arrangement | positioning of the sub base material used by the assembly of the semiconductor package of the lower stage side of the semiconductor device of the modification 3 of embodiment. It is sectional drawing along the AA line shown in FIG. It is a top view before arrangement | positioning of the sub base material used by the assembly of the semiconductor package of the lower stage side of the semiconductor device of the modification 4 of embodiment. It is sectional drawing along the AA line shown in FIG. It is a top view before arrangement | positioning of the sub base material used by the assembly of the semiconductor package of the lower stage side of the semiconductor device of the modification 5 of embodiment. It is sectional drawing along the AA line shown in FIG. It is a top view after arrangement | positioning of the sub base material used by the assembly of the semiconductor package of the lower stage side of the semiconductor device of the modification 5 of embodiment. It is sectional drawing along the AA shown in FIG. It is sectional drawing which shows the structure of the semiconductor device of the modification 6 of embodiment. It is sectional drawing which shows the structure of the other semiconductor device of the modification 6 of embodiment. It is sectional drawing which shows the structure of the semiconductor device of the modification 7 of embodiment.

  In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  Further, in the following embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments, but they are not irrelevant to each other unless otherwise specified. The other part or all of the modifications, details, supplementary explanations, and the like are related.

  Also, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), particularly when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and it may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps) are not necessarily indispensable unless otherwise specified and clearly considered essential in principle. Needless to say.

  Further, in the following embodiments, regarding constituent elements and the like, when “consisting of A”, “consisting of A”, “having A”, and “including A” are specifically indicated that only those elements are included. It goes without saying that other elements are not excluded except in the case of such cases. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. Further, even a plan view may be hatched for easy understanding of the drawing.

(Embodiment)
<Semiconductor device>
FIG. 1 is a cross-sectional view and an enlarged partial cross-sectional view showing an example of the structure of the semiconductor device of the embodiment.

  The structure of the semiconductor device of this embodiment will be described.

  The semiconductor device is a POP (package on package) type semiconductor device (hereinafter simply referred to as POP) in which a semiconductor package on which another semiconductor chip is mounted is mounted (stacked) on a semiconductor package on which a semiconductor chip is mounted. is there.

  The POP 1 of the present embodiment includes a lower package (electronic component) 6 on which a semiconductor chip 2 is mounted and an upper package (electronic component) 7 on which another semiconductor chip 4 is mounted. The sub-board (wiring board) 5 of 6 and the package board (wiring board) 12 of the upper package 7 are electrically connected through a conductive member.

  In the POP 1 of the present embodiment, the semiconductor chip 4 mounted on the upper package 7 is, for example, a memory semiconductor chip, while the semiconductor chip 2 mounted on the lower package 6 is, for example, the upper package. This is a logic semiconductor chip for controlling the memory semiconductor chip 4. Therefore, POP1 can also be called a semiconductor system.

  The POP 1 is mounted on a motherboard (mounting board) of an electronic device or the like via a plurality of external terminals 16 provided on the lower surface side of the base substrate 3 of the lower package 6, for example. The external terminal 16 is made of a conductive member. In this embodiment, the external terminal 16 is, for example, a ball-shaped solder material (solder ball), but the shape is not limited thereto.

  Next, the structure of each package on the lower side and the upper side will be described.

  First, the lower package 6 includes a lower base substrate (base material, wiring substrate) 3 and an upper sub-substrate (base material, wiring substrate) 5, and the upper surface (surface, chip mounting) of the base substrate 3. The semiconductor chip 2 is flip-chip mounted on the surface 3a. That is, the semiconductor chip 2 is disposed (mounted) on the upper surface 3a of the base substrate 3 so that the main surface (surface, upper surface, element forming surface) 2a of the semiconductor chip 2 faces the upper surface 3a of the base substrate 3. . Further, a sub-substrate 5 is disposed on the semiconductor chip 2. That is, the semiconductor chip 2 is arranged between the base substrate 3 and the sub-substrate 5.

  Here, the base substrate 3 is a multilayer wiring substrate having a four-layer wiring layer structure manufactured by, for example, a build-up method. The base substrate 3 has an upper surface 3a having a quadrangular planar shape and a lower surface (back surface, mounting surface) 3b opposite to the upper surface 3a. A plurality of leads (bonding leads, terminals) 3c and a plurality of lands (terminals, electrodes) 3d are provided on the upper surface 3a. The plurality of lands 3d are arranged closer to the peripheral edge side of the upper surface 3a than the plurality of leads 3c. In other words, as shown in FIG. 2, the plurality of leads 3c are arranged in a region surrounded by the plurality of lands 3d.

  Further, a solder resist film (upper surface side insulating film) 3f, which is an insulating film, is formed on the upper surface 3a, and the leads 3c and lands 3d are exposed in the plurality of openings 3i. In other words, the surfaces (exposed surfaces) of the leads 3c and lands 3d are exposed from the solder resist film 3f.

  On the other hand, a plurality of lands 3e are provided on the lower surface 3b, and a plurality of external terminals 16 are connected to the plurality of lands 3e, respectively. The plurality of lands 3e are electrically connected to the plurality of leads 3c or the plurality of lands 3d, respectively. Also, a solder resist film (lower surface side insulating film) 3f, which is an insulating film, is formed on the lower surface 3b, and the lands 3e are exposed in each of the plurality of openings 3j. In other words, the surface (exposed surface) of the land 3e is exposed from the solder resist film 3f.

  In addition, a wiring part (wiring) 3g and an insulating layer 3h are provided inside the base substrate 3, and leads 3c and lands 3d on the upper surface 3a side are formed in the wiring part (wiring) 3g and the insulating layer 3h. The wiring 3 is electrically connected to the land 3e on the lower surface 3b side through a wiring (not shown).

  The sub-board 5 disposed on the semiconductor chip 2 is a multilayer wiring board having a two-layer wiring layer structure. The sub-board 5 has an upper surface (front surface, electronic component mounting surface) 5a having a quadrangular planar shape and a lower surface (back surface) 5b opposite to the upper surface 5a. A plurality of lands (terminals, electrodes) 5c are provided on the upper surface 5a. Here, in the present embodiment, as shown in FIG. 1, the plurality of lands 5c overlap not only the peripheral portion of the upper surface 5a but also the central portion of the upper surface 5a, in other words, the semiconductor chip 2 in the upper surface 5a. The location is also provided.

  On the other hand, a plurality of lands (terminals, electrodes) 5d are provided on the lower surface 5b. The plurality of lands 5d are electrically connected to the plurality of lands 5c via a plurality of wirings (not shown) provided in the insulating layer 5e.

  Furthermore, a solder resist film (upper surface side insulating film) 5f, which is an insulating film, is formed on the upper surface 5a, and the lands 5c are exposed in each of the plurality of openings 5g. In other words, the surface (exposed surface) of the land 5c is exposed from the solder resist film 5f. On the other hand, a solder resist film (lower surface side insulating film) 5f is also formed on the lower surface 5b, and the lands 5d are exposed in each of the plurality of openings 5h. In other words, the surface (exposed surface) of the land 5d is exposed from the solder resist film 5f.

  In the lower package 6, the semiconductor chip 2 is flip-chip connected to the leads 3 c on the upper surface 3 a of the base substrate 3 via conductive members (columnar electrodes, protruding electrodes) 11. That is, the plurality of electrode pads 2 c provided on the main surface 2 a of the semiconductor chip 2 and the plurality of leads 3 c on the upper surface 3 a of the base substrate 3 are electrically connected via the plurality of conductive members 11, respectively. Yes.

  As shown in the enlarged partial sectional view of FIG. 1, in the flip chip connecting portion, the solder layer 11a formed on each lead 3c and the conductive member 11 formed on the electrode pad 2c of the semiconductor chip 2 are electrically connected. Connected.

  Here, although the conductive member 11 of the present embodiment is a columnar (projecting) electrode mainly composed of copper (Cu), the columnar electrode may be made of a metal other than copper. In addition to the columnar (projection-shaped) electrodes mainly composed of copper (Cu), solder bumps, gold bumps, or the like may be used.

  The sub board 5 is electrically connected to the base board 3 through a conductive member (conductive member) 8. The conductive member 8 that electrically connects the base substrate 3 and the sub-substrate 5 is a copper core solder bump. That is, the plurality of lands 3d on the upper surface 3a of the base substrate 3 are electrically connected to the plurality of lands 5d on the lower surface 5b of the sub-substrate 5 via the plurality of copper core solder bumps. The copper core solder bump is made of, for example, a ball-shaped core material (electrode, metal core, conductive member) 8a made of copper (Cu) and a solder film (conductive member) 8b covering the surface of the core material 8a. However, the core material (metal core) 8a is not necessarily made of copper.

  In the lower package 6, a sealing material (sealing layer, adhesive layer) 10 is filled between the base substrate 3 and the sub-substrate 5 (including between the semiconductor chip 2 and the base substrate 3). Yes. The sealing material 10 is, for example, a thermosetting resin.

  In the lower package 6, since the semiconductor chip 2 is disposed between the base substrate 3 and the sub-substrate 5, the lower surface 5b of the sub-substrate 5 and the back surface 2b of the semiconductor chip 2 (the surface located on the upper side in FIG. 1) ) Between them. That is, the base substrate 3 and the mounting height of the semiconductor chip 2 after flip chip connection (distance T1 from the surface of the solder resist film 3f formed on the upper surface 3a of the base substrate 3 to the back surface 2b of the semiconductor chip 2) The distance T2 from the sub-board 5 is larger (T1 <T2).

  As a result, a gap is formed between the back surface 2b of the semiconductor chip 2 and the lower surface 5b of the sub-substrate 5, and contact between the back surface 2b of the semiconductor chip 2 and the lower surface 5b of the sub-substrate 5 can be prevented. In the present embodiment, since the copper core solder bump is adopted as the conductive member 8 used when the sub-board 5 is arranged (mounted) on the base board 3, the base board 3 and the sub-board 5 The distance T2 can be stably secured. Further, as the conductive member, a metal (for example, copper) columnar electrode may be employed instead of the copper core solder bump, and even when the metal columnar electrode is employed, A distance T2 from the sub-substrate 5 can be secured stably.

  Here, the mounting height T1 of the semiconductor chip 2 is, for example, about 80 μm. The distance T2 between the base substrate 3 and the sub substrate 5 is, for example, 150 μm (100 to 200 μm). Further, the thickness T3 of the base substrate 3 is, for example, 230 μm (200 to 300 μm), and the thickness T4 of the sub-substrate 5 is, for example, 140 μm (100 to 200 μm).

  Next, the upper package 7 will be described.

  In the upper package 7, the semiconductor chip 4 is mounted (arranged) on the upper surface (surface, chip mounting surface) 12 a of the package substrate (wiring substrate) 12 via the die bonding material 13. Since the semiconductor chip 4 is wire-connected to the package substrate 12, the semiconductor chip 4 is mounted with the main surface (front surface, upper surface) 4 a facing upward, and the back surface (lower surface) 4 b is the upper surface of the package substrate 12. It faces 12a and is bonded to the die bond material 13.

  The semiconductor chip 4 is provided with a plurality of electrode pads (bonding pads) 4c on the main surface 4a, and leads (bonding leads, terminals) formed on the upper surface 12a of the package substrate 12 by the plurality of electrode pads 4c. ) 12c and a plurality of wires 15 are electrically connected.

  The wire 15 is made of, for example, gold (Au), but a wire made of copper (Cu) may be used.

  The semiconductor chip 4 and the plurality of wires 15 are sealed with a sealing body 14 made of a sealing resin such as a thermosetting resin.

  The package substrate 12 of the upper package 7 is a multilayer wiring substrate having a two-layer wiring layer structure. The package substrate 12 has an upper surface (front surface, chip mounting surface) 12a having a quadrangular planar shape and a lower surface (back surface) 12b opposite to the upper surface 12a. A plurality of leads (bonding leads, terminals) 12c are provided on the upper surface 12a. On the other hand, a plurality of lands (terminals, electrodes) 12d are provided on the lower surface 12b. The plurality of lands 12d are electrically connected to the plurality of leads 12c through a plurality of wirings (not shown) provided on the insulating layer 12e.

  Further, a solder resist film (upper surface side insulating film) 12f, which is an insulating film, is formed on the upper surface 12a, and the leads 12c are exposed in the plurality of openings 12g. In other words, the surface (exposed surface) of the lead 12c is exposed from the solder resist film 12f. On the other hand, a solder resist film (lower surface side insulating film) 12f is also formed on the lower surface 12b, and the lands 12d are exposed in each of the plurality of openings 12h. In other words, the surface (exposed surface) of the land 12d is exposed from the solder resist film 12f.

  Such an upper package 7 is mounted on the lower package 6 via a plurality of external terminals 9 to constitute the POP 1. That is, the lower package 6 and the upper package 7 are electrically connected via the plurality of external terminals 9. Here, the plurality of lands 5 c on the upper surface 5 a of the sub-board 5 of the lower package 6 and the plurality of lands 12 d on the lower surface 12 b of the package substrate 12 of the upper package 7 are electrically connected via the plurality of external terminals 9. It is connected to the. The external terminal 9 is made of a conductive member, like the external terminal 16 of the lower package 6, and is, for example, a ball-shaped solder material (solder ball) in the present embodiment.

  In the POP (semiconductor device) 1 according to the present embodiment, the lower package 6 includes a base substrate 3 and a sub substrate 5, and the sub substrate 5 is disposed on the semiconductor chip 2, in other words, the sub substrate 5. The semiconductor chip 2 is disposed between the base substrate 3 and the semiconductor chip 2. Therefore, when forming the POP 1, the upper package 7 is mounted on the sub-board 5, and the restriction on the position of the external terminals connected to the lower package 6 in the upper package 7 can be eliminated. .

  Further, since the upper package 7 is mounted on the sub-board 5 of the lower package 6, it is not necessary to match the board size of the upper package 7 with the board size of the lower package 6, and the outer size of the upper package 7 Can increase the degree of freedom.

  In the present embodiment, in the POP 1, the base substrate 3 of the lower package 6 is a multilayer wiring substrate having a four-layer wiring layer structure, and the sub substrate 5 of the lower package 6 and the package substrate of the upper package 7. Although the case where 12 is a multilayer wiring board having a two-layer wiring layer structure has been described, the number of wiring layers on each board is not limited thereto.

<Method for Manufacturing Semiconductor Device>
2 is a plan view of a base substrate used in assembling the semiconductor package on the lower side of the semiconductor device shown in FIG. 1, FIG. 3 is a cross-sectional view taken along line AA shown in FIG. 2, and FIG. FIG. 5 is a cross-sectional view taken along the line AA shown in FIG. 4, and FIG. 5 is a plan view showing an example of a structure at the time of die bonding in assembling a semiconductor package on the lower side of the semiconductor device shown. 6 is a plan view showing an example of a structure when forming an electrode for assembling the lower semiconductor package of the semiconductor device shown in FIG. 1, and FIG. 7 is a cross-sectional view taken along the line AA shown in FIG. 8 is a plan view before placement of a sub-base material used in assembling the lower semiconductor package of the semiconductor device shown in FIG. 1, and FIG. 9 is a cross-sectional view taken along the line AA shown in FIG. 10 is a plan view after placement of the sub-base material used in the assembly of the lower semiconductor package of the semiconductor device shown in FIG. 1, and FIG. 11 is a cross-sectional view taken along line AA shown in FIG. 12 is a plan view showing an example of a structure at the time of ball mounting for assembling the semiconductor package on the lower side of the semiconductor device shown in FIG. 1, and FIG. 13 is a cross-sectional view taken along the line AA shown in FIG. Further, FIG. 14 is a plan view showing an example of a structure when the semiconductor package on the lower side of the semiconductor device shown in FIG. 1 is assembled, and FIG. 15 is a sectional view taken along the line AA shown in FIG. is there.

1. Preparation of Base Material (Base) First, a multiple base substrate (wiring substrate) 17 shown in FIGS. 2 and 3 is prepared. The multiple base substrate 17 includes a plurality of device forming portions 17c, a cutting portion (removal portion, dicing portion) 17d provided between adjacent device forming portions 17c among the plurality of device forming portions 17c, and a plan view. 1 includes a frame portion 17e provided around the plurality of device forming portions 17c.

  Each of the plurality of device forming portions 17c of the multiple base substrate 17 includes an upper surface (surface, chip mounting surface) 17a, a plurality of leads (bonding leads, terminals) 3c formed on the upper surface 17a, and a plurality of lands ( Terminal, electrode) 3d. A solder resist film (upper surface side insulating film) 3f, which is an insulating film, is formed on the upper surface 17a, and the leads 3c and lands 3d are exposed in the plurality of openings 3i. In other words, the surfaces (exposed surfaces) of the leads 3c and lands 3d are exposed from the solder resist film 3f.

  Further, each of the plurality of device forming portions 17c has a lower surface (back surface, mounting surface) 17b opposite to the upper surface 17a and a plurality of lands 3e formed on the lower surface 17b. The plurality of lands 3e are electrically connected to the plurality of leads 3c or the plurality of lands 3d, respectively. Also, a solder resist film (lower surface side insulating film) 3f, which is an insulating film, is formed on the lower surface 17b, and the lands 3e are exposed in each of the plurality of openings 3j. In other words, the surface (exposed surface) of the land 3e is exposed from the solder resist film 3f.

  In each device forming portion 17c, the plurality of lands 3d are disposed closer to the peripheral portion of the device forming portion 17c than the plurality of leads 3c. In other words, as shown in FIG. 2, the plurality of leads 3c are arranged in a region surrounded by the plurality of lands 3d. As shown in FIG. 3, a solder layer 11a is formed on the surface of each lead 3c.

  As shown in FIG. 2, an alignment mark (positioning portion) 17 f is formed on the frame portion 17 e on the surface of the multiple base substrate 17. That is, alignment marks 17 f are provided at four corners of the frame portion 17 e on the surface of the multiple base substrate 17. The alignment mark 17f is made of, for example, a metal pattern, and is not necessarily provided at the four corners of the surface, and may be provided at at least two positions facing each other in the frame portion 17e.

2. In the die bonding step, as shown in FIGS. 4 and 5, first, the back surface 2 b of the semiconductor chip 2 is sucked by the suction tool 20 and transferred onto the device forming portion 17 c on the upper surface 17 a of the multiple base substrate 17. After the conveyance, the suction is stopped and placed on the device forming portion 17c. The semiconductor chip 2 has a plurality of electrode pads (bonding pads, terminals, electrodes) 2c formed on the main surface 2a.

  Thereafter, flip chip connection of the semiconductor chip 2 is performed. That is, on the upper surface 17a of each of the plurality of device forming portions 17c via the plurality of conductive members 11 so that the main surface 2a of the semiconductor chip 2 faces the upper surface 17a of the device forming portion 17c of the multiple base substrate 17. The semiconductor chip 2 is mounted on.

  At this time, the heating tool 21 is pressed against the back surface 2 b of the semiconductor chip 2 through the heat-resistant sheet 22, and the flip chip connecting portion is heated through the semiconductor chip 2. By this heating, the solder layer 11a on each lead 3c of the multiple base substrate 17 is melted, the solder is wetted onto the conductive member 11, and the solder and the conductive member 11 are electrically connected.

  Note that a heat source is embedded in the heating tool 21. Furthermore, since the heating tool 21 must be disposed immediately above the bump so that heat can be applied to the conductive member 11 on the electrode pad 2c of the semiconductor chip 2, the size of the heating tool 21 is made smaller than the chip size. That is not preferable. That is, the size of the heating tool 21 is preferably larger than the outer size of the semiconductor chip 2.

  This completes the die bonding process.

3. Electrode Formation After die bonding, as shown in FIGS. 6 and 7, conductive members 8 are formed on the lands 3d of the multiple base substrate 17, respectively. At this time, the conductive member 8 is positioned on the land 3d by using an arrangement mask for mounting bumps, and then the conductive member 8 is melted by heat treatment such as reflow, whereby a plurality of conductive members 8 are obtained. Are connected to a plurality of lands 3d.

  In the electrode forming process of the present embodiment, the height of each of the plurality of conductive members 8 formed on each of the plurality of lands 3d is the mounting height of the semiconductor chip 2 (the upper surface 17a of the multiple base substrate 17). The respective conductive members 8 are formed so as to be higher than the distance from the surface of the solder resist film 3f formed in the above to the back surface (surface located on the upper side) 2b of the semiconductor chip 2.

  This is to prevent the back surface 2b of the semiconductor chip 2 and the lower surface 5b of the sub-substrate 5 from coming into contact with each other, as shown in FIG. Therefore, the conductive member 8 is formed so that the height T2 of the conductive member 8 is larger than the mounting height T1 of the semiconductor chip 2. Thereby, a gap can be formed between the back surface 2 b of the semiconductor chip 2 and the lower surface 5 b of the sub-substrate 5.

  Therefore, in the present embodiment, a copper core solder bump is employed as the conductive member 8 that connects the base substrate 3 and the sub substrate 5, thereby stably securing the distance between the base substrate 3 and the sub substrate 5. can do.

  Further, when a columnar electrode such as a copper post bump is used as the conductive member 8, the distance between the base substrate 3 and the sub substrate 5 can be stably secured in the same manner.

  Moreover, it is necessary to perform electrode formation after die bonding.

  This is because when the flip chip connection of the semiconductor chip 2 is performed in the die bonding process, the heating tool 21 is pressed against the back surface 2b of the semiconductor chip 2 to perform the flip chip connection, as shown in FIG. This is because the tool 21 is larger than the chip size. That is, if each conductive member 8 is formed on the multiple base substrate 17 before die bonding, the heating tool 21 and the conductive member 8 may come into contact with each other at the time of die bonding, thereby hindering die bonding. Therefore, in the assembly of the present embodiment, electrode formation is performed after die bonding (flip chip connection) is performed.

4). Substrate (Sub) Arrangement After the electrodes are formed, a multiple sub-substrate (wiring substrate) 18 is disposed on the multiple base substrate 17 as shown in FIGS.

  Here, the multiple sub-board 18 having the plurality of sub-boards 5 will be described.

  As shown in FIGS. 8 and 9, the multiple sub-substrate 18 includes a plurality of device forming portions 18 c and a cut portion (removal) provided between the device forming portions 18 c adjacent to each other among the plurality of device forming portions 18 c. Part, dicing part) 18d, and a frame part 18e provided around the plurality of device forming parts 18c in plan view.

  Each of the plurality of device forming portions 18c of the multiple sub-board 18 includes an upper surface (main surface, component mounting surface) 18a and a plurality of lands (terminals, electrodes) 5c formed on the upper surface 18a. Yes. A solder resist film (upper surface side insulating film) 5f, which is an insulating film, is formed on the upper surface 18a, and the lands 5c are exposed in the plurality of openings 5g. In other words, the surface (exposed surface) of the land 5c is exposed from the solder resist film 5f.

  Further, each of the plurality of device forming portions 18c has a lower surface (back surface, mounting surface, chip facing surface) 18b opposite to the upper surface 18a, and a plurality of lands 5d formed on the lower surface 18b. The plurality of lands 5d are electrically connected to the plurality of lands 5c, respectively. Also, a solder resist film (lower surface side insulating film) 5f, which is an insulating film, is formed on the lower surface 18b, and the lands 5d are exposed in the plurality of openings 5h. In other words, the surface (exposed surface) of the land 5d is exposed from the solder resist film 5f.

  Further, as shown in FIG. 9, a sealing material (sealing layer, adhesive layer) 10 is formed on the solder resist film 5 f on the lower surface 18 b of the multiple sub-substrate 18.

  Here, the sealing material 10 used in the present embodiment is a film-like material called NCF (Non-Conductive Film), and is made of, for example, a thermosetting epoxy resin. The sealing material 10 is also an adhesive for fixing the multiple sub-substrate 18.

  The sealing material 10 is formed over the entire lower surface (back surface) 18 b of the multiple sub-substrate 18. The sealing material 10 does not necessarily have to be formed on the entire lower surface 18b of the multiple sub-substrate 18. That is, as long as the sealing material 10 covers at least each of the plurality of device forming portions 18c, a part of the frame portion 18e may be exposed.

  Further, the thickness of the sealing material 10 before bringing the sealing material 10 into contact with the multiple base substrate 17 is larger than the mounting height of the semiconductor chip 2. That is, the thickness T5 of the sealing material 10 in FIG. 9 is larger than the mounting height T1 of the semiconductor chip 2 shown in FIG. 1 (T1 <T5). As an example, T1 = 80 μm and T5 = 180 μm (130 to 230 μm). The thickness T6 of the multiple sub-board 18 is, for example, T6 = 140 μm (100 to 200 μm).

  Thus, the multiple base substrate 17 and the multiple sub-substrate are formed by making the thickness of the sealing material 10 before contacting the multiple base substrate 17 larger (thicker) than the mounting height of the semiconductor chip 2. 18 is connected via the plurality of conductive members 8, the sealing material 10 can be reliably filled between the multiple base substrate 17 and the multiple sub-substrate 18.

  Further, as shown in FIGS. 8 and 9, the relationship between the size of the multiple base substrate 17 and the multiple sub substrate 18 in plan view is the multiple sub substrate 18 <the multiple base substrate 17.

  The sealing material 10 is attached (formed) to the solder resist film 5f formed on the lower surface 18b of the multiple sub-substrate 18 by a vacuum pressing method (vacuum laminating method). That is, in a vacuum atmosphere, the film-like sealing material 10 is attached to the lower surface (back surface, mounting surface) 18b of the multiple sub-board 18 by pressing while applying heat.

  Thereby, it can reduce that a void is formed in the sealing material 10. FIG. Furthermore, the lower surface 10a of the sealing material 10 can be flattened.

  Next, attachment of the multiple base substrate 17 and the multiple sub-substrate 18 will be described.

  First, as shown in FIG. 8, the alignment marks 17f at the four corners of the upper surface 17a of the multiple base substrate 17 are recognized, and the multiple base substrate 17 and the multiple sub-substrate 18 are aligned. As shown in FIG. 2, the multiple sub-substrate 18 is arranged on the upper surface 17 a of the multiple base substrate 17 so that the lower surface 18 b of the multiple sub-substrate 18 faces the upper surface 17 a of the multiple base substrate 17.

  Thereafter, a load (vertical load) is applied to the multiple sub-substrate 18 from above while applying heat to the multiple base substrate 17, the multiple sub-substrate 18 and the sealing material 10 in a vacuum atmosphere.

  Thereby, as shown in FIG. 11, the plurality of conductive members 8 and the plurality of lands 5d on the lower surfaces 18b of the plurality of multiple sub-boards 18 are electrically connected to each other. Further, the sealing material 10 is brought into contact with the upper surface 17 a of the multiple base substrate 17 to seal the gap between the semiconductor chip 2 and the multiple base substrate 17 and the sealing of the semiconductor chip 2 and the plurality of conductive members 8. This is done with material 10. That is, the sealing material 10 is filled between the multiple base substrate 17 and the multiple sub substrate 18, whereby the multiple base substrate 17 and the multiple sub substrate 18 are bonded, and the semiconductor chip 2 The gaps between the multiple base substrates 17, and the uneven portions made up of the semiconductor chip 2 and the plurality of conductive members 8 can be sealed with the sealing material 10.

  In addition, the formation of voids in the sealing material 10 can be reduced by attaching the substrate with the sealing material 10 in a vacuum atmosphere.

  Further, from the mounting height of the semiconductor chip 2 shown in FIG. 1 (distance from the surface of the solder resist film 3f formed on the upper surface 3a of the base substrate 3 to the back surface 2b of the semiconductor chip 2) T1, before the attachment of FIG. Since the thickness T5 of the sealing material 10 is larger (T1 <T5), the sealing material 10 is surely filled into the space between the multiple base substrate 17 and the multiple sub-substrates 18 when the substrate is attached. can do.

  In addition, as described above, the thickness T5 of the sealing material 10 before bonding is larger than the mounting height T1 of the semiconductor chip 2, and the semiconductor chip 2 and the plurality of conductive materials are provided on the multiple base substrate 17. Since the member 8 is mounted, a part of the sealing material 10 protrudes outside (around) the multiple sub-substrates 18 after the substrate is arranged as shown in FIGS. 10 and 11.

  However, since the size of the substrate in plan view is the multiple base substrate 17> the multiple sub-substrate 18, the protruding portion of the sealing material 10 can be disposed at the end of the multiple base substrate 17.

  As shown in FIG. 10, each of the plurality of lands (electrode pads, terminals) 5c electrically connected to the electronic components mounted on the multiple sub-board 18 has a circular planar shape. However, the planar shape of the land 5c may be a square or the like. That is, it is preferable to match the shape of the external terminal of the electronic component to be mounted.

  The base material (sub) arrangement is thus completed.

5. Ball Mount After the substrate (sub) is arranged, the ball mount is performed as shown in FIGS. Here, as shown in FIG. 13, the upper and lower surfaces (front and back surfaces) of the bonded multiple substrates are reversed, and the plurality of external terminals 16 are arranged with the lower surface 17 b of the multiple base substrate 17 facing upward. It is arranged on the land 3e. The external terminal 16 is made of a conductive member. In the present embodiment, the external terminal 16 is, for example, a ball-shaped solder material (solder ball), but the shape is not limited thereto.

  Thereafter, the solder is melted by heat treatment such as a reflow furnace to form the external terminals 16 on the plurality of lands 3e.

6). Individualization After ball mounting, individualization is performed as shown in FIGS. In the singulation process, as shown in FIG. 15, the upper surface 18 a of the multiple sub-board 18 is attached to the dicing sheet 24, and the multiple sub-board 18 side of the multiple boards whose front and back are reversed is separated by the dicing sheet 24. In this state, the dicing blade 23 is rotated and entered from above the lower surface 17b of the multiple base substrate 17 to perform dicing (divided into individual pieces).

  That is, the blade 23 that rotates along the cutting portion 18d of the multiple sub-board 18 (or the cutting portion 17d of the multiple base substrate 17) is caused to travel so that the cutting portion 17d of the multiple base substrate 17 and the multiple sub-board 18 portions 18d and portions of the sealing material 10 that overlap with the cut portions 18d of the multiple sub-boards 18 are removed (cut), and each of the plurality of device forming portions 17c (or the plurality of device forming portions 18c) is removed. Divide into pieces.

  Thereby, the assembly of the lower package 6 is completed.

7). Package Mounting After the assembly of the lower package 6 is completed, the POP 1 shown in FIG. 1 is assembled. Here, the upper package 7, which is another package, is mounted on the lower package 6. The upper package 7 is a semiconductor package on which, for example, a memory semiconductor chip 4 is mounted. The upper package 7 is disposed on the upper surface 5 a of the sub-board 5 of the lower package 6 via a plurality of external terminals (conductive members) 9. The package 7 is mounted. That is, an upper terminal 7 is prepared in which each of the plurality of lands 12d on the lower surface 12b of the package substrate 12 is provided with an external terminal 9 and determined to be non-defective by inspection, and the plurality of external terminals 9 of the upper package 7 are prepared. Are arranged on a plurality of lands 5 c on the upper surface 5 a of the sub-board 5 of the lower package 6. The external terminal 9 is made of a conductive member. In this embodiment, the external terminal 9 is, for example, a ball-shaped solder material (solder ball), but the shape is not limited thereto.

  Thereafter, the plurality of external terminals 9 are melted by heat treatment, whereby the upper package 7 is electrically connected to the lower package 6 via the plurality of external terminals 9.

  Thereby, the assembly of POP1 is completed.

  According to the method for manufacturing the semiconductor device (POP1) of the present embodiment, when the multiple base substrate 17 and the multiple sub-substrate 18 are bonded together, the chip mounting that is previously bonded to the multiple sub-substrate 18 is mounted. Compared to filling the resin between the substrates after bonding the substrates, the film-like sealing material 10 thicker than the height is interposed between the substrates and heat and load (vertical load) are applied and bonded together. Can be reduced.

  Thereby, the void formed in the sealing material 10 can be reduced, and the reliability of the semiconductor device (POP1) can be improved.

  In other words, when the resin is filled between the bonded substrates later, there are many regions with large uneven portions between the substrates because semiconductor chips and multiple ball electrodes are provided, causing voids. Easy to do. However, in this embodiment, when the substrates are bonded together using the sealing material 10 previously bonded to the substrate, the bonding of the substrate and the sealing of the semiconductor chip or the like are performed together. Void entrainment during sealing can be reduced.

  In addition, the sealing method disclosed in [Patent Document 3 (Japanese Patent Laid-Open No. 2012-15546)] of [Prior Art Document] arranges the thermosetting resin sheet between the substrates in advance, and the substrates are arranged from both sides. Heating and pressurizing to form a sealing layer composed of a thermosetting resin sheet between the substrates, but in this case, the thermosetting resin sheet is spread during heating and pressurization, Voids are easily generated above the chip.

  On the other hand, in the manufacturing method of the semiconductor device of the present embodiment, among the substrates to be bonded, the entire surface of one substrate (however, a part of the frame portion 18e may be exposed) is a film shape. Since the substrates are bonded together with the sealing material 10 attached, generation of voids due to entrainment can be suppressed. Furthermore, the generation of local voids can be suppressed.

  As a result, the reliability of the semiconductor device (POP1) can be improved.

  Further, in assembling the POP 1, since the lower package 6 and the upper package 7 mounted on the lower package 6 use packages determined to be non-defective by inspection, the yield of each package can be eliminated. , The yield of POP1 (product) can be improved.

<Modification>
As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments of the invention. However, the present invention is not limited to the embodiments of the invention, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

(Modification 1)
In the above embodiment, the case where the semiconductor device is POP1 (a package in which the upper package 7 is mounted on the lower package 6) shown in FIG. 1 has been described. However, the semiconductor device includes the upper package 7 ( Only the lower package 6 that is not stacked may be a finished product (semiconductor device).

(Modification 2)
In the above embodiment, in assembling the semiconductor device, the conductive member (conductive member) 8 that electrically connects the base substrate 3 and the sub-substrate 5 is formed on the base substrate 3 when the substrates are bonded together. Although the method has been described, the conductive member may be formed on the sub-substrate 5 (see FIG. 19 described later).

(Modification 3)
16 is a plan view before placement of a sub-base material used in assembling the lower semiconductor package of the semiconductor device of Modification 3 of the embodiment, and FIG. 17 is a cross-sectional view taken along the line AA shown in FIG. It is.

  In the above embodiment, when the multiple base substrate 17 and the multiple sub substrate 18 are bonded together in the assembly of the semiconductor device, the sealing material (sealing layer, adhesive layer) 10 is formed on the multiple sub substrate 18 side. However, the sealing material 10 may be disposed on the multiple base substrate 17 as shown in FIG.

  As a result, when the multiple base substrate 17 and the multiple sub-substrate 18 are bonded together, there is no gap as compared with the case where the sealing material 10 is bonded to the multiple sub-substrate 18 as in the above embodiment. The sealing material 10 can be affixed.

  This is because the semiconductor chip 2 and the plurality of conductive members (conducting members) 8 are provided on the multiple base substrate 17, so that a plurality of relatively large irregularities are formed compared to the multiple sub-substrate 18. In the multiple base substrate 17, voids are easily formed.

  In the case of the above-described embodiment, the surface of the sealing material 10 after being attached to the multiple sub-substrate 18 has high flatness, but the conductive member 8 and the semiconductor chip 2 are formed with unevenness by heat and load. Since the sealing material 10 is bonded to the multiple base substrate 17, there is a possibility that voids are generated.

  Therefore, in order to suppress the generation of voids as much as possible, it is preferable that the sealing material 10 is attached in advance to the base substrate 3 side in a vacuum environment as shown in FIG. That is, as shown in FIGS. 16 and 17, the sealing material 10 having a thickness larger than the mounting height of the semiconductor chip 2 is disposed in advance on the upper surface 17 a of the multiple base substrate 17, and further a vacuum environment (vacuum) The sealing material 10 is brought into contact with the upper surface 17a of the multiple base substrate 17 by a pressing method, and the semiconductor chip 2 and the plurality of conductive members 8 are sealed with the sealing material 10. Air is extracted from the stopper 10. By bonding the multiple sub-substrates 18 to the multiple base substrate 17 in this state, the air entrained at the time of bonding can also be reduced, and the multiple base substrate 17 having many lower unevennesses can be reduced. Void countermeasures are taken more reliably.

  Furthermore, the sealing material 10 is pressed in a vacuum environment (vacuum press system), and this sealing material 10 is attached to the multiple base substrate 17 to face the upper surface of the sealing material 10 (the multiple sub-substrate 18 is opposed). The flatness of the surface) can also be improved.

  Thereby, generation | occurrence | production of a void can be suppressed also in adhesion | attachment with the multiple sub board | substrate 18, and the adhesiveness with the multiple sub board | substrate 18 of the sealing material 10 can be raised.

(Modification 4)
18 is a plan view before placement of a sub-base material used in assembling the lower semiconductor package of the semiconductor device of Modification 4 of the embodiment, and FIG. 19 is a cross-sectional view taken along the line AA shown in FIG. It is.

  In Modification 4 shown in FIG. 18 and FIG. 19, a plurality of semiconductor chips 2 mounted on the multiple base substrate 17 are covered with the sealing material 10 in a vacuum environment (vacuum press method), and the multiple sub-substrate 18. A plurality of conductive members (conducting members) 8 are formed on the side, and then multiple sub-substrates 18 are arranged on the multiple base substrate 17.

  However, in the case of the method of the modification example 4, since the protruding conductive member 8 is inserted into the sealing material 10, it is easy to entrap a void in the sealing material 10. Therefore, when the countermeasure against voids is taken into consideration, the method of Modification 3 is preferable.

(Modification 5)
20 is a plan view before placement of a sub-base material used in assembling the lower semiconductor package of the semiconductor device of Modification 5 of the embodiment, and FIG. 21 is a cross-sectional view taken along the line AA shown in FIG. FIG. 22 is a plan view after placement of the sub-base material used in assembling the lower semiconductor package of the semiconductor device of Modification 5 of the embodiment, and FIG. 23 is a cross-sectional view taken along the line AA shown in FIG. FIG.

  Modification 5 shown in FIGS. 20 to 23 uses a sub-substrate 5 that has been separated into pieces on the sub-substrate side in assembling a semiconductor device. That is, as shown in FIGS. 20 and 21, in each device forming portion 17c, each device forming portion 17c of the multiple base substrate 17 provided with the semiconductor chip 2 and the plurality of conductive members (conducting members) 8 is provided. On the top, the sub-substrates 5 that are pre-divided and formed with the individual sealing material 10 are disposed on the lower surface 5b.

  Thereafter, as shown in FIG. 22 and FIG. 23, the plurality of divided sub-substrates 5 are pasted (adhered) to the respective device forming portions 17 c of the multiple base substrate 17 through the individual sealing materials 10. In addition, the semiconductor chip 2 and the plurality of conductive members 8 are sealed.

  Note that the height relationship between the semiconductor chip 2 and the plurality of conductive members 8 provided on the multiple base substrate 17, the thickness of the sealing material 10 on the sub-substrate 5 side, and the method of attaching to the base substrate 3, Furthermore, the method for attaching each sub-substrate 5 on the multiple base substrate 17 and the method for dividing the multiple base substrate 17 are the same as those described in the above embodiment. A duplicate description is omitted.

  As described above, in assembling the semiconductor device, by using a plurality of sub-substrates 5 separated in advance on the base substrate side, when the multiple base substrates 17 and the sub-substrates 5 are bonded together, they are separated into individual pieces. The formed sub-board 5 has a far shorter distance for air to escape than the larger multi-sub-board 18, so that voids are less likely to be formed than the multi-sub-board 18.

  That is, as in the fifth modification, assembling a semiconductor device using the sub-substrate 5 that has been separated into pieces in advance can reduce voids formed in the sealing material 10.

  Furthermore, in the case of assembling using the sub-substrate 5 separated in advance, only the non-defective substrate can be used on the sub-substrate side, so that the yield of the semiconductor device can be improved.

  However, when considering the efficiency of the assembly work, the efficiency of the assembly work is improved by using the multiple substrates (the multiple base substrates 17 and the multiple sub-substrates 18) on the upper and lower sides as in the above embodiment. In this case, the assembling method of the above embodiment is more advantageous.

  In addition, when using what the sub-board | substrate 5 is separated into pieces, since the void | hole omission is good as mentioned above, the sealing material (sealing layer, adhesive layer) 10 is not restricted to a film form, A paste-like material may be used.

  Furthermore, when the paste-like sealing material 10 is used, the electrical connection of the semiconductor chip 2 to the substrate is not limited to flip chip connection, and wire connection may be employed. However, when the generation of voids is taken into consideration, it is preferable to use the film-like sealing material 10 as in the above embodiment.

  Further, in the case of the fifth modification, as shown in FIG. 20, a large number of alignment marks 17 f are provided so as to correspond to the individual sub-substrates 5. That is, it is provided at each corner portion corresponding to each device forming portion (each device region) 17 c of the multiple base substrate 17.

  As a result, even when the sub-boards 5 separated into individual pieces are used, when the sub-boards 5 and the multiple base boards 17 are bonded together, the alignment marks 17f are recognized and aligned before being pasted. Can be matched.

(Modification 6)
24 is a cross-sectional view showing the structure of a semiconductor device according to Modification 6 of the embodiment, and FIG. 25 is a cross-sectional view showing the structure of another semiconductor device according to Modification 6 of the embodiment.

  Modification 6 of FIG. 24 shows a case where a column (projection) electrode 25 is used as a conductive member (conductive member) for electrically connecting the base substrate 3 and the sub-substrate 5. The electrode 25 is electrically connected to the land 3d of the base substrate 3 through the solder material 25a. The electrode 25 is a column (projection) electrode and is made of, for example, an alloy containing copper as a main component. The horizontal cross-sectional shape of the columnar electrode is circular or polygonal, but in consideration of the stress applied to the electrode, a circular shape (cylindrical electrode) is preferable. Since it is columnar, the electrode height can be secured stably.

  Therefore, according to POP1 shown in FIG. 24, by using the columnar electrode 25 as the conductive member, the distance between the base substrate 3 and the sub-substrate 5 can be made in-plane uniform. However, it does not necessarily have a columnar shape, and may have a protruding shape as long as the height can be ensured.

  FIG. 25 shows a sixth modification in which a ball-shaped electrode (solder ball) 26 is used as the conductive member. However, when the electrode 26 is employed, it is necessary to increase the ball diameter in order to ensure the height. Therefore, when considering the increase in the number of pins and the reduction in pitch, it is preferable to employ a core ball (bump) such as a copper core solder bump or the columnar electrode as described in the above embodiment. In the core solder ball (bump), the core member is a ball-shaped member made of metal, the surface of the metal ball (metal core) is covered with a solder film, and the metal ball is provided inside the solder film. Therefore, the height of the electrode can be ensured similarly to the columnar electrode.

(Modification 7)
FIG. 26 is a cross-sectional view showing the structure of a semiconductor device according to Modification 7 of the embodiment.

  For example, in the above embodiment, it has been described that the upper package (electronic component) 7 having the memory semiconductor chip 4 is mounted on the sub-substrate 5 of the lower package 6. It is not limited to. That is, instead of the upper package 7, resistors, capacitors, and electronic components (chip components) such as vibrators may be mounted.

  In addition, as shown in Modification 7 of FIG. 26, a POP 29 or the like on which a plurality of electronic components (for example, an electronic component or a semiconductor package having a memory semiconductor chip 4) 27 and a chip component 28 are mounted. Also good. In the POP 29, the electronic component 27 is mounted on the sub-board 5 of the lower package 6 via the external terminal 9, and the chip component 28 is further mounted via the solder material 28a.

(Modification 8)
In the above embodiment, when the alignment mark 17f is formed on the multiple base substrate 17 as a positioning mark (positioning part) when the multiple base substrate 17 and the multiple sub-substrate 18 are bonded together. However, not only the alignment mark 17f but also a positioning pin or the like may be used. In other words, positioning pins may be formed on one of the substrates, and the holes for inserting the pins may be provided on the other substrate, thereby aligning the pins.

  However, in the case of the above-described modified example 5, a space for providing pins or holes is required in each sub-substrate 5, and in the case of the above-described modified example 5, an alignment mark 17f is formed on the multiple base substrate 17. It is preferable to perform alignment by recognizing the alignment mark 17f.

(Modification 9)
In the above embodiment, the mounting of the semiconductor device on the mounting substrate (motherboard) using the solder material that does not substantially contain lead (Pb) has been described. However, the solder material containing lead (Pb) is used. May be used. However, considering environmental pollution measures, it is preferable to use a solder material that does not substantially contain lead (Pb). Here, solder that does not substantially contain lead, so-called lead-free solder, means that the content of lead (Pb) is 0.1 wt% or less, and this content is defined by RoHS (Restriction of Hazardous Substances). ) It is defined as a standard for the directive. The solder material is a solder material used for the copper core solder bump, the solder film 8b, the external terminals 9 and 16, the solder layer 11a, the solder materials 25a and 28a, the electrode 26, and the like.

(Modification 10)
Furthermore, the modified examples can be applied in combination within a range not departing from the gist of the technical idea described in the above embodiment.

In addition, a part of the contents described in the embodiment will be described below.
(Claim 1)
A semiconductor device manufacturing method including the following steps:
(A) a plurality of first device forming portions, a first cutting portion provided between first device forming portions adjacent to each other among the plurality of first device forming portions, and the plurality of first in plan view Preparing a first wiring board having a first frame portion provided around the device forming portion and a plurality of second wiring boards each having one second device forming portion;
here,
Each of the plurality of first device forming portions includes a first upper surface, a plurality of first bonding leads formed on the first upper surface, a plurality of first bonding leads formed on the first upper surface, and A plurality of first upper surface lands electrically connected to each other, and a plurality of first bonding leads and a plurality of first upper surface lands formed on the first upper surface so as to be exposed. A plurality of first lower surface sides formed on the first lower surface and electrically connected to the plurality of first bonding leads, respectively, on the upper surface side insulating film, the first lower surface opposite to the first upper surface, and A land, and a first lower surface side insulating film formed on the first lower surface so that each of the plurality of first lower surface side lands is exposed,
The second device forming portion of each of the plurality of second wiring boards includes a second upper surface, a plurality of second upper surface side lands formed on the second upper surface, and a plurality of second upper surface side lands. A second upper surface insulating film formed on the second upper surface so as to be exposed, a second lower surface opposite to the second upper surface, the second lower surface, and the plurality of second surfaces. A plurality of second lower surface side lands electrically connected to the upper surface side lands, respectively, and a second lower surface side insulating film formed on the second lower surface so that each of the plurality of second lower surface side lands is exposed. And a sealing material formed on the second lower surface side insulating film,
(B) After the step (a), a first main surface, a plurality of first bonding pads formed on the first main surface, and a first back surface opposite to the first main surface. Mounting a semiconductor chip on the first upper surface of each of the plurality of first device forming portions;
(C) After the step (b), a step of forming a plurality of conductive members on each of the plurality of first upper surface lands;
here,
Each of the plurality of conductive members formed on each of the plurality of first upper surface lands is higher than a mounting height of the first semiconductor chip,
(D) After the step (c), the plurality of second wiring boards are arranged on the first upper surface of each of the plurality of first device forming portions of the first wiring board, and the first wiring board Each of the plurality of conductive members and the plurality of second wiring substrates by applying a load to the plurality of second wiring substrates while applying heat to the plurality of second wiring substrates and the plurality of sealing materials. The plurality of second lower surface side lands are electrically connected to each other, the plurality of sealing materials are brought into contact with the first upper surface of the first wiring board, and the first semiconductor chip and the plurality of conductive materials Sealing the conductive member;
here,
Each thickness of the plurality of sealing materials before bringing the plurality of sealing materials into contact with the first wiring substrate is larger than the mounting height of the first semiconductor chip,
(E) After the step (d), a step of removing the first cut portion of the first wiring board and a portion overlapping with the first cut portion of each of the plurality of sealing materials.

1 POP
2 Semiconductor chip 2a Main surface (surface, upper surface)
2b Back side (lower side)
2c Electrode pads (bonding pads, terminals, electrodes)
3 Base board (wiring board)
3a Top surface (surface, chip mounting surface)
3b Lower surface (back surface, mounting surface)
3c Lead (bonding lead, terminal)
3d, 3e Land (terminal, electrode)
3f Solder resist film 3g Wiring part (wiring)
3h Insulating layer 3i, 3j Opening 4 Semiconductor chip 4a Main surface (surface, upper surface)
4b Back side (lower side)
4c Electrode pad (bonding pad)
5 Sub-board (wiring board)
5a Top surface (surface, electronic component mounting surface)
5b Bottom (back)
5c, 5d Land (terminal, electrode)
5e Insulating layer 5f Solder resist film 5g, 5h Opening 6 Lower package 7 Upper package 8 Conductive member (conductive member)
8a Core material (electrode, metal core, conductive member)
8b Solder film (conductive member)
9 External terminal (conductive member)
10 Sealing material (sealing layer, adhesive layer)
10a Lower surface 11 Conductive member (columnar electrode, protruding electrode)
11a Solder layer 12 Package substrate (wiring substrate)
12a Top surface (surface, chip mounting surface)
12b Bottom (back)
12c Lead (bonding lead, terminal)
12d land (terminal, electrode)
12e Insulating layer 12f Solder resist film 12g, 12h Opening 13 Die bonding material 14 Sealing body 15 Wire 16 External terminal 17 Multiple base substrate 17a Upper surface 17b Lower surface 17c Device forming portion 17d Cutting portion (removal portion, dicing portion)
17e Frame portion 17f Alignment mark (metal pattern)
18 Multiple Sub-Substrate 18a Upper Surface 18b Lower Surface 18c Device Forming Section 18d Cutting Section 18e Frame 20 Adsorption Tool 21 Heating Tool 22 Heat Resistant Sheet 23 Blade 24 Dicing Sheet 25 Electrode 25a Solder Material 26 Electrode 27 Electronic Component 28 Chip Component 28a Solder Material 29 POP

Claims (9)

A semiconductor device manufacturing method including the following steps:
(A) a plurality of first device forming portions, a first cutting portion provided between first device forming portions adjacent to each other among the plurality of first device forming portions, and the plurality of first in plan view A first wiring board having a first frame portion provided around the device forming portion, a plurality of second device forming portions, and a second device forming portion adjacent to each other among the plurality of second device forming portions. A step of preparing a second cutting board provided therebetween, and a second wiring board provided with a second frame provided around the plurality of second device forming parts in plan view;
here,
Each of the plurality of first device forming portions includes a first upper surface, a plurality of first bonding leads formed on the first upper surface, a plurality of first bonding leads formed on the first upper surface, and A plurality of first upper surface lands electrically connected to each other, and a plurality of first bonding leads and a plurality of first upper surface lands formed on the first upper surface so as to be exposed. A plurality of first lower surface sides formed on the first lower surface and electrically connected to the plurality of first bonding leads, respectively, on the upper surface side insulating film, the first lower surface opposite to the first upper surface, and A land, and a first lower surface side insulating film formed on the first lower surface so that each of the plurality of first lower surface side lands is exposed,
Each of the plurality of second device forming portions is configured to expose the second upper surface, the plurality of second upper surface side lands formed on the second upper surface, and the plurality of second upper surface side lands. The second upper surface side insulating film formed on the second upper surface, the second lower surface opposite to the second upper surface, and the second upper surface side lands formed on the second lower surface and electrically A plurality of second lower surface lands that are connected to each other, a second lower surface side insulating film formed on the second lower surface so that each of the plurality of second lower surface lands is exposed, and the second lower surface And a sealing material formed on the side insulating film,
(B) After the step (a), a first main surface, a plurality of first bonding pads formed on the first main surface, and a first back surface opposite to the first main surface. Mounting a semiconductor chip on the first upper surface of each of the plurality of first device forming portions;
(C) After the step (b), a step of forming a plurality of conductive members on each of the plurality of first upper surface lands;
here,
Each of the plurality of conductive members formed on each of the plurality of first upper surface lands is higher than a mounting height of the first semiconductor chip,
(D) After the step (c), the second wiring board is placed on the first wiring board so that the second lower surface of the second wiring board faces the first upper surface of the first wiring board. The plurality of conductive members and the plurality of conductive members are disposed on the first upper surface and apply a load to the second wiring substrate while applying heat to the first wiring substrate, the second wiring substrate, and the sealing material. The second lower surface side lands are electrically connected to each other, the sealing material is brought into contact with the first upper surface of the first wiring board, and the first semiconductor chip and the plurality of conductive members are sealed. Sealing with a sealing material;
here,
The thickness of the sealing material before bringing the sealing material into contact with the first wiring substrate is larger than the mounting height of the first semiconductor chip,
(E) After the step (d), the first cutting part of the first wiring board, the second cutting part of the second wiring board, and the second cutting part of the sealing material overlap. Removing the portion. In the manufacturing method of the semiconductor device according to claim 1,
In the step (a), the sealing material is formed on the entire surface of the second lower surface of the second wiring board. In the manufacturing method of the semiconductor device according to claim 2,
The method for manufacturing a semiconductor device, wherein the sealing material is formed by pressing the second lower surface of the second wiring board. In the manufacturing method of the semiconductor device according to claim 3,
The step (d) is a method for manufacturing a semiconductor device, which is performed in a vacuum atmosphere. In the manufacturing method of the semiconductor device according to claim 4,
The method for manufacturing a semiconductor device, wherein the conductive member is a ball electrode or a columnar electrode in which a metal core is covered with a solder film. In the manufacturing method of the semiconductor device according to claim 5,
A method for manufacturing a semiconductor device, wherein a positioning portion is formed on the first wiring board. A semiconductor device manufacturing method including the following steps:
(A) a plurality of first device forming portions, a first cutting portion provided between first device forming portions adjacent to each other among the plurality of first device forming portions, and the plurality of first in plan view A first wiring board having a first frame portion provided around the device forming portion, a plurality of second device forming portions, and a second device forming portion adjacent to each other among the plurality of second device forming portions. A step of preparing a second cutting board provided therebetween, and a second wiring board provided with a second frame provided around the plurality of second device forming parts in plan view;
here,
Each of the plurality of first device forming portions includes a first upper surface, a plurality of first bonding leads formed on the first upper surface, a plurality of first bonding leads formed on the first upper surface, and A plurality of first upper surface lands electrically connected to each other, and a plurality of first bonding leads and a plurality of first upper surface lands formed on the first upper surface so as to be exposed. A plurality of first lower surface sides formed on the first lower surface and electrically connected to the plurality of first bonding leads, respectively, on the upper surface side insulating film, the first lower surface opposite to the first upper surface, and A land, and a first lower surface side insulating film formed on the first lower surface so that each of the plurality of first lower surface side lands is exposed,
Each of the plurality of second device forming portions is configured to expose the second upper surface, the plurality of second upper surface side lands formed on the second upper surface, and the plurality of second upper surface side lands. The second upper surface side insulating film formed on the second upper surface, the second lower surface opposite to the second upper surface, and the second upper surface side lands formed on the second lower surface and electrically And a plurality of second lower surface side lands connected to each other, and a second lower surface side insulating film formed on the second lower surface so that each of the plurality of second lower surface side lands is exposed,
(B) After the step (a), a first main surface, a plurality of first bonding pads formed on the first main surface, and a first back surface opposite to the first main surface. Mounting a semiconductor chip on the first upper surface of each of the plurality of first device forming portions;
(C) After the step (b), a step of forming a plurality of conductive members on each of the plurality of first upper surface lands;
here,
Each of the plurality of conductive members formed on each of the plurality of first upper surface lands is higher than a mounting height of the first semiconductor chip,
(D) After the step (c), a sealing material having a thickness larger than the mounting height of the first semiconductor chip is disposed on the first upper surface of the first wiring board, and further, the sealing Bringing a material into contact with the first upper surface of the first wiring substrate and sealing the first semiconductor chip and the plurality of conductive members with the sealing material;
here,
The step (d) is performed in a vacuum atmosphere,
(E) After the step (d), the second wiring board is placed on the first wiring board so that the second lower surface of the second wiring board faces the first upper surface of the first wiring board. The plurality of conductive members and the plurality of conductive members are disposed on the first upper surface and apply a load to the second wiring substrate while applying heat to the first wiring substrate, the second wiring substrate, and the sealing material. Electrically connecting the second lower surface-side lands, and bringing the sealing material into contact with the second lower surface of the second wiring board;
(F) After the step (e), the first cutting part of the first wiring board, the second cutting part of the second wiring board, and the second cutting part of the sealing material overlap. Removing the portion. In the manufacturing method of the semiconductor device according to claim 7,
In the step (d), the method for manufacturing a semiconductor device further comprises pressing the sealing material. In the manufacturing method of the semiconductor device according to claim 8,
The method for manufacturing a semiconductor device, wherein the conductive member is a ball electrode or a columnar electrode in which a metal core is covered with a solder film.

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