JP2014146649A - Method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the reliability of a semiconductor device.SOLUTION: A sealing material 10 is arranged on an upper surface 17a including a chip mounting region, of a multi-piece substrate 17 to cover respective surfaces of a plurality of pre-stack lands 3d with the sealing material 10. Semiconductor chips 2 each having a plurality of conductive members 11 formed on a plurality of electrode pads 2c are arranged on the chip mounting region of the multi-piece substrate 17. The plurality of conductive members 11 and a plurality of leads 3c are electrically connected via a solder layer 11a. Further, a flip-chip bonding part 5 of the plurality of conductive members 11 and the plurality of leads 3c is sealed with the sealing material 10. Thereafter, a surface of the plurality of pre-stack lands 3d is exposed.

Description

  The present invention relates to a semiconductor device and its manufacturing technology, and more particularly to an electronic device and its manufacturing technology, and more particularly to a technology effective when applied to a semiconductor device in which a semiconductor chip is mounted on a wiring substrate via a sealing material. It is.

  A structure of a stacked semiconductor device in which a semiconductor element is flip-chip connected to a substrate and underfill resin is filled between the substrate and the semiconductor element is disclosed in, for example, Japanese Patent Application Laid-Open No. 2008-166373 (Patent Document 1). Has been.

JP 2008-166373 A

  The inventor arranges (stacks and mounts) another semiconductor device (assembly, semiconductor package) on a certain semiconductor device (assembly, semiconductor package) as shown in FIG. We are considering lowering the so-called POP (Package On Package) mounting height.

  As a means for reducing the mounting height of the POP, for example, it is conceivable to reduce the thickness of the wiring board (interposer board) to be used.

  However, if the thickness of the wiring board is reduced, the mounting height of the POP can be kept within a desired height range, but the rigidity (strength) of the wiring board is lowered.

  Here, the expansion coefficient of the semiconductor chip mounted on the wiring board is different from the expansion coefficient of the wiring board. For this reason, for example, if the thickness of the wiring board of the semiconductor device disposed on the lower stage side is reduced (for example, 0.3 mm or less), the rigidity of the wiring board is reduced, so that the completed lower side semiconductor device (lower package) Is warped. As a result, it becomes difficult to dispose a semiconductor device (upper package) disposed on the upper stage side than the semiconductor device disposed on the lower stage side.

  An object of the embodiment disclosed in the present application is to provide a technique capable of improving the reliability of a semiconductor device.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  According to one embodiment, a method of manufacturing a semiconductor device includes a step of preparing a wiring board, and a sealing material is disposed on a first surface including a chip mounting region of the wiring board to seal each surface of a plurality of first lands. A step of covering with a stopping material. Furthermore, a semiconductor chip having a plurality of protruding electrodes formed on a plurality of electrodes is arranged on the chip mounting region of the wiring board, and the plurality of protruding electrodes and a plurality of leads are electrically connected via a solder material. And a step of sealing the joint portions of the plurality of protruding electrodes and the plurality of leads with a sealing material, and a step of exposing the respective surfaces of the plurality of first lands.

  According to the one embodiment, the reliability of the semiconductor device can be improved.

1A and 1B are a cross-sectional view and an enlarged partial cross-sectional view illustrating an example of a structure of an electronic device according to an embodiment. It is a top view of the wiring board used by the assembly of the lower package of the electronic device shown in FIG. It is sectional drawing along the AA line shown in FIG. It is a top view which shows an example of the structure at the time of sealing material arrangement | positioning of the assembly of the lower stage package of the electronic device shown in FIG. It is sectional drawing along the AA line shown in FIG. It is a top view which shows an example of the structure at the time of die bonding of the assembly of the lower stage package of the electronic device shown in FIG. It is sectional drawing along the AA line shown in FIG. It is a top view which shows an example of the structure at the time of opening formation of the assembly of the lower package of the electronic device shown in FIG. It is sectional drawing along the AA line shown in FIG. It is a top view which shows an example of the structure at the time of external terminal formation of the assembly of the lower stage package of the electronic device shown in FIG. It is sectional drawing along the AA line shown in FIG. It is a top view which shows an example of the structure at the time of individualization of the assembly of the lower package of the electronic device shown in FIG. It is sectional drawing along the AA shown in FIG. It is sectional drawing which shows an example of the structure at the time of the package arrangement | positioning in the socket in the test process of the assembly of the lower package of the electronic device shown in FIG. It is sectional drawing which shows an example of the structure at the time of the package accommodation in the socket shown in FIG. It is sectional drawing which shows an example of the method of mounting an upper stage package on the lower stage package shown in FIG. It is sectional drawing which shows the structure of the electronic device of the modification 1 of embodiment. It is a top view which shows the structure at the time of sealing material arrangement | positioning of the assembly of the lower stage package of the electronic device of the modification 2 of embodiment. It is sectional drawing along the AA line shown in FIG. It is a top view which shows the structure after the die bonding of the assembly of the lower stage package of the electronic device of the modification 3 of an embodiment. It is an expanded sectional view which shows the structure of one device formation part in the AA line shown in FIG. It is a top view which shows the structure at the time of die bonding of the assembly of the lower package of the electronic device of the modification 4 of an embodiment. It is an expanded sectional view which shows the structure of one device formation part in the AA line shown in FIG. It is sectional drawing which shows the structure at the time of accommodation in the socket of the lower stage package shown in FIG. It is a top view which shows the structure at the time of die bonding of the assembly of the lower stage package of the electronic device of the modification 5 of embodiment. FIG. 26 is an enlarged cross-sectional view illustrating a structure of one device forming unit along line AA illustrated in FIG. 25. It is sectional drawing which shows the structure at the time of accommodation in the socket of the lower package shown in FIG. It is sectional drawing which shows the structure of the semiconductor device of the modification 7 of embodiment.

  In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  Further, in the following embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments, but they are not irrelevant to each other unless otherwise specified. The other part or all of the modifications, details, supplementary explanations, and the like are related.

  Also, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), particularly when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and it may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps) are not necessarily indispensable unless otherwise specified and clearly considered essential in principle. Needless to say.

  Further, in the following embodiments, regarding constituent elements and the like, when “consisting of A”, “consisting of A”, “having A”, and “including A” are specifically indicated that only those elements are included. It goes without saying that other elements are not excluded except in the case of such cases. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. Further, even a plan view may be hatched for easy understanding of the drawing.

(Embodiment)
<Electronic device>
1A and 1B are a cross-sectional view and an enlarged partial cross-sectional view illustrating an example of the structure of an electronic device according to an embodiment.

  The electronic device shown in FIG. 1 is a POP (package on package) type electronic device (hereinafter simply referred to as a POP) in which a semiconductor package on which another semiconductor chip is mounted is mounted or stacked on a semiconductor package on which a semiconductor chip is mounted. Say).

  A POP 1 according to the present embodiment shown in FIG. 1 includes a lower package 6 that is a semiconductor device on which a semiconductor chip 2 is mounted, and an upper package 7 that is a semiconductor device on which another semiconductor chip 4 is mounted. The system is configured by electrically connecting the package substrate (wiring substrate) 3 of the package 6 and the package substrate (wiring substrate) 12 of the upper package 7 via a conductive member. Therefore, POP1 is also an electronic device and can also be called a semiconductor system.

  The POP 1 is mounted on a mounting substrate such as a mother board of an external electronic device via an external terminal 16 provided on the lower surface side of the package substrate 3 of the lower package 6, for example. The plurality of external terminals 16 of the POP 1 are, for example, solder balls, but the shape / material is not limited thereto.

  In the POP 1 of the present embodiment, the semiconductor chip 4 mounted on the upper package 7 is, for example, a memory semiconductor chip, while the semiconductor chip 2 mounted on the lower package 6 is, for example, an upper memory system chip. Although it is a logic type semiconductor chip that controls the semiconductor chip 4, the function of each semiconductor chip is not limited to these.

<Semiconductor device (lower package)>
The lower package 6 includes a package substrate 3, also called a base material, a semiconductor chip 2 flip-chip mounted on the package substrate 3, a sealing material 10 for sealing the semiconductor chip 2, and a plurality of external terminals 16. doing.

  That is, the semiconductor chip 2 is flip-chip mounted on the upper surface (chip mounting surface, main surface) 3 a of the package substrate 3, and further, on the upper surface 3 a side of the package substrate 3, the semiconductor chip 2, the semiconductor chip 2 and the package substrate 3 The flip chip joint 5 is sealed with a sealing material 10.

  Here, the package substrate 3 is a multilayer wiring substrate having a four-layer wiring layer structure manufactured by, for example, a build-up method, and includes an upper surface 3a having a square planar shape and a lower surface (mounting surface) opposite to the upper surface 3a. , Back surface) 3b. The upper surface 3 a is provided with a plurality of leads (bonding leads, electrodes, terminals) 3 c and a plurality of prestack lands (terminals, electrodes) 3 d for connection to the upper package 7. Is arranged outside the plurality of leads 3c.

  Further, a solder resist film 3f, which is an insulating film, is formed on the surface layer of the upper surface 3a, and the leads 3c and the prestack lands 3d are exposed in the plurality of openings 3i.

  On the other hand, a plurality of lands 3e to which a plurality of external terminals 16 are connected are provided on the lower surface 3b. A solder resist film 3f, which is an insulating film, is also formed on the surface layer of the lower surface 3b, and the lands 3e are exposed in each of the plurality of openings 3j.

  The plurality of lands 3e include a plurality of lands 3ea arranged at positions inside the plurality of prestack lands 3d and a plurality of lands arranged at positions below the plurality of prestack lands 3d in plan view. There are 3eb.

  Further, inside the package substrate 3 having a multilayer wiring structure, there is a wiring portion (wiring) 3g for electrically connecting the lead 3c or prestack land 3d on the upper surface 3a side and the land 3e on the lower surface 3b side to the insulating layer 3h. Is provided.

  In the lower package 6, the semiconductor chip 2 is flip-chip bonded to the leads 3 c on the upper surface 3 a of the package substrate 3 via the conductive member 11. That is, a plurality of electrode pads (bonding pads, terminals, electrodes) 2c provided on the main surface (element formation surface, surface, upper surface) 2a of the semiconductor chip 2 and a plurality of leads 3c on the upper surface 3a of the package substrate 3 are provided. Are electrically connected through a plurality of conductive members 11. Here, the conductive member 11 is, for example, a copper post bump.

  The copper post bump is a columnar or projecting electrode mainly composed of copper, but the columnar electrode may be made of a metal other than copper, and may be an electrode made of a columnar metal. Further, the flip chip bonding electrode is not limited to a columnar electrode such as a copper post bump, but may be a solder bump, a gold bump, or the like.

  As a detailed configuration of the semiconductor chip 2, for example, a plurality of semiconductor elements (transistors) are formed on a main surface of a semiconductor substrate made of silicon (Si), and a plurality of wiring layers and a plurality of insulating layers are formed on the main surface. Are provided, and the plurality of electrode pads 2c are formed of a part of the uppermost wiring layer among the plurality of wiring layers. Therefore, the main surface 2a of the semiconductor chip 2 in the present embodiment includes the surface on which the plurality of electrode pads 2c are formed.

  As shown in the enlarged partial sectional view of FIG. 1, in the flip chip bonding portion 5, the solder layer 11 a formed on each lead 3 c and the conductive member 11 formed on the electrode pad 2 c of the semiconductor chip 2. Electrically connected.

  In the lower package 6, a sealing material 10 that seals the semiconductor chip 2 and protects the flip chip bonding portion 5 is disposed on the entire upper surface 3 a of the package substrate 3. The sealing material 10 is, for example, a thermosetting resin.

  The sealing material 10 includes a stepped portion 10a that is disposed around the side surface of the semiconductor chip 2 and that is thick at the same height as the back surface (surface opposite to the main surface 2a) 2b of the semiconductor chip 2. Yes. That is, the thickness of the sealing material 10 is different between the periphery of the side surface of the semiconductor chip 2 and the peripheral edge portion of the substrate on which the prestack land 3d is disposed, and a plurality of pre-filling materials 10 are provided as compared with the step portion 10a. The sealing material 10 in the region where the stack land 3d is formed is formed much thinner. Further, an opening is formed on the prestack land 3d of the sealing material 10, and the prestack land 3d is exposed in each of the openings 10b shown in FIG.

  Further, the sealing material 10 is also disposed in a space between the main surface 2a of the semiconductor chip 2 and the upper surface 3a of the package substrate 3, whereby the semiconductor chip 2 is bonded and the flip chip bonding portion 5 is bonded. Is protecting.

  Since the lower package 6 has the sealing material 10 disposed on the upper surface 3a of the package substrate 3 over the entire surface, the rigidity of the package substrate 3 is enhanced. As a result, the warpage of the lower package 6 is reduced. It can be reduced.

<Semiconductor device (upper package)>
In the upper package 7, the semiconductor chip 4 is mounted on the upper surface (surface, chip mounting surface) 12 a of the package substrate 12 via the die bonding material 13. Since the semiconductor chip 4 is wire-connected to the package substrate 12, the semiconductor chip 4 is mounted with its main surface (front surface, upper surface) 4a facing upward, and back surface (surface opposite to the element formation surface, lower surface) 4b. Faces the upper surface 12 a of the package substrate 12 and is bonded to the die bond material 13.

  The semiconductor chip 4 is provided with a plurality of electrode pads (bonding pads, terminals, electrodes) 4c on the main surface 4a, and the leads (a plurality of electrode pads 4c formed on the upper surface 12a of the package substrate 12). Bonding leads, electrodes, and terminals) 12c and a plurality of wires 15 are electrically connected. Since the detailed configuration of the semiconductor chip 4 and the definition of the main surface 4a of the semiconductor chip 4 are the same as the detailed configuration of the semiconductor chip 2 described above, the description thereof is omitted here.

  The wire 15 is, for example, a gold (Au) wire or a copper (Cu) wire.

  Further, the semiconductor chip 4 and the plurality of wires 15 are made of a sealing resin such as a thermosetting resin and are sealed by a sealing body 14 formed on the upper surface 12 a side of the package substrate 12.

  The package substrate 12 of the upper package 7 is, for example, a multilayer wiring substrate having a two-layer wiring layer structure. The package substrate 12 has an upper surface 12a having a quadrangular planar shape and a lower surface (back surface) 12b opposite to the upper surface 12a. A plurality of leads 12c for wire connection with the electrode pads 4c of the semiconductor chip 4 are provided on the upper surface 12a, while a plurality of prestacks on the upper surface 3a of the package substrate 3 of the lower package 6 are provided on the lower surface 12b. A plurality of lands (terminals, electrodes) 12d for connection to each of the lands 3d are provided via an insulating layer 12e.

  That is, the plurality of lands 12 d of the package substrate 12 of the upper package 7 are provided in the same arrangement as the plurality of prestack lands 3 d of the package substrate 3 of the lower package 6.

  Also, a solder resist film 12f, which is an insulating film, is formed on the surface layer of the upper surface 12a, and the leads 12c are exposed in each of the plurality of openings 12g, while the solder resist film 12f is also formed on the surface layer of the lower surface 12b. The land 12d is exposed in each of the plurality of openings 12h.

  Such an upper package 7 is mounted on the lower package 6 via a plurality of external terminals (conductive members) 9, thereby constituting a POP 1 that is an electronic device. That is, the lower package 6 and the upper package 7 are electrically connected through the plurality of external terminals 9. Here, the plurality of prestack lands 3 d on the upper surface 3 a of the package substrate 3 of the lower package 6 and the plurality of lands 12 d on the lower surface 12 b of the package substrate 12 of the upper package 7 are electrically connected via the plurality of external terminals 9. It is connected to the. Here, the external terminal 9 is, for example, a solder ball.

  In the present embodiment, the package substrate 3 of the lower package 6 is a multilayer wiring substrate having a four-layer wiring layer structure, and the package substrate 12 of the upper package 7 is a multilayer wiring substrate having a two-layer wiring layer structure. However, the number of wiring layers on each substrate is not limited to these.

  The plurality of leads 3c, 12c, lands 3e, 12d, prestack lands 3d, and wiring portions 3g of the package substrates 3 and 12 are made of, for example, a material mainly composed of copper (Cu).

<Method for Manufacturing Semiconductor Device (Lower Package)>
2 is a plan view of a wiring board used in assembling the lower package of the electronic device shown in FIG. 1, FIG. 3 is a cross-sectional view taken along line AA shown in FIG. 2, and FIG. 4 is a diagram of the electronic device shown in FIG. FIG. 5 is a cross-sectional view taken along the line AA shown in FIG. 4, and FIG. 5 is a plan view showing an example of the structure when the sealing material is arranged in assembling the lower package. 6 is a plan view showing an example of a structure during die bonding for assembling the lower package of the electronic device shown in FIG. 1, FIG. 7 is a cross-sectional view taken along the line AA shown in FIG. 6, and FIG. FIG. 9 is a plan view showing an example of a structure when forming an opening for assembling the lower package of the electronic device shown in FIG. 1, and FIG. 9 is a cross-sectional view taken along line AA shown in FIG. Further, FIG. 10 is a plan view showing an example of a structure when forming an external terminal for assembling the lower package of the electronic device shown in FIG. 1, FIG. 11 is a cross-sectional view taken along line AA shown in FIG. FIG. 13 is a plan view showing an example of a structure when the lower package of the electronic device shown in FIG. 1 is assembled, and FIG. 13 is a cross-sectional view taken along line AA shown in FIG.

1. Preparation of Wiring Board (Multi-Ply Board) In this embodiment, a case where a semiconductor device is assembled using the multi-chip board 17 shown in FIGS. 2 and 3 will be described. However, a pre-separated wiring board is used. It is also possible to assemble a semiconductor device.

  First, the multi-piece substrate 17 is prepared. The multi-chip substrate 17 has an upper surface (front surface, chip mounting surface) 17a and a lower surface (back surface, mounting surface) 17b opposite to the upper surface 17a. Further, the multi-piece substrate 17 includes a plurality of device forming portions 17c, a cutting portion (removal portion, dicing portion) 17d provided between adjacent device forming portions 17c among the plurality of device forming portions 17c, and A frame portion 17e provided around the plurality of device forming portions 17c in plan view is provided.

  Each of the plurality of device forming portions 17c on the upper surface 17a is provided with a chip mounting area 17f at the center thereof, and a plurality of leads 3c are formed in each chip mounting area 17f. Further, a plurality of prestack lands 3d that are respectively electrically connected to the plurality of leads 3c are formed around the chip mounting region 17f, in other words, around the periphery of the device forming portion 17c.

  Further, the multi-chip substrate 17 has a solder resist film 3f which is an insulating film formed on the upper surface 17a so that each of the plurality of leads 3c and the prestack land 3d is exposed.

  A plurality of lands 3e electrically connected to a plurality of leads 3c on the upper surface 17a are formed on the lower surface 17b of the multi-chip substrate 17, and each of the plurality of lands 3e is exposed. A solder resist film 3f is formed on the lower surface 17b.

  In each device forming portion 17c, as shown in FIG. 3, a solder layer 11a or a solder material is formed on the surface of each lead 3c.

  Further, the plurality of lands 3e on the lower surface 17b side formed in each device forming portion 17c includes a plurality of lands 3e that overlap with the chip mounting region 17f on the upper surface 17a side in plan view. In other words, the number of columns of the land 3e on the lower surface 17b side is larger than the number of columns of the prestack land 3d on the upper surface 17a side.

  In the multi-chip substrate 17, the plurality of leads 3c, prestack lands 3d, and lands 3e are made of a conductive member. In the present embodiment, for example, the lead 3c, the prestack land 3d, and the land 3e are made of a material mainly composed of copper (Cu).

2. Sealing Material Arrangement As shown in FIGS. 4 and 5, the sealing material 10 is disposed on the upper surface 17a of the multi-chip substrate 17, and the sealing material 10 is attached to the upper surface 17a. In the present embodiment, a case will be described in which a large number of film-like sealing materials 10 are arranged on the entire upper surface 17 a of the substrate 17 as the sealing material 10.

  That is, in each device forming portion 17c of FIG. 3, a film-like sealing material (NCF (Non-Conductive Film)) 10 is applied to the chip mounting region 17f and the region where the plurality of prestack lands 3d around it are provided. Thus, the surfaces of the chip mounting area 17f and the plurality of prestack lands 3d are covered with the sealing material 10, respectively. Each surface of the plurality of prestack lands 3d is a surface to which the external terminals 9 of the upper package 7 are connected in the mounting process of the upper package 7 in the assembly process of the POP1.

  The sealing material 10 is made of an insulating material, and is, for example, a thermosetting epoxy resin. Further, the sealing material 10 is also an adhesive for the semiconductor chip 2. The thickness of the sealing material 10 is preferably thinner than the thickness of the semiconductor chip 2. By being thinner than the chip thickness, each prestack land 3d can be easily exposed in the step of opening the surfaces of a plurality of prestack lands 3d described later by laser irradiation.

  Note that, as in the present embodiment, gold (Au) or copper (Cu) is used as a protruding electrode material for flip-chip bonding, and the bonding is performed with the lead 3c via the solder layer 11a or the solder material. Then, when the heat of the flip chip bonding portion 5 between the protruding electrode and the lead 3c is cooled, bonding failure such as breakage is likely to occur. Therefore, it is preferable to place the sealing material 10 in the chip mounting region 17f before the die bonding process and seal or protect the flip chip bonding portion 5 at an early stage.

  Further, by sticking the sealing material 10 to the upper surface 17a of the multi-piece substrate 17, the strength of the multi-piece substrate 17 can be increased, and the warp of the multi-piece substrate 17 can be reduced. In particular, by sticking over the entire upper surface 17a, the strength of the multi-chip substrate 17 can be further increased, and the warpage can be further reduced.

  In this embodiment, the case where NCF is used as the sealing material 10 is described. However, the sealing material 10 is not limited to NCF, but NCP (Non-Conductive Paste) which is a paste-like sealing material. It may be used.

  However, since the film-shaped sealing material 10 is easier to cope with, for example, control of a region (shape) to be applied or applied or a film thickness, it is preferable to employ the film-shaped sealing material 10.

3. In the die bonding step, as shown in FIGS. 6 and 7, first, the back surface 2b of the semiconductor chip 2 is sucked by the suction tool 20 and further supported by the stage 8 for die bonding. The semiconductor chip 2 is transported onto the chip mounting area 17f of the device forming portion 17c on the upper surface 17a of the upper surface 17a. The semiconductor chip 2 has a plurality of electrode pads 2c formed on the main surface 2a.

  Thereafter, flip chip bonding of the semiconductor chip 2 is performed. That is, the chip mounting regions 17 f of the plurality of device forming portions 17 c are interposed via the plurality of conductive members 11 so that the main surface 2 a of the semiconductor chip 2 faces the upper surface 17 a of the device forming portion 17 c of the multi-chip substrate 17. The semiconductor chip 2 is mounted or disposed on each upper surface 17a.

  Furthermore, the heating tool 21 is pressed against the back surface 2b of the semiconductor chip 2 through a heat-resistant sheet 22 for preventing tool contamination, a load (preferably a vertical load is applied here) is applied to the semiconductor chip 2, and the semiconductor chip 2 is interposed. Then, the flip chip bonding portion 5 is heated. By this heating, the solder layer 11a or the solder material on each lead 3c of the multi-chip substrate 17 is melted, the solder is wetted onto the conductive member 11, and the solder material and the conductive member 11 are electrically connected.

  Note that the heating tool 21 may be directly pressed against the semiconductor chip 2 without using the heat-resistant sheet 22 to perform flip chip bonding. However, when taking measures against contamination of the heating tool 21, it is preferable to use the heat-resistant sheet 22 so that the sealing material 10 does not adhere to the heating tool 21.

  In addition, a heat source is embedded in the heating tool 21. Furthermore, the pressing surface 21 a that is brought into contact with the semiconductor chip 2 of the heating tool 21 is a flat surface so that heat can be easily transferred from the heating tool 21 to the semiconductor chip 2.

  Further, since the heating tool 21 must be disposed immediately above the bump so that heat can be applied to the conductive member 11 on the electrode pad 2c of the semiconductor chip 2, the size of the heating tool 21 is made smaller than the chip size. That is not preferable. That is, the size of the heating tool 21 is preferably larger than the outer size of the semiconductor chip 2.

  Further, the melting of the solder layer 11a on the leads 3c of the multi-piece substrate 17 may be performed by applying heat from the stage 8 side via the multi-piece substrate 17 or both sides of the stage 8 and the heating tool 21. Heat may be applied.

  Furthermore, by applying heat from the heating tool 21 or the stage 8 or both, the sealing material 10 is also melted to seal the gap between the semiconductor chip 2 and the multi-chip substrate 17 and further the flip chip bonding portion 5. Seal with material 10.

  This completes the die bonding process.

4). Opening Formation In the opening forming step, as shown in FIGS. 8 and 9, the surfaces of the plurality of prestack lands 3 d on the upper surface 17 a of the multi-chip substrate 17 are exposed. In the present embodiment, as shown in FIG. 9, the sealing material 10 that covers the surface of each of the plurality of prestack lands 3d is irradiated with the laser light 26 to be formed on the surface of each prestack land 3d. The encapsulating material 10 is removed. Then, by removing the sealing material 10, an opening 10b is formed in the sealing material 10, and each prestack land 3d is exposed from the opening 10b.

  Since each prestack land 3d is made of a material containing copper (Cu) as a main component, the copper material emits laser light 26 onto the sealing material 10 to form an opening. It becomes a stopper. Here, as a method of removing the sealing material 10 on each prestack land 3d, it is also possible to remove it by etching.

  Thereafter, the conductive member 25 is arranged (formed) on each surface (exposed surface) of the plurality of prestack lands 3d exposed from the sealing material 10 (see FIG. 16). Here, the conductive member 25 of the present embodiment is made of so-called lead-free solder that does not substantially contain lead (Pb), for example, but a solder material having lead (Pb) may be used. Thereby, it can suppress that the surface of the prestack land 3d oxidizes. The material formed on the surface of the prestack land 3d is not limited to the above-described solder material as long as it is a conductive member 25, but considering the bonding property with the external terminal 9 of the upper package 7, It is preferable to use a solder material. Further, the conductive member 25 may be formed (plated) by a plating method.

5. External Terminal Formation In the external terminal formation step, as shown in FIGS. 10 and 11, a plurality of lands (lands 3ea, 3eb) 3e in a plurality of device formation portions 17c shown in FIG. The external terminals 16 are respectively formed or connected. The external terminal 16 is, for example, a ball-shaped electrode such as a solder ball, but the shape is not limited to the ball shape.

  The external terminal 16 may be a terminal in which the surface of each of the plurality of lands 3e is coated with a solder material. In this case, the semiconductor device is an LGA (Land Grid Array).

  In addition, the solder material used in the present embodiment, such as the solder ball and each solder material, is composed of so-called lead-free solder that does not substantially contain lead (Pb), for example, only tin (Sn), or tin -Copper-silver (Sn-Cu-Ag) or the like. Here, the lead-free solder means a lead (Pb) content of 0.1 wt% or less, and this content is defined as a standard of the RoHS (Restriction of Hazardous Substances) directive.

6). Individualization In the individualization step, individualization is performed as shown in FIGS. 12 and 13. Here, the dicing is performed using a dicing blade 23 which is a rotating cutting blade. Specifically, the front and back surfaces of the multi-piece substrate 17 are reversed, the lower surface 17b side of the multi-piece substrate 17 is directed upward, and the upper surface 17a side facing downward is held by the dicing jig 24. In this state, as shown in FIG. 13, dicing is performed by causing the blade 23 to enter and rotate from above the multi-piece substrate 17. That is, individualization is performed.

  At this time, in the present embodiment, since the sealing material 10 is formed on the entire surface of the multi-chip substrate 17 on the upper surface 17a side, the cut portion 17d of the multi-chip substrate 17 and the sealing material 10 The portion overlapping with the cutting portion 17d is cut and separated into a plurality of device forming portions 17c.

  Note that the singulation is not limited to cutting by dicing using the blade 23, but cutting by a mold may be performed.

  Thereby, the assembly of the lower package 6 shown in FIG. 1 is completed.

<Testing method of semiconductor device (lower package)>
14 is a cross-sectional view showing an example of the structure when the package is placed in the socket in the test process of assembling the lower package of the electronic device shown in FIG. 1, and FIG. 15 is the structure when the package is stored in the socket shown in FIG. It is sectional drawing which shows an example.

  In the test process, as shown in FIG. 14, first, the lower package 6 is disposed in the storage portion 18 b of the test socket 18. Here, each external terminal 16 is disposed in each recess 18c of the storage portion 18b.

  Since the sealing material 10 is formed on the upper surface 3a of the package substrate 3 in the lower package 6 as described above, the warpage can be suppressed, but the case where the warpage could not be suppressed is considered.

  The warpage described above is caused by the influence of heat at the time of flip chip bonding, and the package substrate (or the multi-chip substrate 17) 3 is warped in a convex shape on the chip mounting surface side. That is, since the expansion coefficients of the materials of the semiconductor chip 2, the sealing material 10, and the package substrate 3 are different, the central portion of the package substrate 3 protrudes toward the upper surface 3a due to the influence of heat in the flip chip process. ing.

  Further, in the lower package 6 of the present embodiment, a part of the plurality of lands 3e is arranged inside the plurality of prestack lands 3d. Specifically, a part (land 3ea) of the plurality of lands 3e is provided in a central portion of the lower surface 3b of the package substrate 3, in other words, in a region overlapping the semiconductor chip 2 in the lower surface 3b. The pre-stack land 3d is arranged on the peripheral edge side of the wiring board with respect to the land 3ea. An external terminal 16 is also formed on each of the plurality of lands 3ea.

  When the above-described warpage occurs in the lower package 6 in such a configuration, the socket pin 18d, which is a test pin, is less likely to contact the external terminal 16 provided at the center of the lower surface 3b of the package substrate 3.

  However, in the assembly of the lower package 6 of the present embodiment, since the sealing material 10 is attached over the entire upper surface 17a of the multi-cavity substrate 17 in the die bonding process, as shown in FIG. When the upper lid 18a is closed in the test socket 18, the peripheral portion in the vicinity of the chip can be pushed by the load P by the protrusion 18ab provided on the upper lid 18a.

  Therefore, by pressing the position closer to the center of the package substrate 3 with respect to the lower package 6, the contact property with respect to the socket pins 18d of the plurality of external terminals 16 disposed at positions below the chip that are difficult to contact with the socket pins 18d is achieved. Can be improved. That is, in the lower package 6 of the present embodiment, during the test, the external terminals 16 (external terminals formed on the land 3e provided at the center of the lower surface 3b of the package substrate 3 among the plurality of external terminals 16). Continuity can be ensured for 16).

  The inventor of the present application is considering reducing the mounting height of POP1 (for example, 1.2 to 1.0 mm) in POP1 in which upper package 7 is mounted on lower package 6. As a countermeasure, it is conceivable to reduce the thickness of the package substrate 3 to 0.3 mm or less, for example. However, in this case, it has been found that the rigidity (strength) of the package substrate 3 is lowered and the package substrate 3 is warped.

  Furthermore, as the functionality of the POP 1 increases, the number of external terminals 16 or lands 3e tends to increase, and the external terminals 16 that have been arranged only at the peripheral edge of the lower surface 3b of the package substrate 3 of the lower package 6 so far. Needs to be arranged at a position closer to the center of the package substrate 3 (an area under the chip).

  At this time, in the test process, in the position closer to the center of the package substrate 3 (region under the chip) as described above, when the substrate warps in a convex shape on the chip mounting surface side, the connection with the socket pin 18d is established. It has been found that the land 3ea or the external terminal 16 that cannot be secured easily occurs. As a countermeasure against this poor conduction, it is desired to press a position as close as possible to the center of the package substrate 3 with a tool such as the upper lid 18a. However, if a load is directly applied to the chip, it will cause a chip crack.

  Furthermore, the surface of the sealing material 10 that is an adhesive is inclined with respect to the upper surface 3a of the package substrate 3 (or the back surface 2b of the semiconductor chip 2), and the amount of protrusion of the sealing material 10 from the chip. (The distance L in FIG. 21 is significantly shorter than the distance M). As a result, it was difficult to press the tool, and therefore it was found that the contact failure with the socket pin 18d is likely to occur at the external terminal 16 near the center where the package substrate 3 is likely to be warped.

  However, in the assembly according to the present embodiment, the sealing material 10 is attached to the entire surface of the package substrate 3, whereby the strength of the package substrate 3 is increased and the warpage of the substrate is reduced. Yes.

  Thereby, the mountability of the lower package 6 can be improved.

  Further, since the sealing material 10 is attached over the entire surface of the package substrate 3, when the lower package 6 is accommodated in the test socket 18, the peripheral portion in the vicinity of the chip can be pressed, and the position under the chip The contact property of the plurality of external terminals 16 with respect to the socket pin 18d can be improved.

  As a result, the test accuracy of the lower package 6 can be increased, and the reliability of the lower package 6 and the POP 1 can be improved.

<Method for Manufacturing Electronic Device (POP)>
FIG. 16 is a cross-sectional view showing an example of a method of mounting the upper package on the lower package shown in FIG.

  In the present embodiment, another semiconductor device mounted on the lower package 6 is the upper package 7, and the semiconductor chip 4 mounted on the upper package 7 is, for example, a memory chip. Therefore, by stacking the upper package 7 on the lower package 6 and electrically connecting each other, an electronic device (or semiconductor device) in which one system is constructed by one POP 1 is obtained.

  Here, the upper package 7 includes a package substrate 12 having a plurality of lands 12 d formed on the lower surface 12 b, a semiconductor chip (for example, a memory chip) 4 mounted on the upper surface 12 a of the package substrate 12, and the semiconductor chip 4. The plurality of electrode pads 4c and the plurality of leads 12c of the package substrate 12 are electrically connected to the plurality of wires (conductive members) 15, respectively. Further, the upper package 7 includes a sealing body 14 that seals the semiconductor chip 4 and the plurality of wires 15, and a plurality of external terminals 9 that are respectively formed on the plurality of lands 12 d.

  Therefore, when the upper package 7 is mounted on the lower package 6, the plurality of prestack lands 3d of the lower package 6 and the plurality of external terminals 9 of the upper package 7 are electrically connected to each other.

  At that time, a conductive member (for example, a solder material) 25 is applied in advance to each of the plurality of prestack lands 3 d of the lower package 6, and the conductive member 25 and the external terminals 9 of the upper package 7 are melted. The upper package 7 and the lower package 6 are electrically connected by soldering.

<Modification>
As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments of the invention. However, the present invention is not limited to the embodiments of the invention, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

(Modification 1)
FIG. 17 is a cross-sectional view illustrating the structure of an electronic device according to the first modification of the embodiment.

  In Modification 1 of FIG. 17, the thickness of the sealing material 10 in the lower package 6 is further increased. For example, the thickness of the sealing material 10 on the plurality of prestack lands 3d is flip-chip bonded. The height (thickness) is the same as the height of the back surface 2 b of the semiconductor chip 2, that is, the mounting height of the semiconductor chip 2.

  That is, the thickness of the sealing material 10 is adjusted so that the thickness of the sealing material 10 at the position on the prestack land 3d, which is the position outside the semiconductor chip 2, is the same as the mounting height of the semiconductor chip 2. The thickness is greater than 2.

  As a result, when the lower package 6 is accommodated in the test socket 18 and the upper lid 18a is closed, the vicinity of the chip of the lower package 6, that is, the position near the center of the package substrate 12 can be pressed. As a result, the contact property of the socket pin 18d of the test socket 18 to the external terminal 16 can be improved.

(Modification 2)
18 is a plan view showing a structure when the sealing material is arranged in assembling the lower package of the electronic device according to the second modification of the embodiment, and FIG. 19 is a cross-sectional view taken along the line AA in FIG.

  The region to which the sealing material 10 is attached does not have to be the entire upper surface 17a of the multi-piece substrate 17, and when only the contact property in the test process is considered, as shown in FIGS. You may arrange | position the sealing material 10 of the magnitude | size separated into pieces for every 17c.

  In other words, a part of the upper surface 17a (for example, the dicing portion 17d or the peripheral portion including the dicing portion) of the multi-chip substrate 17 may not be covered with the sealing material 10.

  In this case, although the strength of the multi-piece substrate 17 is slightly inferior, since the sealing material 10 is attached to the entire surface of each package substrate 3, the contact property in the test process is similar to the above embodiment. Can be improved.

  Furthermore, since the sealing material 10 is not cut at the time of dicing, the amount of foreign matter scattering such as the sealing material 10 can be reduced.

(Modification 3)
20 is a plan view showing a structure after die bonding in assembling the lower package of the electronic device according to the third modification of the embodiment, and FIG. 21 shows the structure of one device forming portion along the line AA shown in FIG. It is an expanded sectional view.

  The third modification shows an example in which the sealing material 10 is not disposed on the prestack land 3d in the lower package 6, and the prestack land 3d may not necessarily be covered with the sealing material 10.

  In this case, as shown in FIG. 21, the region where the sealing material 10 is pasted is a distance L between the end of the semiconductor chip 2 and the end of the sealing material 10> the end of the sealing material 10 and the prestack land. When the inner end portion of 3d is formed over a plurality of rows and along each side of the package substrate 3, the distance M (L> from the prestack land 3d located in the innermost circumferential row. M).

  That is, the sealing material 10 is attached to the region where the semiconductor chip 2 is mounted, here the chip mounting region 17f shown in FIG. 3, and the region around the innermost peripheral row of the prestack land 3d. Each prestack land 3 d may not be covered with the sealing material 10.

  Also in this case, the strength of the package substrate 3 can be increased, and the warpage of the package substrate 3 can be reduced.

  In addition to the above-described chip mounting region 17f, the sealing material 10 is also applied to a region up to the front of the prestack land 3d disposed in the innermost peripheral row among the plurality of prestack lands 3d disposed around the chip mounting region 17f. In the case of arranging the paste, it is also possible to apply a paste-like sealing material 10 (NCP (Non-Conductive Paste)) that is difficult to control compared to the film-like sealing material 10 (NCF).

(Modification 4)
FIG. 22 is a plan view showing a structure at the time of die bonding in assembling the lower package of the electronic device according to the fourth modification of the embodiment, and FIG. 23 shows the structure of one device forming portion along the line AA shown in FIG. FIG. 24 is an enlarged cross-sectional view, and FIG. 24 is a cross-sectional view showing a structure when the lower package shown in FIG. 22 is stored in the socket.

  In the fourth modification, in the die bonding process for assembling the lower package 6, as shown in FIG. 23, the back surface 2b of the semiconductor chip 2 is pressed using the heating tool 21 having the convex portions 21b.

  At this time, the outer size of the pressing surface (also referred to as a contact surface) 21 a of the convex portion 21 b is smaller than the outer size of the back surface 2 b of the semiconductor chip 2. Therefore, the convex portion 21 b of the heating tool 21 presses a part (center portion) of the back surface 2 b of the semiconductor chip 2. That is, at the time of die bonding, the convex portion 21b of the heating tool 21 is pressed against a part (center portion) of the back surface 2b of the semiconductor chip 2 to apply pressure.

  Thereby, the lead 3c of the package substrate 3 and the conductive member 11 of the semiconductor chip 2 are solder-bonded, and the flip-chip bonding is completed.

  At that time, a covering portion 10 c of the sealing material 10 is formed on the peripheral edge portion of the back surface 2 b of the semiconductor chip 2. That is, as shown in FIG. 22, the peripheral portion of the back surface 2 b of the semiconductor chip 2 is covered with the covering portion 10 c of the sealing material 10.

  Thereafter, in the test process, as shown in FIG. 24, when the lower package 6 is disposed in the storage portion 18b of the test socket 18 and the upper lid 18a is closed, the projection 18ac provided on the upper lid 18a is sealed. A load P is applied to the covering portion 10c that is a portion covering the peripheral edge portion of the back surface 2b of the semiconductor chip 2 in the stopper 10.

  Thereby, the plurality of external terminals 16 of the lower package 6 and the plurality of socket pins 18d of the test socket 18 are brought into contact with each other, and an electrical test of the lower package 6 is performed in this state.

  As shown in FIG. 24, warpage occurred in the lower package 6 in which a plurality of external terminals 16 are provided at the center portion of the lower surface 3b of the package substrate 3 and the peripheral portion located around the center portion. In some cases, the plurality of external terminals 16 arranged at the center, that is, the lower part of the chip, are difficult to contact the socket pins 18d.

  However, in the lower package 6 of the fourth modification, a load is applied to the covering portion 10c on the peripheral edge of the semiconductor chip 2 when housed in the test socket 18, so that the vicinity of the center portion of the substrate can be pressed. Therefore, the contact property between the plurality of external terminals 16 at the lower part of the chip and the plurality of socket pins 18d can be improved, and the reliability of the test can also be improved.

(Modification 5)
FIG. 25 is a plan view showing a structure at the time of die bonding in assembling the lower package of the electronic device according to the modified example 5 of the embodiment, and FIG. 26 shows the structure of one device forming portion along the line AA shown in FIG. FIG. 27 is an enlarged cross-sectional view, and FIG. 27 is a cross-sectional view showing the structure of the lower package shown in FIG. 25 when stored in the socket.

  In the modified example 5 as well, in the die bonding process for assembling the lower package 6, as shown in FIG. 26, the back surface 2b of the semiconductor chip 2 is pressed using the heating tool 21 having the convex portions 21b.

  In the fifth modification, the outer size of the pressing surface 21 a of the convex portion 21 b of the heating tool 21 is larger than the outer size of the back surface 2 b of the semiconductor chip 2. Therefore, the convex portion 21 b of the heating tool 21 presses the entire back surface 2 b (entire surface) of the semiconductor chip 2. That is, at the time of die bonding, the convex portion 21b of the heating tool 21 is pressed against the entire back surface 2b of the semiconductor chip 2 to apply pressure.

  Thereby, the lead 3c of the package substrate 3 and the conductive member 11 of the semiconductor chip 2 are solder-bonded, and the flip-chip bonding is completed. As shown in FIG. 26, since the entire back surface 2b of the semiconductor chip 2 is pressed by the convex portion 21b of the heating tool 21, for example, the conductive member 11 is positioned on the peripheral side of the main surface 2a of the semiconductor chip 2. Even if it does, heat and a load can be reliably applied from directly above the conductive member 11. Therefore, heat is easily transmitted to the conductive member 11, and as a result, the bondability of flip chip bonding can be improved.

  Further, when pressed by the heating tool 21, around the side surface of the semiconductor chip 2, a step portion 10a of the sealing material 10 formed by the convex portion 21b of the heating tool 21, and a position higher than the step portion 10a. Step portion 10d is formed. That is, as shown in FIGS. 25 and 26, the position is higher than the back surface 2b of the semiconductor chip 2, that is, a portion thicker than the chip mounting height, and between the semiconductor chip 2 and the plurality of prestack lands 3d in plan view. The stepped portion 10d of the sealing material 10 is formed at the position.

  Thereafter, in the test process, as shown in FIG. 27, when the lower package 6 is disposed in the storage portion 18b of the test socket 18 and the upper lid 18a is closed, the projection 18ac provided on the upper lid 18a is sealed. A load P is applied to the step portion 10d at a position higher than the back surface 2b of the semiconductor chip 2 in the stopper 10.

  Thereby, the plurality of external terminals 16 of the lower package 6 and the plurality of socket pins 18d of the test socket 18 are brought into contact with each other, and an electrical test of the lower package 6 is performed in this state. In the fifth modification as well, as shown in FIG. 27, a lower stage in which a plurality of external terminals 16 are provided on the center portion of the lower surface 3b of the package substrate 3 and the peripheral portion located around the center portion. When the package 6 is warped, the plurality of external terminals 16 arranged at the center, that is, at the lower part of the chip, are difficult to contact the socket pin 18d.

  However, also in the lower package 6 of the fifth modified example, when a load is applied to the covering portion 10c on the peripheral edge portion of the semiconductor chip 2 when housed in the test socket 18, the vicinity of the center portion of the substrate can be pressed. . Therefore, the contact property between the plurality of external terminals 16 at the lower part of the chip and the plurality of socket pins 18d can be improved, and the reliability of the test can be improved as in the fourth modification.

(Modification 6)
In the above embodiment, the case where the finished product is POP1 has been described as an example. However, the finished product is not limited to POP1, and the lower package 6 after the completion of the test process may be shipped as a finished product.

(Modification 7)
FIG. 28 is a cross-sectional view showing the structure of a semiconductor device according to Modification 7 of the embodiment.

  In the above embodiment, the case where the finished product is POP1 has been described as an example. However, the finished product is not limited to POP1, but is a flip-chip type as shown in FIG. 28 and has no prestack land. (Ball Grid Array) 27 may be used.

  In the BGA 27 as well, the sealing material 10 is attached to the upper surface 3 a of the package substrate 3.

(Modification 8)
Furthermore, the modified examples can be applied in combination within a range not departing from the gist of the technical idea described in the above embodiment.

In addition, a part of the contents described in the embodiment will be described below.
(Claim 1)
A semiconductor device manufacturing method including the following steps:
(A) preparing a first semiconductor device;
Here, the first semiconductor device is manufactured by the following steps (a1) to (a5);
(A1) a first upper surface, a first chip mounting region provided on the first upper surface, a plurality of first bonding leads formed in the first chip mounting region, and disposed around the first chip mounting region Preparing a first wiring substrate having a plurality of first prestack lands, a first lower surface opposite to the first upper surface, and a plurality of first bump lands formed on the first lower surface;
(A2) After the step (a1), a sealing material is disposed on the first upper surface of the first wiring board including the first chip mounting region, and each surface of the plurality of first prestack lands is formed. Covering with the sealing material;
(A3) After the step (a2), a first main surface, a plurality of first bonding pads formed on the first main surface, and a plurality of first protrusions formed on the plurality of first bonding pads, respectively. A first semiconductor chip having an electrode and a first back surface opposite to the first main surface is arranged such that the first main surface of the first semiconductor chip faces the first upper surface of the first wiring board. Further, the first semiconductor chip is disposed on the first chip mounting region, a load is applied to the first semiconductor chip, and the plurality of first protruding electrodes and the plurality of first bonding leads are electrically connected to each other through a solder material. And further, sealing each joint portion of the plurality of first protruding electrodes and the plurality of first bonding leads with the sealing material;
(A4) After the step (a3), exposing the surface of each of the plurality of first prestack lands from the sealing material;
(A5) After the step (a4), forming a plurality of first external terminals on the plurality of first bump lands on the first wiring board;
(B) preparing a second semiconductor device;
Here, the second semiconductor device is
(B1) a second upper surface, a plurality of second bonding leads formed on the second upper surface, a second lower surface opposite to the second upper surface, and a plurality of second bump lands formed on the second lower surface. A second wiring board having:
(B2) a second main surface, a plurality of second bonding pads formed on the second main surface, and a second back surface opposite to the second main surface; 2 a second semiconductor chip mounted on the upper surface;
(B3) a plurality of conductive members that electrically connect the plurality of second bonding pads and the plurality of second bonding leads, respectively.
(B4) a sealing body for sealing the second semiconductor chip;
(B5) a plurality of second external terminals respectively formed on the plurality of second bump lands;
Including
(C) a step of mounting the second semiconductor device on the first semiconductor device after the steps (a) and (b);
Here, in the step (c), the plurality of second external terminals and the plurality of first prestack lands are electrically connected to each other.

1 POP
2 Semiconductor chip 2a Main surface (element formation surface, surface, top surface)
2b Back side (lower side)
2c Electrode pads (bonding pads, terminals, electrodes)
3 Package board (wiring board)
3a Top surface (chip mounting surface, main surface)
3b Bottom surface (mounting surface, back surface)
3c Lead (bonding lead, electrode, terminal)
3d pre-stack land (terminal, electrode)
3e, 3ea, 3eb Land (terminal, electrode)
3f Solder resist film 3g Wiring part (wiring)
3h Insulating layer 3i, 3j Opening 4 Semiconductor chip 4a Main surface (element formation surface, surface, top surface)
4b Back side (lower side)
4c Electrode pads (bonding pads, terminals, electrodes)
5 Flip chip joint 6 Lower package 7 Upper package 8 Stage 9 External terminal (conductive member)
DESCRIPTION OF SYMBOLS 10 Sealing material 10a Step part 10b Opening part 10c Covering part 10d Step part 11 Conductive member (columnar electrode, protruding electrode)
11a Solder layer 12 Package substrate (wiring substrate)
12a Top surface (surface, chip mounting surface)
12b Bottom (back)
12c Lead (bonding lead, electrode, terminal)
12d land (terminal, electrode)
12e Insulating layer 12f Solder resist film 12g, 12h Opening 13 Die bonding material 14 Sealing body 15 Wire 16 External terminal 17 Multi-piece substrate (wiring substrate)
17a Top surface (surface, chip mounting surface)
17b Lower surface (back surface, mounting surface)
17c Device formation part 17d Cutting part (removal part, dicing part)
17e Frame portion 17f Chip mounting area 18 Test socket 18a Upper lid 18ab, 18ac Protruding portion 18b Receiving portion 18c Recessed portion 18d Socket pin 20 Adsorption tool 21 Heating tool 21a Pressing surface 21b Protruding portion 22 Heat resistant sheet 23 Blade 24 Dicing jig 25 Conductivity Member 26 Laser light 27 BGA

Claims (8)

A semiconductor device manufacturing method including the following steps:
(A) a first surface, a chip mounting area provided on the first surface, a plurality of leads formed in the chip mounting area, a plurality of first lands disposed around the chip mounting area, the first Preparing a wiring board having a second surface opposite to the surface and a plurality of second lands formed on the second surface;
(B) After the step (a), a sealing material is disposed on the first surface of the wiring board including the chip mounting region, and each surface of the plurality of first lands is covered with the sealing material. Process;
(C) After the step (b), a main surface, a plurality of electrodes formed on the main surface, a plurality of projecting electrodes formed on the plurality of electrodes, and a back surface opposite to the main surface A semiconductor chip having a semiconductor chip is disposed on the chip mounting region such that the main surface of the semiconductor chip faces the first surface of the wiring substrate, and a load is applied to the semiconductor chip via a solder material. Electrically connecting the plurality of protruding electrodes and the plurality of leads, respectively, and further sealing each joint portion of the plurality of protruding electrodes and the plurality of leads with the sealing material;
(D) After the step (c), exposing the surface of each of the plurality of first lands from the sealing material;
(E) A step of forming a plurality of external terminals on the plurality of second lands of the wiring board after the step (d), respectively. Each of the plurality of first lands is made of copper,
In the step (d), the sealing material formed on the surface is removed by irradiating the sealing material covering the surface of each of the plurality of first lands with laser light.
The method for manufacturing a semiconductor device according to claim 1, wherein after the step (d), a conductive member is formed on each surface of the plurality of first lands exposed from the sealing material. The plurality of second lands are respectively provided in a central portion of the second surface of the wiring board and a peripheral portion located around the central portion,
The method for manufacturing a semiconductor device according to claim 1, wherein in the step (c), a convex portion of a tool is pressed against the back surface of the semiconductor chip.   After the step (e), the semiconductor device is disposed in a storage portion of a test socket, and a load is applied to a portion of the sealing material that covers the peripheral edge portion of the back surface of the semiconductor chip. 4. The method of manufacturing a semiconductor device according to claim 3, wherein the plurality of external terminals of the device and the plurality of test pins of the test socket are brought into contact with each other.   After the step (e), the semiconductor device is arranged in a test socket housing, the sealing material is located between the semiconductor chip and the plurality of first lands, and the semiconductor chip is mounted. The method of manufacturing a semiconductor device according to claim 3, wherein the plurality of external terminals of the semiconductor device and the plurality of test pins of the test socket are brought into contact with each other by applying a load to a portion thicker than the height.   The plurality of first lands are arranged closer to the peripheral portion of the wiring board than a part of the plurality of second lands arranged at the central portion of the second surface of the wiring board. A method for manufacturing a semiconductor device according to claim 3.   The method for manufacturing a semiconductor device according to claim 3, wherein in the step (c), the convex portion of the tool is pressed against the entire back surface of the semiconductor chip.   2. The method of manufacturing a semiconductor device according to claim 1, wherein in the step (b), a film-like sealing material is disposed on the first surface of the wiring board as the sealing material.

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