JP2014123589A - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor device Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 239000004065 semiconductor Substances 0.000 title claims description 17
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims abstract description 139
- 229910052759 nickel Inorganic materials 0.000 claims abstract description 69
- 229910052751 metal Inorganic materials 0.000 claims abstract description 56
- 239000002184 metal Substances 0.000 claims abstract description 56
- 239000000758 substrate Substances 0.000 claims abstract description 51
- 239000010936 titanium Substances 0.000 claims abstract description 34
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 33
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 33
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 22
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 22
- 229910010271 silicon carbide Inorganic materials 0.000 claims abstract description 10
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims abstract description 9
- 230000001678 irradiating effect Effects 0.000 claims abstract description 4
- 230000008018 melting Effects 0.000 claims description 13
- 238000002844 melting Methods 0.000 claims description 13
- 238000000034 method Methods 0.000 claims description 11
- 238000010438 heat treatment Methods 0.000 abstract description 4
- 238000004088 simulation Methods 0.000 description 22
- 238000000137 annealing Methods 0.000 description 16
- 238000005224 laser annealing Methods 0.000 description 11
- 238000004151 rapid thermal annealing Methods 0.000 description 6
- 230000007423 decrease Effects 0.000 description 3
- 229910021334 nickel silicide Inorganic materials 0.000 description 3
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 description 3
- 230000003746 surface roughness Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1608—Silicon carbide
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
- H01L21/048—Making electrodes
- H01L21/0485—Ohmic electrodes
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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Abstract
Description
本発明は、炭化シリコン（ＳｉＣ）からなる基板の表面に金属シリサイド膜を形成する半導体装置の製造方法に関する。 The present invention relates to a method for manufacturing a semiconductor device in which a metal silicide film is formed on the surface of a substrate made of silicon carbide (SiC).
半導体パワーデバイス用の半導体材料として、シリコンよりも広いバンドギャップを有するＳｉＣが注目されている。ショットキバリアダイオードに代表される縦型半導体デバイスにおいては、一方の表面に素子構造が形成され、他方の表面（背面）にオーミック電極が形成される。オーミック電極として、ニッケルシリサイド等の金属シリサイドが用いられる。金属シリサイドは、背面に金属膜を形成した後、ラピッドサーマルアニール（ＲＴＡ）等を行うことにより形成される。 As a semiconductor material for a semiconductor power device, SiC having a wider band gap than silicon has attracted attention. In a vertical semiconductor device typified by a Schottky barrier diode, an element structure is formed on one surface, and an ohmic electrode is formed on the other surface (back surface). A metal silicide such as nickel silicide is used as the ohmic electrode. The metal silicide is formed by performing rapid thermal annealing (RTA) or the like after forming a metal film on the back surface.
半導体パワーデバイスの素子抵抗を低減させるために、ＳｉＣ基板の一方の表面に素子構造を形成した後、他方の表面（背面）を研削して基板を薄くする手法が採用される。基板を薄くすることにより、素子抵抗を低減させることができる。基板を薄くするための研削を行わない場合には、素子構造を形成する前に、背面に金属シリサイド膜を形成しておくことが可能である。ところが、素子構造を形成した後に、基板を薄くする手法を採用する場合には、素子構造を形成し、かつ基板を薄くした後に、基板の背面に金属シリサイド膜を形成しなければならない。このため、基板の一方の表面に形成されている素子構造が、他方の表面（背面）に金属シリサイド膜を形成するときの熱の影響を受ける。素子構造が熱の影響を受けると、半導体パワーデバイスの電気的特性が低下する場合がある。 In order to reduce the element resistance of the semiconductor power device, a method is adopted in which an element structure is formed on one surface of an SiC substrate, and then the other surface (back surface) is ground to thin the substrate. By reducing the thickness of the substrate, the element resistance can be reduced. When grinding for thinning the substrate is not performed, it is possible to form a metal silicide film on the back surface before forming the element structure. However, when the method of thinning the substrate after the element structure is formed, the metal silicide film must be formed on the back surface of the substrate after the element structure is formed and the substrate is thinned. For this reason, the element structure formed on one surface of the substrate is affected by heat when the metal silicide film is formed on the other surface (back surface). When the element structure is affected by heat, the electrical characteristics of the semiconductor power device may deteriorate.
本発明の目的は、基板の一方の表面に形成されている素子構造が、金属シリサイド膜形成のための熱処理時に発生する熱の影響を受けにくい製造方法を提供することである。 An object of the present invention is to provide a manufacturing method in which an element structure formed on one surface of a substrate is not easily affected by heat generated during heat treatment for forming a metal silicide film.
本発明の一観点によると、
炭化シリコンからなる基板の第１の表面に、ニッケルまたはチタンからなる金属膜を形成する工程と、
前記金属膜に紫外域の波長を有するパルスレーザビームを照射して、前記基板と前記金属膜との界面においてシリサイド反応を生じさせることにより、金属シリサイド膜を形成する工程と
を有し、
前記金属シリサイド膜を形成する工程において、前記金属膜の表面が溶融しない条件で前記パルスレーザビームを照射する半導体装置の製造方法が提供される。
According to one aspect of the invention,
Forming a metal film made of nickel or titanium on a first surface of a substrate made of silicon carbide;
Irradiating the metal film with a pulsed laser beam having a wavelength in the ultraviolet region to cause a silicide reaction at the interface between the substrate and the metal film, thereby forming a metal silicide film,
In the step of forming the metal silicide film, a method of manufacturing a semiconductor device is provided in which the pulse laser beam is irradiated under a condition that the surface of the metal film does not melt.
パルスレーザビームの照射によってシリサイド反応を生じさせることにより、ＲＴＡ等でシリサイド反応を生じさせる場合に比べて、基板の第１の表面とは反対側の表面の温度上昇を抑制することができる。 By causing a silicide reaction by irradiation with a pulsed laser beam, a temperature increase on the surface opposite to the first surface of the substrate can be suppressed as compared with a case where a silicide reaction is caused by RTA or the like.
図１Ａ〜図１Ｆを参照して、実施例による半導体装置の製造方法について説明する。 With reference to FIG. 1A to FIG. 1F, a method of manufacturing a semiconductor device according to an embodiment will be described.
図１Ａに示すように、ｎ型ＳｉＣからなる基板１０の一方の表層部に、イオン注入によりｐ型のガードリング１１を形成する。ガードリング１１が形成された表面とは反対側の表面を「第１の表面」１０Ａといい、ガードリング１１が形成された表面を「第２の表面」１０Ｂということとする。図１Ｂに示すように、第２の表面１０Ｂに、酸化シリコンからなる絶縁膜１２を形成する。絶縁膜１２には、ガードリング１１に囲まれた領域を露出させる開口が形成されている。
As shown in FIG. 1A, a p-
図１Ｃに示すように、絶縁膜１２に形成されている開口の底面に露出している基板１０の表面に、ショットキ電極１３を形成する。一例として、チタン膜を形成した後、熱処理を行うことにより、ショットキコンタクトが実現される。ショットキ電極１３の上に表面電極１４を形成する。表面電極１４には、例えばアルミニウムが用いられる。ガードリング１１、ショットキ電極１３、及び表面電極１４を、「素子構造」１５ということとする。
As shown in FIG. 1C, a Schottky
図１Ｄに示すように、基板１０を第１の表面１０Ａから研削することにより、基板１０を薄くする。図１Ｅに示すように、基板１０の第１の表面１０Ａに、金属膜１６を形成する。金属膜１６には、例えばニッケル（Ｎｉ）、チタン（Ｔｉ）が用いられる。
As shown in FIG. 1D, the
図１Ｆに示すように、金属膜１６にパルスレーザビーム２０を照射することにより、レーザアニールを行う。このレーザアニールは、パルスレーザビーム２０の入射領域を金属
膜１６の表面内で移動させながら行われる。入射領域のオーバラップ率は、例えば５０％〜９０％とする。
As shown in FIG. 1F, laser annealing is performed by irradiating the
このレーザアニールにより、基板１０と金属膜１６との界面に、金属シリサイド膜１７が形成される。このレーザアニールは、金属膜１６の表面が溶融しない条件で行われる。金属膜１６の表面が溶融すると、固化した後、金属膜１６の表面が荒れてしまう。実施例による方法では、金属膜１６の表面が溶融しない条件でアニールが行われるため、金属膜１６の表面荒れを抑制することができる。金属膜の表面を溶融させることなく、界面でシリサイド化を行うことを「非溶融シリサイド化」ということとする。
By this laser annealing, a
金属膜１６の表面が、全体としては融点に達していなくても、物性上、「表面の極一部分がわずかに溶融する場合が考えられる。ここで、「金属膜の表面を溶融させることなく」という表現は、金属膜の表面荒れに影響を及ぼす程度の実質的な溶融が生じないことを意味しており、表面荒れにほとんど影響を及ぼさない程度のわずかな溶融が生じることまで排除しているわけではない。
Even if the surface of the
パルスレーザビーム２０のパルス幅は、ラピッドサーマルアニール（ＲＴＡ）による加熱時間よりも短い。基板１０を透過しない波長域のパルスレーザビーム２０を使用すると、パルスレーザビームは第２の表面１０Ｂに形成された素子構造１５まで到達しない。このため、基板１０の第２の表面１０Ｂの温度上昇が軽減される。実施例によるアニール方法を採用すると、ＲＴＡを採用する場合に比べて、素子構造１５の温度上昇を抑制することができる。
The pulse width of the
次に、図２Ａ〜図５Ｂを参照して、金属膜１６（図１Ｅ）にニッケルを用いた場合のレーザアニールの好ましい条件について説明する。４Ｈ−ＳｉＣからなる基板の表面に、ニッケル膜を形成し、ニッケル膜に波長３５５ｎｍのパルスレーザビームを照射したときの、基板とニッケル膜との界面の最高到達温度、及びニッケル膜の表面の最高到達温度をシミュレーションにより求めた。図２Ａ〜図５Ｂに、シミュレーション結果を示す。 Next, referring to FIG. 2A to FIG. 5B, preferable conditions for laser annealing when nickel is used for the metal film 16 (FIG. 1E) will be described. When the nickel film is formed on the surface of the substrate made of 4H—SiC and the pulsed laser beam having a wavelength of 355 nm is irradiated onto the nickel film, the highest temperature at the interface between the substrate and the nickel film, and the highest surface of the nickel film The ultimate temperature was determined by simulation. 2A to 5B show simulation results.
図２Ａ、図３Ａ、図４Ａ、及び図５Ａに、基板とニッケル膜との界面（以下、単に「界面」という。）の最高到達温度とニッケル膜の厚さとの関係を示す。横軸は、ニッケル膜の厚さを単位「ｎｍ」で表し、縦軸は、界面の最高到達温度を単位「℃」で表す。図２Ｂ、図３Ｂ、図４Ｂ、及び図５Ｂに、ニッケル膜の表面（以下、単に「表面」という。）の最高到達温度と、ニッケル膜の厚さとの関係を示す。横軸は、ニッケル膜の厚さを単位「ｎｍ」で表し、縦軸は、表面の最高到達温度を単位「℃」で表す。 2A, FIG. 3A, FIG. 4A, and FIG. 5A show the relationship between the maximum temperature reached at the interface between the substrate and the nickel film (hereinafter simply referred to as “interface”) and the thickness of the nickel film. The horizontal axis represents the thickness of the nickel film in the unit “nm”, and the vertical axis represents the maximum temperature reached at the interface in the unit “° C.”. 2B, FIG. 3B, FIG. 4B, and FIG. 5B show the relationship between the maximum temperature reached on the surface of the nickel film (hereinafter simply referred to as “surface”) and the thickness of the nickel film. The horizontal axis represents the thickness of the nickel film in the unit “nm”, and the vertical axis represents the maximum surface temperature of the surface in the unit “° C.”.
図２Ａ及び図２Ｂは、パルスレーザビームのパルス幅Ｐｗを１０ｎｓにした場合のシミュレーション結果を示す。図３Ａ及び図３Ｂは、パルスレーザビームのパルス幅Ｐｗを２０ｎｓにした場合のシミュレーション結果を示す。図４Ａ及び図４Ｂは、パルスレーザビームのパルス幅Ｐｗを３０ｎｓにした場合のシミュレーション結果を示す。図５Ａ及び図５Ｂは、パルスレーザビームのパルス幅Ｐｗを５０ｎｓにした場合のシミュレーション結果を示す。 2A and 2B show simulation results when the pulse width Pw of the pulse laser beam is 10 ns. 3A and 3B show simulation results when the pulse width Pw of the pulse laser beam is 20 ns. 4A and 4B show simulation results when the pulse width Pw of the pulse laser beam is 30 ns. 5A and 5B show simulation results when the pulse width Pw of the pulse laser beam is 50 ns.
図２Ａ及び図２Ｂの菱形記号、四角記号、三角記号、及び丸記号は、それぞれニッケル膜の表面におけるパルスエネルギ密度（以下、単に「パルスエネルギ密度」という。）が１．２Ｊ／ｃｍ２、１．３Ｊ／ｃｍ２、１．４Ｊ／ｃｍ２、及び１．５Ｊ／ｃｍ２の条件でレーザアニールを行った場合に対応する。図３Ａ及び図３Ｂの菱形記号、四角記号、三角記号、及び丸記号は、それぞれパルスエネルギ密度が１．６Ｊ／ｃｍ２、１．７Ｊ／ｃｍ２、１．８Ｊ／ｃｍ２、及び１．９Ｊ／ｃｍ２の条件でレーザアニールを行った場合に対応する。図４Ａ及び図４Ｂの菱形記号、四角記号、三角記号、及び丸記号は、それぞれ
パルスエネルギ密度が１．８Ｊ／ｃｍ２、２．０Ｊ／ｃｍ２、２．２Ｊ／ｃｍ２、及び２．４Ｊ／ｃｍ２の条件でレーザアニールを行った場合に対応する。図５Ａ及び図５Ｂの菱形記号、四角記号、三角記号、及び丸記号は、それぞれパルスエネルギ密度が２．４Ｊ／ｃｍ２、２．６Ｊ／ｃｍ２、２．８Ｊ／ｃｍ２、及び３．０Ｊ／ｃｍ２の条件でレーザアニールを行った場合に対応する。
The rhombus symbol, square symbol, triangle symbol, and circle symbol in FIGS. 2A and 2B each have a pulse energy density (hereinafter simply referred to as “pulse energy density”) of 1.2 J / cm 2 on the surface of the nickel film. This corresponds to the case where laser annealing is performed under the conditions of 3 J / cm 2 , 1.4 J / cm 2 , and 1.5 J / cm 2 . The rhombus, square, triangle, and circle symbols in FIGS. 3A and 3B have pulse energy densities of 1.6 J / cm 2 , 1.7 J / cm 2 , 1.8 J / cm 2 , and 1.9 J, respectively. This corresponds to the case where laser annealing is performed under the condition of / cm 2 . The rhombus, square, triangle, and circle symbols in FIGS. 4A and 4B have pulse energy densities of 1.8 J / cm 2 , 2.0 J / cm 2 , 2.2 J / cm 2 , and 2.4 J, respectively. This corresponds to the case where laser annealing is performed under the condition of / cm 2 . The rhombus, square, triangle, and circle symbols in FIGS. 5A and 5B have pulse energy densities of 2.4 J / cm 2 , 2.6 J / cm 2 , 2.8 J / cm 2 , and 3.0 J, respectively. This corresponds to the case where laser annealing is performed under the condition of / cm 2 .
「パルスエネルギ密度」は、パルスレーザビームの１パルスあたりのエネルギを、ビーム断面の面積で除算して得られる。本明細書において、「ビーム断面の面積」として、ビーム断面内において、光強度が最大値の１／２となる位置を結ぶ閉曲線に囲まれた領域の面積を採用した。 The “pulse energy density” is obtained by dividing the energy per pulse of the pulse laser beam by the area of the beam cross section. In this specification, the area of a region surrounded by a closed curve connecting positions where the light intensity is ½ of the maximum value in the beam cross section is adopted as the “area of the beam cross section”.
パルスレーザビーム照射後の、界面の最高到達温度が約９５０℃以上になると、基板とニッケル膜との界面でシリサイド反応が生じ、ニッケルシリサイド膜が形成される。 When the maximum temperature reached at the interface after pulse laser beam irradiation reaches about 950 ° C. or higher, a silicide reaction occurs at the interface between the substrate and the nickel film, and a nickel silicide film is formed.
図２Ａに示すように、パルス幅が１０ｎｓのとき、ニッケル膜の厚さが約２０ｎｍ以下であると、界面の最高到達温度が９５０℃に達しない。これは、ＳｉＣからなる基板がヒートシンクとして作用し、界面に熱が蓄積されないためである。ニッケル膜の厚さを３０ｎｍ以上にすると、パルスエネルギ密度が少なくとも１．３〜１．５Ｊ／ｃｍ２の範囲内で、界面の最高到達温度が９５０℃以上になる。 As shown in FIG. 2A, when the pulse width is 10 ns, the maximum temperature at the interface does not reach 950 ° C. when the thickness of the nickel film is about 20 nm or less. This is because the substrate made of SiC acts as a heat sink and heat is not accumulated at the interface. When the thickness of the nickel film is 30 nm or more, the maximum temperature at the interface becomes 950 ° C. or more within a pulse energy density range of at least 1.3 to 1.5 J / cm 2 .
パルスエネルギ密度をより高くすれば、ニッケル膜の厚さが２０ｎｍ以下であっても、界面の最高到達温度を９５０℃以上にするアニール条件が存在するであろう。しかし、後に図２Ｂを参照して説明するように、パルスエネルギ密度を高くすると、ニッケル膜の表面が溶融しやすくなる。このため、界面にニッケルシリサイド膜を形成するために、ニッケル膜の厚さを３０ｎｍ以上にすることが好ましい。
If the pulse energy density is made higher, there will be an annealing condition that makes the maximum temperature at the
ニッケル膜の厚さが３０ｎｍ以上の範囲では、膜厚が厚くなるに従って、界面の最高到達温度が低下する。ただし、少なくとも膜厚が２００ｎｍ以下の範囲で、パルスエネルギ密度を１．４Ｊ／ｃｍ２以上にすると、界面の最高到達温度を９５０℃以上にすることができる。図２Ａには示されていないが、ニッケル膜の厚さが２５０ｎｍ以上であっても、パルスエネルギ密度を調節すれば、界面の最高到達温度を９５０℃以上にすることができる。 In the range where the thickness of the nickel film is 30 nm or more, the maximum temperature at the interface decreases as the film thickness increases. However, when the pulse energy density is 1.4 J / cm 2 or more at least in the range where the film thickness is 200 nm or less, the maximum temperature at the interface can be 950 ° C. or more. Although not shown in FIG. 2A, even if the thickness of the nickel film is 250 nm or more, the maximum temperature at the interface can be made 950 ° C. or more by adjusting the pulse energy density.
図２Ｂに示すように、ニッケル膜が厚くなるに従って、表面の最高到達温度が高くなる。ニッケル膜が薄いと、基板のヒートシンク効果によって、ニッケル膜の表面の温度上昇が抑制され、ニッケル膜が厚くなると、基板のヒートシンク効果が弱まるためである。ニッケル膜の表面温度が、ニッケルの融点である１４５５℃を超えると、表面が溶融してしまう。表面の溶融を回避するために、表面の最高到達温度が１４５５℃以下の条件でアニールを行うことが好ましい。 As shown in FIG. 2B, the maximum temperature reached on the surface increases as the nickel film becomes thicker. This is because when the nickel film is thin, the temperature rise of the surface of the nickel film is suppressed by the heat sink effect of the substrate, and when the nickel film is thick, the heat sink effect of the substrate is weakened. When the surface temperature of the nickel film exceeds 1455 ° C., which is the melting point of nickel, the surface is melted. In order to avoid melting of the surface, it is preferable to perform annealing under the condition that the maximum surface temperature is 1455 ° C. or less.
一例として、パルスエネルギ密度を１．３Ｊ／ｃｍ２以上の条件の下で、ニッケル膜の厚さを調節することにより、界面の最高到達温度を９５０℃以上にすることができる。パルスエネルギ密度を高くすると、ニッケル膜の表面の最高到達温度がニッケルの融点以上になる。照射するパルスレーザビームのパルスエネルギ密度は、ニッケル膜の表面の最高到達温度がニッケルの融点と等しくなる大きさよりも低い範囲内に設定される。 As an example, by adjusting the thickness of the nickel film under the condition where the pulse energy density is 1.3 J / cm 2 or more, the maximum temperature reached at the interface can be made 950 ° C. or more. When the pulse energy density is increased, the maximum temperature reached on the surface of the nickel film becomes equal to or higher than the melting point of nickel. The pulse energy density of the pulse laser beam to be irradiated is set in a range lower than the magnitude at which the maximum temperature reached on the surface of the nickel film is equal to the melting point of nickel.
図３Ａに示すように、パルス幅が２０ｎｓのときにも、ニッケル膜の厚さが３０ｎｍ〜２５０ｎｍの範囲内で、界面の最高到達温度を９５０℃以上にすることができる。例えば、パルスエネルギ密度を１．９Ｊ／ｃｍ２にすると、ニッケル膜の厚さ３０ｎｍ〜２５０ｎｍの範囲内で、界面の最高到達温度を９５０℃以上にすることができる。 As shown in FIG. 3A, even when the pulse width is 20 ns, the maximum temperature at the interface can be set to 950 ° C. or more within the range of the thickness of the nickel film of 30 nm to 250 nm. For example, when the pulse energy density is set to 1.9 J / cm 2 , the maximum temperature reached at the interface can be set to 950 ° C. or higher within the thickness range of 30 nm to 250 nm of the nickel film.
図３Ｂに示すように、一例として、パルスエネルギ密度が１．８Ｊ／ｃｍ２以上の条件の下で、ニッケル膜の厚さを調節することにより、界面の最高到達温度を９５０℃以上にし、かつ表面の最高到達温度を１４５５℃以下にすることができる。 As shown in FIG. 3B, by way of example, by adjusting the thickness of the nickel film under a condition where the pulse energy density is 1.8 J / cm 2 or more, the maximum temperature at the interface is set to 950 ° C. or more, and The maximum temperature reached on the surface can be made 1455 ° C. or lower.
図４Ａに示すように、パルス幅が３０ｎｓのときにも、ニッケル膜の厚さが３０ｎｍ〜２００ｎｍの範囲内で、界面の最高到達温度を９５０℃以上にすることができる。図４Ａには示されていないが、ニッケル膜の厚さが２５０ｎｍのときにも、界面の最高到達温度を９５０℃以上にすることができる。例えば、パルスエネルギ密度を２．２Ｊ／ｃｍ２にすると、ニッケル膜の厚さ３０ｎｍ〜２００ｎｍの範囲内で、界面の最高到達温度を９５０℃以上にすることができる。図４Ａには示されていないが、ニッケル膜の厚さが２５０ｎｍ以上であっても、パルスエネルギ密度を調節すれば、界面の最高到達温度を９５０℃以上にすることができる。 As shown in FIG. 4A, even when the pulse width is 30 ns, the maximum temperature at the interface can be set to 950 ° C. or more within the range of the thickness of the nickel film of 30 nm to 200 nm. Although not shown in FIG. 4A, even when the thickness of the nickel film is 250 nm, the maximum temperature at the interface can be made 950 ° C. or higher. For example, when the pulse energy density is set to 2.2 J / cm 2 , the highest temperature at the interface can be set to 950 ° C. or more within the thickness range of the nickel film of 30 nm to 200 nm. Although not shown in FIG. 4A, even if the thickness of the nickel film is 250 nm or more, the maximum temperature at the interface can be made 950 ° C. or more by adjusting the pulse energy density.
図４Ｂに示すように、一例として、パルスエネルギ密度が２．２Ｊ／ｃｍ２以上の条件の下で、ニッケル膜の厚さを調節することにより、界面の最高到達温度を９５０℃以上にし、かつ表面の最高到達温度を１４５５℃以下にすることができる。 As shown in FIG. 4B, as an example, by adjusting the thickness of the nickel film under the condition where the pulse energy density is 2.2 J / cm 2 or more, the maximum temperature at the interface is set to 950 ° C. or more, and The maximum temperature reached on the surface can be made 1455 ° C. or lower.
図５Ａに示すように、パルス幅が５０ｎｓのときにも、ニッケル膜の厚さが３０ｎｍ〜２５０ｎｍの範囲内で、界面の最高到達温度を９５０℃以上にすることができる。例えば、パルスエネルギ密度を２．８Ｊ／ｃｍ２にすると、ニッケル膜の厚さが３０ｎｍ〜２５０ｎｍの範囲内で、界面の最高到達温度を９５０℃以上にすることができる。 As shown in FIG. 5A, even when the pulse width is 50 ns, the maximum temperature at the interface can be set to 950 ° C. or more within the range of the thickness of the nickel film of 30 nm to 250 nm. For example, when the pulse energy density is 2.8 J / cm 2 , the maximum temperature reached at the interface can be set to 950 ° C. or higher within the thickness range of 30 nm to 250 nm.
図５Ｂに示すように、一例として、パルスエネルギ密度が２．８Ｊ／ｃｍ２以上の条件の下で、ニッケル膜の厚さを調節することにより、界面の最高到達温度を９５０℃以上にし、かつ表面の最高到達温度を１４５５℃以下にすることができる。 As shown in FIG. 5B, by way of example, by adjusting the thickness of the nickel film under the condition where the pulse energy density is 2.8 J / cm 2 or more, the maximum temperature at the interface is set to 950 ° C. or more, and The maximum temperature reached on the surface can be made 1455 ° C. or lower.
図２Ａ〜図５Ｂを参照して説明したように、パルス幅が１０ｎｓ〜５０ｎｓの範囲内、かつニッケル膜の厚さが３０ｎｍ〜２５０ｎｍの範囲内で、パルスエネルギ密度を調節することにより、界面の最高到達温度が９５０℃以上になり、かつ表面の最高到達温度が１４５５℃以下となる条件でアニールを行うことができる。すなわち、非溶融シリサイド化を行うことが可能になる。 As described with reference to FIGS. 2A to 5B, by adjusting the pulse energy density within the range of the pulse width of 10 ns to 50 ns and the thickness of the nickel film of 30 nm to 250 nm, Annealing can be performed under conditions where the maximum temperature reached 950 ° C. or higher and the surface maximum temperature reached 1455 ° C. or lower. That is, non-molten silicidation can be performed.
パルスエネルギ密度を一定にしたまま、パルス幅を長くすると、ピークパワー密度が低くなってしまう。ピークパワー密度の低下によって、界面の最高到達温度が９５０℃に達しにくくなる。このため、図２Ａ、図３Ａ、図４Ａ、図５Ａに示したように、界面の最高到達温度を９５０℃以上にするために必要なパルスエネルギ密度は、パルス幅が長くなるに従って高くなっている。 If the pulse width is increased while the pulse energy density is kept constant, the peak power density is lowered. Due to the decrease in the peak power density, the maximum temperature reached at the interface hardly reaches 950 ° C. Therefore, as shown in FIG. 2A, FIG. 3A, FIG. 4A, and FIG. 5A, the pulse energy density required to increase the maximum temperature at the interface to 950 ° C. or higher increases as the pulse width increases. .
パルス幅が１０ｎｓ未満になると、表面が局所的に加熱され、界面まで熱が伝わりにくくなる。表面の温度上昇を抑制して、界面まで熱を伝えるために、パルス幅を１０ｎｓ以上にすることが好ましい。パルス幅が５０ｎｓより長くなると、界面の最高到達温度を９５０℃以上にするために必要なパルスエネルギ密度が高くなってしまい、アニール効率が低下する。効率的なアニールを行うために、パルス幅を５０ｎｓ以下にすることが好ましい。 When the pulse width is less than 10 ns, the surface is locally heated and it becomes difficult for heat to be transmitted to the interface. In order to suppress the temperature rise on the surface and conduct heat to the interface, the pulse width is preferably 10 ns or more. If the pulse width is longer than 50 ns, the pulse energy density required for setting the maximum temperature at the interface to 950 ° C. or higher increases, and the annealing efficiency decreases. In order to perform efficient annealing, the pulse width is preferably 50 ns or less.
次に、図６Ａ〜図６Ｂを参照して、金属膜１６（図１Ｅ）にチタンを用いた場合のレーザアニールの好ましい条件について説明する。４Ｈ−ＳｉＣからなる基板の表面に、チタン膜を形成し、チタン膜に波長３５５ｎｍのパルスレーザビームを照射したときの、基板とチタン膜との界面の最高到達温度、及びチタン膜の表面の最高到達温度をシミュレーシ
ョンにより求めた。図６Ａ〜図６Ｂに、シミュレーション結果を示す。
Next, with reference to FIGS. 6A to 6B, preferable conditions for laser annealing when titanium is used for the metal film 16 (FIG. 1E) will be described. When a titanium film is formed on the surface of a substrate made of 4H—SiC and the titanium film is irradiated with a pulsed laser beam having a wavelength of 355 nm, the highest temperature reached at the interface between the substrate and the titanium film, and the highest surface of the titanium film The ultimate temperature was determined by simulation. 6A to 6B show simulation results.
図６Ａに、基板とチタン膜との界面（以下、単に「界面」という。）の最高到達温度とチタン膜の厚さとの関係を示す。横軸は、チタン膜の厚さを単位「ｎｍ」で表し、縦軸は、界面の最高到達温度を単位「℃」で表す。図６Ｂに、チタン膜の表面（以下、単に「表面」という。）の最高到達温度と、チタン膜の厚さとの関係を示す。横軸は、チタン膜の厚さを単位「ｎｍ」で表し、縦軸は、表面の最高到達温度を単位「℃」で表す。パルスレーザビームのパルス幅Ｐｗは１０ｎｓとした。 FIG. 6A shows the relationship between the maximum temperature reached at the interface between the substrate and the titanium film (hereinafter simply referred to as “interface”) and the thickness of the titanium film. The horizontal axis represents the thickness of the titanium film in the unit “nm”, and the vertical axis represents the maximum temperature reached at the interface in the unit “° C.”. FIG. 6B shows the relationship between the maximum temperature reached on the surface of the titanium film (hereinafter simply referred to as “surface”) and the thickness of the titanium film. The abscissa represents the thickness of the titanium film in the unit “nm”, and the ordinate represents the highest surface temperature in the unit “° C.”. The pulse width Pw of the pulse laser beam was 10 ns.
図６Ａ及び図６Ｂの菱形記号、四角記号、三角記号、及び丸記号は、それぞれチタン膜の表面におけるパルスエネルギ密度（以下、単に「パルスエネルギ密度」という。）が０．８Ｊ／ｃｍ２、１．０Ｊ／ｃｍ２、１．２Ｊ／ｃｍ２、及び１．４Ｊ／ｃｍ２の条件でレーザアニールを行った場合の界面の最高到達温度を示す。チタンは、ニッケルに比べて熱伝導度が低いため、基板とチタン膜との界面まで熱が伝わりにくい。このため、界面の温度を９５０℃まで加熱したとき、ニッケル膜の表面の温度上昇に比べてチタン膜の表面の温度上昇が大きい。 The rhombus symbols, square symbols, triangle symbols, and circle symbols in FIGS. 6A and 6B each have a pulse energy density (hereinafter simply referred to as “pulse energy density”) of 0.8 J / cm 2 on the surface of the titanium film. The maximum temperature at the interface when laser annealing is performed under the conditions of 0.0 J / cm 2 , 1.2 J / cm 2 , and 1.4 J / cm 2 is shown. Since titanium has a lower thermal conductivity than nickel, heat is not easily transmitted to the interface between the substrate and the titanium film. For this reason, when the interface temperature is heated to 950 ° C., the temperature rise on the surface of the titanium film is larger than the temperature rise on the surface of the nickel film.
図６Ａに示すように、パルス幅が１０ｎｓのとき、チタン膜の厚さが３０ｎｍ〜１５０ｎｍの範囲内で、界面の最高到達温度を９５０℃以上にすることができる。 As shown in FIG. 6A, when the pulse width is 10 ns, the maximum temperature reached at the interface can be set to 950 ° C. or higher within the thickness range of 30 nm to 150 nm.
図６Ｂに示すように、一例として、パルスエネルギ密度が１．２Ｊ／ｃｍ２以上の条件の下で、チタン膜の厚さを調節することにより、界面の最高到達温度を９５０℃以上にし、かつ表面の最高到達温度をチタンの融点である１６６８℃以下にすることができる。 As shown in FIG. 6B, by way of example, by adjusting the thickness of the titanium film under a condition where the pulse energy density is 1.2 J / cm 2 or more, the maximum temperature at the interface is set to 950 ° C. or more, and The highest surface temperature can be made 1668 ° C. or lower, which is the melting point of titanium.
ニッケル膜を用いたときのシミュレーション結果から、パルス幅を長くすると、界面の最高到達温度が９５０℃以上になるアニール条件を維持したまま、ニッケル膜の表面の温度が上昇しにくくなることが確認された。ニッケル膜に代えてチタン膜を用いた場合でも、パルス幅を長くすると、界面の最高到達温度が９５０℃以上になるアニール条件を維持したまま、チタン膜の表面の温度上昇を抑制することができる。 From the simulation results when using a nickel film, it was confirmed that increasing the pulse width makes it difficult for the surface temperature of the nickel film to rise while maintaining the annealing conditions at which the maximum interface temperature reaches 950 ° C or higher. It was. Even when a titanium film is used instead of the nickel film, if the pulse width is increased, the temperature rise on the surface of the titanium film can be suppressed while maintaining the annealing condition where the maximum temperature at the interface is 950 ° C. or higher. .
チタン膜の厚さが３０ｎｍ〜１００ｎｍの範囲内で、界面の最高到達温度が９５０℃、かつチタン膜の表面の最高到達温度が１６６８℃以下となるアニール条件が存在することがシミュレーションにより確認された。パルス幅が２０ｎｓ以上、かつパルスエネルギ密度が１．６Ｊ／ｃｍ２以上の条件で、非溶融シリサイド化が可能であることが確認された。パルスエネルギ密度は、チタン膜の表面の最高到達温度がチタンの融点と等しくなる大きさよりも低い範囲内に設定される。 It was confirmed by simulation that there are annealing conditions in which the maximum reached temperature of the interface is 950 ° C. and the maximum reached temperature of the surface of the titanium film is 1668 ° C. or less within the thickness range of 30 nm to 100 nm. . It was confirmed that non-molten silicidation was possible under the conditions of a pulse width of 20 ns or more and a pulse energy density of 1.6 J / cm 2 or more. The pulse energy density is set in a range lower than the magnitude at which the maximum temperature reached on the surface of the titanium film is equal to the melting point of titanium.
上記シミュレーションでは、パルスレーザビームの波長を３５５ｎｍとしたが、波長３００ｎｍ〜４００ｎｍの紫外域のパルスレーザビームを用いても、ほぼ同様の条件で非溶融シリサイド化を行うことが可能である。パルスレーザビームとして、Ｎｄ：ＹＡＧレーザ、Ｎｄ：ＹＶＯ４レーザ、Ｎｄ：ＹＬＦレーザ等の固体レーザの３倍高調波、エキシマレーザ等を用いることができる。 In the above simulation, the wavelength of the pulsed laser beam is 355 nm, but non-molten silicidation can be performed under substantially the same conditions using a pulsed laser beam in the ultraviolet region with a wavelength of 300 nm to 400 nm. As the pulse laser beam, a third harmonic of a solid-state laser such as an Nd: YAG laser, an Nd: YVO 4 laser, or an Nd: YLF laser, an excimer laser, or the like can be used.
ＳｉＣは、この波長域の光を吸収するため、金属膜１６（図１Ｆ）に入射したパルスレーザビーム２０が、基板１０の第２の表面１０Ｂまで到達しない。このため、素子構造１５の温度上昇を抑制することができる。
Since SiC absorbs light in this wavelength range, the
上記シミュレーションでは、パルス幅Ｐｗを１０ｎｓ〜５０ｎｓの範囲に設定したが、パルス幅Ｐｗが５０ｎｓ以上の範囲にも、非溶融シリサイド化を行うことが可能なアニール条件が存在する。パルス幅Ｐｗが５０ｎｓ以上になると、十分なピークパワー密度を維
持するために、パルスエネルギ密度を高くすることが好ましい。
In the above simulation, the pulse width Pw is set in the range of 10 ns to 50 ns, but there are annealing conditions that enable non-molten silicidation even in the range of the pulse width Pw of 50 ns or more. When the pulse width Pw is 50 ns or more, it is preferable to increase the pulse energy density in order to maintain a sufficient peak power density.
以上実施例に沿って本発明を説明したが、本発明はこれらに制限されるものではない。例えば、種々の変更、改良、組み合わせ等が可能なことは当業者に自明であろう。 Although the present invention has been described with reference to the embodiments, the present invention is not limited thereto. It will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.
１０ 基板
１０Ａ 第１の表面
１０Ｂ 第２の表面
１１ ガードリング
１２ 絶縁膜
１３ ショットキ電極
１４ 表面電極
１５ 素子構造
１６ 金属膜
１７ 金属シリサイド膜
２０ パルスレーザビーム
10
Claims (6)
前記金属膜に紫外域の波長を有するパルスレーザビームを照射して、前記基板と前記金属膜との界面においてシリサイド反応を生じさせることにより、金属シリサイド膜を形成する工程と
を有し、
前記金属シリサイド膜を形成する工程において、前記金属膜の表面が溶融しない条件で前記パルスレーザビームを照射する半導体装置の製造方法。 Forming a metal film made of nickel or titanium on a first surface of a substrate made of silicon carbide;
Irradiating the metal film with a pulsed laser beam having a wavelength in the ultraviolet region to cause a silicide reaction at the interface between the substrate and the metal film, thereby forming a metal silicide film,
A method of manufacturing a semiconductor device, wherein, in the step of forming the metal silicide film, the pulsed laser beam is irradiated under a condition that a surface of the metal film is not melted.
前記金属膜がニッケルからなり、前記金属膜の厚さが３０ｎｍ〜２５０ｎｍの範囲内である請求項１に記載の半導体装置の製造方法。 The pulsed laser beam has a wavelength in the range of 300 nm to 400 nm;
The method of manufacturing a semiconductor device according to claim 1, wherein the metal film is made of nickel, and the thickness of the metal film is in a range of 30 nm to 250 nm.
前記金属膜がチタンからなり、前記金属膜の厚さが３０ｎｍ〜１００ｎｍの範囲内である請求項１に記載の半導体装置の製造方法。 The pulsed laser beam has a wavelength in the range of 300 nm to 400 nm;
The method for manufacturing a semiconductor device according to claim 1, wherein the metal film is made of titanium, and the thickness of the metal film is in a range of 30 nm to 100 nm.
前記基板の、前記第１の表面とは反対側の第２の表面に、素子構造を形成する工程と、
前記素子構造を形成した後、前記基板を、前記第１の表面から研削することにより薄くする工程と
を含み、
前記金属膜を形成する工程において、薄くされた前記基板の前記第１の表面に前記金属膜を形成する請求項１乃至５のいずれか１項に記載の半導体装置の製造方法。 Before the step of forming the metal film,
Forming an element structure on a second surface of the substrate opposite to the first surface;
After forming the device structure, the substrate is thinned by grinding from the first surface,
The method for manufacturing a semiconductor device according to claim 1, wherein in the step of forming the metal film, the metal film is formed on the first surface of the thinned substrate.
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| JP2015513218A (en) * | 2012-03-05 | 2015-04-30 | アーベーベー・テクノロジー・アーゲー | Power semiconductor device and manufacturing method thereof |
| WO2016031312A1 (en) * | 2014-08-26 | 2016-03-03 | 住友重機械工業株式会社 | Method for manufacturing semiconductor element |
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| JP2017130550A (en) * | 2016-01-20 | 2017-07-27 | 国立大学法人広島大学 | Silicon carbide semiconductor device and manufacturing method of the same |
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| JP3184115B2 (en) * | 1997-04-11 | 2001-07-09 | 松下電器産業株式会社 | Ohmic electrode formation method |
| US20050104072A1 (en) * | 2003-08-14 | 2005-05-19 | Slater David B.Jr. | Localized annealing of metal-silicon carbide ohmic contacts and devices so formed |
| JP5436231B2 (en) * | 2009-01-16 | 2014-03-05 | 昭和電工株式会社 | Semiconductor element manufacturing method, semiconductor element, and semiconductor device |
| JP2012069798A (en) * | 2010-09-24 | 2012-04-05 | Toyota Motor Corp | Method of manufacturing semiconductor device |
| JP5418466B2 (en) * | 2010-11-01 | 2014-02-19 | 住友電気工業株式会社 | Semiconductor device and manufacturing method thereof |
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