JP2014120609A - Semiconductor device, and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an excellent semiconductor device having a high radiation resistance, and to provide a method of manufacturing the same.SOLUTION: A semiconductor device comprises: a first well 16N of a second conductivity type formed in a semiconductor substrate 10 of a first conductivity type; a first transistor 22 of the first conductivity type formed to the first well; a second well 16P of the first conductivity type formed in the semiconductor substrate, and adjacent to the first well; and a second transistor 18 of the second conductivity type formed to the second well, and electrically connected with the first transistor. The semiconductor device comprises an embedded impurity layer 14 of the first conductivity type formed in the semiconductor substrate at least at a lower part of the first well. A distance between a concentration peak position of the embedded impurity layer and that of the first well is 1 μm or more.

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  A single event effect (SEE) is known as a phenomenon that occurs when radiation passes through a semiconductor chip.

  One of the typical phenomena of the single event effect is latch-up, which is called single event latch-up (SEL).

  In addition, as one of the typical phenomena of the single event effect, a single event upset (SEU), which is a phenomenon in which memory data is inverted, is also known.

  In order to prevent malfunction or breakage of electronic equipment, it is important to make errors due to the single event effect less likely to occur.

Japanese Patent Laid-Open No. 2003-60071 International Publication No. 2006/131986 Pamphlet Japanese Patent Laid-Open No. 9-223747

  However, with recent miniaturization of semiconductor devices, single event latch-up tends to occur.

  An object of the present invention is to provide a good semiconductor device having high radiation resistance and a method for manufacturing the same.

  According to one aspect of the embodiment, the first conductivity type first well formed in the first conductivity type, the first conductivity type first well formed in the first conductivity type semiconductor substrate, and the first conductivity type first well formed in the first well. A transistor, a second well of the first conductivity type formed in the semiconductor substrate and adjacent to the first well, and formed in the second well and electrically connected to the first transistor The second conductivity type second transistor, and at least the first conductivity type buried impurity layer formed in the semiconductor substrate below the first well. A semiconductor device is provided in which the distance between the concentration peak position of the impurity layer and the concentration peak position of the first well is 1 μm or more.

  According to another aspect of the embodiment, a dopant impurity of a first conductivity type is introduced into at least a first region of a semiconductor substrate of a first conductivity type by a first energy, and the surface of the semiconductor substrate is introduced into the semiconductor substrate. Forming a buried impurity layer of the first conductivity type separated from the first conductivity type, and introducing a second conductivity type dopant impurity into the first region of the semiconductor substrate by a second energy lower than the first energy; Forming a first well of the second conductivity type in the semiconductor substrate; and adding a first impurity impurity of the first conductivity type to a second region of the semiconductor substrate adjacent to the first region. Introducing a second well of the first conductivity type in the semiconductor substrate, introducing the first transistor of the first conductivity type into the first transistor Forming a second transistor of the second conductivity type formed in the well and connected to the first transistor in the second well, and a concentration peak position of the buried impurity layer and the first transistor A method for manufacturing a semiconductor device is provided, wherein the distance from the concentration peak position of one well is 1 μm or more.

  According to the disclosed semiconductor device and the manufacturing method thereof, the conductivity type of the buried impurity layer is set to the first conductivity type that is the same conductivity type as that of the semiconductor substrate. When neutrons or α particles pass through a depletion layer located between the second conductivity type first well and the second conductivity type buried impurity layer, the second conductivity type buried impurity layer functions as a barrier. And funneling is cut. Only a small amount of charge is generated until the funneling is cut off, and even if a small amount of charge is taken into the first well or the second well, the parasitic thyristor is unlikely to be turned on. It is hard to reach up. Since no depletion layer is formed below the first conductivity type second well, no funneling occurs even if neutrons or the like pass through the second well. Moreover, the distance between the concentration peak position of the second conductivity type first well and the concentration peak position of the first conductivity type buried impurity layer is set to 1 μm or more. Since the distance between the concentration peak position of the second conductivity type first well and the concentration peak position of the first conductivity type buried impurity layer is not excessively small, the electrical resistance in the second conductivity type first well Is relatively small, making it difficult for the parasitic thyristor to turn on. In addition, since the distance between the concentration peak position of the second conductivity type first well and the concentration peak position of the first conductivity type buried impurity layer is not excessively small, the second conductivity type first well The impurity profile between the buried impurity layer of the first conductivity type is not excessively steep. For this reason, the junction leakage current between the first well of the second conductivity type and the buried impurity layer of the first conductivity type is suppressed to be small. For this reason, it is possible to provide a semiconductor device having high radiation resistance while suppressing junction leakage current.

FIG. 1 is a cross-sectional view illustrating a semiconductor device according to an embodiment. FIG. 2 is a diagram illustrating a layout of the memory cell array of the semiconductor device according to the embodiment. FIG. 3 is a schematic diagram showing a phenomenon that occurs when neutrons or α particles are incident. FIG. 4 is a graph showing an impurity profile of the semiconductor device according to the embodiment. FIG. 5 is a graph showing the occurrence rate of single event latch-up. FIG. 6 is a graph showing the measurement result of the junction leakage current. FIG. 7 is a process cross-sectional view (part 1) illustrating the method for manufacturing the semiconductor device according to the embodiment. FIG. 8 is a process cross-sectional view (Part 2) illustrating the method for manufacturing the semiconductor device according to the embodiment. FIG. 9 is a process cross-sectional view (Part 3) illustrating the method for manufacturing the semiconductor device according to the embodiment. FIG. 10 is a process cross-sectional view (Part 4) illustrating the method for manufacturing the semiconductor device according to the embodiment. FIG. 11 is a process cross-sectional view (part 5) illustrating the method for manufacturing the semiconductor device according to the embodiment. FIG. 12 is a process cross-sectional view (Part 6) illustrating the method for manufacturing a semiconductor device according to the embodiment. FIG. 13 is a cross-sectional view schematically showing a semiconductor device having a CMOS inverter. FIG. 14 is an equivalent circuit showing a parasitic thyristor formed in the semiconductor device shown in FIG. FIG. 15 is a cross-sectional view showing a semiconductor device according to a reference example.

  FIG. 13 is a cross-sectional view schematically showing a semiconductor device having a CMOS inverter.

  As shown in FIG. 13, a P-type semiconductor substrate 110 is formed with a P-type well 116P and an N-type well 116N. An NMOS transistor 118 having a gate electrode 128a and a source / drain diffusion layer 140 is formed in the P-type well 116P. In the N-type well 116N, a PMOS transistor 122 having a gate electrode 128b and a source / drain diffusion layer 144 is formed. An input signal line Vin is connected to the gate electrodes 128a and 128b. The drain 144 of the PMOS transistor 122 and the drain 144 of the NMOS transistor 118 are electrically connected to each other and to the output signal line Vout. The source 140 of the NMOS transistor 118 and the well tap region 120 of the P-type well 116P are connected to the ground potential Vss. The source 144 of the PMOS transistor and the well tap region 124 of the N-type well 116N are connected to the power supply potential Vdd. The NMOS transistor 118 and the PMOS transistor 122 form a CMOS inverter.

  In a semiconductor device having such a CMOS inverter, a parasitic thyristor is formed as shown in FIG.

  FIG. 14 is an equivalent circuit showing a parasitic thyristor formed in the semiconductor device shown in FIG.

  As shown in FIG. 14, a parasitic PNP transistor Tr1, a parasitic NPN transistor Tr2, and parasitic resistors R1 to R4 are formed. The parasitic resistance R1 is a parasitic resistance between the emitter of the parasitic PNP transistor Tr1 and the source 144 of the PMOS transistor 122. The parasitic resistance R2 is a parasitic resistance between the base of the parasitic PNP transistor Tr1 and the well tap region 124 of the N-type well 116N. The parasitic resistance R3 is a parasitic resistance between the emitter of the parasitic NPN transistor Tr2 and the source 140 of the NMOS transistor 118. The parasitic resistance R4 is a parasitic resistance between the base of the parasitic NPN transistor and the well tap region 120 of the P-type well 116P.

  When neutrons or α particles are incident on the depletion layer of a semiconductor device in which such a parasitic thyristor is formed, funneling occurs, which is a phenomenon in which the depletion layer extends along the locus of neutrons, etc., and charge ( Electron hole pairs) are generated. When the charge thus generated reaches the wells 116P and 116N, the parasitic thyristor is turned on, and latch-up may occur. Such a phenomenon is called single event latch-up.

  In order to prevent the parasitic thyristor from being turned on, it is conceivable to reduce the parasitic resistance R2 and the parasitic resistance R4.

  For example, if a large number of well tap regions 120 and 124 are arranged at each location in the wells 116P and 116N, the parasitic resistance R2 and the parasitic resistance R4 can be reduced, and the parasitic thyristor is hardly turned on.

  However, in the case where the well tap regions 120 and 124 are arranged at the respective locations in the wells 116P and 116N, the total space required for arranging the well tap regions 120 and 124 becomes large, and the semiconductor device can be downsized. Contrary to the request.

  FIG. 15 is a cross-sectional view showing a semiconductor device according to a reference example.

  In the P-type semiconductor substrate 110, an element isolation region 112 that defines an element region is formed. A P-type well 116P and an N-type well 116N are formed on the semiconductor substrate 110 on which the element isolation region is formed. An NMOS transistor 118 having a gate electrode 128a and a source / drain diffusion layer 140 is formed in the P-type well 116P. In the N-type well 116N, a PMOS transistor 122 having a gate electrode 128b and a source / drain diffusion layer 144 is formed. A P-type well tap region 120 is formed in the P-type well 116P. An N-type well tap region 124 is formed in the N-type well 116N.

  An N-type buried impurity layer 114 is formed below the P-type well 116P and the N-type well 116N. The N-type buried impurity layer 114 is for suppressing single event latch-up.

  When neutrons or the like pass through a depletion layer positioned between the P-type well 116P and the N-type buried impurity layer 114, funneling occurs along the locus of neutrons or the like. At this time, the N-type buried impurity layer 114 functions as a barrier, and funneling is cut in the N-type buried impurity layer 114. For this reason, the amount of charges taken into the wells 116P and 116N can be suppressed to a small value. Minimizing the amount of charge taken into the wells 116P and 116N when funneling occurs can contribute to prevention of single event latch-up.

  However, when neutrons or the like enter the region where the N-type well 116N is formed, the neutrons or the like pass through the depletion layer formed between the N-type buried impurity layer 114 and the P-type semiconductor substrate 110. Funneling occurs. In this case, since there is no barrier for cutting the funneling, a relatively large amount of charge is taken into the well 116N, which may cause a single event latch-up.

[One Embodiment]
A semiconductor device and a manufacturing method thereof according to an embodiment will be described with reference to FIGS.

(Semiconductor device)
First, the semiconductor device according to the present embodiment will be explained with reference to FIGS. FIG. 1 is a sectional view of the semiconductor device according to the present embodiment.

  In this embodiment, a semiconductor device having a static memory cell having a flip-flop circuit, that is, an SRAM (Static Random Access Memory) will be described as an example.

  As the semiconductor substrate 10, for example, a P-type semiconductor substrate is used. As the P-type semiconductor substrate 10, for example, a P-type silicon substrate is used.

  In the semiconductor substrate 10, an element isolation region 12 that defines an element region is formed. As a material of the element isolation region 12, for example, a silicon oxide film is used.

  A buried impurity layer (buried well) 14 is formed in the semiconductor substrate 10 in which the element region is defined by the element isolation region 12. The conductivity type of the buried impurity layer 14 is set to P type, which is the same conductivity type as that of the semiconductor substrate 10. The P type buried impurity layer (deep P type well, Deep P-Well) 14 is formed below the P type well 16P and the N type well 16N. The embedded impurity layer 14 is embedded in the semiconductor substrate 10 at a distance from the surface of the semiconductor substrate 10. The concentration peak of the buried impurity layer 16P is located at a depth of, for example, about 1.8 μm from the surface of the semiconductor substrate 10. Since the conductivity type of the P-type well 16, the conductivity type of the buried impurity layer 14, and the conductivity type of the semiconductor substrate 10 are all the same P-type, the lower side of the P-type well 16 is a continuous P-type semiconductor. Yes. Therefore, no depletion layer exists below the P-type well 16.

  The P-type well 16P is formed so as to include a region where the NMOS transistor 18 is formed and a well tap region (contact layer) 20. The well tap region 20 is for connecting the P-type well 16P to the ground potential Vss. The concentration peak of the P-type well 16P is located at a depth of about 0.6 μm from the surface of the semiconductor substrate 10, for example. A P-type channel dope layer (threshold voltage control layer) (not shown) for controlling the threshold voltage of the NMOS transistor 18 is formed in the P-type well 16P.

  An N-type well 16N is formed adjacent to the P-type well 16P. The N-type well is formed to include a region where the PMOS transistor 22 is formed and a well tap region 24. The well tap region 24 is for connecting the N-type well 16N to the power supply potential Vdd. The concentration peak of the N-type well 16N is located at a depth of about 0.5 μm from the surface of the semiconductor substrate 10, for example. The distance between the concentration peak position of the N-type well 16N and the concentration peak position of the P-type buried impurity layer 14 is, for example, about 1.3 μm. An N-type channel dope layer (threshold voltage control layer) (not shown) for controlling the threshold voltage of the PMOS transistor 22 is formed in the N-type well 16N.

  On the semiconductor substrate 10 on which the P-type well 16P, the N-type well 16N, and the p-type buried impurity layer 14 are formed, a gate insulating film 26 of, for example, a silicon oxide film with a film thickness of about 3 nm is formed.

  On the gate insulating film 26, for example, polysilicon gate electrodes 28a and 28b having a height of about 100 nm are formed. The gate length is, for example, about 40 to 90 nm.

  In the semiconductor substrate 10 on both sides of the gate electrode 28a of the NMOS transistor 18, an N-type extension region (low-concentration impurity region) 30 for forming a shallow impurity region having an extension source / drain structure is formed. A P-type pocket region (not shown) is formed between the channel region 32 and the extension region 30 of the NMOS transistor 18.

  In the semiconductor substrate 10 on both sides of the gate electrode 28b of the PMOS transistor 22, a P-type extension region (low-concentration impurity region) 34 for forming a shallow impurity region having an extension source / drain structure is formed. An N-type pocket region (not shown) is formed between the channel region 35 and the extension region 34 of the PMOS transistor 22.

  Side wall spacers 36 made of, for example, a silicon oxide film are formed on the side walls of the gate electrodes 28a and 28b.

  In the semiconductor substrate 10 on both sides of the gate electrode 28a of the NMOS transistor 18 in which the sidewall spacer 36 is formed, an N-type high concentration impurity region 38 for forming a deep impurity region of the extension source / drain structure is formed. . A source / drain diffusion layer 40 having an extension source / drain structure is formed by the N-type low concentration impurity region 30 and the N-type high concentration impurity region 38.

  Thus, an NMOS transistor (N-channel MOS transistor) 18 having the gate electrode 28a and the source / drain diffusion layer 40 is formed.

  In the semiconductor substrate 10 on both sides of the gate electrode 28b of the PMOS transistor 22 in which the sidewall spacers 36 are formed, a P-type high concentration impurity region 42 for forming a deep impurity region of an extension source / drain structure is formed. . A source / drain diffusion layer 44 having an extension source / drain structure is formed by the P-type low concentration impurity region 34 and the P-type high concentration impurity region 42.

  Thus, the PMOS transistor (P-channel MOS transistor) 22 having the gate electrode 28b and the source / drain diffusion layer 44 is formed.

  On the source / drain diffusion layer 40 of the NMOS transistor 18 and the source / drain diffusion layer 44 of the PMOS transistor 22, for example, a silicide film 46 of cobalt silicide is formed. The silicide film 46 on the source / drain diffusion layers 40 and 44 functions as a source / drain electrode. In addition, a silicide film 46 of, for example, cobalt silicide is formed on the gate electrode 28a of the NMOS transistor 18 and the gate electrode 28b of the PMOS transistor 22. Also, a silicide film 46 of cobalt silicide, for example, is formed on the well tap regions 20 and 24.

  On the semiconductor substrate 10 on which the NMOS transistor 18 and the PMOS transistor 22 are formed, an interlayer insulating film 48 of, for example, a silicon oxide film having a thickness of about 1 μm is formed.

  A contact hole 50 reaching the source / drain electrode 46 is formed in the interlayer insulating film 48. In addition, contact holes (not shown) reaching the gate electrodes 28 a and 28 b are formed in the interlayer insulating film 48. A contact hole 50 reaching the silicide film 46 on the well tap regions 20 and 24 is formed in the interlayer insulating film 48.

  In the contact hole 50, for example, a barrier film (not shown) formed of a laminated film of a Ti film having a thickness of about 5 to 20 nm and a TiN film having a thickness of about 5 to 20 nm is formed.

  For example, a tungsten conductor plug 52 is buried in the contact hole 50 in which the barrier film is formed.

  On the inter-layer insulation film 48 with the conductor plugs 52 buried in, an inter-layer insulation film 54 of, eg, a silicon oxide film with a film thickness of about 300 nm is formed.

  In the interlayer insulating film 54, a groove 56 exposing the upper portion of the conductor plug 52 is formed.

  A barrier film (not shown) is formed in the groove 56.

  For example, a Cu wiring 58 is buried in the groove 56 in which the barrier film is formed.

  FIG. 2 is a diagram showing a layout of the memory cell array of the semiconductor device according to the present embodiment.

  In FIG. 2, a portion surrounded by a broken line indicates one memory cell MC. As shown in FIG. 2, a plurality of static memory cells MC having flip-flop circuits 62 are arranged in a matrix.

  The memory cell MC has a flip-flop circuit 62 in which two CMOS inverters (CMOS circuits) 60a and 60b formed by PMOS transistors L1 and L2 and NMOS transistors D1 and D2 connected in series are complementarily connected. ing. The PMOS transistors L1 and L2 are called load transistors. The NMOS transistors D1 and D2 are called driver transistors.

  An input node (input terminal) 64 of the CMOS inverter 60a formed by the load transistor L1 and the driver transistor D2 is connected to an output node (output terminal) 66 of the CMOS inverter 60b. An input node 68 of the inverter 60b formed by the load transistor L2 and the driver transistor D2 is connected to an output node 70 of the CMOS inverter 60a.

  The CMOS inverter 60a receives the signal of the output node 66 of the CMOS inverter 60b and outputs a logic inversion signal of the input signal. Further, the CMOS inverter 60b receives the signal of the output node 70 of the CMOS inverter 60a and outputs a logically inverted signal of the input signal.

  The output node 70 of the inverter 60a and the input node 68 of the inverter 60b are connected to one of the source / drain of the transfer transistor T1 formed by an NMOS transistor. The other of the source / drain of the transfer transistor T1 is connected to the bit line BL.

  The output node 66 of the CMOS inverter 60b and the input node 64 of the CMOS inverter 60a are connected to one of the source / drain of the transfer transistor T2 formed by an NMOS transistor. The other of the source / drain of the transfer transistor T2 is connected to the bit line / BL.

  The NMOS transistors 22 shown in FIG. 1 correspond to the driver transistors D1, D2 and transfer transistors T1, T2 used in the memory cell MC. Further, the PMOS transistors 18 shown in FIG. 1 correspond to the load transistors L1 and L2 used in the memory cell MC.

  The gates of the transfer transistors T1 and T2 are connected to the word lines WL and / WL.

  The gates of the transfer transistors T1 and T2 of the plurality of memory cells MC arranged in the same row are commonly connected by the same word lines WL and / WL.

  The other of the sources / drains of the transfer transistors T1, T2 of the plurality of memory cells 10 arranged in the same column is commonly connected by the same bit lines BL, / BL.

  Each word line WL, / WL is connected to a row decoder (not shown).

  Each bit line BL, / BL is connected to a column decoder (not shown).

  From the viewpoint of space saving or the like, as shown in FIG. 2, a plurality of transistors L1, L2, D1, D2, T1, T2 are formed in one well 16P, 16N. Further, from the viewpoint of space saving, the well tap regions 20 and 24 are not arranged in the vicinity of each of the plurality of transistors L1, L2, D1, D2, T1, and T2, but as shown in FIG. Well tap regions 20 and 24 are arranged at the edges of 16P and 16N.

  The reason why the conductivity type of the buried impurity layer 14 is set to P type in this embodiment will be described below.

  FIG. 3 is a schematic diagram showing a phenomenon that occurs when neutrons or α particles are incident.

  FIG. 3B shows a case where the conductivity type of the buried impurity layer is N-type, that is, a case where the conductivity type of the buried impurity layer is different from the conductivity type of the semiconductor substrate.

  In the semiconductor device in which the N type buried impurity layer 14N is formed as shown in FIG. 3B, when neutrons pass through the depletion layer located between the P type well 16P and the N type buried impurity layer 14N, Funneling, a phenomenon in which a depletion layer extends along an orbit of neutrons or the like, occurs. At this time, the N-type buried impurity layer 14N functions as a barrier against funneling, and the funneling is cut. In the region below the portion where the funneling is cut, electron-hole pairs generated along the locus of neutrons and the like are recombined without being taken into the wells 16P and 16N. Only a few electron-hole pairs are generated before the funneling is cut off, and even if a small amount of charge is taken into the wells 16N and 16P, it is difficult to achieve single event latch-up.

  However, in the semiconductor device in which the N-type buried impurity layer 14N is formed, a depletion layer positioned between the N-type buried impurity layer 14N and the P-type semiconductor substrate 10 in a portion below the N-type well 16N is formed as a neutron. And so on, it will be as follows. That is, when neutrons or the like pass through a depletion layer located between the N-type buried impurity layer 14N and the P-type semiconductor substrate 10 in the lower part of the N-type well 16N, funneling occurs along the orbit of the neutrons. At this time, since there is no functioning as a barrier for funneling, the funneling is elongated for a long time. Since the funneling extends for a long time, there is a risk that a large amount of charge generated along the locus of neutrons and the like may be taken into the wells 16N and 16P, and the parasitic thyristor is turned on, leading to a single event latch-up.

  FIG. 3A shows the case of this embodiment, that is, the case where the conductivity type of the buried impurity layer is the same P type as that of the semiconductor substrate.

  In the semiconductor device in which the P-type buried impurity layer 14 is formed as shown in FIG. 3A, even if neutrons or the like pass through the P-type well 16P, there is no depletion layer below the P-type well 16P. Therefore, no funneling occurs. For this reason, a large amount of charge is not taken into the wells 16N and 16P, and single event latch-up does not occur.

  In the semiconductor device in which the P type buried impurity layer 14 is formed, funneling occurs when neutrons or the like pass through a depletion layer located between the N type well 16N and the P type buried impurity layer 14. . At this time, the P-type buried impurity layer 14 functions as a barrier against funneling, and the funneling is cut. In the region below the portion where the funneling is cut, electron-hole pairs generated along the locus of neutrons and the like are recombined without being taken into the wells 16P and 16N. Only a few electron-hole pairs are generated before the funneling is cut off, and even if a small amount of charge is taken into the wells 16N and 16P, it is difficult to achieve single event latch-up.

  For this reason, in this embodiment, the conductivity type of the buried impurity layer 14 is set to P type, which is the same conductivity type as that of the semiconductor substrate.

  Next, the distance between the concentration peak position of the P-type buried impurity layer 14 and the concentration peak position of the N-type well 16N will be described. In the present embodiment, the distance between the concentration peak position of the P-type buried impurity layer 14 and the concentration peak position of the N-type well 16N is set to an appropriate value from the following viewpoint.

  That is, if the distance between the concentration peak position of the P-type buried impurity layer 14 and the concentration peak position of the N-type well 16N is reduced, the electrical resistance in the N-type well 16N increases. When the electric resistance in the N-type well 16N increases, the parasitic thyristor is likely to be turned on, and single event latch-up is likely to occur. When the distance between the position of the concentration peak of the P-type buried impurity layer 14 and the position of the concentration peak of the N-type well 16N is smaller than 1 μm, the N-type well is apt to cause single event latch-up or the like. The electrical resistance at 16N increases.

  Further, if the distance between the concentration peak position of the P-type buried impurity layer 14 and the concentration peak position of the N-type well 16N is reduced, the impurity is introduced between the P-type buried impurity layer 14 and the N-type well 16N. The profile becomes steep and the junction leakage current increases. In order to reduce the junction leakage current to a desired level, the distance between the concentration peak position of the P-type buried impurity layer 14 and the concentration peak position of the N-type well 16N is preferably 1 μm or more. .

  As described above, in order to surely prevent single event latch-up and the like while sufficiently suppressing the junction leakage current, the position between the concentration peak position of the P-type buried impurity layer 14 and the concentration peak position of the N-type well 16N. The distance between them is preferably 1 μm or more.

  On the other hand, the distance between the concentration peak position of the P-type buried impurity layer 14 and the concentration peak position of the N-type well 16N is preferably less than 4 μm. The reason why the distance between the concentration peak position of the P-type buried impurity layer 14 and the concentration peak position of the N-type well 16N is less than 4 μm is as follows.

  That is, when the distance between the concentration peak position of the N-type well 16N and the concentration peak position of the P-type buried impurity layer 14 is increased, the depletion layer formed under the N-type well 16N is changed to the P-type buried diffusion layer. The distance up to 14 increases. A depletion layer generated under the N-type well 16N can be a starting point of funneling. On the other hand, the P-type buried diffusion layer 14 functions as a barrier against funneling and can serve as an end point of funneling. As the distance between the concentration peak position of the N-type well 16N and the concentration peak position of the P-type buried impurity layer 16P increases, the distance from the start point to the end point of the funneling increases and is taken into the wells 16N and 16P. The amount of charge generated becomes large. When the distance between the concentration peak position of the P-type buried impurity layer 14 and the concentration peak position of the N-type well 16N is 4 μm or more, the well 16N, The amount of charge taken into 16P increases. Therefore, when the distance between the concentration peak position of the P-type buried impurity layer 14 and the concentration peak position of the N-type well 16N is 4 μm or more, single event latch-up or the like cannot be sufficiently suppressed.

  Therefore, the distance between the concentration peak position of the P-type buried impurity layer 14 and the concentration peak position of the N-type well 16N is preferably less than 4 μm.

  As described above, the distance between the position of the concentration peak of the P-type buried impurity layer 14 and the position of the concentration peak of the N-type well 16N can sufficiently suppress the junction leakage current, and can reduce the single event latch-up. What is necessary is just to set suitably so that it can fully suppress.

  From this point of view, in this embodiment, the distance between the concentration peak position of the P-type buried impurity layer 14 and the concentration peak position of the N-type well 16N is set to 1.3 μm, for example.

  The distance between the concentration peak position of the P-type buried impurity layer 14 and the concentration peak position of the N-type well 16N is not limited to 1.3 μm. As described above, the distance between the concentration peak position of the P-type buried impurity layer 14 and the concentration peak position of the N-type well 16N can be appropriately set to 1 μm or more. As described above, the distance between the concentration peak position of the P-type buried impurity layer 14 and the concentration peak position of the N-type well 16N is preferably less than 4 μm.

  FIG. 4 is a graph showing an impurity profile of the semiconductor device according to the present embodiment. FIG. 4A is a graph showing the impurity profile along the depth direction in the region where the P-type well 16P is formed. FIG. 4B is a graph showing the impurity profile along the depth direction in the region where the N-type well 16N is formed. The horizontal axis in FIGS. 4A and 4B indicates the depth from the surface of the semiconductor substrate 10. The vertical axis in FIGS. 4A and 4B indicates the impurity concentration.

  As can be seen from FIG. 4B, the distance between the position of the N-type impurity concentration peak in the N-type well 16N and the position of the P-type impurity concentration peak in the P-type buried impurity layer 14 is 1 μm or more. It has become.

(Evaluation results)
Next, the evaluation results of the semiconductor device according to the present embodiment will be explained with reference to FIGS.

  First, the occurrence rate of single event latch-up will be described with reference to FIG. FIG. 5 is a graph showing the occurrence rate of single event latch-up.

  Comparative Example 1 shows a case where the buried impurity layer 14 is not provided in the semiconductor substrate 10. Comparative Example 2 shows a case where the distance between the concentration peak position of the N-type well 16N and the concentration peak position of the P-type buried impurity layer 14 is 4 μm. In Comparative Example 3, the conductivity type of the buried impurity layer 14 is N-type, and the distance between the concentration peak position of the N-type well 16N and the concentration peak position of the N-type buried impurity layer 14 is 1 μm. Show. Example 1 corresponds to this embodiment, and shows a case where the distance between the concentration peak position of the N-type well 16N and the concentration peak position of the P-type buried impurity layer 14 is 1 μm. Yes.

When measuring the occurrence rate of single event latch-up, the memory cell MC was irradiated with a neutron beam, and the number of occurrences of single event latch-up per 1 × 10 ⁹ hours was determined. Then, normalization was performed so that the occurrence rate of single event latch-up in Comparative Example 1 was 1.

  As can be seen from FIG. 5, in Comparative Example 2, that is, when the distance between the concentration peak position of the N-type well 16N and the concentration peak position of the P-type buried impurity layer 14 is 4 μm, a single event latch is used. The occurrence rate of up was the same as in Comparative Example 1.

  Therefore, when the distance between the concentration peak position of the N-type well 16N and the concentration peak position of the P-type buried impurity layer 14 is 4 μm, single event latch-up can be sufficiently prevented. It turns out to be difficult.

  Comparative Example 3, that is, the conductivity type of the buried impurity layer 14 is N-type, and the distance between the concentration peak position of the N-type well 16N and the concentration peak position of the N-type buried impurity layer 14 is 1 μm. The occurrence rate of single event latch-up was about 0.06 times that of Comparative Example 1.

  In the case of Example 1, that is, in the case of the present embodiment, no single event latch-up occurred.

  From these things, it turns out that according to this embodiment, single event latch-up can be suppressed reliably.

  Next, the evaluation result of the junction leakage current will be described with reference to FIG. FIG. 6 is a graph showing the measurement result of the junction leakage current.

  Comparative Example 4 shows a case where the buried impurity layer 14 is not provided in the semiconductor substrate 10. In Comparative Example 5, the conductivity type of the buried impurity layer 14 is N-type, and the distance between the concentration peak position of the N-type well 16N and the concentration peak position of the N-type buried impurity layer 14 is 1 μm. Show. Example 2 corresponds to this embodiment, and shows a case where the distance between the concentration peak position of the N-type well 16N and the concentration peak position of the P-type buried impurity layer 14 is 1 μm. Yes.

  The ambient temperature when measuring the junction leakage current was 125 ° C. And it normalized so that the junction leakage current value in the case of the comparative example 4 might be set to 1.

  As can be seen from FIG. 6, the conductivity type of the buried impurity layer 14 is N-type, and between the concentration peak position of the N-type well 16N and the concentration peak position of the N-type buried impurity layer 14. When the distance was 1 μm, the junction leakage current increased by 10% compared to the case of Comparative Example 4.

  In Comparative Example 5, the junction leakage current increases because in Comparative Example 5, the N-type buried impurity layer 14 is provided in a wider range than the range in which the N-type well 16P is formed, and the N-type buried impurity layer This is probably because the bonding area between the P-type semiconductor substrate 10 and P-type semiconductor substrate 10 is large.

  On the other hand, in the case of Example 2, that is, in the case of the present embodiment, the junction leakage current was equivalent to that of Comparative Example 4.

  From this, it can be seen that according to the present embodiment, the leakage current can be kept low.

  As described above, according to the present embodiment, the buried impurity layer 14 is set to the P type, which is the same conductivity type as that of the semiconductor substrate 10. When neutrons and α particles pass through a depletion layer located between the N-type well 16N and the buried impurity layer 14, the P-type buried impurity layer 14 functions as a barrier, and funneling is cut. Only a small amount of charge is generated until the funneling is cut off, and even if a small amount of charge is taken into the wells 16N and 16P, the parasitic thyristor is unlikely to be turned on, and therefore is unlikely to reach single event latch-up. . Since no depletion layer is formed below the P-type well 16P, no funneling occurs even if neutrons or the like pass through the P-type well 16P. Moreover, according to the present embodiment, the distance between the concentration peak position of the N-type well 16N and the concentration peak position of the P-type buried impurity layer 14 is set to 1 μm or more. Since the distance between the concentration peak position of the N-type well 16N and the concentration peak position of the P-type buried impurity layer 14 is not excessively small, the electrical resistance in the N-type well 16N is relatively small, and the parasitic The thyristor is difficult to turn on. Further, since the distance between the concentration peak position of the N-type well 16N and the concentration peak position of the P-type buried impurity layer 14 is not excessively small, the distance between the N-type well 16N and the P-type buried impurity layer 14 is The impurity profile between them is not excessively steep, and the junction leakage current is kept small. For this reason, according to the present embodiment, it is possible to provide a semiconductor device having high radiation resistance while suppressing junction leakage current.

(Method for manufacturing semiconductor device)
Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS. 7 to 12 are process cross-sectional views illustrating the semiconductor device manufacturing method according to the present embodiment.

  First, as shown in FIG. 7A, an element isolation region 12 that defines an element region is formed in a semiconductor substrate 10 by, for example, an STI (Shallow Trench Isolation) method. For example, a P-type silicon substrate is used as the semiconductor substrate 10. As a material of the element isolation region 12, for example, a silicon oxide film is used. The depth of the element isolation region 12 is, for example, about 0.25 μm.

  Next, a photoresist film 72 is formed by, eg, spin coating.

  Next, an opening 74 is formed in the photoresist film 72 using a photolithography technique (see FIG. 7B). The planar shape of the opening 74 is the same as the planar shape of the P-type buried impurity layer 14.

Next, using the photoresist film 72 as a mask, a P-type dopant impurity is introduced into the semiconductor substrate 10 by, for example, ion implantation. For example, boron (B) is used as the P-type dopant impurity. The acceleration energy is, for example, about 1 MeV. The dose amount is, for example, about 1 × 10 ¹³ cm ⁻² . As a result, a P-type buried impurity layer 14 is formed in the semiconductor substrate 10. The depth of the concentration peak position in the P-type buried impurity layer 14, that is, the distance from the surface of the semiconductor substrate 10 at the concentration peak position of the P-type buried impurity layer 14 is, for example, about 1.8 μm.

  Thereafter, the photoresist film 72 is peeled off.

  Note that the depth of the concentration peak position of the P-type buried impurity layer 14 is not limited to about 1.8 μm. The depth of the concentration peak position of the P-type buried impurity layer 14 is appropriately set so that the distance between the concentration peak position of the P-type buried impurity layer 14 and the concentration peak position of the N-type well 16N is 1 μm or more. Is done.

  Note that the distance between the concentration peak position of the P-type buried impurity layer 14 and the concentration peak position of the N-type well 16N is preferably less than 4 μm as described above.

  Next, a photoresist film 76 is formed by, eg, spin coating.

  Next, an opening 78 is formed in the photoresist film 76 by using a photolithography technique (see FIG. 7C). The planar shape of the opening 78 is equivalent to the planar shape of the P-type well 16P.

Next, using the photoresist film 76 as a mask, a P-type well 16P is formed in the semiconductor substrate 10 by introducing a P-type dopant impurity into the semiconductor substrate 10 by, for example, ion implantation. For example, boron is used as the P-type dopant impurity. The acceleration energy when forming the P-type well 16P is set lower than the acceleration energy when forming the P-type buried impurity layer. Here, the acceleration energy is, for example, 150 keV. The dose amount is, for example, about 3 × 10 ¹³ cm ⁻² . The depth of the concentration peak position of the P-type well 16P, that is, the distance from the surface of the semiconductor substrate 10 at the concentration peak position of the P-type well 16P is, for example, about 0.6 μm.

  Thereafter, the photoresist film 76 is peeled off.

  Next, a photoresist film 80 is formed by, eg, spin coating.

  Next, an opening 82 is formed in the photoresist film 80 by using a photolithography technique (see FIG. 8A). The planar shape of the opening 82 is equivalent to the planar shape of the N-type well 16N.

Next, an N-type well 16N is formed in the semiconductor substrate 10 by introducing an N-type dopant impurity into the semiconductor substrate 10 by, for example, ion implantation using the photoresist film 80 as a mask. For example, phosphorus (P) is used as the N-type dopant impurity. The acceleration energy when forming the N-type well 16N is set lower than the acceleration energy when forming the P-type buried impurity layer. Here, the acceleration energy is set to 360 keV, for example. The dose amount is, for example, about 3 × 10 ¹³ cm ⁻² . The depth of the concentration peak position of the N-type well 16N, that is, the distance from the surface of the semiconductor substrate 10 at the concentration peak position of the N-type well 16N is, for example, about 0.5 μm. In this case, the distance between the concentration peak position of the P-type buried impurity layer 14 and the concentration peak position of the N-type well 16N is, for example, about 1.3 μm.

  Thereafter, the photoresist film 80 is peeled off.

  The depth of the concentration peak position of the N-type well 16N is not limited to about 0.5 μm. The depth of the concentration peak position of the N-type well 16N is appropriately set so that the distance between the concentration peak position of the P-type buried impurity layer 14 and the concentration peak position of the N-type well 16N is 1 μm or more.

  As described above, the distance between the concentration peak position of the P-type buried impurity layer 14 and the concentration peak position of the N-type well 16N is preferably less than 4 μm as described above.

  Next, a photoresist film (not shown) is formed by, eg, spin coating.

  Next, using a photolithography technique, an opening (not shown) that exposes a region where the NMOS transistor 18 (see FIG. 1) is to be formed is formed in the photoresist film.

Next, using the photoresist film as a mask, a P-type dopant impurity is introduced into the semiconductor substrate 10 by, eg, ion implantation. For example, boron is used as the P-type dopant impurity. The acceleration energy is, for example, 30 keV. The dose amount is, for example, about 3 × 10 ¹² cm ⁻² . Thereby, a channel dope layer (not shown) for controlling the threshold voltage of the NMOS transistor 18 is formed.

  Thereafter, the photoresist film is peeled off.

  Next, a photoresist film (not shown) is formed by, eg, spin coating.

  Next, using a photolithography technique, an opening (not shown) exposing a region where the PMOS transistor 22 (see FIG. 1) is to be formed is formed in the photoresist film.

Next, using the photoresist film as a mask, an N-type dopant impurity is introduced into the semiconductor substrate 10 by, eg, ion implantation. For example, arsenic (As) is used as the N-type dopant impurity. The acceleration energy is, for example, 150 keV. The dose amount is, for example, about 2 × 10 ¹³ cm ⁻² . Thereby, a channel dope layer (not shown) for controlling the threshold voltage of the PMOS transistor 22 is formed.

  Thereafter, the photoresist film is peeled off.

  Next, a gate insulating film 26 of a silicon oxide film having a thickness of about 3 nm is formed on the entire surface by, eg, thermal oxidation (see FIG. 8B).

  Next, a polysilicon film 28 having a thickness of about 100 nm is formed on the entire surface by, eg, CVD (Chemical Vapor Deposition) (see FIG. 8C).

  Next, the polysilicon film 28 is patterned into the shape of the gate electrodes 28a and 28b by using a photolithography technique (see FIG. 9A). When patterning the polysilicon film 28, for example, anisotropic etching is used. Thus, the gate electrodes 28a and 28b of the transistors 18 and 22 are formed, respectively.

  Next, a photoresist film 84 is formed by, eg, spin coating.

  Next, an opening 86 exposing a region where the NMOS transistor 18 is to be formed is formed in the photoresist film using a photolithography technique (see FIG. 9B).

Next, using the photoresist film 84 and the gate electrode 28a as a mask, an N-type dopant impurity is introduced into the semiconductor substrate 10 on both sides of the gate electrode 28a. For example, phosphorus or arsenic is used as the N-type dopant impurity. The acceleration energy is, for example, 5 keV. The dose amount is about 1 × 10 ¹⁵ cm ⁻² , for example. As a result, an N-type extension region (low-concentration impurity region) 30 that forms a shallow region of the extension source / drain structure is formed.

Next, a P-type dopant impurity is introduced into the semiconductor substrate 10 by oblique ion implantation using the photoresist film 84 and the gate electrode 28a as a mask. For example, boron or boron fluoride is used as the P-type dopant impurity. The acceleration energy is, for example, 10 keV. The dose amount is, for example, about 1 × 10 ¹³ cm ⁻² . As a result, a P-type pocket region (not shown) is formed. The pocket region is for preventing a short channel effect.

  Thereafter, the photoresist film 84 is peeled off.

  Next, a photoresist film 88 is formed by, eg, spin coating.

  Next, an opening 90 exposing a region where the PMOS transistor 22 is to be formed is formed in the photoresist film 88 by using a photolithography technique (see FIG. 9C).

Next, using the photoresist film 88 and the gate electrode 28b as a mask, a P-type dopant impurity is introduced into the semiconductor substrate 10 on both sides of the gate electrode 28b. For example, boron or boron fluoride is used as the P-type dopant impurity. The acceleration energy is, for example, 1 keV. The dose amount is about 5 × 10 ¹⁴ cm ⁻² , for example. As a result, a P-type extension region (low concentration impurity region) 34 that forms a shallow region of the extension source / drain structure is formed.

Next, N-type dopant impurities are introduced into the semiconductor substrate 10 by oblique ion implantation using the photoresist film 88 and the gate electrode 28b as a mask. For example, phosphorus or arsenic is used as the N-type dopant impurity. The acceleration energy is, for example, 25 keV. The dose amount is, for example, about 1 × 10 ¹³ cm ⁻² . As a result, an N-type pocket region (not shown) is formed.

  Thereafter, the photoresist film 88 is peeled off.

  Next, an insulating film of a silicon oxide film having a thickness of, for example, about 800 nm is formed on the entire surface by, eg, CVD.

  Next, the insulating film is anisotropically etched. Thereby, sidewall spacers 36 formed of an insulating film are formed on the sidewall portions of the gate electrodes 28a and 28b (see FIG. 10A).

  Next, a photoresist film 92 is formed by, eg, spin coating.

  Next, an opening 94 a that exposes a region where the NMOS transistor 18 is formed and an opening 94 b that exposes a region where the N-type well tap region 24 is formed are formed in the photoresist film 92 using photolithography technology. (See FIG. 10B).

Next, an N-type dopant impurity is introduced into the semiconductor substrate 10 using the gate electrode 28 a on which the sidewall spacer 36 is formed and the photoresist film 92 as a mask. For example, phosphorus is used as the N-type dopant impurity. The acceleration energy is, for example, 10 keV. The dose amount is, for example, about 5 × 10 ¹⁵ cm ⁻² . As a result, N-type high-concentration impurity regions 38 that form deep regions of the extension source / drain structure are formed in the semiconductor substrate 10 on both sides of the gate electrode 28a where the sidewall spacers 36 are formed. A source / drain diffusion layer 40 having an extension source / drain structure is formed by the low concentration impurity region 30 and the high concentration impurity region 38. At this time, N-type dopant impurities are also introduced into the gate electrode 28a, and the conductivity type of the gate electrode 28a becomes N-type. At this time, an N-type well tap region 24 is also formed.

  Thereafter, the photoresist film 92 is peeled off.

  Next, a photoresist film 96 is formed by, eg, spin coating.

  Next, an opening 98a exposing a region where the PMOS transistor 22 is formed and an opening 98b exposing a region where the P-type well tap region 20 is formed are formed in the photoresist film 96 using photolithography technology. (See FIG. 10C).

Next, a P-type dopant impurity is introduced into the semiconductor substrate 10 using the gate electrode 28b on which the sidewall spacers 36 are formed and the photoresist film 96 as a mask. For example, boron or boron fluoride is used as the P-type dopant impurity. The acceleration energy is, for example, 10 keV. The dose amount is, for example, about 5 × 10 ¹⁵ cm ⁻² . As a result, a P-type high-concentration impurity region 42 that forms a deep region of the extension source / drain structure is formed in the semiconductor substrate 10 on both sides of the gate electrode 28b where the sidewall spacers 36 are formed. A source / drain diffusion layer 44 having an extension source / drain structure is formed by the low concentration impurity region 34 and the high concentration impurity region 42. At this time, a P-type dopant impurity is also introduced into the gate electrode 28b, and the conductivity type of the gate electrode 28b becomes P-type. At this time, a P-type well tap region 20 is also formed.

  Thereafter, the photoresist film 96 is peeled off.

  Next, a cobalt (Co) film having a thickness of, for example, about 5 nm is formed on the entire surface by, eg, sputtering.

  Next, by performing heat treatment, cobalt atoms of the cobalt film react with silicon atoms of the semiconductor substrate to form a cobalt silicide film. The heat treatment temperature is about 500 ° C., for example.

  Thereafter, the unreacted cobalt film is removed by etching.

  Thus, for example, a silicide film 46 of cobalt silicide is formed on the source / drain diffusion layers 40 and 44. The silicide film 46 on the source / drain diffusion layers 40 and 44 functions as a source / drain electrode. A silicide film 46 is also formed on the well tap regions 20 and 24. A silicide film 46 is also formed on the gate electrodes 28a and 28b (see FIG. 11A).

  Thus, a plurality of NMOS transistors 18 having the gate electrode 28a and the source / drain diffusion layers 40 are formed in the P-type well 16P. Further, the PMOS transistor 22 having the gate electrode 28b and the source / drain diffusion layer 44 is formed in the N-type well 16N. The NMOS transistor 18 corresponds to the driver transistors D1 and D2 and the transfer transistors T1 and T2 that form part of the SRAM memory cell MC (see FIG. 2). The driver transistor D1, the driver transistor D2, the transfer transistor T1, and the transfer transistor T2 respectively formed by the plurality of NMOS transistors 18 are formed together in the same process as described above. The PMOS transistor 22 corresponds to the load transistors L1 and L2 that form part of the SRAM memory cell MC. The load transistor L1 and the load transistor L2 respectively formed by the plurality of PMOS transistors 22 are formed together in the same process as described above.

  Next, an interlayer insulating film 48 of, eg, a 1 μm-thick silicon oxide film is formed on the entire surface by, eg, CVD (see FIG. 11B).

  Next, contact holes 50 are formed in the interlayer insulating film 48 by using a photolithography technique. Thus, contact hole 50 reaching source / drain electrodes 40, 44, contact hole 50 reaching silicide films 40, 44 on well tap regions 20, 24, and contact holes reaching gate electrodes 28a, 28b (not shown). ) And are formed.

  Next, a Ti film (not shown) having a thickness of about 5 to 20 nm and a TiN film (not shown) having a thickness of about 5 to 20 nm are stacked on the entire surface by, eg, sputtering. Thereby, a barrier film (not shown) formed of the laminated film is formed.

  Next, a tungsten film having a thickness of about 200 nm is formed on the entire surface by, eg, CVD.

  Next, the tungsten film and the barrier film are removed by polishing until the surface of the interlayer insulating film 48 is exposed, for example, by CMP (Chemical Mechanical Polishing). Thus, the tungsten conductor plug 52 is buried in the contact hole 50 (see FIG. 11C).

  Next, an interlayer insulating film 54 of, eg, a silicon oxide film of about 300 nm thickness is formed on the entire surface by, eg, CVD.

  Next, a trench 56 for embedding the wiring 58 is formed in the interlayer insulating film 54 by using a photolithography technique. The groove 56 is formed so as to expose the upper part of the conductor plug 52.

  Next, a barrier film (not shown) is formed on the entire surface by, eg, sputtering.

  Next, for example, a Cu seed layer (not shown) is formed on the entire surface by, eg, sputtering.

  Next, for example, a Cu layer is formed on the entire surface by, for example, electrolytic plating.

  Next, the Cu layer and the barrier film are polished by CMP, for example, until the surface of the interlayer insulating film 54 is exposed. Thus, the Cu wiring 58 is buried in the groove 56.

  Thus, the semiconductor device according to the present embodiment is manufactured.

[Modified Embodiment]
The present invention is not limited to the above embodiment, and various modifications are possible.

  For example, in the above embodiment, the P-type buried impurity layer 14 is formed below the P-type well 16P and the N-type well 16N. However, the present invention is not limited to this. It is not necessary to form the P type buried impurity layer 14 below the N type well 16N and form the P type buried impurity layer 14 below the P type well 16P. If the P-type buried impurity layer 14 is formed at least under the N-type well 16N, the funneling extending from the depletion layer under the N-type well 16N can be cut by the P-type buried impurity layer 14.

  However, from the viewpoint of further improving the radiation resistance, it is preferable to form the P-type buried impurity layer 14 below the P-type well 16P. That is, embedding the P-type buried impurity layer 14 also under the P-type well 16P contributes to reducing the electrical resistance of the P-type well 16P and contributes to improvement in resistance to single event latch-up. In addition, when neutrons or the like penetrate through the depletion layer at the junction of the source / drain diffusion layer 40 of the NMOS transistor 18, a single event upset in which charges are captured and data stored in the memory cell MC is inverted is prevented. Can also contribute.

  In the above embodiment, the case where a P-type semiconductor substrate is used as the semiconductor substrate has been described as an example. However, the present invention is not limited to this. For example, an N-type semiconductor substrate may be used. In this case, the conductivity type of each component may be set to the opposite conductivity type.

  In the above embodiment, the step of forming the P-type well 16P and the step of forming the N-type well 16N are performed after the step of forming the buried impurity layer 14. However, the order of these steps is limited to the above. It can be set as appropriate.

DESCRIPTION OF SYMBOLS 10 ... Semiconductor substrate 12 ... Element isolation region 14 ... Embedded impurity layer 16P ... P-type well 16N ... N-type well 18 ... NMOS transistor 20 ... Well tap region 22 ... PMOS transistor 24 ... Well tap region 26 ... Gate insulating film 28 ... Poly Silicon film 28a, 28b ... gate electrode 30 ... extension region, low concentration impurity region 32 ... channel region 34 ... extension region, low concentration impurity region 35 ... channel region 36 ... side wall spacer 38 ... high concentration impurity region 40 ... source / drain Diffusion layer 42 ... High-concentration impurity region 44 ... Source / drain diffusion layer 46 ... Silicide film 48 ... Interlayer insulating film 50 ... Contact hole 52 ... Conductor plug 54 ... Interlayer insulating film 56 ... Groove 58 ... Wirings 60a, 60b ... CMOS inverter 62 …flip flop Path 64 ... Input node 66 ... Output node 68 ... Input node 70 ... Output node 72 ... Photoresist film 74 ... Opening 76 ... Photoresist film 78 ... Opening 80 ... Photoresist film 82 ... Opening 84 ... Photoresist film 86 ... Opening 88 ... Photoresist film 90 ... Opening 92 ... Photoresist films 94a, 94b ... Opening 96 ... Photoresist films 98a, 98b ... Opening 110 ... Semiconductor substrate 114 ... N type buried impurity layer 116P ... P type Well 116N ... N-type well 118 ... NMOS transistor 120 ... Well tap region 124 ... Well tap region 122 ... PMOS transistors 128a, 128b ... Gate electrodes 140 ... Source / drain diffusion layers 144 ... Source / drain diffusion layers

Claims (8)

A first well of the second conductivity type formed in the semiconductor substrate of the first conductivity type;
A first transistor of the first conductivity type formed in the first well;
A second well of the first conductivity type formed in the semiconductor substrate and adjacent to the first well;
A second transistor of the second conductivity type formed in the second well and electrically connected to the first transistor;
A buried impurity layer of the first conductivity type formed in the semiconductor substrate at least below the first well;
The distance between the concentration peak position of the buried impurity layer and the concentration peak position of the first well is 1 μm or more. The semiconductor device according to claim 1,
One of the source / drain of the first transistor and one of the source / drain of the second transistor are electrically connected. A semiconductor device, wherein: The semiconductor device according to claim 1 or 2,
A third transistor of the first conductivity type formed in the first well;
A second transistor of the second conductivity type formed in the second well, wherein one of the source / drain is electrically connected to one of the source / drain of the third transistor;
The output node of the first inverter formed by the first transistor and the second transistor is electrically connected to the input node of the second inverter formed by the third transistor and the fourth transistor. Connected,
The semiconductor device, wherein an output node of the second inverter is electrically connected to an input node of the first inverter. The semiconductor device according to any one of claims 1 to 3,
The embedded impurity layer is also formed in the semiconductor substrate below the second well. A semiconductor device, wherein: A first conductivity type dopant impurity is introduced into at least a first region of the first conductivity type semiconductor substrate by a first energy, and the first conductivity type buried in the semiconductor substrate is spaced from the surface of the semiconductor substrate. Forming an impurity layer;
A second conductivity type dopant impurity is introduced into the first region of the semiconductor substrate by a second energy lower than the first energy to form the second conductivity type first well in the semiconductor substrate. Process,
The dopant impurity of the first conductivity type is introduced into the second region of the semiconductor substrate adjacent to the first region by a third energy lower than the first energy, and the first conductivity is introduced into the semiconductor substrate. Forming a second well of the mold;
Forming the first conductivity type first transistor in the first well, and forming the second conductivity type second transistor connected to the first transistor in the second well; Have
The distance between the concentration peak position of the buried impurity layer and the concentration peak position of the first well is 1 μm or more. In the manufacturing method of the semiconductor device according to claim 5,
In the step of forming the first transistor and the second transistor, one of the source / drain of the first transistor and one of the source / drain of the second transistor are electrically connected. A method for manufacturing a semiconductor device. In the manufacturing method of the semiconductor device according to claim 5 or 6,
In the step of forming the first transistor and the second transistor, the third transistor of the first conductivity type is further formed in the first well, and one of the source / drain is the source of the third transistor. / The fourth transistor of the second conductivity type that is electrically connected to one of the drains is further formed in the second well. In the manufacturing method of the semiconductor device according to any one of claims 5 to 7,
In the step of forming the buried impurity layer, the buried impurity layer is also formed in the semiconductor substrate below the second well.

Images